i.MX28 nand driver broken in Linux 4.18

Wolfgang Grandegger wg at grandegger.com
Mon Apr 1 13:08:45 PDT 2019


Hello Miquel;

Am 01.04.19 um 11:23 schrieb Miquel Raynal:
> Hi Wolfgang,
> 
> Wolfgang Grandegger <wg at grandegger.com> wrote on Sat, 23 Mar 2019
> 20:55:19 +0100:
> 
>> Hello Miquel,
>>
>> Am 06.03.19 um 14:59 schrieb Miquel Raynal:
>>> Hi Wolfgang,
>>>
>>> Wolfgang Grandegger <wg at grandegger.com> wrote on Tue, 5 Mar 2019
>>> 15:52:52 +0100:
>>>   
>>>> Hello,
>>>>
>>>> I will bisect the problem next week when I have access to the
>>>> hardware... more soon...
>>>>  
>>>
>>> Great, thanks.  
>>
>> Here is the result of git bisection:
>>
>> wolf at bernex:~/git/linux$ git bisect good
>> 76e1a0086a0c3276b384f77905345e0fcc886fdd is the first bad commit
>> commit 76e1a0086a0c3276b384f77905345e0fcc886fdd
>> Author: Miquel Raynal <miquel.raynal at bootlin.com>
>> Date:   Fri Mar 2 15:38:39 2018 +0100
>>
>>     mtd: rawnand: gpmi: support ->setup_data_interface()
>>     
>>     Until now the GPMI driver had its own timings logic while the core
>>     already handles that and request the NAND controller drivers to support
>>     the ->setup_data_interface() hook. Implement that hook by reusing the
>>     already existing function. No real glue is necessary between core timing
>>     delays and GPMI registers because the driver already translates the
>>     ONFI timing modes into register values.
>>     
>>     Make use of the core's tREA, tRLOH and tRHOH values that allow computing
>>     more precise timings for mode [0-3] and get significantly better values
>>     (+20% with an i.MX6 Sabre Auto board). Otherwise use the existing logic.
>>     
>>     Signed-off-by: Miquel Raynal <miquel.raynal at bootlin.com>
>>     Tested-by: Han Xu <han.xu at nxp.com>
>>     Signed-off-by: Boris Brezillon <boris.brezillon at bootlin.com>
> 
> Thank you for the bisection, there is definitely something wrong with
> this commit but it worked for me and for Han so it's quite difficult to
> find out what is failing if I cannot reproduce. Could you please dump
> the timing registers in both cases (working/not working) and observer if
> there are odd values ? (0, too short or too big values, etc).

here are some first figures:

76e1a0086a0c3276b384f77905345e0fcc886fdd^:
[    1.911760] clock_period_in_ns : 41
[    1.922818] address_setup_in_cycles : 1
[    1.915343] data_setup_in_cycles : 3
[    1.919254] data_hold_in_cycles : 2
[    1.926709] HW_GPMI_TIMING0 : 0x10203
[    1.930641] HW_GPMI_TIMING1 : 0x5000000

v4.18:
[    2.090621] period_ps : 45454
[    2.076601] addr_setup_cycles : 1
[    2.080002] data_setup_cycles : 1
[    2.083598] data_hold_cycles : 1
[    2.093849] HW_GPMI_TIMING0 : 0x10101
[    2.096890] HW_GPMI_TIMING1 : 0x90000000

Hope that's what you are looking for. Unfortunately, the code of both
versions is very different (complete rewrite). I will have a closer look
tomorrow.

Wolfgang.



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