[PATCH][v2] mtd: rawnand: fsl_ifc: Fix nand waitfunc return value

[Jagdish Gediya]

As per the IFC hardware manual, Most significant 2 bytes in
nand_fsr register are the outcome of NAND READ STATUS command.

So status value need to be shifted and aligned as per the nand
framework requirement.

Fixes: 82771882d960 ("NAND Machine support for Integrated Flash Controller")
Cc: stable at vger.kernel.org # v3.18+
Signed-off-by: Jagdish Gediya <jagdish.gediya at nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha at nxp.com>
---
Changes for v2: Incorporated comments from Boris Brezillon
        - Added fixes tag

 drivers/mtd/nand/fsl_ifc_nand.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 9390cbd..0aa03ba 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -643,12 +643,13 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	fsl_ifc_run_command(mtd);
 
 	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
-
+	nand_fsr >>= 16;
+	nand_fsr = (nand_fsr >> 8) | (nand_fsr << 8);
 	/*
 	 * The chip always seems to report that it is
 	 * write-protected, even when it is not.
 	 */
-	return nand_fsr | NAND_STATUS_WP;
+	return (nand_fsr & 0xff) | NAND_STATUS_WP;
 }
 
 /*
-- 
1.9.1