[PATCH 0/3] mtd: fix AMD/Intel flash bugs

[Boris Brezillon]

On Thu, 15 Mar 2018 17:55:57 +0000
Joakim Tjernlund <Joakim.Tjernlund at infinera.com> wrote:

> On Thu, 2018-03-15 at 16:54 +0100, Boris Brezillon wrote:
> > CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
> > 
> > 
> > On Sun, 11 Mar 2018 16:06:03 +0000
> > Joakim Tjernlund <Joakim.Tjernlund at infinera.com> wrote:
> >   
> > > On Thu, 2018-03-01 at 14:39 +0100, Joakim Tjernlund wrote:  
> > > > This fixes a bug which allows read/write to a erase block currently
> > > > erasing.
> > > > Also works around a chip bug in Micron 28F00AP30 chips.
> > > > 
> > > > Joakim Tjernlund (3):
> > > >   cfi_cmdset_0001: Do not allow read/write to suspend erase block.
> > > >   cfi_cmdset_0001: Workaround Micron Erase suspend bug.
> > > >   cfi_cmdset_0002: Do not allow read/write to suspend erase block.
> > > > 
> > > >  drivers/mtd/chips/cfi_cmdset_0001.c | 33 ++++++++++++++++++++++++++++-----
> > > >  drivers/mtd/chips/cfi_cmdset_0002.c |  9 ++++++---
> > > >  include/linux/mtd/flashchip.h       |  1 +
> > > >  3 files changed, 35 insertions(+), 8 deletions(-)
> > > >   
> > > 
> > > Ping?  
> > 
> > You didn't Cc the MTD maintainers, so that's not surprising you don't
> > get a reply from us :P.  
> 
> I find it more surprising that the MTD maintainers doesn't read the MTD list ?

I do read the ML occasionally, though I tend to rely on what's in my
inbox, so there might be a bigger latency if you don't Cc me. I guess
the process differ for each maintainer, but it's a good practice to Cc
maintainers when you send a patch.

> I figured this was a requirement.
> 
> >   
> > > This is a fairly serious bug as it confuses the flash state machine,
> > > making further flash access fail.  
> > 
> > I'll try to have a look.  
> 
> Thanks


-- 
Boris Brezillon, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com