[PATCH 1/3] spi-nor: intel-spi: Prefer WREN over other write enables

Mika Westerberg mika.westerberg at linux.intel.com
Tue Jan 30 02:50:13 PST 2018

On Thu, Jan 04, 2018 at 12:07:42PM +0300, Mika Westerberg wrote:
> On many older systems using SW sequencer the PREOP_OPTYPE register
> contains two preopcodes as following:
>   PREOP_OPTYPE=0xf2785006
> The last two bytes are the opcodes decoded to:
>   0x50 - Write enable for volatile status register
>   0x06 - Write enable
> The former is used to modify volatile bits in the status register. For
> non-volatile bits the latter is needed. Preopcodes are used in SW
> sequencer to send one command "atomically" without anything else
> interfering the transfer. The sequence that gets executed is:
>   - Send preopcode (write enable) from PREOP_OPTYPE register
>   - Send the actual SPI command
>   - Poll busy bit in the status register (0x05, RDSR)
> Commit 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be
> programmed by BIOS") enabled atomic sequence handling but because both
> preopcodes are programmed, the following happens:
>   if (preop >> 8)
>   	val |= SSFSTS_CTL_SPOP;
> Since on these systems preop >> 8 == 0x50 we end up picking volatile
> write enable instead. Because of this the actual write command is pretty
> much NOP unless there is a WREN latched in the chip already.
> Fix this by preferring WREN over other write enable preopcodes.
> Fixes: 8c473dd61bb5 ("spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS")
> Signed-off-by: Mika Westerberg <mika.westerberg at linux.intel.com>
> Cc: stable at vger.kernel.org


Any change getting these merged for v4.16?

More information about the linux-mtd mailing list