[PATCHv4 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants

[Chris Packham]

On 08/01/18 11:35, Chris Packham wrote:
> Hi Miquel, Ezequiel,
> 
> On 23/12/17 05:56, Ezequiel Garcia wrote:
>> On 22 December 2017 at 12:53, Miquel RAYNAL
>> <miquel.raynal at free-electrons.com> wrote:
>>> Hello Chris,
>>>
>>> On Fri, 22 Dec 2017 12:19:04 +1300
>>> Chris Packham <chris.packham at alliedtelesis.co.nz> wrote:
>>>
>>>> From: Kalyan Kinthada <kalyan.kinthada at alliedtelesis.co.nz>
>>>>
>>>> The Armada-370 based SoCs support arbitration between the NAND Flash
>>>> interface and NOR (i.e. devbus) on the same chip select. However there
>>>> are two guidelines that must be followed to avoid data corruption in
>>>> this scenario.
>>>
>>> Sorry to bother you again with that but, do you actually face any
>>> issue/data corruption with this scenario?
>>>
>>
>> Indeed. We need a description of a real world problem this patch is fixing.
>>
> 
> I totally agree. The Marvell FAE used words like "data corruption" hence
> my re-newed interest in this. I had hoped these patches would pique the
> interest of someone from Marvell's engineering team with some more info
> on how the data corruption exhibits.
> 
> I've been running some of the mtd-utils tests on my hardware and haven't
> detected any failures yet.
> 
> I think the key would be to be doing interleaved accesses between nand
> and the parallel device. I've just kicked off something I think should
> do this on my hardware but I'm unsure as to how long I should wait for
> an issue to present itself.
> 
> I'll leave it running for as long as I can today. If I find a failure
> I'll report back otherwise we can leave this patch for the mailing list
> archives waiting for an issue to be seen.
> 

I've been running my test for several hours an no obvious problem has 
presented itself so I'm happy to leave it there until such time as a 
problem is observed or Marvell provide a reproduction.