Integration of Samsung On-Die ECC Nand Flash

[M D]

Processor                 :  ARM imx21
NAND Flash             :  On Die ECC Flash (K9F1G08U0F)

We are presently using an ARM imx21 processor interfaced with a Nand
chip that does not support on die ECC (samsung e-die). The Nand Flash
Controller on board the processor, calculates ECC for the data that is
read/written to /from the Flash. The device driver reads the ECC
status register to make a decision on the Integrity of the data. The
NFC supports 1 bit error correction.

We now want to integrate the new Samsung F-Die chip that supports on
die ECC calculation and correction. The On Die ECC logic does not use
the Spare/OOB area of the Nand Flash to store the ECC information. The
on die ECC flash logic will process the data and correct errors and
provide this to the NFC. The NFC can then proceed to further correct
data as suitable.


Example  - The page being read has < 4 bit errors

1) NFC requests data from the F-Die Nand Flash
2) F-Die on die ECC will calculate and correct ECC errors on the whole
(Main + Spare) Area data and provide this information to the NFC
3) The NFC will then read the Main area and not find any errors


Example - The page being read has > 4 bit erros

1) NFC requests data from the F-Die Nand Flash
2) F-Die on die ECC will calculate and fail to correct >4 bit ECC
errors on the whole (Main + Spare) Area data and provide this
information to the NFC
3) The NFC will then read the Main area and find > 1 bit error. NFC
will report this status to the above mtd layers

>From the above two analysis, we think that we do not need any code
changes in the driver to integrate the Samsumg F-die on chip ECC

Regards
Max