[PATCH 1/2] dt-bindings: mtd: pxa3xx: Add "marvell, nand-force-csx" compatible string

[Kalyan Kinthada]

When the arbitration between NOR and NAND flash is enabled
the <FORCE_CSX> field bit[21] in the Data Flash Control Register
needs to be set to 1 according to guidleine GL-5830741.

This patch introduces a new compatible string "marvell,nand-force-csx"
which is activated through device tree to implement the guideline
GL-5830741.

Signed-off-by: Kalyan Kinthada <kalyan.kinthada at alliedtelesis.co.nz>
---
 Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
index d9b655f11048..157ca7efa3d3 100644
--- a/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/pxa3xx-nand.txt
@@ -20,6 +20,7 @@ Optional properties:
 				not present false
  - nand-ecc-strength:           number of bits to correct per ECC step
  - nand-ecc-step-size:          number of data bytes covered by a single ECC step
+ - marvell,nand-force-csx:      Set to implement guideline when arbitration of NAND and NOR flash is enabled.
 
 The following ECC strength and step size are currently supported:
 
-- 
2.14.1