[PATCH 2/2] mtd: spi-nor: add GigaDevice gd25q512

[Cyrille Pitchen]

Hi Roman,

+ Marek

please add spi-nor maintainers in CC when submitting spi-nor patches.

Le 17/09/2017 à 23:54, Roman Yeryomin a écrit :
> Signed-off-by: Roman Yeryomin <roman at advem.lv>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 1d0e114..a6e56f4 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -984,6 +984,11 @@ static const struct flash_info spi_nor_ids[] = {
>  			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
>  			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
>  	},
> +	{
> +		"gd25q512", INFO(0xc84020, 0, 64 * 1024, 1024,
> +			SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> +			SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4B_OPCODES)
> +	},

According to the datasheet found of the Gigadevice web site for GD25Q512
(JEDEC ID C84020), the Quad Enable (QE) bit of this memory part is
BIT(6) of the Status Register 1 hence you must set .quad_enable =
macronix_quad_enable otherwise spansion_quad_enable() would be called
instead but this latest function is suited only when the QE bit is
BIT(1) of the Status Register 2, like for older Gigadevice memory parts.

Please have a look at the gd25q256 entry as an example.

Best regards,

Cyrille

>  	/* Intel/Numonyx -- xxxs33b */
>  	{ "160s33b",  INFO(0x898911, 0, 64 * 1024,  32, 0) },
>