[PATCH v6 00/15] A SPI NAND framework under generic NAND framework

Peter Pan 潘栋 (peterpandong) peterpandong at micron.com
Tue May 30 23:34:30 PDT 2017

Hi Boris,

> On 31 May 2017, at 14:20, Boris Brezillon <boris.brezillon at free-electrons.com> wrote:
> Le Wed, 31 May 2017 01:12:16 +0000,
> Peter Pan 潘栋 (peterpandong) <peterpandong at micron.com> a écrit :
>> Hi Boris,
>> On Thu, May 30, 2017 at 5:00 AM, Boris Brezillon
>> <boris.brezillon at free-electrons.com> wrote:
>>> Hi Peter,
>>> On Wed, 24 May 2017 15:06:56 +0800
>>> Peter Pan <peterpandong at micron.com> wrote:
>>>> First of all, thank Boris and Marek for your priceless comments
>>>> on v5 and thank everyone reviewed and tested on my previous series.
>>>> I can never be here without your help. This series comes to v6
>>>> and it becomes much better with your help.
>>>> SPI NAND is a new NAND family device with SPI protocol as
>>>> its interface. And its command set is totally different
>>>> with parallel NAND.
>>>> Our first attempt to SPI NAND was more than 2 years ago[1].
>>>> At that time, I didn't make BBT shareable and there were
>>>> too many duplicate code with parallel NAND, so that serie
>>>> stoped. But the discussion never stops. Now Boris has a plan
>>>> to make a generic NAND framework which can be shared with
>>>> both parallel and SPI NAND. Now the first step of the
>>>> new generic NAND framework is finished. And it is waiting
>>>> for a user. After discussion with Boris. We both think it's
>>>> time to rebuild SPI NAND framework based on the new NAND
>>>> framework and send out for reviewing.
>>>> This series includes two part. The first part (patch 1 to 9)
>>>> is a new generic NAND framework from Boris Brezillon, which
>>>> is from Biris's nand/generic branch[2]. The second part
>>>> (patch 10 to 15) introductes a SPI NAND framework based on
>>>> the new generic NAND framework.
>>>> This series only supports basic SPI NAND features and uses
>>>> generic spi controller for data transfer. ECC support is removed
>>>> since it's not in a good structure and more important, it should
>>>> be shared between different NAND devices, which means it should
>>>> be in new NAND core. Support different types of ECC and advanced
>>>> SPI NAND features is the next step.
>>>> This series is based on nand/next branch and is tested on
>>>> Xilinx Zedboard with Micron MT29F2G01ABAGDSF SPI NAND chip.  
>>> As you can see, I started to review this v6, but I don't expect you to
>>> send a new version (at least not immediately).
>>> Here is the plan: I'll finish reviewing the series, and while I'm
>>> reviewing I'll try to address my own comments. Once the review/changes
>>> are done, I'll push a nand/spi branch to the github repo [1] and ask
>>> you and Arnaud to review/test the whole thing. If you're happy with
>>> my changes (it should only be minor changes to your
>>> initial implementation) I'll ask you to send a v7. I'll then wait for
>>> 4.13-rc1 to be out and apply everything to my nand/next branch (I
>>> expect a few conflicting changes in the nand/mtd area caused by the
>>> migration to the new doc format, that's why I'd like to wait one more
>>> cycle).
>>> If everything goes well, we should be good for 4.14, and the patches
>>> will have spent enough time in linux-next to discover obvious bugs.
>>> Let me know if you have a problem with this approach.  
>> You plan is great, I'm OK with it. Looking forward to merge SPI NAND
>> to main line :)
> I'm still expecting replies to my review(s) to know if the changes I
> plan to do are correct ;-).

Actually I'm looking at your comments right now. Something was wrong with my mailbox. Hope to give you feedback today or tomorrow.

Peter Pan 

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