SW ECC - double bit flip detection on old NAND devices

[Richard Weinberger]

Lukasz,

On Fri, May 5, 2017 at 3:14 PM, Lukasz Majewski <lukma at denx.de> wrote:
> Dear All,
>
> I've a problem with pretty old Flash NAND memory (Samsung 128Mx8) [1]
>
> It doesn't support On-Chip ECC - one needs to calculate ECC manually.
>
> The Yaffs2 FS (for this version) uses "1bit correction
> ECC" (yaffs_ecc.c). It calculates ECC for 256 bytes -> we have got 22
> bits for ECC (rounded up to 3 bytes).
>
> For 2048 bytes page we do have 8 such ECC blocks -> 24 ECC bytes in
> total in OOB.
>
> This code (as noted in yaffs_ecc.* header) is able to correct one
> single bit flip.
>
> I've also looked into Linux kernel code for SW ECC calculation:
>
> http://elixir.free-electrons.com/linux/latest/source/drivers/mtd/nand/nand_ecc.c#L523

This is for ecc->algo == NAND_ECC_HAMMING.

> And here it is also explicitly said that we can correct one bit in such
> chunk.
>
> Please correct me if I'm wrong but when we have two bit-flips in such
> 256 bytes chunk, the ECC will be still correct and such obviously
> broken page will not be "retired".
>
> What one can do to prevent such situation?
>
> My idea, if the above holds, would be to implement better ECC scheme as
> proposed in "Error Correction Code (ECC) in Micron" doc [2].
>
> Maybe somebody knows better/simpler solution?

I'd suggest to use BCH instead of Hamming.
Please see NAND_ECC_BCH.

-- 
Thanks,
//richard