[PATCH v3] mtd: spi-nor: Add support for N25Q256A13

[岩松信洋 / IWAMATSU，NOBUHIRO]

Hi,

> -----Original Message-----
> From: Cyrille Pitchen [mailto:cyrille.pitchen at wedev4u.fr]
> Sent: Wednesday, March 08, 2017 7:11 AM
> To: 岩松信洋 / IWAMATSU，NOBUHIRO; linux-mtd at lists.infradead.org
> Cc: Marek Vasut; Cyrille Pitchen; Jagan Teki
> Subject: Re: [PATCH v3] mtd: spi-nor: Add support for N25Q256A13
> 
> Hi Nobuhiro,
> 
> Le 02/03/2017 à 03:42, Nobuhiro Iwamatsu a écrit :
> > Add new Micron N25Q256A (N25Q256A13) 256Mbit NOR Flash in the list
>                             ^
> You mean N25Q256A11, don't you? Otherwise it's not consistent with the
> actual patch!
> 

Yes, this is my bad.

> > of supported devices. This chip has the same structure as the N25Q256A
> > but ID and voltage (1V8) to use is different. Therefore, this adds
> > N25Q256A13 as n25q256ax1.
> 
>   ^
> N25Q256A11 as n25q256ax1

Indeed, thanks.


> 
> >
> > In the future, for new Micron memories we could use the patterns
> > "n25q*ax1" for 1V8 and "n25q*ax3" for 3V3 memories.
> >
> 
> Sound like a good idea :)
> Marek, do you agree with that?
> 
> Best regards,
> 
> Cyrille
> 

I will send 4th patch soon.

Thanks,
  Nobuhiro

> > Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw at hitachi.com>
> > CC: Jagan Teki <jagan at openedev.com>
> > CC: Marek Vasut <marek.vasut at gmail.com>
> > CC: Cyrille Pitchen <cyrille.pitchen at atmel.com>
> > ---
> >  drivers/mtd/spi-nor/spi-nor.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index 1ae872bfc3ba..2e02991d93aa
> > 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1031,6 +1031,7 @@ static const struct flash_info spi_nor_ids[] = {
> >  	{ "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q128a13",  INFO(0x20ba18, 0, 64 * 1024,  256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> >  	{ "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> > +	{ "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K |
> > +SPI_NOR_QUAD_READ) },
> >  	{ "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> >  	{ "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> >  	{ "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ) },
> >