[PATCH v6 11/15] nand: spi: add basic operations support

[Boris Brezillon]

Le Wed, 28 Jun 2017 11:41:03 +0200,
Arnaud Mouiche <arnaud.mouiche at gmail.com> a écrit :

> Hello Boris,
> 
> On 27/06/2017 22:15, Boris Brezillon wrote:
> >    
> > Hm, actually I wonder if this ->prepare_op() method is really what we
> > want. It seems to be here to set the proper plane number and the
> > number of dummy bytes after the address cycles.
> > I'd say deducing the plane from the page is something standard. Whether
> > we need it or not depends on the information provide in the memorg
> > object (->nplanes).
> >
> > Regarding the dummy byte, do you have examples of SPI NANDs requiring
> > less or more dummy bytes in this read/write from/to cache use case?
> > If not, I'd prefer to keep it hardcoded in the core for know, and add
> > a hook when the need appears.  
> Here is the page read description for various devices I have:
> 
> MT29FxG01AAADD
> - fetch to internal: CMD_READ (0x13) + (3 bytes page_id)
> - read from internal: CMD_READ_RDM (0x03) + (2 bytes address + pane 
> selection @ bit 12) + 1 dummy byte
> 
> GD5FxxQ4xC
> - fetch to internal: CMD_READ (0x13) + (3 bytes page_id)
> - read from internal: CMD_FAST_READ (0x0B) + 1 dummy byte + (2 bytes 
> address) + 1 dummy byte

Ok, so this is the one causing trouble :-). That's a good reason for
making the read-from-internal (or read-from-cache) operation
customizable.

> 
> MX35LFxGE4AB
> F50L1G41A
> W25N01GVZEIG
> - fetch to internal: CMD_READ (0x13) + (3 bytes page_id)
> - read from internal: CMD_READ_RDM (0x03) + (2 bytes address) + 1 dummy byte

Hm, I guess those NANDs only have one plane, so it should be compatible
with the MT29Fx logic.

> 
> But you are right. It's time to have an adopted implementation for 
> Micron as proposed by Peter, and we will adapt it later for others.

Ok.