[PATCH 2/2] mtd: spi-nor: fix mr25h* definitions

[Marek Vasut]

On 01/16/2017 04:12 PM, Bastian Stender wrote:
> The previous definitions for mr25h* chips lead to unnecessary limits
> regarding writesize and eraseblocksize for MRAM. MRAM is random access
> memory rather than page, sector, or block organized memory.
> 
> Instead of 1 sector with 512KB the mr25h40 MRAM chip should be defined
> as 512K sectors with 1 byte each. This makes it writesize and
> eraseblocksize aligned and reflects MRAM functionality properly.

Wouldn't this degrade the performance ? ie. if you write the flash, it
will send PP opcode + 1 byte in a loop, right ?

> Signed-off-by: Bastian Stender <bst at pengutronix.de>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index c8399522c69d..6a39b18baa70 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -824,9 +824,9 @@ static const struct flash_info spi_nor_ids[] = {
>  	{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
>  
>  	/* Everspin */
> -	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> -	{ "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> -	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> +	{ "mr25h256", CAT25_INFO(1,  32 * 1024, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> +	{ "mr25h10",  CAT25_INFO(1, 128 * 1024, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
> +	{ "mr25h40",  CAT25_INFO(1, 512 * 1024, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
>  
>  	/* Fujitsu */
>  	{ "mb85rs1mt", INFO(0x047f27, 0, 128 * 1024, 1, SPI_NOR_NO_ERASE) },
> 


-- 
Best regards,
Marek Vasut