[PATCH 10/11] nand: spi: Add generic SPI controller support

[Peter Pan]

Hi Richard,


On Tue, Feb 21, 2017 at 4:03 PM, Richard Weinberger <richard at nod.at> wrote:
> Peter,
>
> Am 21.02.2017 um 09:00 schrieb Peter Pan:
>> This commit supports to use generic spi controller
>> as SPI NAND controller.
>>
>> Signed-off-by: Peter Pan <peterpandong at micron.com>
>
> ...
>
>> +static void spi_nand_mt29f_ecc_status(struct spi_nand_chip *chip,
>> +                                     unsigned int status,
>> +                                     unsigned int *corrected,
>> +                                     unsigned int *ecc_error)
>> +{
>> +     unsigned int ecc_status = status & SPI_NAND_MT29F_ECC_MASK;
>> +
>> +     *ecc_error = (ecc_status == SPI_NAND_MT29F_ECC_UNCORR);
>> +     switch (ecc_status) {
>> +     case SPI_NAND_MT29F_ECC_0_BIT:
>> +             *corrected = 0;
>> +             break;
>> +     case SPI_NAND_MT29F_ECC_1_3_BIT:
>> +             *corrected = 3;
>> +             break;
>> +     case SPI_NAND_MT29F_ECC_4_6_BIT:
>> +             *corrected = 6;
>> +             break;
>> +     case SPI_NAND_MT29F_ECC_7_8_BIT:
>> +             *corrected = 8;
>> +             break;
>> +     }
>> +}
>
> I'm confused. What value will the corrected value be when only 1 bit flipped and got corrected?

According to Micron data sheet, Micron MT29F SPI NAND series only
report 5 level ECC status:
     No errors
     1-3 bit errors detected and corrected
     4-6 bit errors detected and corrected. This indicates data
refreshment might be taken
     7-8 bit errors detected and corrected. This indicates data
refreshment must be taken to guarantee the data retention
     Bit errors greater than 8 bits detected and not corrected

So I report 3 when only 1 bit flipped.

Thanks,
Peter Pan