[BUG] pxa3xx: wait time out when scanning for bb
Sean Nyekjær
sean.nyekjaer at prevas.dk
Mon Dec 11 00:25:45 PST 2017
Hi Miquel,
> Hi Sean,
>
>> Thanks I didn't know about that :-)
>>
>> I had a look at it and I have rebased my stuff on top of your branch.
>> I have edited my devicetree to look like this:
>> &nand_controller {
>> status = "okay";
>> pinctrl-names = "default";
>> pinctrl-0 = <&nand_pins>, <&nand_rb>;
>>
>> nand at 0 {
>> reg = <0>;
>> label = "pxa3xx_nand-0";
>> marvell,rb = <0>;
>> marvell,nand-keep-config;
>> nand-on-flash-bbt;
>> nand-ecc-strength = <4>;
>> nand-ecc-step-size = <512>;
>> };
>> };
>>
>> It produces a lot of bad eraseblocks entrys
>> [ 2.693343] nand: device found, Manufacturer ID: 0x2c, Chip ID:
>> 0xda [ 2.699717] nand: Micron MT29F2G08ABAEAH4
>> [ 2.703772] nand: 256 MiB, SLC, erase size: 128 KiB, page size:
>> 2048, OOB size: 64
>> [ 2.714286] Bad block table not found for chip 0
>> [ 2.721509] Bad block table not found for chip 0
>> [ 2.726139] Scanning device for bad blocks
>> [ 2.730583] Bad eraseblock 0 at 0x000000000000
>> [ 2.735365] Bad eraseblock 1 at 0x000000020000
>> [ 2.740145] Bad eraseblock 2 at 0x000000040000
>> [ 2.744934] Bad eraseblock 3 at 0x000000060000
>> [ 2.749714] Bad eraseblock 4 at 0x000000080000
>>
>> Is my devicetree correct?
> It depends:
> - Did you already use bad block tables before ?
Yes because if I don't i would get the timeouts described in this thread :-)
> - Is your bootloader using 4b/512B ECC strength ?
strength 4, ecc_stepsize 512, page_size 2048 but the uboot driver sets
it to strength 16, ecc_stepsize 512, page_size 2048,
just like the current pxa3xx driver in the kernel does.
>
> Besides:
>
> - What filesystem are you booting? Is it UBIFS or JFFS2 or
> something else?
UBI
> - Did you show the 5 first bad eraseblocks only or all of them?
It continues to count to:
Bad eraseblock 2047 at 0x00000ffe0000
> - Do you have good blocks ?
No
> - Can you make use of the NAND chip after?
No
Correct me if i'm wrong, but i can't find anywhere the
nand-ecc-step-size is read by the new nand driver?
/Sean
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