[PATCH v3] mtd: spi-nor: fix spansion quad enable

[Cyrille Pitchen]

Hi Marek,

Le 25/11/2016 à 15:17, Marek Vasut a écrit :
> On 11/23/2016 12:47 PM, Joël Esponde wrote:
>> With the S25FL127S nor flash part, each writing to the configuration
>> register takes hundreds of ms. During that  time, no more accesses to
>> the flash should be done (even reads).
>>
>> This commit adds a wait loop after the register writing until the flash
>> finishes its work.
>>
>> This issue could make rootfs mounting fail when the latter was done too
>> much closely to this quad enable bit setting step. And in this case, a
>> driver as UBIFS may try to recover the filesystem and may broke it
>> completely.
> 
> Does this apply to all spansion chips or only to selected few ?
>

I've recently faced the very same issue with Winbond memories, which use
the same procedure as Spansion to set the Quad Enable bit.
More precisely, in my case it was some bare metal (bootloader) code but the
issue was the same, there was no polling of busy bit from the Status
Register after having set the QE bit in the Status Register 2 / Control
Register 1. Then the next SPI command came too early and failed because the
memory was actually still busy.

I faced this issue with Winbond W25Q256 and W25M512.

Best regards,

Cyrille

>> Signed-off-by: Joël Esponde <joel.esponde at honeywell.com>
>> ---
>>  drivers/mtd/spi-nor/spi-nor.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
>> index d0fc165..21dde52 100644
>> --- a/drivers/mtd/spi-nor/spi-nor.c
>> +++ b/drivers/mtd/spi-nor/spi-nor.c
>> @@ -1255,6 +1255,13 @@ static int spansion_quad_enable(struct spi_nor *nor)
>>  		return -EINVAL;
>>  	}
>>  
>> +	ret = spi_nor_wait_till_ready(nor);
>> +	if (ret) {
>> +		dev_err(nor->dev,
>> +			"timeout while writing configuration register\n");
>> +		return ret;
>> +	}
>> +
>>  	/* read back and check it */
>>  	ret = read_cr(nor);
>>  	if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
>>
> 
>