Handling soft reset on mt7261 Soc with 32M flash

[Dominik Menke]

Hello list,

I've been redirected here by Mathias Kresin (mkresin; LEDE project) to
ask for comments on how to handle the following situation:

We have a router board using MediaTek's MT7261 SoC with 32M flash memory
(Winbond W25Q256FV [1]). To address >16M, the SPI bus must be configured
to use 4-byte addressing mode. The problem arises after a soft reset,
when the SoC expects the SPI to be in 3-byte addressing mode, but then
can't communicate with the flash memory.

When researching the issue, I've found this [2] mail in the OpenWRT
mailing list archives, describing the problem as

> Paul Fertser on openwrt-devel, 2015-07-08
> 
> Apparently MT7620 can't handle 4 byte addressing mode of the flash
> memory on hardware level so it needs to be reset somehow prior to
> resetting the SoC.

From that mail, I have buthered together a patch [3] which fixes the
problem for my hardware, but it'll most likely not work with other flash
chips (cp. [4]):

> Daniel Golle on commit comment, 2015-11-11
> 
> At least on Macronix SPI chips, using 0x66, 0x99 to reset the chip is
> not nough as that will not clear the adressing-mode bits.
> Using 0xE9 (EX4B; exit 4-byte mode) instead fixes the issue eg. on
> MX25L256.

In another Pull Request [5], introducing a modalias for a Macronix
MX25l25635E flash on the Lenovo Newifi D1 [6], the same reset sequence
appears. Mathias hinted in the PR, that the flash reset sequence should
be executed conditionally, based on the JEDED id (I have not a clue
though, how to do that, to be honest).

How would you proceed?

Thanks for your advice,
Dominik


[1]:
https://www.winbond.com/resource-files/w25q256fv_revg1_120214_qpi_website_rev_g.pdf
[2]:
https://lists.openwrt.org/pipermail/openwrt-devel/2015-July/034153.html
[3]: https://gist.github.com/dmke/d389bc364b3f73f525076eaee0019dc1
[4]: https://patchwork.ozlabs.org/patch/541391/
[5]: https://github.com/lede-project/source/pull/464
[6]: https://wikidevi.com/wiki/Lenovo_Newifi_D1


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