[PATCH 1/2] mtd: spi-nor: disable software protection for Macronix flash at startup

[Cyrille Pitchen]

Hi Matthias,

Le 18/05/2016 15:32, Matthias Schiffer a écrit :
> This patch has been tested in OpenWrt for a few months and seems to work
> correctly.
> 
> Signed-off-by: Felix Fietkau <nbd at nbd.name>
> Signed-off-by: Matthias Schiffer <mschiffer at universe-factory.net>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 157841d..d681003 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1304,6 +1304,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
>  
>  	if (JEDEC_MFR(info) == SNOR_MFR_ATMEL ||
>  	    JEDEC_MFR(info) == SNOR_MFR_INTEL ||
> +	    JEDEC_MFR(info) == SNOR_MFR_MACRONIX ||
>  	    JEDEC_MFR(info) == SNOR_MFR_SST ||
>  	    info->flags & SPI_NOR_HAS_LOCK) {
>  		write_enable(nor);
> 
The line following this patch chunk is "write_sr(nor, 0);" however, if I refer
to the Macronix mx25l25673g datasheet about the Status Register, bits[5:2]
(BP0, BP1, BP2 and BP3) are non-volatile and define the protected area.
Also bit6 (Quad Enable) is also non-volatile and is used to reassign #WP and
#Hold pins to IO2 and IO3 functions needed by Quad SPI protocols on many other
Macronix memories (indeed on the 73g part, the Quad Enable bit is always 1).

So you should not write 0 directly into the Status Register if you only want to
clear bit7 (Status Register Write Disable): use a read, modify, write sequence
instead.


Best regards,

Cyrille