[PATCH 1/3] mtd: mediatek: device tree docs for MTK Smart Device Gen1 NAND

[Boris Brezillon]

Hi Jorge,

On Wed,  2 Mar 2016 12:00:11 -0500
Jorge Ramirez-Ortiz <jorge.ramirez-ortiz at linaro.org> wrote:

> This patch adds documentation support for Smart Device Gen1 type of
> NAND controllers.
> 
> Mediatek's SoC 2701 is one of the SoCs that implements this controller.
> 
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz at linaro.org>
> ---
>  .../devicetree/bindings/mtd/mtksdg1-nand.txt       | 38 ++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
> 
> diff --git a/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
> new file mode 100644
> index 0000000..129d17b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/mtksdg1-nand.txt
> @@ -0,0 +1,38 @@
> +MTK Smart Device SoCs NAND controller DT binding
> +
> +Required properties:
> +- compatible:          Should be "mediatek,mt2701-nfc".
> +- reg:                 The first contains base physical address and size of
> +                       NAND controller's registers. The second contains base
> +                       physical address and size of NAND ECC engine.
> +- interrupts:          the NFC NFI interrupt, and the NFC ECC interrupt
> +- clocks:              NAND controller clocks.
> +- clock-names:         NAND controller clocks internal name.
> +- vmch-supply:         NAND power supply.
> +- #address-cells:      Partition address, should be set 1.
> +- #size-cells:         Partition size, should be set 1.
> +
> +Optional properties:
> +
> +nand-on-flash-bbt:  Use a flash based bad block table.
> +
> +Optional subnodes:
> +- Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
> +
> +Example:
> +
> +	nand: nand at 1100d000 {
> +		compatible = "mediatek,mt2701-nfc";
> +		reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
> +		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
> +			<GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
> +		clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
> +			<&pericfg CLK_PERI_NFI_PAD>;
> +		clock-names = "nfi_ck", "nfi_ecc_ck", "nfi_pad_ck";
> +		vmch-supply = <&mt6323_vmch_reg>;
> +		status = "disabled";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		...
> +	};

We're trying to enforce the NAND controller and NAND chip separation
for all new NAND controller drivers, and representing those 2 elements
in the DT is now the preferred approach.

You can have a look at the sunxi-nand bindings [1].

Thanks,

Boris

[1]http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/mtd/sunxi-nand.txt

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com