[mtd-next:master 30/33] drivers/mtd/spi-nor/cadence-quadspi.c:529:4: error: implicit declaration of function 'readsl'

[kbuild test robot]

tree:   git://git.infradead.org/linux-mtd-next.git master
head:   f78921b9020c510ed222a6c2402e2aa126432415
commit: 140623410536905fa6ab737b625decfde6c64a72 [30/33] mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-6 (Debian 6.1.1-1) 6.1.1 20160430
reproduce:
        git checkout 140623410536905fa6ab737b625decfde6c64a72
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/mtd/spi-nor/cadence-quadspi.c: In function 'cqspi_indirect_read_execute':
>> drivers/mtd/spi-nor/cadence-quadspi.c:529:4: error: implicit declaration of function 'readsl' [-Werror=implicit-function-declaration]
       readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
       ^~~~~~
   drivers/mtd/spi-nor/cadence-quadspi.c: In function 'cqspi_indirect_write_execute':
>> drivers/mtd/spi-nor/cadence-quadspi.c:613:3: error: implicit declaration of function 'writesl' [-Werror=implicit-function-declaration]
      writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
      ^~~~~~~
   cc1: some warnings being treated as errors

vim +/readsl +529 drivers/mtd/spi-nor/cadence-quadspi.c

   523			}
   524	
   525			while (bytes_to_read != 0) {
   526				bytes_to_read *= cqspi->fifo_width;
   527				bytes_to_read = bytes_to_read > remaining ?
   528						remaining : bytes_to_read;
 > 529				readsl(ahb_base, rxbuf, DIV_ROUND_UP(bytes_to_read, 4));
   530				rxbuf += bytes_to_read;
   531				remaining -= bytes_to_read;
   532				bytes_to_read = cqspi_get_rd_sram_level(cqspi);
   533			}
   534	
   535			if (remaining > 0)
   536				reinit_completion(&cqspi->transfer_complete);
   537		}
   538	
   539		/* Check indirect done status */
   540		ret = cqspi_wait_for_bit(reg_base + CQSPI_REG_INDIRECTRD,
   541					 CQSPI_REG_INDIRECTRD_DONE_MASK, 0);
   542		if (ret) {
   543			dev_err(nor->dev,
   544				"Indirect read completion error (%i)\n", ret);
   545			goto failrd;
   546		}
   547	
   548		/* Disable interrupt */
   549		writel(0, reg_base + CQSPI_REG_IRQMASK);
   550	
   551		/* Clear indirect completion status */
   552		writel(CQSPI_REG_INDIRECTRD_DONE_MASK, reg_base + CQSPI_REG_INDIRECTRD);
   553	
   554		return 0;
   555	
   556	failrd:
   557		/* Disable interrupt */
   558		writel(0, reg_base + CQSPI_REG_IRQMASK);
   559	
   560		/* Cancel the indirect read */
   561		writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
   562		       reg_base + CQSPI_REG_INDIRECTRD);
   563		return ret;
   564	}
   565	
   566	static int cqspi_indirect_write_setup(struct spi_nor *nor,
   567					      const unsigned int to_addr)
   568	{
   569		unsigned int reg;
   570		struct cqspi_flash_pdata *f_pdata = nor->priv;
   571		struct cqspi_st *cqspi = f_pdata->cqspi;
   572		void __iomem *reg_base = cqspi->iobase;
   573	
   574		/* Set opcode. */
   575		reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
   576		writel(reg, reg_base + CQSPI_REG_WR_INSTR);
   577		reg = cqspi_calc_rdreg(nor, nor->program_opcode);
   578		writel(reg, reg_base + CQSPI_REG_RD_INSTR);
   579	
   580		writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
   581	
   582		reg = readl(reg_base + CQSPI_REG_SIZE);
   583		reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
   584		reg |= (nor->addr_width - 1);
   585		writel(reg, reg_base + CQSPI_REG_SIZE);
   586		return 0;
   587	}
   588	
   589	static int cqspi_indirect_write_execute(struct spi_nor *nor,
   590						const u8 *txbuf, const unsigned n_tx)
   591	{
   592		const unsigned int page_size = nor->page_size;
   593		struct cqspi_flash_pdata *f_pdata = nor->priv;
   594		struct cqspi_st *cqspi = f_pdata->cqspi;
   595		void __iomem *reg_base = cqspi->iobase;
   596		unsigned int remaining = n_tx;
   597		unsigned int write_bytes;
   598		int ret;
   599	
   600		writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
   601	
   602		/* Clear all interrupts. */
   603		writel(CQSPI_IRQ_STATUS_MASK, reg_base + CQSPI_REG_IRQSTATUS);
   604	
   605		writel(CQSPI_IRQ_MASK_WR, reg_base + CQSPI_REG_IRQMASK);
   606	
   607		reinit_completion(&cqspi->transfer_complete);
   608		writel(CQSPI_REG_INDIRECTWR_START_MASK,
   609		       reg_base + CQSPI_REG_INDIRECTWR);
   610	
   611		while (remaining > 0) {
   612			write_bytes = remaining > page_size ? page_size : remaining;
 > 613			writesl(cqspi->ahb_base, txbuf, DIV_ROUND_UP(write_bytes, 4));
   614	
   615			ret = wait_for_completion_timeout(&cqspi->transfer_complete,
   616							  msecs_to_jiffies

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