[PATCH v2] mtd: spi-nor: add hisilicon spi-nor flash controller driver

Rob Herring robh at kernel.org
Sat Jan 9 07:42:49 PST 2016


On Fri, Jan 08, 2016 at 09:26:45AM +0800, Jiancheng Xue wrote:
> add hisilicon spi-nor flash controller driver
> 
> Signed-off-by: Binquan Peng <pengbinquan at huawei.com>
> Signed-off-by: Jiancheng Xue <xuejiancheng at huawei.com>
> ---

Next time, please include changes in v2 here.

>  .../devicetree/bindings/spi/spi-hisi-sfc.txt       |  24 +
>  drivers/mtd/spi-nor/Kconfig                        |   6 +
>  drivers/mtd/spi-nor/Makefile                       |   1 +
>  drivers/mtd/spi-nor/hisi-sfc.c                     | 498 +++++++++++++++++++++
>  4 files changed, 529 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt
>  create mode 100644 drivers/mtd/spi-nor/hisi-sfc.c
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt
> new file mode 100644
> index 0000000..a0d1e04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt
> @@ -0,0 +1,24 @@
> +HiSilicon SPI-NOR Flash Controller
> +
> +Required properties:
> +- compatible : Should be "hisilicon,hisi-sfc".

I missed this last time, but you also need a more specific compatible 
string with the SOC name in it.

> +- address-cells : number of cells required to define a chip select
> +        address on the SPI bus. Should be set to 1. See spi-bus.txt.
> +- size-cells : Should be 0.
> +- reg : Offset and length of the register set for the controller device.
> +- reg-names : Must include the following two entries: "control", "memory".
> +- clocks : handle to spi-nor flash controller clock.
> +
> +Example:
> +spi-nor-controller at 10000000 {
> +	compatible = "hisilicon,hisi-sfc";
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
> +	reg-names = "control", "memory";
> +	clocks = <&clock HI3519_FMC_CLK>;
> +	spi-nor at 0 {
> +		compatible = "jedec,spi-nor";
> +		reg = <0>;
> +	};
> +};



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