[PATCH v3 2/5] mtd: aspeed: add memory controllers for the Aspeed AST2400 SoC

[Cédric Le Goater]

On 12/10/2016 05:03 AM, Marek Vasut wrote:
>> +/*
>> + * The AST2400 SPI flash controller does not have a CE Control
>> + * register. It uses the CE0 control register to set 4Byte mode at the
>> + * controller level.
>> + */
>> +static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip)
>> +{
>> +	chip->ctl_val[smc_base] |= CONTROL_IO_ADDRESS_4B;
>> +	chip->ctl_val[smc_read] |= CONTROL_IO_ADDRESS_4B;
> How do you know the SPI NOR is in 4B mode ?

in aspeed_smc_chip_setup_finish() :

	if (chip->nor.addr_width == 4 && info->set_4b)
		info->set_4b(chip);

C.

 
>> +}
>> +
>>  static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip,
>>  				      struct resource *res)
>>  {
>>