[LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq MPSoC GQSPI controller

[Ranjit Abhimanyu Waghmode]

Hi Marek,

> -----Original Message-----
> From: Marek Vasut [mailto:marex at denx.de]
> Sent: Wednesday, August 26, 2015 12:26 PM
> To: Ranjit Abhimanyu Waghmode
> Cc: dwmw2 at infradead.org; computersforpeace at gmail.com;
> broonie at kernel.org; Michal Simek; Soren Brinkmann; zajec5 at gmail.com;
> ben at decadent.org.uk; b32955 at freescale.com; knut.wohlrab at de.bosch.com;
> juhosg at openwrt.org; beanhuo at micron.com; linux-mtd at lists.infradead.org;
> linux-kernel at vger.kernel.org; linux-spi at vger.kernel.org; linux-arm-
> kernel at lists.infradead.org; Harini Katakam; Punnaiah Choudary Kalluri
> Subject: Re: [LINUX RFC v2 0/4] spi: add dual parallel mode support in Zynq
> MPSoC GQSPI controller
> 
> On Wednesday, August 26, 2015 at 08:26:03 AM, Ranjit Waghmode wrote:
> > This series adds dual parallel mode support for Zynq Ultrascale+ MPSoC
> > GQSPI controller driver.
> >
> > What is dual parallel mode?
> > ---------------------------
> > ZynqMP GQSPI controller supports Dual Parallel mode with following
> > functionalities: 1) Supporting two SPI flash memories operating in
> > parallel. 8 I/O lines. 2) Chip selects and clock are shared to both
> > the flash devices
> > 3) This mode is targeted for faster read/write speed and also doubles
> > the size 4) Commands/data can be transmitted/received from both the
> > devices(mirror), or only upper or only lower flash memory devices.
> > 5) Data arrangement:
> >    With stripe enabled,
> >    Even bytes i.e. 0, 2, 4,... are transmitted on Lower Data Bus
> >    Odd bytes i.e. 1, 3, 5,.. are transmitted on Upper Data Bus.
> 
> This might be a dumb question, but why don't you just treat this as an SPI NOR
> flash with 8-bit bus ?

In case of dual parallel configuration of this controller there are different modes like single, dual and quad mode.
Whatever you are suggesting would fit only in the case of Quad mode operation as both buses would have 4 lines each.
In case of single mode of parallel configuration, there would be two buses; but the line on each bus would one. So altogether there will be two lines.
And in case of dual mode of parallel configuration each bus will be having two lines. So altogether 4 lines will be there.
So keeping 8 lines would not support above two modes of parallel configuration correctly.

Logically it is a single flash with 8 IO lines but physically it's a two flash devices and each has 4 IO lines. 
So, in this case, read and write addresses should be always even and minimum data that can be accessed is 2 bytes.

Regards,
Ranjit

> 
> Best regards,
> Marek Vasut