MTD challenge for new generation nand

[Bean Huo 霍斌斌 (beanhuo)]

Hi,
I have some questions about MTD supports for new generation MTD, wanting for your 
Help.
1. single chip over 4GB density 
With the development of storage and requirement from customer, the latest new generation 
NANA density will more and more, such as 64Gb, 128Gb. From our latest Linux kernel, seems that 
Maximum single chip density supported is 32Gb, am I right ? 

2. NVDDR (sync mode ) and NVDDR2 interface mode support
We all know , we all use Async (SDR) mode for Linux, under Async mode , read data and ECC just as below:

static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
			      uint8_t *buf, int oob_required, int page)
{
	chip->read_buf(mtd, buf, mtd->writesize);
	if (oob_required)
		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
	return 0;
}

We read data and OOB separately, for Async mode , this is right.
But for NVDDR(sync) or NVDDR2, it does not make sense.
They must read together. If split two steps to read separately, 
First read is ok, but for second read, there will skip several bytes data
At the beginning of data buffer. I mean, under NVDDR mode (sync) , between
the first read and second read time slot, NAND still output data, but at this moment,
host not read, so for second read, there will skip several bytes data.
Am I right ?  

--Bean Huo