RFC: detect and manage power cut on MLC NAND

[Andrea Marson]

> Disturb is a block level affect, as long as partition A and B are in different blocks there will be no disturb between them.   Disturbs, does not damage cells; ERASE returns cells to undisturbed levels.
I think there are two options here: MTD partitioning and UBI 
partitioning. AFAIK one should prefer UBI partitioning to preserve 
device-wide wear leveling. Boris, am I right?

> Officially I would say don't use SLC emulation, but technically I know what your doing.   The reason I say no is because we have very precise recipes designed to create very tight distibutions, and although the first pass distributions might look like an SLC, they are really designed with the expectation of the upper page being programmed.  Not a true SLC.
> With MLC lithography of 25 nm and less  the difference between each level (L0, L1, L2 and L3) is just a few 10's of electrons.  The distribution have to be very tight, in order to meet retention requirements.
This is quite interesting, however I'm afraid I have not fully 
understood it. Let me try to rephrase it. Please correct me if I'm wrong.

1) Technically speaking, it is possible to use an MLC memory in SLC 
mode, even if this is not recommended because MLC is not designed for 
this usage.

2) As indicated by Boris, the easiest way to implement this thing is to 
avoid the use of paired pages, according to paired page table provided 
by datasheet.

3) This technique does not transform an MLC NAND to an SLC magically. 
Thus data retention and lifetime are not increased. However all paired 
pages issues disappear. It is not clear if there are further drawbacks 
that reduce flash reliability if used this way.

Thank you,
Andrea