RFC: detect and manage power cut on MLC NAND

[Boris Brezillon]

Hi Andrea,

I'll let Jeff answer this question, but I'd like to share my
understanding.

On Tue, 17 Mar 2015 10:30:30 +0100
Andrea Scian <rnd4 at dave-tech.it> wrote:

> 
> 
> Dear Jeff,
> 
> Il 16/03/2015 22:11, Jeff Lauruhn (jlauruhn) ha scritto:
> > Good morning Boris;
> > RR is a new feature and not available on all parts few.  I'm not sure 
> > about others, but since these are features, you simply enable of 
> > disable via SET FEATURE/GET FEATURE.  If you already provide that 
> > SET/GET FEATURE functionality then an end-user determine if their 
> > device supports a feature and then write the code to enable when they 
> > need it on their particular design.
> 
> I can confirm this. In fact I'm currently working with two Micron NAND:
> 
> MT29F32G08CBACAWP
> MT29F32G08CBADAWP
> 
> The latter should be "just" a newer die revision of the former (at
> least, this is what our distributor says)
> 
> There's a technology change between the two and, in fact, the latter
> supports RR while there's no mention of such a feature inside rev C.
> 
> Jeff, could you please help me in understanding which if the following
> sentences are true and which are false?
> - rev D is more "robust" than rev C because it has RR (so an additional
> feature that improve error correction)
> - rev D is "robust" like rev C, if rev D is used with RR
> - if RR is not used rev D is more error prone than rev C

RR shouldn't change NAND robustness (or sensitivity to read/write
disturbance generating bitflips).

AFAIU RR will help you improve your NAND lifetime, because you're
allowed to change voltage thresholds which means you can fix errors
that were previously considered as unfixable and lead to blocks being
marked bad earlier.

I'll let Jeff correct me if I'm wrong ;-).

> 
> I think this is crucial to understand how RR works and how much is
> needed inside MTD/UBI code.

Hopefully this can all be handled in the MTD layer, with some help
from the UBI layer to feed the wear information (number of P/E cycles
on each block).

Best Regards,

Boris

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com