NAND/GPMC bus arbitration and MTD/OTP access

[Yani Dubin]

Hi,

I have a NAND driver question I was hoping someone could shed some light on
- it touches on the area of mtd, and I gather this is where the expertise
in such areas lies?

We have an extended NAND driver which adds OTP functionality (which works),
and I now want to determine whether this is robust. We access OTP functions
directly at the NAND driver level via sysfs (read, write, set page
number/offset), rather than coming through the mtd layer.

These (legacy) functions do not put the device into an exclusive OTP mode
(which would alter the semantics of read/write while active and hence would
require an exclusive lock).

We are using a TI Sitara AM3352 (OMAP) processor via its GPMC module,
connected to a parallel 8-bit Micron NAND (MT29F8G08ADBDAH4), with the
Linux-3.14.29ltsi kernel.

While I have locking around the OTP functions
(nand_chip.controller.lock/wq), other requests will be coming in via the
mtd layer.

The bus is driven using hwcontrol, and the command sequences look like:
Drive CLE (command byte 1 sets operation)
Drive ALE (5 cycles to set page row/col address)
[if write operation] write data to bus
Drive CLE (command byte 2 begins read or write)
[if read operation] poll gpmc status register for ready, then read data
from bus
[if write operation] poll gpmc status register for completion

How does bus arbitration work with a NAND device? What (if anything)
ensures the whole operation completes, preventing some other read/write
request coming in (say between first/last CLE) and using the bus?

Is there something at a lower level (perhaps by the GPMC peripheral), or
does this tend to be handled at the higher level (mtd layer)? I couldn't
see any code polling the gpmc register prior to starting a read/write in
the standard read/write functions (omap2-nand - ioread8_rep/iowrite8).

I'm new to this area, so if someone could provide some pointers /
explanation, this would be greatly appreciated.

Regards,
Yani.

-- 
Yani Dubin
Senior Design Engineer
Tait Communications
DDI: +64-3-357-1565
Email: yani.dubin at taitradio.com


www.taitradio.com

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