[PATCH 1/5 v1] mtd: spi-nor: fsl-quadspi: Add a variable in 'fsl_qspi_devtype_data' to enable platform specail feature

[Haikun Wang]

Add a variable in struct fsl_qspi_devtype_data.
Add big endian registers flag.
Enable big endian registers flag for LS1021A.

Signed-off-by: Haikun Wang <haikun.wang at freescale.com>
---
 drivers/mtd/spi-nor/fsl-quadspi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index 6cd14e4..40c7953 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -191,6 +191,9 @@
 #define SEQID_EN4B		10
 #define SEQID_BRWR		11
 
+/* Controller needs swap endian when access registers */
+#define QUADSPI_QUIRK_REGMAP_BE    (1 << 5)
+
 enum fsl_qspi_devtype {
 	FSL_QUADSPI_VYBRID,
 	FSL_QUADSPI_IMX6SX,
@@ -202,6 +205,7 @@ struct fsl_qspi_devtype_data {
 	int rxfifo;
 	int txfifo;
 	int ahb_buf_size;
+	int driver_data;
 };
 
 static struct fsl_qspi_devtype_data vybrid_data = {
@@ -222,7 +226,8 @@ static struct fsl_qspi_devtype_data ls1_data = {
 	.devtype = FSL_QUADSPI_LS1,
 	.rxfifo = 128,
 	.txfifo = 64,
-	.ahb_buf_size = 1024
+	.ahb_buf_size = 1024,
+	.driver_data = QUADSPI_QUIRK_REGMAP_BE
 };
 
 #define FSL_QSPI_MAX_CHIP	4
-- 
2.1.0.27.g96db324