[PATCH 5/8 v5] mtd: spi-nor: fsl-quadspi: Enable support big endian registers

[Haikun Wang]

QSPI registers are big endian on LS1021A.
This patch check endianness before accessing register and
swap the data if QSPI register is big endian.

Signed-off-by: Haikun Wang <haikun.wang at freescale.com>
---
Changes in v5:
- Rebase with l2-mtd.git

Changes in v4:
- Split into three patches:
 1. mtd: spi-nor: fsl-quadspi: Add a variable in struct fsl_qspi_devtype_data to specify platform specail feature
 2. mtd: spi-nor: fsl-quadspi: Wrap writel/readl with qspi_writel/qspi_readl
 3. mtd: spi-nor: fsl-quadspi: Enable support big endian registers

Changes in v3:
- Rebase with l2-mtd.git

Changes in v2:
- Fix compile issue

 drivers/mtd/spi-nor/fsl-quadspi.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
index ec23a74..283e157 100644
--- a/drivers/mtd/spi-nor/fsl-quadspi.c
+++ b/drivers/mtd/spi-nor/fsl-quadspi.c
@@ -262,12 +262,14 @@ static inline int is_imx6sx_qspi(struct fsl_qspi *q)
 
 static void qspi_writel(struct fsl_qspi *q, u32 val, void __iomem *addr)
 {
-	writel(val, addr);
+	q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		writel(cpu_to_be32(val), addr) : writel(val, addr);
 }
 
 static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
 {
-	return	readl(addr);
+	return q->devtype_data->driver_data & QUADSPI_QUIRK_REGMAP_BE ?
+		cpu_to_be32(readl(addr)) : readl(addr);
 }
 
 /*
-- 
2.1.0.27.g96db324