NAND ECC capabilities

[Steve deRosier]

On Thu, Jan 8, 2015 at 8:38 AM, Jeff Lauruhn (jlauruhn)
<jlauruhn at micron.com> wrote:
> You might find this interesting http://www.cyclicdesign.com/index.php/ecc-trends-in-nand-flash.
>
>

Jeff,

Thanks for that.  The diagram on page 7 actually illustrates exactly
what I was getting at.  In my case, the ECC can handle 4-bits on each
512 sector, yet since the increment we handle in the higher levels is
per-page, we really need to set the threshold at a max of 4 (probably
3 as Richard points out) for the page.

- Steve