[PATCH v4 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining
computersforpeace at gmail.com
Sat Feb 28 01:01:22 PST 2015
On Wed, Feb 18, 2015 at 11:32:07AM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> However, during a read PIO access, the datasheet specifies that after each 32
> bytes read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
> Cc: <stable at vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>
Pushed this one to linux-mtd.git. I'll try to get it out in the 4.0
cycle. I assume patch 2 (the DT addition) will go through arm-soc.
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