[PATCH v2 1/2] mtd: nand: pxa3xx: Fix PIO FIFO draining

Maxime Ripard maxime.ripard at free-electrons.com
Wed Feb 4 01:13:17 PST 2015

Hi Brian,

On Mon, Jan 26, 2015 at 03:56:03PM +0100, Maxime Ripard wrote:
> The NDDB register holds the data that are needed by the read and write
> commands.
> However, during a read PIO access, the datasheet specifies that after each 32
> bits read in that register, when BCH is enabled, we have to make sure that the
> RDDREQ bit is set in the NDSR register.
> This fixes an issue that was seen on the Armada 385, and presumably other mvebu
> SoCs, when a read on a newly erased page would end up in the driver reporting a
> timeout from the NAND.
> Cc: <stable at vger.kernel.org> # v3.14
> Signed-off-by: Maxime Ripard <maxime.ripard at free-electrons.com>

Any chance for this fix to come in 3.19?


Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
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