[PATCH V7 1/2] mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver.

[Vikas MANOCHA]

Hi,



> On Aug 20, 2015, at 10:20 PM, Marek Vasut <marex at denx.de> wrote:
> 
>> On Thursday, August 20, 2015 at 06:06:49 PM, vikas wrote:
>> Hi,
> 
> Hi!
> 
> [...]
> 
>>>>> It's the location of the SRAM fifo.  Also direct mode location I think,
>>>>> if that were ever used.
>>>> 
>>>> Hmm...It is the base address of NOR flash. SRAM is not memory mapped.
>>> 
>>> Huh ? I am inclined to trust Graham more -- I have seen memory mapped
>>> SRAM, but I have yet to see memory mapped SPI NOR.
>> 
>> Well, SPI NOR flash in SOCs normally is memory mapped.
> 
> I'm afraid you have some very disturbed views of how SPI NORs are operated
> most of the time.

Just wondering what should I say, hoping you will sit back and try to correct your views.

> No, SPI NOR is most often hanging off of some sort of SPI
> controller just like any other SPI device. It is definitelly not common for
> a SPI NOR to be memory mapped.

Definitely ? And what made you think like this ? Do you even know the spi peripheral you are sending patch for has memory mapped nor flash ?

> 
>> To give some mainline examples, all Spear family SOCs (spear300, 320, 1310,
>> 1340).
> 
> That's an exception, not a rule :)

And there are many such exceptions starting from this cadence qspi :-)

> 
>>> Also, the driver code clearly
>>> uses that area in a way one would use a memory mapped SRAM with FIFO on
>>> the other side. I think the above description is pretty much OK.
>> 
>> that is the purpose of making NOR flash memory mapped.
> 
> I'm not sure if you agree with me or not anymore. I am pretty sure the 
> discussion went quite far for such a trivial matter though.

I definitely disagree with you.
I stop here now.

Cheers,
Vikas

> 
>>>>> The size is determined by a configuration parameter during system
>>>>> design.  On Altera Cyclone5 the size is really big compared to SRAM
>>>>> fifo.  I don't know why, maybe some hw engineer thought it would be
>>>>> better to have a large size in case direct mode was used.
>>>> 
>>>> my comment is about second parameter of property "reg" which is NOR
>>>> flash address, so above explanation does not make sense for it.
>>>> Also in direct mode, sram does not come into play.
>>> 
>>> This is absolutelly not a SPI NOR address.
>> 
>> Then i can only suggest to check out the controller literature.
>> 
>> Think like this : what is the purpose of SRAM in all this flash access
>> business, It can work without SRAM also, the only purpose of sram (& in
>> fact indirect mode) is to access data from flash memory without AHB access
>> to trigger it. Once the data is available in SRAM(in case of read), AHB
>> Master can access it with low letency. Same is true for writes. SRAM is
>> integral internal part of state machine in case of indirect mode, there is
>> no need for it to memory mapped. If the controller does not support
>> indirect mode, there is no need of sram in the system.
>> 
>> Hope it is little bit more clear.
> 
> It is, I understand what you're trying to convey now.
> 
> Yes, this register area can be used in certain modes of the controller in
> such a way that it presents a window of the SPI NOR, which can be directly
> accessed.
> 
> This register area can also be used as a FIFO, which is the way we used this
> area in the driver . We read/write the first four bytes when communicating
> with the flash.
> 
> So I don't really see a problem with calling the second register a "Controller
> data area", that's what the IP documentation also calls it.