i.MX25 NFC with 8 bit ecc strength

[Ricard Wanderlof]

On Mon, 20 Apr 2015, Baruch Siach wrote:

> On Mon, Apr 20, 2015 at 02:19:43PM +0200, Ricard Wanderlof wrote:
> > On Mon, 20 Apr 2015, Baruch Siach wrote:
> > > I'm trying to get nand_ecclayout right on i.MX25 with the Micron 
> > > MT29F8G08ABABA (page size: 4096, oob size: 224). The large OOB size allows 
> > > using hardware ecc strength of 8bit per ecc step (512 bytes). The mxc_nand 
> > > driver code (get_eccsize()) and the reference manual seems to indicate 
> > > that enabling 8 bit ecc mode requires 26 oob bytes per ecc step.
> > 
> > Note sure if these really is relevant to this thread, but using BCH, 8 bit 
> > error correction per 512 byte ECC step requires 13 bytes of ECC codes per 
> > ECC step. (Depending on other factors, this will actually fit nicely even 
> > in a 64 byte OOB).
> 
> The i.MX25 NFC hardware uses Reed-Solomon ECC, according to the documentation, 
> and needs 18 ECC bytes per 512 step. But even with 13 bytes per step, you'll 
> need at least 104 (13*8) OOB bytes for a 4K page.

Yes, you are right, sorry, my mind is firmly fixed on 2k pages.

Interesting that they use Reed-Solomon coding. I thought everyone used BCH 
(which is better suited to the random distribution of error bits that NAND 
flashes exhibit, whereas Reed-Solomon is better suited to an error bit 
distribution where the errors come in clusters, like when reading a CD or 
DVD, IIUC).

/Ricard
-- 
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30