i.MX25 NFC with 8 bit ecc strength

[Baruch Siach]

Hi Shawn, Sascha, all,

I'm trying to get nand_ecclayout right on i.MX25 with the Micron 
MT29F8G08ABABA (page size: 4096, oob size: 224). The large OOB size allows 
using hardware ecc strength of 8bit per ecc step (512 bytes). The mxc_nand 
driver code (get_eccsize()) and the reference manual seems to indicate that 
enabling 8 bit ecc mode requires 26 oob bytes per ecc step. However, this 
seems to contradict the actual hardware test as the shown in the dump below of 
a zero filled page + oob:

# hexdump -C dump4
00000000  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00001000  ff ff ff ff ff ff ff 91  c4 45 be 32 45 6f 5d b1  |.........E.2Eo].|
00001010  b1 b9 13 61 59 7d 42 58  eb ff ff ff ff ff ff ff  |...aY}BX........|
00001020  ff ff ff 91 c4 45 be 32  45 6f 5d b1 b1 b9 13 61  |.....E.2Eo]....a|
00001030  59 7d 42 58 eb ff ff ff  ff ff ff ff ff ff ff 91  |Y}BX............|
00001040  c4 45 be 32 45 6f 5d b1  b1 b9 13 61 59 7d 42 58  |.E.2Eo]....aY}BX|
00001050  eb ff ff ff ff ff ff ff  ff ff ff 91 c4 45 be 32  |.............E.2|
00001060  45 6f 5d b1 b1 b9 13 61  59 7d 42 58 eb ff ff ff  |Eo]....aY}BX....|
00001070  ff ff ff ff ff ff ff 91  c4 45 be 32 45 6f 5d b1  |.........E.2Eo].|
00001080  b1 b9 13 61 59 7d 42 58  eb ff ff ff ff ff ff ff  |...aY}BX........|
00001090  ff ff ff 91 c4 45 be 32  45 6f 5d b1 b1 b9 13 61  |.....E.2Eo]....a|
000010a0  59 7d 42 58 eb ff ff ff  ff ff ff ff ff ff ff 91  |Y}BX............|
000010b0  c4 45 be 32 45 6f 5d b1  b1 b9 13 61 59 7d 42 58  |.E.2Eo]....aY}BX|
000010c0  eb ff ff ff ff ff ff ff  ff ff ff 91 c4 45 be 32  |.............E.2|
000010d0  45 6f 5d b1 b1 b9 13 61  59 7d 42 58 eb ff ff ff  |Eo]....aY}BX....|

As you can easily see, ecc steps start at 28 bytes interval, with 18 bytes for 
ecc (matches documentation), and 10 bytes free.

So who should I believe? Has anyone ever tried using 8 bit ecc mode with any 
variant of the i.MX NFC?

Thanks,
baruch

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