[PATCH 0/2] staging: mtd: Support for GigaDevice SPI NAND flash

[bpqw]

Hi Brian, Arnaud:
> If we are going to a specific spinand framework, my advice would be to 
> read again the spi nor framework carefully first, and do something 
> similar (especially for latests work on quad spi)

I think above idea is good. 
SPI NAND interface and command protocol are similar with SPI NOR, we can 
create a SPI NAND folder with similar framework with SPI NOR. But need to duplicate 
nand_bbt and nand_bch code into this folder due to SPI NAND still need BBM and ECC.
How do you think?

I ever compared the SPI NAND command protocol with different vendor, result is same
with Ionela's answer.  

" As far as I've seen from the datasheets I have available (SPI NAND
GigaDevice 1Gb/2Gb/4Gb, Micron 1Gb/2Gb/4Gb), the command sequencing
is the same for read/write/erase operations (read: enable ECC, read to cache,
wait, read from cache, check for errors, disable ECC; write: enable ECC,
write enable, program load, program execute, wait, verify, disable ECC;
erase: write enable, erase block, verify).

Regarding the stream of bytes for each command, the problematic
commands are the read from cache ones (read, fast read, read x2,
read x4, read dual read quad) that have different command format
(additional dummy bytes, a plane select bit to be set).
Other differences are in the structure of the protection and status registers
(some of them use more ECC and protection bits according to the size
of the chip). Also, each has a different ECC layout "

If you need my detail comparison table, please let me know.

I already set up platform to support SPI NAND now, if you think the framework I mentioned 
above is reasonable, I can start to work on this.

Thanks

Qi Wang