[PATCH 01/47] ARM: sti: Add BCH (NAND Flash) Controller support for STiH41x (Orly) SoCs

[Lee Jones]

Provide device information and flash layout for the NAND Micron
MT29F8G08ABABAWP chip found on the STM B2020 Development Board.

Signed-off-by: Lee Jones <lee.jones at linaro.org>
---
 arch/arm/boot/dts/stih41x-b2020.dtsi | 39 ++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index bc5818d..0fdeb44 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -52,5 +52,44 @@
 			pinctrl-0	= <&pinctrl_rgmii1>;
 		};
 
+		nandbch: nand-bch {
+			compatible = "st,nand-bch";
+			reg = <0xfe901000 0x1000>, <0xfef00800 0x0800>;
+			reg-names = "nand_mem", "nand_dma";
+			interrupts = <0 139 0x0>;
+			interrupt-names = "nand_irq";
+			st,nand-banks = <&nand_banks>;
+
+			status = "okay";
+		};
+
+		nand_banks: nand-banks {
+			/*
+			 * Micron MT29F8G08ABABAWP:
+			 *  - Size = 8Gib(1GiB); Page = 4096+224; Block = 512KiB
+			 *  - ECC = 4-bit/540B min
+			 *  - ONFI 2.1 (timing parameters retrieved during probe)
+			 */
+			bank0 {
+				nand-on-flash-bbt;
+				st,nand-csn		= <0>;
+				st,nand-timing-relax	= <0>;
+
+				partitions {
+					#address-cells	= <1>;
+					#size-cells	= <1>;
+					partition at 0 {
+						/* 8MB */
+						label = "NAND Flash 1";
+						reg = <0x00000000 0x00800000>;
+					};
+					partition at 800000 {
+						/* 1GB - 8MB */
+						label = "NAND Flash 2";
+						reg = <0x00800000 0x1F000000>;
+					};
+				};
+			};
+		};
 	};
 };
-- 
1.8.3.2