[PATCH v1 1/3] ARM: dts: am335x-bone: add support for beaglebone NAND cape

[Tony Lindgren]

* Gupta, Pekon <pekon at ti.com> [140627 14:08]:
> >From: Guido Martínez [mailto:guido at vanguardiasur.com.ar]
> >>On Tue, Jun 24, 2014 at 05:54:24PM +0530, Pekon Gupta wrote:
> 
> [...]
> 
> >> +&gpmc {
> >> +	ranges = <0 0 0 0x01000000>;	/* address range = 16MB (minimum GPMC partition) */
> >> +	nand at 0,0 {
> >> +		status = "disabled";
> >> +		reg = <0 0 4>;		/* device IO registers */
> >> +		pinctrl-names = "default";
> >> +		pinctrl-0 = <&bbcape_nand_flash_pins>;
> >This doesn't seem to work as pinctrl properties are not parsed for
> >childs of the gpmc node. Did this work for you?
> >Putting this in the gpmc node makes it work, but how will we control
> >pins for the nand and nor independently? I believe there is currently no
> >support for muxing individual gpmc devices. If we want to add both
> >devices to the DT and enable them as needed we'd need to add support for
> >this, right?
> >
> Yes, And that should be the case, because different devices would be
> connected to different chip-selects, so there should be support of
> providing individual pin-mux for different GPMC devices.
> 
> Currently both NAND and NOR cape share GPMC_CS0, so both NAND and NOR
> capes will not work simultaneously. But I'm planning to modify NOR cape
> hardware at my end to use GPMC_CS1 instead of GPMC_CS0.
> - NAND on GPMC_CS0
> - NOR on GPMC_CS1

Hmm but we should have these working with both using CS0 without
any need to modify the hardware though?

In that case we should make sure we always set large enough GPMC
partition and that the pins are muxed for the connected GPMC
devices only.

Regards,

Tony