[PATCH v3 0/2] Add NAND ECC devicetree binding

[Ezequiel Garcia]

Third round, fixing a stupid semi-colon miss.

NAND controllers have special ECC modes, raising per-driver ECC mode devicetree
binding. See for instance the binding for OMAP:

 - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
	"sw"		<deprecated> use "ham1" instead
	"hw"		<deprecated> use "ham1" instead
	"hw-romcode"	<deprecated> use "ham1" instead
	"ham1"		1-bit Hamming ecc code
	"bch4"		4-bit BCH ecc code
	"bch8"		8-bit BCH ecc code

Other drivers (such as pxa3xx-nand) have similar requirements, with special
(controller-specific) ECC modes. Instead of adding a possibly different
binding per compatible-string, let's add generic ECC strength and ECC step size.

This properties aim at providing a complete description of the required ECC
correction to let drivers choose the appropriate ECC mode.

Changes from v2:

  * Added a missing semi-colon.

Changes from v1:

  * Improve the binding documentation, as per Brian Norris' suggestions.

  * Added the helper functions.

Ezequiel Garcia (2):
  of_mtd: Add helpers to get ECC strength and ECC step size
  mtd: nand: Add a devicetree binding for ECC strength and ECC step size

 Documentation/devicetree/bindings/mtd/nand.txt | 14 +++++++++++
 drivers/of/of_mtd.c                            | 34 ++++++++++++++++++++++++++
 include/linux/of_mtd.h                         | 12 +++++++++
 3 files changed, 60 insertions(+)

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1.8.1.5