[PATCH] nand: add Types of controllers from ECC point of view

[Oleksij Rempel]

it is mostly copy&paste of Boris Brezillons answer on linux-mtd list.

Signed-off-by: Oleksij Rempel <linux at rempel-privat.de>
---
 doc/nand.xml | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/doc/nand.xml b/doc/nand.xml
index 281e0e0..197241c 100644
--- a/doc/nand.xml
+++ b/doc/nand.xml
@@ -113,6 +113,21 @@ protection or connected to VCC to enable writes unconditionally. As NAND flash u
 a command driven programming and erasing, an  accidental write or erase is not 
 likely to happen. The Ready / Busy output is not necessary for operation, 
  but it can be tied to a GPIO or an interrupt line. </p>
+
+<h3>Types of controllers from ECC point of view</h3>
+<p>1) Wiser controllers are generating 0xff ECC bytes for a data chunk
+(chunk == ECC step size) filled with 0xff. With BCH algorithms this is
+easily done by XORing the ECC bytes with the appropriate pattern (see
+soft BCH implementation)</p>
+<p>2) Some controller just verify if the data chunk + ECC bytes are all
+0xff before passing it to the ECC engine. If they are filled with 0xff
+the ECC correction is bypassed.</p>
+<p>This method has one drawback: it does not properly handle bitflips
+occurring in erased pages (if one bitflip occurs the NAND controller
+consider the chunk as not empty, and pass it to the BCH engine).</p>
+<p>3) The controller does not handle erased pages at all, and in this case
+you'll have to manually test it (see is_buf_blank in drivers/mtd/nand/pxa3xx_nand.c) when you
+encounter an ECC error.</p>
 </div>
 	
 <hr size="2" />
-- 
1.9.1