[PATCH RFC 1/3] Devicetree: Add pl353 smc controller devicetree binding information

[punnaiah choudary kalluri]

On Fri, Mar 28, 2014 at 3:13 PM, punnaiah choudary kalluri
<kalluripunnaiahchoudary at gmail.com> wrote:
> On Fri, Mar 28, 2014 at 2:28 PM, Gupta, Pekon <pekon at ti.com> wrote:
>>>From: Punnaiah Choudary Kalluri [mailto:punnaiah.choudary.kalluri at xilinx.com]
>>>
>>>Add pl353 static memory controller devicetree binding information.
>>>
>>>Signed-off-by: Punnaiah Choudary Kalluri <punnaia at xilinx.com>
>>>---
>>> .../bindings/memory-controllers/pl353-smc.txt      |   53 ++++++++++++++++++++
>>> 1 files changed, 53 insertions(+), 0 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
>>>
>>>diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt b/Documentation/devicetree/bindings/memory-
>>>controllers/pl353-smc.txt
>>>new file mode 100644
>>>index 0000000..623c1c6
>>>--- /dev/null
>>>+++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
>>>@@ -0,0 +1,53 @@
>>>+Device tree bindings for ARM PL353 static memory controller
>>>+
>>>+PL353 static memory controller supports two kinds of memory
>>>+interfaces.i.e NAND and SRAM/NOR interfaces.
>>>+The actual devices are instantiated from the child nodes of pl353 smc node.
>>>+
>>>+Required properties:
>>>+- compatible          : Should be "arm,pl353-smc-r2p1"
>>>+- reg                 : Controller registers map and length.
>>>+- clock-names         : List of input clock names - "ref_clk", "aper_clk"
>>>+                        (See clock bindings for details).
>>>+- clocks              : Clock phandles (see clock bindings for details).
>>>+- address-cells       : Address cells, must be 1.
>>>+- size-cells          : Size cells. Must be 1.
>>>+
>>>+Child nodes:
>>>+ For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
>>>+supported as child nodes.
>>>+
>>>+Mandatory timing properties for child nodes:
>>>+- arm,nand-cycle-t0   : Read cycle time(t_rc).
>>>+- arm,nand-cycle-t1   : Write cycle time(t_wc).
>>>+- arm,nand-cycle-t2   : re_n assertion delay(t_rea).
>>>+- arm,nand-cycle-t3   : we_n de-assertion delay(t_wp).
>>>+- arm,nand-cycle-t4   : Status read time(t_clr)
>>>+- arm,nand-cycle-t5   : ID read time(t_ar)
>>>+- arm,nand-cycle-t6   : busy to re_n(t_rr)
>>>+
>>
>> It would be good to have DT-bindings with meaningful names,
>> and suffixed with timing units like "ns" | "ps".
>
> Ok.  I will add this information.
>
>> Also, as many of these timing parameters are common across NAND device
>> vendors, so why not get them added to  generic NAND bindings list.
>>         Documentation/devicetree/bindings/mtd/nand.txt
>>
>
> Let me check on this and I will get back to you.

Ok. I think the timing parameters defined in ONFI-1.0 spec can be added to the
generic NAND binding list. So that the NAND controllers which have provision for
configuring any of these timing parameters can use the generic binding info
for accessing the NAND device.

I will update accordingly and send v2 patches soon.

Punnaiah
>
> Punnaiah
>
>> Another driver using similar bindings for NAND device timings
>>         [RFC 13/47] mtd: nand: stm_nand_bch: provide Device Tree support
>>         http://lists.infradead.org/pipermail/linux-mtd/2014-March/052890.html
>>
>>
>> with regards, pekon