[PATCH v4 02/12] mtd: nand: rename the cellinfo to bits_per_cell

[Brian Norris]

On Wed, Sep 25, 2013 at 02:58:11PM +0800, Huang Shijie wrote:
> The @cellinfo fields contains unused information, such as write caching,
> internal chip numbering, etc. But we only use it to check the SLC or MLC.
> 
> This patch tries to make it more clear and simple, renames the @cellinfo
> to @bits_per_cell.
> 
> In order to avoiding the bisect issue, this patch also does the following
> changes:
>   (0) add a macro NAND_CI_CELLTYPE_SHIFT to avoid the hardcode.
> 
>   (1) add a helper to parse out the cell type : nand_get_bits_per_cell()
> 
>   (2) parse out the cell type for extended-ID chips and the full-id nand chips.
> 
> Signed-off-by: Huang Shijie <b32955 at freescale.com>
> ---
>  drivers/mtd/nand/nand_base.c |   14 ++++++++++++--
>  include/linux/mtd/nand.h     |    7 ++++---
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 5c05bab..0eb4a63 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -477,7 +478,7 @@ struct nand_buffers {
>   * @badblockbits:	[INTERN] minimum number of set bits in a good block's
>   *			bad block marker position; i.e., BBM == 11110111b is
>   *			not bad when badblockbits == 7
> - * @cellinfo:		[INTERN] MLC/multichip data from chip ident
> + * @bits_per_cell:	[INTERN] the bits of per cell. i.e., 1 means SLC.

s/bits of/number of bits/

>   * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
>   *			Minimum amount of bit errors per @ecc_step_ds guaranteed
>   *			to be correctable. If unknown, set to zero.

I'll squash that change into the patch myself if the rest looks good.

Brian