Page corruption when writing non-sequential pages in an MLC NAND eraseblock

[Avery Pennarun]

On Wed, Oct 2, 2013 at 12:58 AM, Ricard Wanderlof
<ricard.wanderlof at axis.com> wrote:
> On Wed, 2 Oct 2013, Avery Pennarun wrote:
>> Steps:
>> - Disable ECC to avoid any confusion (ECC turns out to not affect the
>> test results, but I wanted to make sure)
>> - Erase any eraseblock
>> - Write all-zeroes to page 0x18 of that eraseblock; read it back -> ok
>> - Write all-zeroes to page 0x12 of that eraseblock; read it back ->
>> FAIL, all 0xff instead
>> - Read page 0x18 -> completely random data (about 12% of bits are flipped)
>
> Not much help, but AFAIU, you can get so-called 'write disturb' when writing
> to the other page in a pair, even without power failure during the write.
> But to my mind, 12% flipped bits sounds very excessive. I don't have any
> experience with MLC though.
>
> Instictively it sounds like there is some other mechanism causing problems,
> for instance if mtd does the write to the pages in two goes, rather than in
> one write, as I think MLC in general can only accept one write operation per
> page, in contrast to SLC where it is legal to write the main and oob data at
> different times (normally 2 or 3 writes per page is legal, after that the
> page must be erased or the data can not be considered stable).

Thanks Ricard.  Based on this suggestion, I added some trace printk's
to the nand driver and did find that it was writing the data, then the
oob, for each page.  So I commented out all the code that writes to
the oob (since I have ECC disabled anyhow for this test).  The traces
now show just two 4096-byte page writes.  But the problem still
occurs.  So I think that rules out this theory, unless I missed some
ways the nand can be written.

Note that I was slightly mistaken earlier: the number of flipped bits
seems to sometimes be 12%, sometimes 25%.  It's a little suspicious
that this is almostly exactly 1/8 and 1/4 respectively.