Page corruption when writing non-sequential pages in an MLC NAND eraseblock

[Avery Pennarun]

On Wed, Oct 2, 2013 at 3:18 AM, Romain Izard <romain.izard.pro at gmail.com> wrote:
> On 2013-10-01, Avery Pennarun <apenwarr at gmail.com> wrote:
>> Steps:
>> - Disable ECC to avoid any confusion (ECC turns out to not affect the
>> test results, but I wanted to make sure)
>> - Erase any eraseblock
>> - Write all-zeroes to page 0x18 of that eraseblock; read it back -> ok
>> - Write all-zeroes to page 0x12 of that eraseblock; read it back ->
>> FAIL, all 0xff instead
>> - Read page 0x18 -> completely random data (about 12% of bits are flipped)
>
> For me you're violating one key MLC assumption: the pages within a block
> must be written in a strictly increasing order. It should be written
> somewhere in the component's datasheet.

Hmm.  I haven't heard of this constraint, but it certainly seems to be
happening in this case (although in fact random-access writes *mostly*
work other than this pairing effect, so it seems like they intended it
to work properly).

This makes /dev/mtdblock completely unusable as it reorders writes.
Is /dev/mtdblock known to not work with MLC chips?

Thanks,

Avery