on-die ECC support

[David Mosberger-Tang]

We need to be able to support 4-bit-correcting ECC with a
micro-controller that doesn't have hardware-support for that.  We are
planning to use the on-die ECC controller supported by Micron flash
chips.  I suppose we could use the BCH swecc support in the Linux
kernel, but I'm concerned about the performance implication of that
and we'd also have to add BCH ecc to our bootloader, which would mean
more development and testing.

For backwards-compatibility, we need to be able to support a
subpage-size of 512 bytes.  From the Micron data sheets, it's not
clear to me whether the on-die controller really supports reading 512
byte subpages but the attached patch certainly *seems* to work fine so
far.

I'd love to get some feedback as to whether I'm on the right track
here or whether I should pursue a different path.  The patch does the
following:

 - Add NAND_ECC_HW_ON_DIE ecc mode
 - Add nand_read_subpage_raw() to read a subpage without worrying about ECC
 - Hack atmel_nand.c to use on-die ECC.

Thanks,

  --david
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