Coping with multibit ECC flashes in UBI

[Ricard Wanderlof]

There have been SLC NAND flashes around for a while which according to 
their data sheets require 4 or even 8 bit ECC (usually BCH). Traditionally 
this was only the case for MLC NAND, with SLC only requiring single-bit 
ECC (Hamming), and even then, bit flips were very rare.

For flashes that require multibit ECC, it's common to have single bits 
which flip fairly quickly after having been written. Thus, the current 
scheme in UBI of rewriting a flash block when an 'ECC corrected' status 
has been returned during a read would quickly wear out certain blocks.

I seem to recall there being a discussion like a year ago about 
introducing a threshold for the number of corrected bits in a page before 
the containing block was rewritten, but I don't know what became of that. 
Anyone who was more involved remember more?

(I was going to search the list archives, but at least the page 
http://lists.infradead.org/pipermail/linux-mtd/ has no search function).

/Ricard
-- 
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30