[PATCH V2 2/2] MTD: MIPS: lantiq: Add NAND support on Lantiq XWAY SoC.

[David Woodhouse]

On Thu, 2012-08-23 at 20:28 +0200, John Crispin wrote:
> 
> +       /* finish with a reset */
> +       spin_lock_irqsave(&ebu_lock, flags);
> +       writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
> +       while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
> +               ;
> +       spin_unlock_irqrestore(&ebu_lock, flags); 

Disable IRQs, spin forever waiting for hardware.

However much you trust the hardware, you should *never* do this.
Implement a timeout of some kind, please.

You do it again in xway_cmd_ctrl().

I've merged the original patch from l2-mtd.git but please send me a
fix...

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation


-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120929/825d78ba/attachment.bin>