[PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1

[Vikram Narayanan]

Hello Huang Shijie,

<Dropped Cc's>

On 9/12/2012 7:45 AM, Huang Shijie wrote:
> 于 2012年09月12日 02:00, Vikram Narayanan 写道:
>> Hello Huang Shijie,
>>
>> On 9/11/2012 11:47 AM, Huang Shijie wrote:
>>> The gpmi_nfc_compute_hardware_timing{} should contains all the
>>> fields setting for gpmi timing registers. It already contains the fields
>>> for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
>>>
>>> So it is better to add a new field setting for HW_GPMI_TIMING1 in
>>> this data structure. This makes the code more clear in logic.
>>>
>>> This patch also changes some comments to make the code more readable.
>>>
>>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>>> ---
>>> drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 17 +++++++++--------
>>> drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 9 +++++++++
>>> drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 3 +++
>>> 3 files changed, 21 insertions(+), 8 deletions(-)
>>>
<snip>
>>> + /* [1] Set HW_GPMI_TIMING0 */
>>> reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
>>> BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
>>> BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
>>>
>>> writel(reg, gpmi_regs + HW_GPMI_TIMING0);
>>>
>>> - /*
>>> - * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
>>> - */
>>> + /* [2] Set HW_GPMI_TIMING1 */
>>> + writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
>>> + gpmi_regs + HW_GPMI_TIMING1);
>>> +
>>> + /* [3] The following code is to set the HW_GPMI_CTRL1. */
>>> +
>>> + /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or
>>> HALF_PERIOD. */
>>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>>
>>
>> Are these [1], [2], [3] notation references to some other comments?
> no.
>
> These notations just help to comment the steps of setting timing registers.
> Are you confused at this?

Not much. But this is the notation usually used for references. you can 
keep this as it is. Not an issue.

Regards,
Vikram