From Julia.Lawall at lip6.fr  Sat Sep  1 12:33:10 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sat,  1 Sep 2012 18:33:10 +0200
Subject: [PATCH 4/4] drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
In-Reply-To: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

devm free functions should not have to be explicitly used.

The only thing left that is useful in the function mpc5121_nfc_free is the
call to clk_disable, which is moved to the call sites.

This function also incorrectly called iounmap on devm_ioremap allocated
data.

Use devm_request_and_ioremap in place of devm_request_mem_region and
devm_ioremap.

Use devm_clk_get.

A semantic match that finds the first problem is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
@@

(
* devm_kfree(...);
|
* devm_free_irq(...);
|
* devm_iounmap(...);
|
* devm_release_region(...);
|
* devm_release_mem_region(...);
)
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
 drivers/mtd/nand/mpc5121_nfc.c |   35 +++++------------------------------
 1 file changed, 5 insertions(+), 30 deletions(-)

diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
index c259c24..45183ba 100644
--- a/drivers/mtd/nand/mpc5121_nfc.c
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -632,21 +632,6 @@ out:
 	return ret;
 }
 
-/* Free driver resources */
-static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
-{
-	struct nand_chip *chip = mtd->priv;
-	struct mpc5121_nfc_prv *prv = chip->priv;
-
-	if (prv->clk) {
-		clk_disable(prv->clk);
-		clk_put(prv->clk);
-	}
-
-	if (prv->csreg)
-		iounmap(prv->csreg);
-}
-
 static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 {
 	struct device_node *rootnode, *dn = op->dev.of_node;
@@ -713,12 +698,7 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	regs_paddr = res.start;
 	regs_size = resource_size(&res);
 
-	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
-		dev_err(dev, "Error requesting memory region!\n");
-		return -EBUSY;
-	}
-
-	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
+	prv->regs = devm_request_and_ioremap(dev, &res);
 	if (!prv->regs) {
 		dev_err(dev, "Error mapping memory region!\n");
 		return -ENOMEM;
@@ -752,11 +732,10 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	of_node_put(rootnode);
 
 	/* Enable NFC clock */
-	prv->clk = clk_get(dev, "nfc_clk");
+	prv->clk = devm_clk_get(dev, "nfc_clk");
 	if (IS_ERR(prv->clk)) {
 		dev_err(dev, "Unable to acquire NFC clock!\n");
-		retval = PTR_ERR(prv->clk);
-		goto error;
+		return PTR_ERR(prv->clk);
 	}
 
 	clk_enable(prv->clk);
@@ -803,7 +782,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	/* Detect NAND chips */
 	if (nand_scan(mtd, be32_to_cpup(chips_no))) {
 		dev_err(dev, "NAND Flash not found !\n");
-		devm_free_irq(dev, prv->irq, mtd);
 		retval = -ENXIO;
 		goto error;
 	}
@@ -828,7 +806,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 
 	default:
 		dev_err(dev, "Unsupported NAND flash!\n");
-		devm_free_irq(dev, prv->irq, mtd);
 		retval = -ENXIO;
 		goto error;
 	}
@@ -839,13 +816,12 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
 	retval = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
 	if (retval) {
 		dev_err(dev, "Error adding MTD device!\n");
-		devm_free_irq(dev, prv->irq, mtd);
 		goto error;
 	}
 
 	return 0;
 error:
-	mpc5121_nfc_free(dev, mtd);
+	clk_disable(prv->clk);
 	return retval;
 }
 
@@ -857,8 +833,7 @@ static int __devexit mpc5121_nfc_remove(struct platform_device *op)
 	struct mpc5121_nfc_prv *prv = chip->priv;
 
 	nand_release(mtd);
-	devm_free_irq(dev, prv->irq, mtd);
-	mpc5121_nfc_free(dev, mtd);
+	clk_disable(prv->clk);
 
 	return 0;
 }



From Julia.Lawall at lip6.fr  Sat Sep  1 12:33:11 2012
From: Julia.Lawall at lip6.fr (Julia Lawall)
Date: Sat,  1 Sep 2012 18:33:11 +0200
Subject: [PATCH 3/4] drivers/mtd/maps/autcpu12-nvram.c: drop frees of devm_
 alloc'd data
In-Reply-To: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1346517191-8794-5-git-send-email-Julia.Lawall@lip6.fr>

From: Julia Lawall <Julia.Lawall at lip6.fr>

devm free functions should not have to be explicitly used.

A semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
@@

(
* devm_kfree(...);
|
* devm_free_irq(...);
|
* devm_iounmap(...);
|
* devm_release_region(...);
|
* devm_release_mem_region(...);
)
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>

---
 drivers/mtd/maps/autcpu12-nvram.c |   18 ++++--------------
 1 file changed, 4 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/maps/autcpu12-nvram.c b/drivers/mtd/maps/autcpu12-nvram.c
index ef420d9..76fb594 100644
--- a/drivers/mtd/maps/autcpu12-nvram.c
+++ b/drivers/mtd/maps/autcpu12-nvram.c
@@ -38,7 +38,6 @@ static int __devinit autcpu12_nvram_probe(struct platform_device *pdev)
 	map_word tmp, save0, save1;
 	struct resource *res;
 	struct autcpu12_nvram_priv *priv;
-	int err;
 
 	priv = devm_kzalloc(&pdev->dev,
 			    sizeof(struct autcpu12_nvram_priv), GFP_KERNEL);
@@ -50,8 +49,7 @@ static int __devinit autcpu12_nvram_probe(struct platform_device *pdev)
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "failed to get memory resource\n");
-		err = -ENOENT;
-		goto out;
+		return -ENOENT;
 	}
 
 	priv->map.bankwidth	= 4;
@@ -61,8 +59,7 @@ static int __devinit autcpu12_nvram_probe(struct platform_device *pdev)
 	strcpy((char *)priv->map.name, res->name);
 	if (!priv->map.virt) {
 		dev_err(&pdev->dev, "failed to remap mem resource\n");
-		err = -EBUSY;
-		goto out;
+		return -EBUSY;
 	}
 
 	simple_map_init(&priv->map);
@@ -90,8 +87,7 @@ static int __devinit autcpu12_nvram_probe(struct platform_device *pdev)
 	priv->mtd = do_map_probe("map_ram", &priv->map);
 	if (!priv->mtd) {
 		dev_err(&pdev->dev, "probing failed\n");
-		err = -ENXIO;
-		goto out;
+		return -ENXIO;
 	}
 
 	priv->mtd->owner	= THIS_MODULE;
@@ -106,12 +102,7 @@ static int __devinit autcpu12_nvram_probe(struct platform_device *pdev)
 
 	map_destroy(priv->mtd);
 	dev_err(&pdev->dev, "NV-RAM device addition failed\n");
-	err = -ENOMEM;
-
-out:
-	devm_kfree(&pdev->dev, priv);
-
-	return err;
+	return -ENOMEM;
 }
 
 static int __devexit autcpu12_nvram_remove(struct platform_device *pdev)
@@ -120,7 +111,6 @@ static int __devexit autcpu12_nvram_remove(struct platform_device *pdev)
 
 	mtd_device_unregister(priv->mtd);
 	map_destroy(priv->mtd);
-	devm_kfree(&pdev->dev, priv);
 
 	return 0;
 }



From snijsure at grid-net.com  Sun Sep  2 01:19:25 2012
From: snijsure at grid-net.com (Subodh Nijsure)
Date: Sat, 1 Sep 2012 22:19:25 -0700
Subject: RCU warning during UBI file system mount
Message-ID: <5042EC5D.1010207@grid-net.com>

Hello,

I am running 3.6-rc4 kernel on my MX28 based board and every time I 
mount UBI file system I see following warning.
Anybody else seen this errors, particularly those running it on MXS 
platform?

I haven't debugged RCU warnings before any clues as to what is the 
source of this warning is, should I be looking at 
start_dma_without_bch_irq() code? Would appreciate any pointers in 
fixing this...

[    4.280000] WARNING: at /opt/git/kernel-mainline/kernel/rcutiny.c:75 
rcu_idle_enter_common.clone.7+0x90/0xac()
[    4.280000] Current pid: 1 comm: swapper / Idle pid: 0 comm: swapper
[    4.280000] Modules linked in:
[    4.280000] [<c0014eec>] (unwind_backtrace+0x0/0x130) from 
[<c001dd94>] (warn_slowpath_common+0x4c/0x64)
[    4.280000] [<c001dd94>] (warn_slowpath_common+0x4c/0x64) from 
[<c001de40>] (warn_slowpath_fmt+0x30/0x40)
[    4.280000] [<c001de40>] (warn_slowpath_fmt+0x30/0x40) from 
[<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
[    4.280000] [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac) 
from [<c0061670>] (rcu_irq_exit+0x3c/0x78)
[    4.280000] [<c0061670>] (rcu_irq_exit+0x3c/0x78) from [<c000fe90>] 
(handle_IRQ+0x34/0x84)
[    4.280000] [<c000fe90>] (handle_IRQ+0x34/0x84) from [<c000ec34>] 
(__irq_svc+0x34/0x58)
[    4.280000] [<c000ec34>] (__irq_svc+0x34/0x58) from [<c0394c4c>] 
(schedule_timeout+0xdc/0x16c)
[    4.280000] [<c0394c4c>] (schedule_timeout+0xdc/0x16c) from 
[<c0395f34>] (wait_for_common+0xb4/0x160)
[    4.280000] [<c0395f34>] (wait_for_common+0xb4/0x160) from 
[<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8)
[    4.280000] [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8) from 
[<c0258660>] (gpmi_send_command+0x120/0x154)
[    4.280000] [<c0258660>] (gpmi_send_command+0x120/0x154) from 
[<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c)
[    4.280000] [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c) from [<c024f8e0>] 
(nand_command_lp+0xe8/0x270)
[    4.280000] [<c024f8e0>] (nand_command_lp+0xe8/0x270) from 
[<c0251e00>] (nand_do_read_ops+0x124/0x444)
[    4.280000] [<c0251e00>] (nand_do_read_ops+0x124/0x444) from 
[<c0252558>] (nand_read+0x54/0x78)
[    4.280000] [<c0252558>] (nand_read+0x54/0x78) from [<c02499a4>] 
(part_read+0x48/0x80)
[    4.280000] [<c02499a4>] (part_read+0x48/0x80) from [<c0246910>] 
(mtd_read+0x88/0xb4)
[    4.280000] [<c0246910>] (mtd_read+0x88/0xb4) from [<c026b188>] 
(ubi_io_read+0xb0/0x3e8)
[    4.280000] [<c026b188>] (ubi_io_read+0xb0/0x3e8) from [<c026740c>] 
(ubi_eba_read_leb+0x198/0x4bc)
[    4.280000] [<c026740c>] (ubi_eba_read_leb+0x198/0x4bc) from 
[<c0266800>] (ubi_leb_read+0xf4/0x16c)
[    4.280000] [<c0266800>] (ubi_leb_read+0xf4/0x16c) from [<c0155550>] 
(ubifs_leb_read+0x24/0x88)
[    4.280000] [<c0155550>] (ubifs_leb_read+0x24/0x88) from [<c01572f8>] 
(ubifs_read_node+0xa8/0x2e4)
[    4.280000] [<c01572f8>] (ubifs_read_node+0xa8/0x2e4) from 
[<c0153c50>] (ubifs_read_sb_node+0x54/0x78)
[    4.280000] [<c0153c50>] (ubifs_read_sb_node+0x54/0x78) from 
[<c0154940>] (ubifs_read_superblock+0xc8c/0x133c)
[    4.280000] [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c) from 
[<c01520ac>] (ubifs_mount+0x73c/0x1bc0)
[    4.280000] [<c01520ac>] (ubifs_mount+0x73c/0x1bc0) from [<c00a49ec>] 
(mount_fs+0x44/0x184)
[    4.280000] [<c00a49ec>] (mount_fs+0x44/0x184) from [<c00baf90>] 
(vfs_kern_mount+0x4c/0xc0)
[    4.280000] [<c00baf90>] (vfs_kern_mount+0x4c/0xc0) from [<c00bb1a0>] 
(do_kern_mount+0x34/0xd0)
[    4.280000] [<c00bb1a0>] (do_kern_mount+0x34/0xd0) from [<c00bc93c>] 
(do_mount+0x15c/0x73c)
[    4.280000] [<c00bc93c>] (do_mount+0x15c/0x73c) from [<c00bcfa0>] 
(sys_mount+0x84/0xc4)
[    4.280000] [<c00bcfa0>] (sys_mount+0x84/0xc4) from [<c04e4a04>] 
(do_mount_root+0x24/0xb0)
[    4.280000] [<c04e4a04>] (do_mount_root+0x24/0xb0) from [<c04e4b78>] 
(mount_block_root+0xe8/0x214)
[    4.280000] [<c04e4b78>] (mount_block_root+0xe8/0x214) from 
[<c04e4e28>] (prepare_namespace+0x8c/0x180)
[    4.280000] [<c04e4e28>] (prepare_namespace+0x8c/0x180) from 
[<c04e4894>] (kernel_init+0x16c/0x1b4)
[    4.280000] [<c04e4894>] (kernel_init+0x16c/0x1b4) from [<c000ff70>] 
(kernel_thread_exit+0x0/0x8)
[    4.280000] ---[ end trace 4d36b722759fdc4f ]---
[    4.950000] UBIFS DBG (pid 58): ubifs_bg_thread: background thread 
"ubifs_bgt0_0" started, PID 58

-Subodh


From dedekind1 at gmail.com  Sun Sep  2 06:54:14 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun,  2 Sep 2012 13:54:14 +0300
Subject: [PATCH] mtd: cmdlinepart: revise error handling
Message-ID: <1346583254-9190-1-git-send-email-dedekind1@gmail.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

This patch revises and fixes error handling in the command line mtd
partitions parser. Namely:
1. we ignored return code of 'mtdpart_setup_real()'.
2. instead of returning 0 for failure and 1 for success, teach
   'mtdpart_setup_real()' to return real error codes.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/cmdlinepart.c | 31 +++++++++++++++++--------------
 1 file changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index b4faca2..5bddecf 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -110,7 +110,7 @@ static struct mtd_partition * newpart(char *s,
 		if (size < PAGE_SIZE)
 		{
 			printk(KERN_ERR ERRP "partition size too small (%lx)\n", size);
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 	}
 
@@ -138,7 +138,7 @@ static struct mtd_partition * newpart(char *s,
 		if (!p)
 		{
 			printk(KERN_ERR ERRP "no closing %c found in partition name\n", delim);
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 		name_len = p - name;
 		s = p + 1;
@@ -172,13 +172,13 @@ static struct mtd_partition * newpart(char *s,
 		if (size == SIZE_REMAINING)
 		{
 			printk(KERN_ERR ERRP "no partitions allowed after a fill-up partition\n");
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 		/* more partitions follow, parse them */
 		parts = newpart(s + 1, &s, num_parts, this_part + 1,
 				&extra_mem, extra_mem_size);
-		if (!parts)
-			return NULL;
+		if (IS_ERR(parts))
+			return parts;
 	}
 	else
 	{	/* this is the last partition: allocate space for all */
@@ -189,7 +189,7 @@ static struct mtd_partition * newpart(char *s,
 			     extra_mem_size;
 		parts = kzalloc(alloc_size, GFP_KERNEL);
 		if (!parts)
-			return NULL;
+			return PTR_ERR(-ENOMEM);
 		extra_mem = (unsigned char *)(parts + *num_parts);
 	}
 	/* enter this partition (offset will be calculated later if it is zero at this point) */
@@ -245,7 +245,7 @@ static int mtdpart_setup_real(char *s)
 		if (!(p = strchr(s, ':')))
 		{
 			printk(KERN_ERR ERRP "no mtd-id\n");
-			return 0;
+			return -EINVAL;
 		}
 		mtd_id_len = p - mtd_id;
 
@@ -262,7 +262,7 @@ static int mtdpart_setup_real(char *s)
 				(unsigned char**)&this_mtd, /* out: extra mem */
 				mtd_id_len + 1 + sizeof(*this_mtd) +
 				sizeof(void*)-1 /*alignment*/);
-		if(!parts)
+		if(IS_ERR(parts))
 		{
 			/*
 			 * An error occurred. We're either:
@@ -271,7 +271,7 @@ static int mtdpart_setup_real(char *s)
 			 * Either way, this mtd is hosed and we're
 			 * unlikely to succeed in parsing any more
 			 */
-			 return 0;
+			 return ERR_PTR(parts);
 		 }
 
 		/* align this_mtd */
@@ -299,11 +299,11 @@ static int mtdpart_setup_real(char *s)
 		if (*s != ';')
 		{
 			printk(KERN_ERR ERRP "bad character after partition (%c)\n", *s);
-			return 0;
+			return -EINVAL;
 		}
 		s++;
 	}
-	return 1;
+	return 0;
 }
 
 /*
@@ -318,13 +318,16 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 				    struct mtd_part_parser_data *data)
 {
 	unsigned long offset;
-	int i;
+	int i, err;
 	struct cmdline_mtd_partition *part;
 	const char *mtd_id = master->name;
 
 	/* parse command line */
-	if (!cmdline_parsed)
-		mtdpart_setup_real(cmdline);
+	if (!cmdline_parsed) {
+		err = mtdpart_setup_real(cmdline);
+		if (err)
+			return err;
+	}
 
 	for(part = partitions; part; part = part->next)
 	{
-- 
1.7.11.4



From dedekind1 at gmail.com  Sun Sep  2 06:56:42 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 02 Sep 2012 13:56:42 +0300
Subject: [PATCH v2] mtd: cmdlinepart: fix the wrong check condition
In-Reply-To: <20120825123149.3fafa4f4@halley>
References: <1345925210-7500-1-git-send-email-shijie8@gmail.com>
 <20120825123149.3fafa4f4@halley>
Message-ID: <1346583402.2533.0.camel@kyv>

On Sat, 2012-08-25 at 12:31 +0300, Shmulik Ladkani wrote:
> Hi Huang, Artem,
> 
> On Sat, 25 Aug 2012 16:06:50 -0400 Huang Shijie <shijie8 at gmail.com> wrote:
> > diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
> > index fc960a3..216d751 100644
> > --- a/drivers/mtd/cmdlinepart.c
> > +++ b/drivers/mtd/cmdlinepart.c
> > @@ -322,13 +322,16 @@ static int parse_cmdline_partitions(struct mtd_info *master,
> >  	struct cmdline_mtd_partition *part;
> >  	const char *mtd_id = master->name;
> >  
> > +	if (!mtd_id)
> > +		return 0;
> > +
> >  	/* parse command line */
> >  	if (!cmdline_parsed)
> >  		mtdpart_setup_real(cmdline);
> >  
> >  	for(part = partitions; part; part = part->next)
> >  	{
> > -		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id)))
> > +		if (!strcmp(part->mtd_id, mtd_id))
> >  		{
> >  			for(i = 0, offset = 0; i < part->num_parts; i++)
> >  			{
> 
> This changes the behavior of cmdling parsing, which might affect users
> expecting the old behavior.

Yes, you are right, we should not change the mtd_id hack unless we have
checked all the users.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120902/5fe1e8a2/attachment.sig>

From dedekind1 at gmail.com  Sun Sep  2 06:57:47 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 02 Sep 2012 13:57:47 +0300
Subject: FW: UBIFS tools and latest 2.6.33 kernel from
 http://git.infradead.org/users/dedekind/ubifs-v2.6.33.git
In-Reply-To: <CAN8TOE8j9gxpXAmL51gqaW8=TFLQLPhp03inryx_-uZv4901Ng@mail.gmail.com>
References: <886EEBE3AFFFB144AA8169C199AB4E6AA7BC4D5FB8@BBMBX.backbone.local>
 <1346416026.9709.47.camel@sauron.fi.intel.com>
 <CAN8TOE8j9gxpXAmL51gqaW8=TFLQLPhp03inryx_-uZv4901Ng@mail.gmail.com>
Message-ID: <1346583467.2533.1.camel@kyv>

On Fri, 2012-08-31 at 15:18 -0700, Brian Norris wrote:
> There was a series of 'writebufsize' fixes that may be missing from
> multiple backport trees. I can help you track them down, if you'd like
> the help.

Sure, go ahead, I can them put them to the backport trees.
-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120902/9a174c5e/attachment-0001.sig>

From computersforpeace at gmail.com  Mon Sep  3 02:05:37 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Sun, 02 Sep 2012 23:05:37 -0700
Subject: FW: UBIFS tools and latest 2.6.33 kernel from
 http://git.infradead.org/users/dedekind/ubifs-v2.6.33.git
In-Reply-To: <1346583467.2533.1.camel@kyv>
References: <886EEBE3AFFFB144AA8169C199AB4E6AA7BC4D5FB8@BBMBX.backbone.local>
 <1346416026.9709.47.camel@sauron.fi.intel.com>
 <CAN8TOE8j9gxpXAmL51gqaW8=TFLQLPhp03inryx_-uZv4901Ng@mail.gmail.com>
 <1346583467.2533.1.camel@kyv>
Message-ID: <504448B1.4050205@gmail.com>

On 09/02/2012 03:57 AM, Artem Bityutskiy wrote:
> On Fri, 2012-08-31 at 15:18 -0700, Brian Norris wrote:
>> There was a series of 'writebufsize' fixes that may be missing from
>> multiple backport trees. I can help you track them down, if you'd like
>> the help.
>
> Sure, go ahead, I can them put them to the backport trees.

OK, I just put up my own github backport tree, with branches for v2.6.32 
through v3.3. I think your v3.4+ repos are fine. URL:

   git://github.com/computersforpeace/UBIFS-backports.git
   https://github.com/computersforpeace/UBIFS-backports.git

Branches:

   ubifs-v2.6.32
   ubifs-v2.6.33
   ubifs-v2.6.34
   ubifs-v2.6.35
   ubifs-v2.6.36
   ubifs-v2.6.37
   ubifs-v2.6.38
   ubifs-v2.6.39
   ubifs-v3.0
   ubifs-v3.1
   ubifs-v3.2
   ubifs-v3.3

Each branch should have some version (amended when necessary) of the 
following commits. Note that docg3 wasn't merged until v3.2. Also, 
spear_smi wasn't merged until v3.4 and was already fixed in the 
appropriate backports, so it is omitted from this list.

Brian

---

[ In 'git log' order ]

commit c4cc625ea5958d065c21cc0fcea29e9ed8f3d2bc
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 10:16:50 2012 +0200

     mtd: sst25l: initialize writebufsize

commit fcc44a07dae0af16e84e93425fc8afe642ddc603
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:53:28 2012 +0200

     mtd: lart: initialize writebufsize

commit 82c4c58d6f1a78e8de875272a19ab9220b8066aa
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:44:32 2012 +0200

     mtd: docg3: initialize writebufsize

commit 71f60fbebf0f18dd4e855335a009efda251b1697
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:43:14 2012 +0200

     mtd: doc2001plus: initialize writebufsize

commit cca84b569ebe3372b28949e00b0a3a17f87e2970
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:42:39 2012 +0200

     mtd: doc2001: initialize writebufsize

commit cd1986a3c111f7ed597619705290fa52a975014f
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:38:43 2012 +0200

     mtd: doc2000: initialize writebufsize

commit b604387411ec6a072e95910099262616edd2bd2f
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Fri Feb 3 09:32:44 2012 +0200

     mtd: block2mtd: initialize writebufsize

commit b54f47c8bcfc5f766bf13ec31bd7dd1d4726d33b
Author: Brian Norris <computersforpeace at gmail.com>
Date:   Tue Jan 31 00:06:03 2012 -0800

     mtd: m25p80: set writebufsize



From dedekind1 at gmail.com  Mon Sep  3 03:18:21 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 10:18:21 +0300
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
Message-ID: <1346656701.3061.8.camel@sauron.fi.intel.com>

On Sun, 2012-08-26 at 13:21 -0400, Huang Shijie wrote:
> + *
> + * Note:
> + * If you choose to set the @offset for the <partdef>, please set all
> + * the partitions with the same syntax, such as:
> + *     gpmi-nand:100m at 0(boot),100m at 100m(kernel),1g at 200m(rootfs)
> + *
> + * Please do _NOT_ set the partitions like this:
> + *     gpmi-nand:100m at 0(boot),100m(kernel),1g at 200m(rootfs)
> + * The `kernel` partition does not set with the @offset, this is not permitted.
>   */

I guess it is indeed OK to sort the partitions, just makes things a lot
simpler. But we probably then should also do the following:

1. Make sure there is only one partition without offset. If there are
several - error out.
2. Check that partitions do not intersect - I did not notice that we do
this in the code.

So AFAICS, this patch is not needed and we better have the following
patches:

1. Add sorting
2. Add a check that partitions do not overlap and there is only one
offset-less partition.

How does this sound?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/116a1487/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 03:21:03 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 10:21:03 +0300
Subject: [PATCH 2/3] mtd: cmdlinepart: sort the unsorted partitions
In-Reply-To: <1346001700-26895-2-git-send-email-shijie8@gmail.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346001700-26895-2-git-send-email-shijie8@gmail.com>
Message-ID: <1346656863.3061.11.camel@sauron.fi.intel.com>

On Sun, 2012-08-26 at 13:21 -0400, Huang Shijie wrote:
> +/* There are only several partitions, so the Bubble sort is enough. */
> +static inline void sort_partitons(struct mtd_partition *parts, int num_parts)
> +{
> +	int i, j;
> +
> +	if (num_parts < 2)
> +		return;

Not necessary, the for loop should work for this case.
> +
> +	if (parts[0].offset == OFFSET_CONTINUOUS)
> +		return;

Hmm, I guess the sorting function should not have this check. You
probably can just sort normally these ones, they will be the last ones.

And then we can do a separate pass where we check for overlapping
partitions and multiple OFFSET_CONTINUOUS.

> +
> +	/* sort by the offset */
> +	for (i = 0; i < num_parts - 1; i++) {
> +		for (j = 1; j < num_parts - i; j++) {
> +			if (parts[j - 1].offset > parts[j].offset) {
> +				struct mtd_partition tmp;
> +
> +				tmp = parts[j - 1];
> +				parts[j - 1] = parts[j];
> +				parts[j] = tmp;
> +			}
> +		}
> +	}
> +	return;
> +}


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/4a3c0d8c/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 03:35:42 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 10:35:42 +0300
Subject: [PATCH] ubirmvol: correct missing space on usage
In-Reply-To: <1346424605-17466-1-git-send-email-richard.genoud@gmail.com>
References: <1346424605-17466-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1346657742.3061.12.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 16:50 +0200, Richard Genoud wrote:
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
> ---
>  ubi-utils/ubirmvol.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)

Pushed, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/0b9554a8/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 03:34:51 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon,  3 Sep 2012 10:34:51 +0300
Subject: [PATCH 1/2] mtd: cmdlinepart: revise error handling
Message-ID: <1346657692-21754-1-git-send-email-dedekind1@gmail.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

This patch revises and fixes error handling in the command line mtd
partitions parser. Namely:
1. we ignored return code of 'mtdpart_setup_real()'.
2. instead of returning 0 for failure and 1 for success, teach
   'mtdpart_setup_real()' to return real error codes.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/cmdlinepart.c |   34 ++++++++++++++++++----------------
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index b4faca2..58dd0d0 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -39,11 +39,10 @@
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <linux/bootmem.h>
 #include <linux/module.h>
+#include <linux/err.h>
 
 /* error message prefix */
 #define ERRP "mtd: "
@@ -110,7 +109,7 @@ static struct mtd_partition * newpart(char *s,
 		if (size < PAGE_SIZE)
 		{
 			printk(KERN_ERR ERRP "partition size too small (%lx)\n", size);
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 	}
 
@@ -138,7 +137,7 @@ static struct mtd_partition * newpart(char *s,
 		if (!p)
 		{
 			printk(KERN_ERR ERRP "no closing %c found in partition name\n", delim);
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 		name_len = p - name;
 		s = p + 1;
@@ -172,13 +171,13 @@ static struct mtd_partition * newpart(char *s,
 		if (size == SIZE_REMAINING)
 		{
 			printk(KERN_ERR ERRP "no partitions allowed after a fill-up partition\n");
-			return NULL;
+			return ERR_PTR(-EINVAL);
 		}
 		/* more partitions follow, parse them */
 		parts = newpart(s + 1, &s, num_parts, this_part + 1,
 				&extra_mem, extra_mem_size);
-		if (!parts)
-			return NULL;
+		if (IS_ERR(parts))
+			return parts;
 	}
 	else
 	{	/* this is the last partition: allocate space for all */
@@ -189,7 +188,7 @@ static struct mtd_partition * newpart(char *s,
 			     extra_mem_size;
 		parts = kzalloc(alloc_size, GFP_KERNEL);
 		if (!parts)
-			return NULL;
+			return ERR_PTR(-ENOMEM);
 		extra_mem = (unsigned char *)(parts + *num_parts);
 	}
 	/* enter this partition (offset will be calculated later if it is zero at this point) */
@@ -245,7 +244,7 @@ static int mtdpart_setup_real(char *s)
 		if (!(p = strchr(s, ':')))
 		{
 			printk(KERN_ERR ERRP "no mtd-id\n");
-			return 0;
+			return -EINVAL;
 		}
 		mtd_id_len = p - mtd_id;
 
@@ -262,7 +261,7 @@ static int mtdpart_setup_real(char *s)
 				(unsigned char**)&this_mtd, /* out: extra mem */
 				mtd_id_len + 1 + sizeof(*this_mtd) +
 				sizeof(void*)-1 /*alignment*/);
-		if(!parts)
+		if (IS_ERR(parts))
 		{
 			/*
 			 * An error occurred. We're either:
@@ -271,7 +270,7 @@ static int mtdpart_setup_real(char *s)
 			 * Either way, this mtd is hosed and we're
 			 * unlikely to succeed in parsing any more
 			 */
-			 return 0;
+			 return PTR_ERR(parts);
 		 }
 
 		/* align this_mtd */
@@ -299,11 +298,11 @@ static int mtdpart_setup_real(char *s)
 		if (*s != ';')
 		{
 			printk(KERN_ERR ERRP "bad character after partition (%c)\n", *s);
-			return 0;
+			return -EINVAL;
 		}
 		s++;
 	}
-	return 1;
+	return 0;
 }
 
 /*
@@ -318,13 +317,16 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 				    struct mtd_part_parser_data *data)
 {
 	unsigned long offset;
-	int i;
+	int i, err;
 	struct cmdline_mtd_partition *part;
 	const char *mtd_id = master->name;
 
 	/* parse command line */
-	if (!cmdline_parsed)
-		mtdpart_setup_real(cmdline);
+	if (!cmdline_parsed) {
+		err = mtdpart_setup_real(cmdline);
+		if (err)
+			return err;
+	}
 
 	for(part = partitions; part; part = part->next)
 	{
-- 
1.7.10.4



From dedekind1 at gmail.com  Mon Sep  3 03:34:52 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon,  3 Sep 2012 10:34:52 +0300
Subject: [PATCH 2/2] mtd: cmdlinepart: minor cleanups
In-Reply-To: <1346657692-21754-1-git-send-email-dedekind1@gmail.com>
References: <1346657692-21754-1-git-send-email-dedekind1@gmail.com>
Message-ID: <1346657692-21754-2-git-send-email-dedekind1@gmail.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

Clean-up the driver a bit to make it easier to read and amend the coding style.
Mostly these are changes like:

if (a)
{
}

=>

if (a) {
}

Some extra blank lines were added.
Indentation was changed to use tabs instead of spaces.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/cmdlinepart.c |  137 +++++++++++++++++++--------------------------
 1 file changed, 59 insertions(+), 78 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 58dd0d0..17b0bd4 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -82,15 +82,14 @@ static int cmdline_parsed;
  * syntax has been verified ok.
  */
 static struct mtd_partition * newpart(char *s,
-                                      char **retptr,
-                                      int *num_parts,
-                                      int this_part,
-                                      unsigned char **extra_mem_ptr,
-                                      int extra_mem_size)
+				      char **retptr,
+				      int *num_parts,
+				      int this_part,
+				      unsigned char **extra_mem_ptr,
+				      int extra_mem_size)
 {
 	struct mtd_partition *parts;
-	unsigned long size;
-	unsigned long offset = OFFSET_CONTINUOUS;
+	unsigned long size, offset = OFFSET_CONTINUOUS;
 	char *name;
 	int name_len;
 	unsigned char *extra_mem;
@@ -98,16 +97,13 @@ static struct mtd_partition * newpart(char *s,
 	unsigned int mask_flags;
 
 	/* fetch the partition size */
-	if (*s == '-')
-	{	/* assign all remaining space to this partition */
+	if (*s == '-') {
+		/* assign all remaining space to this partition */
 		size = SIZE_REMAINING;
 		s++;
-	}
-	else
-	{
+	} else {
 		size = memparse(s, &s);
-		if (size < PAGE_SIZE)
-		{
+		if (size < PAGE_SIZE) {
 			printk(KERN_ERR ERRP "partition size too small (%lx)\n", size);
 			return ERR_PTR(-EINVAL);
 		}
@@ -116,60 +112,51 @@ static struct mtd_partition * newpart(char *s,
 	/* fetch partition name and flags */
 	mask_flags = 0; /* this is going to be a regular partition */
 	delim = 0;
-        /* check for offset */
-        if (*s == '@')
-	{
-                s++;
-                offset = memparse(s, &s);
-        }
-        /* now look for name */
+
+	/* check for offset */
+	if (*s == '@') {
+		s++;
+		offset = memparse(s, &s);
+	}
+
+	/* now look for name */
 	if (*s == '(')
-	{
 		delim = ')';
-	}
 
-	if (delim)
-	{
+	if (delim) {
 		char *p;
 
-	    	name = ++s;
+		name = ++s;
 		p = strchr(name, delim);
-		if (!p)
-		{
+		if (!p) {
 			printk(KERN_ERR ERRP "no closing %c found in partition name\n", delim);
 			return ERR_PTR(-EINVAL);
 		}
 		name_len = p - name;
 		s = p + 1;
-	}
-	else
-	{
-	    	name = NULL;
+	} else {
+		name = NULL;
 		name_len = 13; /* Partition_000 */
 	}
 
 	/* record name length for memory allocation later */
 	extra_mem_size += name_len + 1;
 
-        /* test for options */
-        if (strncmp(s, "ro", 2) == 0)
-	{
+	/* test for options */
+	if (strncmp(s, "ro", 2) == 0) {
 		mask_flags |= MTD_WRITEABLE;
 		s += 2;
-        }
+	}
 
-        /* if lk is found do NOT unlock the MTD partition*/
-        if (strncmp(s, "lk", 2) == 0)
-	{
+	/* if lk is found do NOT unlock the MTD partition*/
+	if (strncmp(s, "lk", 2) == 0) {
 		mask_flags |= MTD_POWERUP_LOCK;
 		s += 2;
-        }
+	}
 
 	/* test if more partitions are following */
-	if (*s == ',')
-	{
-		if (size == SIZE_REMAINING)
-		{
+	if (*s == ',') {
+		if (size == SIZE_REMAINING) {
 			printk(KERN_ERR ERRP "no partitions allowed after a fill-up partition\n");
 			return ERR_PTR(-EINVAL);
 		}
@@ -178,44 +165,38 @@ static struct mtd_partition * newpart(char *s,
 				&extra_mem, extra_mem_size);
 		if (IS_ERR(parts))
 			return parts;
-	}
-	else
-	{	/* this is the last partition: allocate space for all */
+	} else {
+		/* this is the last partition: allocate space for all */
 		int alloc_size;
 
 		*num_parts = this_part + 1;
 		alloc_size = *num_parts * sizeof(struct mtd_partition) +
 			     extra_mem_size;
+
 		parts = kzalloc(alloc_size, GFP_KERNEL);
 		if (!parts)
 			return ERR_PTR(-ENOMEM);
 		extra_mem = (unsigned char *)(parts + *num_parts);
 	}
+
 	/* enter this partition (offset will be calculated later if it is zero at this point) */
 	parts[this_part].size = size;
 	parts[this_part].offset = offset;
 	parts[this_part].mask_flags = mask_flags;
 	if (name)
-	{
 		strlcpy(extra_mem, name, name_len + 1);
-	}
 	else
-	{
 		sprintf(extra_mem, "Partition_%03d", this_part);
-	}
 	parts[this_part].name = extra_mem;
 	extra_mem += name_len + 1;
 
 	dbg(("partition %d: name <%s>, offset %llx, size %llx, mask flags %x\n",
-	     this_part,
-	     parts[this_part].name,
-	     parts[this_part].offset,
-	     parts[this_part].size,
-	     parts[this_part].mask_flags));
+	     this_part, parts[this_part].name, parts[this_part].offset,
+	     parts[this_part].size, parts[this_part].mask_flags));
 
 	/* return (updated) pointer to extra_mem memory */
 	if (extra_mem_ptr)
-	  *extra_mem_ptr = extra_mem;
+		*extra_mem_ptr = extra_mem;
 
 	/* return (updated) pointer command line string */
 	*retptr = s;
@@ -235,14 +216,14 @@ static int mtdpart_setup_real(char *s)
 	{
 		struct cmdline_mtd_partition *this_mtd;
 		struct mtd_partition *parts;
-	    	int mtd_id_len;
-		int num_parts;
+		int mtd_id_len, num_parts;
 		char *p, *mtd_id;
 
-	    	mtd_id = s;
+		mtd_id = s;
+
 		/* fetch <mtd-id> */
-		if (!(p = strchr(s, ':')))
-		{
+		p = strchr(s, ':');
+		if (!p) {
 			printk(KERN_ERR ERRP "no mtd-id\n");
 			return -EINVAL;
 		}
@@ -261,8 +242,7 @@ static int mtdpart_setup_real(char *s)
 				(unsigned char**)&this_mtd, /* out: extra mem */
 				mtd_id_len + 1 + sizeof(*this_mtd) +
 				sizeof(void*)-1 /*alignment*/);
-		if (IS_ERR(parts))
-		{
+		if (IS_ERR(parts)) {
 			/*
 			 * An error occurred. We're either:
 			 * a) out of memory, or
@@ -275,7 +255,7 @@ static int mtdpart_setup_real(char *s)
 
 		/* align this_mtd */
 		this_mtd = (struct cmdline_mtd_partition *)
-			ALIGN((unsigned long)this_mtd, sizeof(void*));
+				ALIGN((unsigned long)this_mtd, sizeof(void *));
 		/* enter results */
 		this_mtd->parts = parts;
 		this_mtd->num_parts = num_parts;
@@ -295,13 +275,13 @@ static int mtdpart_setup_real(char *s)
 			break;
 
 		/* does another spec follow? */
-		if (*s != ';')
-		{
+		if (*s != ';') {
 			printk(KERN_ERR ERRP "bad character after partition (%c)\n", *s);
 			return -EINVAL;
 		}
 		s++;
 	}
+
 	return 0;
 }
 
@@ -328,20 +308,18 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 			return err;
 	}
 
-	for(part = partitions; part; part = part->next)
-	{
-		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id)))
-		{
-			for(i = 0, offset = 0; i < part->num_parts; i++)
-			{
+	for (part = partitions; part; part = part->next) {
+		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id))) {
+			for (i = 0, offset = 0; i < part->num_parts; i++) {
 				if (part->parts[i].offset == OFFSET_CONTINUOUS)
-				  part->parts[i].offset = offset;
+					part->parts[i].offset = offset;
 				else
-				  offset = part->parts[i].offset;
+					offset = part->parts[i].offset;
+
 				if (part->parts[i].size == SIZE_REMAINING)
-				  part->parts[i].size = master->size - offset;
-				if (offset + part->parts[i].size > master->size)
-				{
+					part->parts[i].size = master->size - offset;
+
+				if (offset + part->parts[i].size > master->size) {
 					printk(KERN_WARNING ERRP
 					       "%s: partitioning exceeds flash size, truncating\n",
 					       part->mtd_id);
@@ -350,14 +328,17 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 				}
 				offset += part->parts[i].size;
 			}
+
 			*pparts = kmemdup(part->parts,
 					sizeof(*part->parts) * part->num_parts,
 					GFP_KERNEL);
 			if (!*pparts)
 				return -ENOMEM;
+
 			return part->num_parts;
 		}
 	}
+
 	return 0;
 }
 
-- 
1.7.10.4



From dedekind1 at gmail.com  Mon Sep  3 04:00:39 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 11:00:39 +0300
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
Message-ID: <1346659239.3061.17.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 16:46 +0200, Richard Genoud wrote:
> BUT, I ran into a bug, I don't know if it's my kernel (as I've got
> quite a lot of patches ahead of 3.6 to get my board run), but it's
> kind of nasty.

What is your kernel? Why don't you just pull the corresponding ubifs
backport tree?

> It's not related to this patch serie, I could trigger it with a
> 3.6-rc1 kernel (and my board-patches).
> I get some memory crashing when I do :
> flash_erase /dev/mtd2 0 160 (it's a whole mtd partition)
> ubiattach -m 2

Would you please be able to reproduce this with linux-ubi tree and also
send be the full oops?

> After that, I can have a OOPS right away, but sometimes not.
> but if I run someting (top for exemple) I get an oops then.
> So, the memory is beeing corrupted somewhere, but I couldn't find out
> exactly where.

If you could somehow reproduce this with nandsim, it would make it easy
for me to find the bug.

> But I found that if I comment out the lines :
> diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
> --- a/drivers/mtd/ubi/vtbl.c
> +++ b/drivers/mtd/ubi/vtbl.c
> @@ -346,8 +346,8 @@ retry:
>          */
>         err = ubi_scan_add_used(ubi, si, new_seb->pnum, new_seb->ec,
>                                 vid_hdr, 0);

We renamed all scan functions recently, so AFAICS you are not using the
latest UBI code-base. How about picking the latest back-port tree?

> +//     kfree(new_seb);
> +//     ubi_free_vid_hdr(ubi, vid_hdr);

This is strange, I think these 2 frees are all-right, I think the
root-cause is somewhere else.


> Does someone can reproduce that ?

It is difficult to say because you did not send the full oops.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/074900bd/attachment.sig>

From s.hauer at pengutronix.de  Mon Sep  3 04:55:17 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 3 Sep 2012 10:55:17 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <504098A1.4050208@antcom.de>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de>
 <503E3331.8050203@antcom.de> <20120829172820.43bbe68e@eb-e6520>
 <50407E44.5080408@antcom.de> <504098A1.4050208@antcom.de>
Message-ID: <20120903085517.GE26594@pengutronix.de>

On Fri, Aug 31, 2012 at 12:57:37PM +0200, Roland Stigge wrote:
> On 08/31/2012 11:05 AM, Roland Stigge wrote:
> > I tried to port this on top of Sascha's patches for imx53, only for mxc v3 for now, as below.
> > 
> > Unfortunately, I still get:
> > 
> > ...
> > UnCorrectable RS-ECC Error
> > UnCorrectable RS-ECC Error
> > UnCorrectable RS-ECC Error
> > UnCorrectable RS-ECC Error
> > UnCorrectable RS-ECC Error

Have you written the data you are unable to read with this driver?

> > ...
> > 
> > from mxc_nand.c's mxc_nand_correct_data_v2_v3(). Maybe there's still sth. missing in the
> > error correction code?
> 
> With the below incremental fix, it works. :-)
> 
> Thanks,
> 
> Roland
> 
> PS: Will you prepare a patch for l2-mtd.git? I only have an imx53, can't test the v1/v2 etc.
> configs.
> 
> 
> --- linux-2.6.orig/drivers/mtd/nand/mxc_nand.c
> +++ linux-2.6/drivers/mtd/nand/mxc_nand.c
> @@ -1141,14 +1141,14 @@ static void mxc_nand_command(struct mtd_
>                 host->devtype_data->send_cmd(host, command, true);
>                 mxc_do_addr_cycle(mtd, column, page_addr);
>                 host->devtype_data->send_read_id(host);
> -               host->buf_start = column;
> +               host->buf_start = 0;
>                 break;
>  
>         case NAND_CMD_PARAM:
>                 host->devtype_data->send_cmd(host, command, true);
>                 mxc_do_addr_cycle(mtd, column, page_addr);
>                 host->devtype_data->send_read_param(host);
> -               host->buf_start = column;
> +               host->buf_start = 0;

On what tree are you working? I cannot find a handling of
NAND_CMD_PARAM in my tree.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From zajec5 at gmail.com  Mon Sep  3 05:03:12 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Mon,  3 Sep 2012 11:03:12 +0200
Subject: [PATCH] mtd: basic (read only) driver for BCMA serial flash
Message-ID: <1346662992-23205-1-git-send-email-zajec5@gmail.com>

This registers MTD driver for serial flash platform device. Right now it
supports reading only, writing still has to be implemented.
At this point it's marked as BROKEN, because it requires code present in
net tree that wasn't mainlined yet.
---
Resending without RFC, after not receiving any.
---
 drivers/mtd/devices/Kconfig         |    8 +++
 drivers/mtd/devices/Makefile        |    1 +
 drivers/mtd/devices/bcm47xxsflash.c |  120 +++++++++++++++++++++++++++++++++++
 3 files changed, 129 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/devices/bcm47xxsflash.c

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 4cdb2af..4b4f7d2 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -120,6 +120,14 @@ config MTD_SST25L
 	  Set up your spi devices with the right board-specific platform data,
 	  if you want to specify device partitioning.
 
+config MTD_BCM47XXSFLASH
+	tristate "Support for serial flash on BCMA bus"
+	depends on BCMA_SFLASH && BROKEN
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  serial flash memories.
+
 config MTD_SLRAM
 	tristate "Uncached system RAM"
 	help
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index a4dd1d8..395733a 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
 obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
 obj-$(CONFIG_MTD_SPEAR_SMI)	+= spear_smi.o
 obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
+obj-$(CONFIG_MTD_BCM47XXSFLASH)	+= bcm47xxsflash.o
 
 CFLAGS_docg3.o			+= -I$(src)
\ No newline at end of file
diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
new file mode 100644
index 0000000..a9a8b75
--- /dev/null
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -0,0 +1,120 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+			      size_t *retlen, u_char *buf)
+{
+	struct bcma_sflash *sflash = mtd->priv;
+	size_t bytes_read = 0;
+	u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
+	int i;
+	size_t unaligned_before, unaligned_after;
+
+	/* Check address range */
+	if ((from + len) > mtd->size)
+		return -EINVAL;
+
+	unaligned_before = from & 0x3;
+	unaligned_after = (from + len) & 0x3;
+
+	for (i = 0; i < unaligned_before; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+	for (i = from - unaligned_before; i < from + len - unaligned_after;
+	     i += 4) {
+		*(u32 *)buf = readl((u32 *)src);
+		buf += 4;
+		src += 4;
+		bytes_read += 4;
+	}
+	for (i = 0; i < unaligned_after; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+
+	*retlen = bytes_read;
+
+	return 0;
+}
+
+static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
+				   struct mtd_info *mtd)
+{
+	mtd->priv = sflash;
+	mtd->name = "bcm47xxsflash";
+	mtd->owner = THIS_MODULE;
+	mtd->type = MTD_ROM;
+	mtd->size = sflash->size;
+	mtd->_read = bcm47xxsflash_read;
+	mtd->writesize = 1; /* FIXME */
+}
+
+static int bcm47xxsflash_probe(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+	int err;
+
+	sflash->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
+	if (!sflash->mtd)
+		return -ENOMEM;
+	bcm47xxsflash_fill_mtd(sflash, sflash->mtd);
+
+	err = mtd_device_parse_register(sflash->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int __devexit bcm47xxsflash_remove(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+
+	if (sflash->mtd)
+		mtd_device_unregister(sflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcma_sflash_driver = {
+	.remove = __devexit_p(bcm47xxsflash_remove),
+	.driver = {
+		.name = "bcma_sflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxsflash_init(void)
+{
+	int err;
+
+	err = platform_driver_probe(&bcma_sflash_driver, bcm47xxsflash_probe);
+	if (err)
+		pr_err("Failed to register BCMA serial flash driver: %d\n", err);
+
+	return err;
+}
+
+static void __exit bcm47xxsflash_exit(void)
+{
+	platform_driver_unregister(&bcma_sflash_driver);
+}
+
+module_init(bcm47xxsflash_init);
+module_exit(bcm47xxsflash_exit);
-- 
1.7.7



From stigge at antcom.de  Mon Sep  3 05:10:27 2012
From: stigge at antcom.de (Roland Stigge)
Date: Mon, 03 Sep 2012 11:10:27 +0200
Subject: mxc_nand.c on mach-imx/imx53
In-Reply-To: <20120903085517.GE26594@pengutronix.de>
References: <5035F84E.3000901@antcom.de>
 <20120829074122.GV26594@pengutronix.de> <503E3331.8050203@antcom.de>
 <20120829172820.43bbe68e@eb-e6520> <50407E44.5080408@antcom.de>
 <504098A1.4050208@antcom.de> <20120903085517.GE26594@pengutronix.de>
Message-ID: <50447403.4010003@antcom.de>

On 09/03/2012 10:55 AM, Sascha Hauer wrote:
> On Fri, Aug 31, 2012 at 12:57:37PM +0200, Roland Stigge wrote:
>> On 08/31/2012 11:05 AM, Roland Stigge wrote:
>>> I tried to port this on top of Sascha's patches for imx53, only for mxc v3 for now, as below.
>>>
>>> Unfortunately, I still get:
>>>
>>> ...
>>> UnCorrectable RS-ECC Error
>>> UnCorrectable RS-ECC Error
>>> UnCorrectable RS-ECC Error
>>> UnCorrectable RS-ECC Error
>>> UnCorrectable RS-ECC Error
> 
> Have you written the data you are unable to read with this driver?

No, maybe that's one of the reasons. The bootloader also seems to
implement a different on-flash layout. But as written, the problem is
gone with the below fix.

>> --- linux-2.6.orig/drivers/mtd/nand/mxc_nand.c
>> +++ linux-2.6/drivers/mtd/nand/mxc_nand.c
>> @@ -1141,14 +1141,14 @@ static void mxc_nand_command(struct mtd_
>>                 host->devtype_data->send_cmd(host, command, true);
>>                 mxc_do_addr_cycle(mtd, column, page_addr);
>>                 host->devtype_data->send_read_id(host);
>> -               host->buf_start = column;
>> +               host->buf_start = 0;
>>                 break;
>>  
>>         case NAND_CMD_PARAM:
>>                 host->devtype_data->send_cmd(host, command, true);
>>                 mxc_do_addr_cycle(mtd, column, page_addr);
>>                 host->devtype_data->send_read_param(host);
>> -               host->buf_start = column;
>> +               host->buf_start = 0;
> 
> On what tree are you working? I cannot find a handling of
> NAND_CMD_PARAM in my tree.

That's on top of the patch I ported from Eric's barebox driver (other
mail, but only for imx53/v3 for now). Sorry for the confusion.

I can prepare a single patch, but maybe Eric's more knowledgeable on
this driver (including v1/v2 that I can't test), he announced a patch
for this week.

Roland


From dedekind1 at gmail.com  Mon Sep  3 05:23:42 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 12:23:42 +0300
Subject: UBI on SPI NOR flash
In-Reply-To: <1346084156.3722.9.camel@coredoba.hi.pengutronix.de>
References: <1345050600.3514.11.camel@coredoba.hi.pengutronix.de>
 <1345811483.2848.310.camel@sauron.fi.intel.com>
 <1346084156.3722.9.camel@coredoba.hi.pengutronix.de>
Message-ID: <1346664222.3061.21.camel@sauron.fi.intel.com>

On Mon, 2012-08-27 at 18:15 +0200, Jan L?bbe wrote:
> > Another problem I know with SPI flashes is that UBIFS uses vmalloc'd
> > memory for I/O, which is not suitable for DMA-ing on ARM platforms
> and
> > may cause subtle bugs and curruptions. Can you try to disable DMA
> and
> > see if the issues go away?
> 
> It works if I disable DMA in drivers/spi/spi-omap2-mcspi.c (simply
> comment out the DMA branch in omap2_mcspi_work). I can use UBI&UBIFS
> without problems for far. When rebooting to a kernel with DMA enabled
> I
> can no longer attach the previously working volume. Moving back to the
> PIO-Kernel, it works again.
> 
> Where should this be fixed? Should UBI use kmalloc'ed memory?

Yes, the best way to fix this is to teach UBI and UBIFS stop using
vmalloc(). It is not straight-forward, but doable. As I said several
times, I can assist by giving ideas and directions, but someone who
needs this should probably allocate a couple of men-months for this
project.

> Why does this work for NAND controllers using DMA? :) 

I am not sure, you should investigate. I think some drivers just check
if this is vmalloced memory, and avoid DMA for that. Some (e.g.,
onenand) use various hacks which appear to work.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/ebcfc109/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 05:27:20 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 12:27:20 +0300
Subject: UBI error: nor_erase_prepare: cannot invalidate PEB 76, write
 returned -5 read returned 2
In-Reply-To: <201012011437.16978.alexander.stein@systec-electronic.com>
References: <201012011437.16978.alexander.stein@systec-electronic.com>
Message-ID: <1346664440.3061.23.camel@sauron.fi.intel.com>

On Wed, 2010-12-01 at 14:37 +0100, Alexander Stein wrote:
> Hello,
> 
> I'm observing the given error after starting Linux. ubiattach is called from 
> within the init-script. Currently I'm running v2.6.34. The filesystem is 
> mounted read-only as expected.
> It gets curious that afterwards in u-boot the corresponding sector is complety 
> empty, read 0xff. It seems the sector cannot be written, although it is empty.
> Has anybody an idea about such phenomenon? Oh, before it forget, I use a 
> Numonyx Axcell M29EW NOR-Flash 128MiB.

Sorry guys, cannot help, but if you happen to find the root-cause and
fix it - patches are welcome :)

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/3545d57a/attachment-0001.sig>

From jlu at pengutronix.de  Mon Sep  3 05:44:01 2012
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Mon, 03 Sep 2012 11:44:01 +0200
Subject: UBI on SPI NOR flash
In-Reply-To: <1346664222.3061.21.camel@sauron.fi.intel.com>
References: <1345050600.3514.11.camel@coredoba.hi.pengutronix.de>
 <1345811483.2848.310.camel@sauron.fi.intel.com>
 <1346084156.3722.9.camel@coredoba.hi.pengutronix.de>
 <1346664222.3061.21.camel@sauron.fi.intel.com>
Message-ID: <1346665441.3429.14.camel@coredoba.hi.pengutronix.de>

Hi Artem,

On Mon, 2012-09-03 at 12:23 +0300, Artem Bityutskiy wrote:
> On Mon, 2012-08-27 at 18:15 +0200, Jan L?bbe wrote:
> > It works if I disable DMA in drivers/spi/spi-omap2-mcspi.c (simply
> > comment out the DMA branch in omap2_mcspi_work). I can use UBI&UBIFS
> > without problems for far. When rebooting to a kernel with DMA enabled
> > I
> > can no longer attach the previously working volume. Moving back to the
> > PIO-Kernel, it works again.
> > 
> > Where should this be fixed? Should UBI use kmalloc'ed memory?
> 
> Yes, the best way to fix this is to teach UBI and UBIFS stop using
> vmalloc(). It is not straight-forward, but doable. As I said several
> times, I can assist by giving ideas and directions, but someone who
> needs this should probably allocate a couple of men-months for this
> project.

I can't commit to spending months on this, but I do have some time.
Do you think the vmalloc-using places could be fixed step by step or
must this be done over UBI&UBIFI in one go?
Is there a specific thread where the approach fixing this has been
discussed before? Could the CMA be used instead of vmalloc?

You mentioned flexible arrays before. It seems it is targeted at items
smaller than a page and needs to copy each item when placing it into the
array. I'm not sure how this would help UBI/UBIF.

We probably also need an explicit way to tell MTD if a buffer is DMA
capable or not. Then we could avoid deciding based on the buffer pointer
in the storage drivers.

> > Why does this work for NAND controllers using DMA? :) 
> 
> I am not sure, you should investigate. I think some drivers just check
> if this is vmalloced memory, and avoid DMA for that. Some (e.g.,
> onenand) use various hacks which appear to work.

I was able to get it to work using this kind of hack (check in SPI host
driver for buf >= high_memory and fall back to PIO). It's submitted to
the SPI list, but I'm not sure if it's acceptable for them.

Regards,
Jan
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From dedekind1 at gmail.com  Mon Sep  3 06:00:50 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 13:00:50 +0300
Subject: UBI on SPI NOR flash
In-Reply-To: <1346665441.3429.14.camel@coredoba.hi.pengutronix.de>
References: <1345050600.3514.11.camel@coredoba.hi.pengutronix.de>
 <1345811483.2848.310.camel@sauron.fi.intel.com>
 <1346084156.3722.9.camel@coredoba.hi.pengutronix.de>
 <1346664222.3061.21.camel@sauron.fi.intel.com>
 <1346665441.3429.14.camel@coredoba.hi.pengutronix.de>
Message-ID: <1346666450.3061.34.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 11:44 +0200, Jan L?bbe wrote:
> Hi Artem,
> 
> On Mon, 2012-09-03 at 12:23 +0300, Artem Bityutskiy wrote:
> > On Mon, 2012-08-27 at 18:15 +0200, Jan L?bbe wrote:
> > > It works if I disable DMA in drivers/spi/spi-omap2-mcspi.c (simply
> > > comment out the DMA branch in omap2_mcspi_work). I can use UBI&UBIFS
> > > without problems for far. When rebooting to a kernel with DMA enabled
> > > I
> > > can no longer attach the previously working volume. Moving back to the
> > > PIO-Kernel, it works again.
> > > 
> > > Where should this be fixed? Should UBI use kmalloc'ed memory?
> > 
> > Yes, the best way to fix this is to teach UBI and UBIFS stop using
> > vmalloc(). It is not straight-forward, but doable. As I said several
> > times, I can assist by giving ideas and directions, but someone who
> > needs this should probably allocate a couple of men-months for this
> > project.
> 
> I can't commit to spending months on this, but I do have some time.
> Do you think the vmalloc-using places could be fixed step by step or
> must this be done over UBI&UBIFI in one go?
> Is there a specific thread where the approach fixing this has been
> discussed before? Could the CMA be used instead of vmalloc?

I believe it can be done step by step. You can start from UBI I guess.
Basically we use vmalloc everywhere when we need to read entire
eraseblock. The reason for this is that the eraseblock is large, so
kmalloc() would often fail.

So the idea is to allocate smaller buffers and then iterate. There are
places which are easier to handle, and some are more difficult to handle
(e.g., those where we index elements in the eraseblock array).

> You mentioned flexible arrays before. It seems it is targeted at items
> smaller than a page and needs to copy each item when placing it into the
> array. I'm not sure how this would help UBI/UBIF.

I think I meant something like flexible arrays. The idea was to create
an API which you can use as if you had a single vmalloc buffer. Indexing
operation then could be changed with a helper function.

> We probably also need an explicit way to tell MTD if a buffer is DMA
> capable or not. Then we could avoid deciding based on the buffer pointer
> in the storage drivers.

I think it is better to eliminate vmalloc from UBI/UBIFS.

> > > Why does this work for NAND controllers using DMA? :) 
> > 
> > I am not sure, you should investigate. I think some drivers just check
> > if this is vmalloced memory, and avoid DMA for that. Some (e.g.,
> > onenand) use various hacks which appear to work.
> 
> I was able to get it to work using this kind of hack (check in SPI host
> driver for buf >= high_memory and fall back to PIO). It's submitted to
> the SPI list, but I'm not sure if it's acceptable for them.

I hope not :-) We need to fix things properly.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/0ecbb3b6/attachment.sig>

From jlu at pengutronix.de  Mon Sep  3 06:10:29 2012
From: jlu at pengutronix.de (Jan =?ISO-8859-1?Q?L=FCbbe?=)
Date: Mon, 03 Sep 2012 12:10:29 +0200
Subject: UBI on SPI NOR flash
In-Reply-To: <1346666450.3061.34.camel@sauron.fi.intel.com>
References: <1345050600.3514.11.camel@coredoba.hi.pengutronix.de>
 <1345811483.2848.310.camel@sauron.fi.intel.com>
 <1346084156.3722.9.camel@coredoba.hi.pengutronix.de>
 <1346664222.3061.21.camel@sauron.fi.intel.com>
 <1346665441.3429.14.camel@coredoba.hi.pengutronix.de>
 <1346666450.3061.34.camel@sauron.fi.intel.com>
Message-ID: <1346667029.3429.21.camel@coredoba.hi.pengutronix.de>

On Mon, 2012-09-03 at 13:00 +0300, Artem Bityutskiy wrote:
> On Mon, 2012-09-03 at 11:44 +0200, Jan L?bbe wrote:
> > I can't commit to spending months on this, but I do have some time.
> > Do you think the vmalloc-using places could be fixed step by step or
> > must this be done over UBI&UBIFI in one go?
> > Is there a specific thread where the approach fixing this has been
> > discussed before? Could the CMA be used instead of vmalloc?
> 
> I believe it can be done step by step. You can start from UBI I guess.
> Basically we use vmalloc everywhere when we need to read entire
> eraseblock. The reason for this is that the eraseblock is large, so
> kmalloc() would often fail.

Ok.

> So the idea is to allocate smaller buffers and then iterate. There are
> places which are easier to handle, and some are more difficult to handle
> (e.g., those where we index elements in the eraseblock array).
> 
> > You mentioned flexible arrays before. It seems it is targeted at items
> > smaller than a page and needs to copy each item when placing it into the
> > array. I'm not sure how this would help UBI/UBIF.
> 
> I think I meant something like flexible arrays. The idea was to create
> an API which you can use as if you had a single vmalloc buffer. Indexing
> operation then could be changed with a helper function.

Would you then iterate inside of UBI using this API, making page-sized
calls to MTD? Or would MTD need to be extended to pass around these
"DMA-lists"?

Do we need multiple large buffers at the same time for one UBI device?
If not, we could get one EB-size buffer from CMA on probe/mount and
reuse it.

> > We probably also need an explicit way to tell MTD if a buffer is DMA
> > capable or not. Then we could avoid deciding based on the buffer pointer
> > in the storage drivers.
> 
> I think it is better to eliminate vmalloc from UBI/UBIFS.

So in the end, MTD drivers would expect to only receive DMA capable
buffers?

> > I was able to get it to work using this kind of hack (check in SPI host
> > driver for buf >= high_memory and fall back to PIO). It's submitted to
> > the SPI list, but I'm not sure if it's acceptable for them.
> 
> I hope not :-) We need to fix things properly.

It's the same approach as taken by some NAND drivers. :-)

Regards,
Jan
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |



From afzal at ti.com  Mon Sep  3 06:14:54 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Mon, 3 Sep 2012 10:14:54 +0000
Subject: [PATCH 6/9] ARM: OMAP: Move gpio.h to include/linux/platform_data
In-Reply-To: <20120831005234.28732.10624.stgit@muffinssi.local>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <20120831005234.28732.10624.stgit@muffinssi.local>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9DC3AF@DBDE01.ent.ti.com>

Hi,

On Fri, Aug 31, 2012 at 06:22:34, Tony Lindgren wrote:
> This way we can remove includes of plat/gpio.h which won't work
> with the single zImage support.
> 
> Note that we also remove the cpu_class_is_omap2() check
> in gpio-omap.c as the drivers should not call it as we need to
> make it local to arch/arm/mach-omap2 for single zImage support.
> 
> While at it, arrange the related includes in the standard way.
> 
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: linux-mtd at lists.infradead.org
> Cc: alsa-devel at alsa-project.org
> Acked-by: Tony Lindgren <tony at atomide.com>

I think there is only one Tony ;)

Regards
Afzal

From jayakumar.lkml at gmail.com  Mon Sep  3 06:31:35 2012
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Mon, 3 Sep 2012 18:31:35 +0800
Subject: Problems after 2nd bootup with NAND and ubifs/ubi
In-Reply-To: <1345810383.2848.304.camel@sauron.fi.intel.com>
References: <CADqH6Vx_doWcOFP6N8qSV-h+KdZi8cqdxyHCROf-SKFvUiYNhg@mail.gmail.com>
 <1345810383.2848.304.camel@sauron.fi.intel.com>
Message-ID: <CADqH6Vw4FtGjLF-oPVwg0YcwOoQxk90whB6YoYh4mt=1D2SGmw@mail.gmail.com>

On Fri, Aug 24, 2012 at 8:13 PM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> ECC errors you see and the failing mtd tests mean you need to dig what's
> going on on the driver leve.

Hi Artem,

Thanks for your reply. I was finally able to resolve most of the
driver issues. The main problem turned out to be because the TI kernel
had issues in drivers/mtd/nand/omap2.c, where it forced ecc_opt to be
OMAP_ECC_HAMMING_CODE_HW, and it seems that this setting is buggy.
I've changed that to OMAP_ECC_HAMMING_CODE_DEFAULT and now everything
except for mtd_oobtest is passing (full log below). I'm able to flash
ubifs image on this and it appears to survive multiple boots. I have
not tested very thoroughly but it seems to be working.

Would I be correct in assuming that the mtd_oobtest failure can be
ignored since ubi does not use OOB?

Thanks,
jayakumar

root at android:/mtdtest # insmod mtd_speedtest.ko dev=4

=================================================
mtd_speedtest: MTD device: 4
mtd_speedtest: MTD device size 529006592, eraseblock size 131072, page
size 2048, count of eraseblocks 4036, pages per eraseblock 64, OOB
size 64
mtd_speedtest: scanning for bad eraseblocks
mtd_speedtest: scanned 4036 eraseblocks, 0 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 5185 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 10867 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 6290 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 10814 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 6306 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 10810 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 156595 KiB/s
mtd_speedtest: finished
=================================================

root at android:/mtdtest # insmod mtd_nandecctest.ko

mtd_nandecctest: ok - nand-ecc-256
mtd_nandecctest: ok - nand-ecc-512
root at android:/mtdtest # insmod mtd_stresstest.ko dev=4 count=10

=================================================
mtd_stresstest: MTD device: 4
mtd_stresstest: MTD device size 529006592, eraseblock size 131072,
page size 2048, count of eraseblocks 4036, pages per eraseblock 64,
OOB size 64
mtd_stresstest: scanning for bad eraseblocks
mtd_stresstest: scanned 4036 eraseblocks, 0 are bad
mtd_stresstest: doing operations
mtd_stresstest: 0 operations done
mtd_stresstest: finished, 10 operations done
=================================================
root at android:/mtdtest # insmod mtd_readtest.ko dev=4

=================================================
mtd_readtest: MTD device: 4
mtd_readtest: MTD device size 529006592, eraseblock size 131072, page
size 2048, count of eraseblocks 4036, pages per eraseblock 64, OOB
size 64
mtd_readtest: scanning for bad eraseblocks
mtd_readtest: scanned 4036 eraseblocks, 0 are bad
mtd_readtest: testing page read
mtd_readtest: finished
=================================================
root at android:/mtdtest # insmod mtd_subpagetest.ko dev=4

=================================================
mtd_subpagetest: MTD device: 4
mtd_subpagetest: MTD device size 529006592, eraseblock size 131072,
page size 2048, subpage size 512, count of eraseblocks 0, pages per
eraseblock 0, OOB size 64
mtd_subpagetest: scanning for bad eraseblocks
mtd_subpagetest: scanned 4036 eraseblocks, 0 are bad
mtd_subpagetest: erasing whole device
mtd_subpagetest: erased 4036 eraseblocks
mtd_subpagetest: writing whole device
mtd_subpagetest: written up to eraseblock 0
mtd_subpagetest: written up to eraseblock 256
mtd_subpagetest: written up to eraseblock 512
mtd_subpagetest: written up to eraseblock 768
mtd_subpagetest: written up to eraseblock 1024
mtd_subpagetest: written up to eraseblock 1280
mtd_subpagetest: written up to eraseblock 1536
mtd_subpagetest: written up to eraseblock 1792
mtd_subpagetest: written up to eraseblock 2048
mtd_subpagetest: written up to eraseblock 2304
mtd_subpagetest: written up to eraseblock 2560
mtd_subpagetest: written up to eraseblock 2816
mtd_subpagetest: written up to eraseblock 3072
mtd_subpagetest: written up to eraseblock 3328
mtd_subpagetest: written up to eraseblock 3584
mtd_subpagetest: written up to eraseblock 3840
mtd_subpagetest: written 4036 eraseblocks
mtd_subpagetest: verifying all eraseblocks
mtd_subpagetest: verified up to eraseblock 0
mtd_subpagetest: verified up to eraseblock 256
mtd_subpagetest: verified up to eraseblock 512
mtd_subpagetest: verified up to eraseblock 768
mtd_subpagetest: verified up to eraseblock 1024
mtd_subpagetest: verified up to eraseblock 1280
mtd_subpagetest: verified up to eraseblock 1536
mtd_subpagetest: verified up to eraseblock 1792
mtd_subpagetest: verified up to eraseblock 2048
mtd_subpagetest: verified up to eraseblock 2304
mtd_subpagetest: verified up to eraseblock 2560
mtd_subpagetest: verified up to eraseblock 2816
mtd_subpagetest: verified up to eraseblock 3072
mtd_subpagetest: verified up to eraseblock 3328
mtd_subpagetest: verified up to eraseblock 3584
mtd_subpagetest: verified up to eraseblock 3840
mtd_subpagetest: verified 4036 eraseblocks
mtd_subpagetest: erasing whole device
mtd_subpagetest: erased 4036 eraseblocks
mtd_subpagetest: verifying all eraseblocks for 0xff
mtd_subpagetest: verified up to eraseblock 0
mtd_subpagetest: verified up to eraseblock 256
mtd_subpagetest: verified up to eraseblock 512
mtd_subpagetest: verified up to eraseblock 768
mtd_subpagetest: verified up to eraseblock 1024
mtd_subpagetest: verified up to eraseblock 1280
mtd_subpagetest: verified up to eraseblock 1536
mtd_subpagetest: verified up to eraseblock 1792
mtd_subpagetest: verified up to eraseblock 2048
mtd_subpagetest: verified up to eraseblock 2304
mtd_subpagetest: verified up to eraseblock 2560
mtd_subpagetest: verified up to eraseblock 2816
mtd_subpagetest: verified up to eraseblock 3072
mtd_subpagetest: verified up to eraseblock 3328
mtd_subpagetest: verified up to eraseblock 3584
mtd_subpagetest: verified up to eraseblock 3840
mtd_subpagetest: verified 4036 eraseblocks
mtd_subpagetest: writing whole device
mtd_subpagetest: written up to eraseblock 0
mtd_subpagetest: written up to eraseblock 256
mtd_subpagetest: written up to eraseblock 512
mtd_subpagetest: written up to eraseblock 768
mtd_subpagetest: written up to eraseblock 1024
mtd_subpagetest: written up to eraseblock 1280
mtd_subpagetest: written up to eraseblock 1536
mtd_subpagetest: written up to eraseblock 1792
mtd_subpagetest: written up to eraseblock 2048
mtd_subpagetest: written up to eraseblock 2304
mtd_subpagetest: written up to eraseblock 2560
mtd_subpagetest: written up to eraseblock 2816
mtd_subpagetest: written up to eraseblock 3072
mtd_subpagetest: written up to eraseblock 3328
mtd_subpagetest: written up to eraseblock 3584
mtd_subpagetest: written up to eraseblock 3840
mtd_subpagetest: written 4036 eraseblocks
mtd_subpagetest: verifying all eraseblocks
mtd_subpagetest: verified up to eraseblock 0
mtd_subpagetest: verified up to eraseblock 256
mtd_subpagetest: ECC correction at 0x24e0000
mtd_subpagetest: ECC correction at 0x2760000
mtd_subpagetest: ECC correction at 0x2bc0000
mtd_subpagetest: verified up to eraseblock 512
mtd_subpagetest: verified up to eraseblock 768
mtd_subpagetest: ECC correction at 0x6080000
mtd_subpagetest: ECC correction at 0x6140000
mtd_subpagetest: ECC correction at 0x7620000
mtd_subpagetest: verified up to eraseblock 1024
mtd_subpagetest: ECC correction at 0x81c0000
mtd_subpagetest: ECC correction at 0x9040200
mtd_subpagetest: ECC correction at 0x94c0200
mtd_subpagetest: ECC correction at 0x9740200
mtd_subpagetest: ECC correction at 0x9a60200
mtd_subpagetest: ECC correction at 0x9c40200
mtd_subpagetest: ECC correction at 0x9de0000
mtd_subpagetest: verified up to eraseblock 1280
mtd_subpagetest: ECC correction at 0xa4c0000
mtd_subpagetest: ECC correction at 0xa940000
mtd_subpagetest: ECC correction at 0xabc0000
mtd_subpagetest: ECC correction at 0xad40000
mtd_subpagetest: ECC correction at 0xbd80000
mtd_subpagetest: ECC correction at 0xbfc0000
mtd_subpagetest: verified up to eraseblock 1536
mtd_subpagetest: ECC correction at 0xc200000
mtd_subpagetest: ECC correction at 0xc586e00
mtd_subpagetest: ECC correction at 0xd49ce00
mtd_subpagetest: ECC correction at 0xde40200
mtd_subpagetest: verified up to eraseblock 1792
mtd_subpagetest: ECC correction at 0xe5c0000
mtd_subpagetest: ECC correction at 0xe8e0000
mtd_subpagetest: ECC correction at 0xead7c00
mtd_subpagetest: ECC correction at 0xf1c0000
mtd_subpagetest: ECC correction at 0xf320200
mtd_subpagetest: verified up to eraseblock 2048
mtd_subpagetest: ECC correction at 0x10860000
mtd_subpagetest: ECC correction at 0x115c0000
mtd_subpagetest: ECC correction at 0x11bc0200
mtd_subpagetest: verified up to eraseblock 2304
mtd_subpagetest: ECC correction at 0x12449c00
mtd_subpagetest: ECC correction at 0x12560000
mtd_subpagetest: ECC correction at 0x13fc0200
mtd_subpagetest: verified up to eraseblock 2560
mtd_subpagetest: ECC correction at 0x15b40000
mtd_subpagetest: verified up to eraseblock 2816
mtd_subpagetest: ECC correction at 0x17040000
mtd_subpagetest: ECC correction at 0x17340000
mtd_subpagetest: ECC correction at 0x178e0000
mtd_subpagetest: ECC correction at 0x17b80000
mtd_subpagetest: verified up to eraseblock 3072
mtd_subpagetest: ECC correction at 0x18260200
mtd_subpagetest: ECC correction at 0x18f40000
mtd_subpagetest: verified up to eraseblock 3328
mtd_subpagetest: ECC correction at 0x1a0c0000
mtd_subpagetest: ECC correction at 0x1a220000
mtd_subpagetest: ECC correction at 0x1a40f000
mtd_subpagetest: ECC correction at 0x1a960200
mtd_subpagetest: ECC correction at 0x1b840000
mtd_subpagetest: verified up to eraseblock 3584
mtd_subpagetest: ECC correction at 0x1d100200
mtd_subpagetest: ECC correction at 0x1d640000
mtd_subpagetest: verified up to eraseblock 3840
mtd_subpagetest: ECC correction at 0x1e1c0000
mtd_subpagetest: verified 4036 eraseblocks
mtd_subpagetest: erasing whole device
mtd_subpagetest: erased 4036 eraseblocks
mtd_subpagetest: verifying all eraseblocks for 0xff
mtd_subpagetest: verified up to eraseblock 0
mtd_subpagetest: verified up to eraseblock 256
mtd_subpagetest: verified up to eraseblock 512
mtd_subpagetest: verified up to eraseblock 768
mtd_subpagetest: verified up to eraseblock 1024
mtd_subpagetest: verified up to eraseblock 1280
mtd_subpagetest: verified up to eraseblock 1536
mtd_subpagetest: verified up to eraseblock 1792
mtd_subpagetest: verified up to eraseblock 2048
mtd_subpagetest: verified up to eraseblock 2304
mtd_subpagetest: verified up to eraseblock 2560
mtd_subpagetest: verified up to eraseblock 2816
mtd_subpagetest: verified up to eraseblock 3072
mtd_subpagetest: verified up to eraseblock 3328
mtd_subpagetest: verified up to eraseblock 3584
mtd_subpagetest: verified up to eraseblock 3840
mtd_subpagetest: verified 4036 eraseblocks
mtd_subpagetest: finished with 0 errors
=================================================
root at android:/mtdtest # insmod mtd_pagetest.ko dev=4

=================================================
mtd_pagetest: MTD device: 4
mtd_pagetest: MTD device size 529006592, eraseblock size 131072, page
size 2048, count of eraseblocks 4036, pages per eraseblock 64, OOB
size 64
mtd_pagetest: scanning for bad eraseblocks
mtd_pagetest: scanned 4036 eraseblocks, 0 are bad
mtd_pagetest: erasing whole device
mtd_pagetest: erased 4036 eraseblocks
mtd_pagetest: writing whole device
mtd_pagetest: written up to eraseblock 0
mtd_pagetest: written up to eraseblock 256
mtd_pagetest: written up to eraseblock 512
mtd_pagetest: written up to eraseblock 768
mtd_pagetest: written up to eraseblock 1024
mtd_pagetest: written up to eraseblock 1280
mtd_pagetest: written up to eraseblock 1536
mtd_pagetest: written up to eraseblock 1792
mtd_pagetest: written up to eraseblock 2048
mtd_pagetest: written up to eraseblock 2304
mtd_pagetest: written up to eraseblock 2560
mtd_pagetest: written up to eraseblock 2816
mtd_pagetest: written up to eraseblock 3072
mtd_pagetest: written up to eraseblock 3328
mtd_pagetest: written up to eraseblock 3584
mtd_pagetest: written up to eraseblock 3840
mtd_pagetest: written 4036 eraseblocks
mtd_pagetest: verifying all eraseblocks
mtd_pagetest: verified up to eraseblock 0
mtd_pagetest: verified up to eraseblock 256
mtd_pagetest: verified up to eraseblock 512
mtd_pagetest: verified up to eraseblock 768
mtd_pagetest: verified up to eraseblock 1024
mtd_pagetest: verified up to eraseblock 1280
mtd_pagetest: verified up to eraseblock 1536
mtd_pagetest: verified up to eraseblock 1792
mtd_pagetest: verified up to eraseblock 2048
mtd_pagetest: verified up to eraseblock 2304
mtd_pagetest: verified up to eraseblock 2560
mtd_pagetest: verified up to eraseblock 2816
mtd_pagetest: verified up to eraseblock 3072
mtd_pagetest: verified up to eraseblock 3328
mtd_pagetest: verified up to eraseblock 3584
mtd_pagetest: verified up to eraseblock 3840
mtd_pagetest: verified 4036 eraseblocks
mtd_pagetest: crosstest
mtd_pagetest: reading page at 0x0
mtd_pagetest: reading page at 0x1f87f800
mtd_pagetest: reading page at 0x0
mtd_pagetest: verifying pages read at 0x0 match
mtd_pagetest: crosstest ok
mtd_pagetest: erasecrosstest
mtd_pagetest: erasing block 0
mtd_pagetest: writing 1st page of block 0
mtd_pagetest: reading 1st page of block 0
mtd_pagetest: verifying 1st page of block 0
mtd_pagetest: erasing block 0
mtd_pagetest: writing 1st page of block 0
mtd_pagetest: erasing block 4035
mtd_pagetest: reading 1st page of block 0
mtd_pagetest: verifying 1st page of block 0
mtd_pagetest: erasecrosstest ok
mtd_pagetest: erasetest
mtd_pagetest: erasing block 0
mtd_pagetest: writing 1st page of block 0
mtd_pagetest: erasing block 0
mtd_pagetest: reading 1st page of block 0
mtd_pagetest: verifying 1st page of block 0 is all 0xff
mtd_pagetest: erasetest ok
mtd_pagetest: finished with 0 errors
=================================================
root at android:/mtdtest # insmod mtd_oobtest.ko dev=4

=================================================
mtd_oobtest: MTD device: 4
mtd_oobtest: MTD device size 529006592, eraseblock size 131072, page
size 2048, count of eraseblocks 4036, pages per eraseblock 64, OOB
size 64
mtd_oobtest: scanning for bad eraseblocks
mtd_oobtest: scanned 4036 eraseblocks, 0 are bad
mtd_oobtest: test 1 of 5
mtd_oobtest: erasing whole device
mtd_oobtest: erased 4036 eraseblocks
mtd_oobtest: writing OOBs of whole device
mtd_oobtest: written up to eraseblock 0
mtd_oobtest: written up to eraseblock 256
mtd_oobtest: written up to eraseblock 512
mtd_oobtest: written up to eraseblock 768
mtd_oobtest: written up to eraseblock 1024
mtd_oobtest: written up to eraseblock 1280
mtd_oobtest: written up to eraseblock 1536
mtd_oobtest: written up to eraseblock 1792
mtd_oobtest: written up to eraseblock 2048
mtd_oobtest: written up to eraseblock 2304
mtd_oobtest: written up to eraseblock 2560
mtd_oobtest: written up to eraseblock 2816
mtd_oobtest: written up to eraseblock 3072
mtd_oobtest: written up to eraseblock 3328
mtd_oobtest: written up to eraseblock 3584
mtd_oobtest: written up to eraseblock 3840
mtd_oobtest: written 4036 eraseblocks
mtd_oobtest: verifying all eraseblocks
mtd_oobtest: verified up to eraseblock 0
mtd_oobtest: verified up to eraseblock 256
mtd_oobtest: verified up to eraseblock 512
mtd_oobtest: verified up to eraseblock 768
mtd_oobtest: verified up to eraseblock 1024
mtd_oobtest: verified up to eraseblock 1280
mtd_oobtest: verified up to eraseblock 1536
mtd_oobtest: verified up to eraseblock 1792
mtd_oobtest: verified up to eraseblock 2048
mtd_oobtest: verified up to eraseblock 2304
mtd_oobtest: verified up to eraseblock 2560
mtd_oobtest: verified up to eraseblock 2816
mtd_oobtest: verified up to eraseblock 3072
mtd_oobtest: verified up to eraseblock 3328
mtd_oobtest: verified up to eraseblock 3584
mtd_oobtest: verified up to eraseblock 3840
mtd_oobtest: verified 4036 eraseblocks
mtd_oobtest: test 2 of 5
mtd_oobtest: erasing whole device
mtd_oobtest: erased 4036 eraseblocks
mtd_oobtest: writing OOBs of whole device
mtd_oobtest: written up to eraseblock 0
mtd_oobtest: written up to eraseblock 256
mtd_oobtest: written up to eraseblock 512
mtd_oobtest: written up to eraseblock 768
mtd_oobtest: written up to eraseblock 1024
mtd_oobtest: written up to eraseblock 1280
mtd_oobtest: written up to eraseblock 1536
mtd_oobtest: written up to eraseblock 1792
mtd_oobtest: written up to eraseblock 2048
mtd_oobtest: written up to eraseblock 2304
mtd_oobtest: written up to eraseblock 2560
mtd_oobtest: written up to eraseblock 2816
mtd_oobtest: written up to eraseblock 3072
mtd_oobtest: written up to eraseblock 3328
mtd_oobtest: written up to eraseblock 3584
mtd_oobtest: written up to eraseblock 3840
mtd_oobtest: written 4036 eraseblocks
mtd_oobtest: verifying all eraseblocks
mtd_oobtest: verified up to eraseblock 0
mtd_oobtest: error: verify failed at 0xc60000
mtd_oobtest: error: verify failed at 0x15c0000
mtd_oobtest: verified up to eraseblock 256
mtd_oobtest: error: verify failed at 0x20a0000
mtd_oobtest: error: verify failed at 0x2cc0000
mtd_oobtest: error: verify failed at 0x2f00000
mtd_oobtest: error: verify failed at 0x3260000
mtd_oobtest: error: verify failed at 0x3a40000
mtd_oobtest: error: verify failed at 0x3e20000
mtd_oobtest: error: verify failed at 0x3e80000
mtd_oobtest: verified up to eraseblock 512
mtd_oobtest: error: verify failed at 0x49e0000
mtd_oobtest: error: verify failed at 0x4fc0000
mtd_oobtest: error: verify failed at 0x54a0000
mtd_oobtest: error: verify failed at 0x5800000
mtd_oobtest: error: verify failed at 0x59a0000
mtd_oobtest: verified up to eraseblock 768
mtd_oobtest: error: verify failed at 0x7260000
mtd_oobtest: verified up to eraseblock 1024
mtd_oobtest: error: verify failed at 0x82e0000
mtd_oobtest: error: verify failed at 0x93a0000
mtd_oobtest: error: verify failed at 0x9820000
mtd_oobtest: verified up to eraseblock 1280
mtd_oobtest: error: verify failed at 0xa1a0000
mtd_oobtest: error: verify failed at 0xaaa0000
mtd_oobtest: error: verify failed at 0xbac0000
mtd_oobtest: verified up to eraseblock 1536
mtd_oobtest: error: verify failed at 0xc1a0000
mtd_oobtest: error: verify failed at 0xc660000
mtd_oobtest: error: verify failed at 0xd420000
mtd_oobtest: verified up to eraseblock 1792
mtd_oobtest: error: verify failed at 0xe1a0000
mtd_oobtest: error: verify failed at 0xfcc0000
mtd_oobtest: error: verify failed at 0xfea0000
mtd_oobtest: verified up to eraseblock 2048
mtd_oobtest: error: verify failed at 0x105e0000
mtd_oobtest: error: verify failed at 0x118a0000
mtd_oobtest: verified up to eraseblock 2304
mtd_oobtest: error: verify failed at 0x12180000
mtd_oobtest: verified up to eraseblock 2560
mtd_oobtest: error: verify failed at 0x14880000
mtd_oobtest: error: verify failed at 0x14b80000
mtd_oobtest: error: verify failed at 0x14ca0000
mtd_oobtest: verified up to eraseblock 2816
mtd_oobtest: error: verify failed at 0x16520000
mtd_oobtest: error: verify failed at 0x16780000
mtd_oobtest: error: verify failed at 0x16e20000
mtd_oobtest: error: verify failed at 0x17520000
mtd_oobtest: error: verify failed at 0x178e0000
mtd_oobtest: verified up to eraseblock 3072
mtd_oobtest: error: verify failed at 0x190c0000
mtd_oobtest: verified up to eraseblock 3328
mtd_oobtest: error: verify failed at 0x1a160000
mtd_oobtest: error: verify failed at 0x1af60000
mtd_oobtest: verified up to eraseblock 3584
mtd_oobtest: error: verify failed at 0x1d700000
mtd_oobtest: error: verify failed at 0x1dda0000
mtd_oobtest: error: verify failed at 0x1de20000
mtd_oobtest: verified up to eraseblock 3840
mtd_oobtest: error: verify failed at 0x1ee20000
mtd_oobtest: error: verify failed at 0x1f1c0000
mtd_oobtest: verified 4036 eraseblocks
mtd_oobtest: test 3 of 5
mtd_oobtest: erasing whole device
mtd_oobtest: erased 4036 eraseblocks
mtd_oobtest: writing OOBs of whole device
mtd_oobtest: written up to eraseblock 0
mtd_oobtest: written up to eraseblock 256
mtd_oobtest: written up to eraseblock 512
mtd_oobtest: written up to eraseblock 768
mtd_oobtest: written up to eraseblock 1024
mtd_oobtest: written up to eraseblock 1280
mtd_oobtest: written up to eraseblock 1536
mtd_oobtest: written up to eraseblock 1792
mtd_oobtest: written up to eraseblock 2048
mtd_oobtest: written up to eraseblock 2304
mtd_oobtest: written up to eraseblock 2560
mtd_oobtest: written up to eraseblock 2816
mtd_oobtest: written up to eraseblock 3072
mtd_oobtest: written up to eraseblock 3328
mtd_oobtest: written up to eraseblock 3584
mtd_oobtest: written up to eraseblock 3840
mtd_oobtest: written 4036 eraseblocks
mtd_oobtest: verifying all eraseblocks
mtd_oobtest: verified up to eraseblock 0
mtd_oobtest: verified up to eraseblock 256
mtd_oobtest: verified up to eraseblock 512
mtd_oobtest: verified up to eraseblock 768
mtd_oobtest: verified up to eraseblock 1024
mtd_oobtest: verified up to eraseblock 1280
mtd_oobtest: verified up to eraseblock 1536
mtd_oobtest: verified up to eraseblock 1792
mtd_oobtest: verified up to eraseblock 2048
mtd_oobtest: verified up to eraseblock 2304
mtd_oobtest: verified up to eraseblock 2560
mtd_oobtest: verified up to eraseblock 2816
mtd_oobtest: error: verify failed at 0x172eb000
mtd_oobtest: error: verify failed at 0x172eb000
mtd_oobtest: verified up to eraseblock 3072
mtd_oobtest: verified up to eraseblock 3328
mtd_oobtest: verified up to eraseblock 3584
mtd_oobtest: verified up to eraseblock 3840
mtd_oobtest: verified 4036 eraseblocks
mtd_oobtest: test 4 of 5
mtd_oobtest: erasing whole device
mtd_oobtest: erased 4036 eraseblocks
mtd_oobtest: attempting to start write past end of OOB
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: attempting to start read past end of OOB
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: attempting to write past end of device
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: attempting to read past end of device
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: attempting to write past end of device
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: attempting to read past end of device
mtd_oobtest: an error is expected...
mtd_oobtest: error occurred as expected
mtd_oobtest: test 5 of 5
mtd_oobtest: erasing whole device
mtd_oobtest: erased 4036 eraseblocks
mtd_oobtest: writing OOBs of whole device
mtd_oobtest: written up to eraseblock 0
mtd_oobtest: written up to eraseblock 0
mtd_oobtest: written up to eraseblock 256
mtd_oobtest: written up to eraseblock 256
mtd_oobtest: written up to eraseblock 512
mtd_oobtest: written up to eraseblock 512
mtd_oobtest: written up to eraseblock 768
mtd_oobtest: written up to eraseblock 768
mtd_oobtest: written up to eraseblock 1024
mtd_oobtest: written up to eraseblock 1024
mtd_oobtest: written up to eraseblock 1280
mtd_oobtest: written up to eraseblock 1280
mtd_oobtest: written up to eraseblock 1536
mtd_oobtest: written up to eraseblock 1536
mtd_oobtest: written up to eraseblock 1792
mtd_oobtest: written up to eraseblock 1792
mtd_oobtest: written up to eraseblock 2048
mtd_oobtest: written up to eraseblock 2048
mtd_oobtest: written up to eraseblock 2304
mtd_oobtest: written up to eraseblock 2304
mtd_oobtest: written up to eraseblock 2560
mtd_oobtest: written up to eraseblock 2560
mtd_oobtest: written up to eraseblock 2816
mtd_oobtest: written up to eraseblock 2816
mtd_oobtest: written up to eraseblock 3072
mtd_oobtest: written up to eraseblock 3072
mtd_oobtest: written up to eraseblock 3328
mtd_oobtest: written up to eraseblock 3328
mtd_oobtest: written up to eraseblock 3584
mtd_oobtest: written up to eraseblock 3584
mtd_oobtest: written up to eraseblock 3840
mtd_oobtest: written up to eraseblock 3840
mtd_oobtest: written 4035 eraseblocks
mtd_oobtest: verifying all eraseblocks
mtd_oobtest: verified up to eraseblock 0
mtd_oobtest: verified up to eraseblock 256
mtd_oobtest: verified up to eraseblock 512
mtd_oobtest: verified up to eraseblock 768
mtd_oobtest: verified up to eraseblock 1024
mtd_oobtest: verified up to eraseblock 1280
mtd_oobtest: verified up to eraseblock 1536
mtd_oobtest: verified up to eraseblock 1792
mtd_oobtest: verified up to eraseblock 2048
mtd_oobtest: verified up to eraseblock 2304
mtd_oobtest: verified up to eraseblock 2560
mtd_oobtest: verified up to eraseblock 2816
mtd_oobtest: verified up to eraseblock 3072
mtd_oobtest: verified up to eraseblock 3328
mtd_oobtest: verified up to eraseblock 3584
mtd_oobtest: verified up to eraseblock 3840
mtd_oobtest: verified 4035 eraseblocks
mtd_oobtest: finished with 48 errors
=================================================


From jayakumar.lkml at gmail.com  Mon Sep  3 06:45:28 2012
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Mon, 3 Sep 2012 18:45:28 +0800
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
Message-ID: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>

Hi mtd friends,

Sorry, I have a somewhat offtopic question. I'm using ubifs, and I'm
trying to figure out what would be a good way to handle browser based
firmware upgrades. I've implemented the following:

- NAND is partitioned into bootloader, kernel, ubifs
- system is running from ubifs
- httpd with CGI is running from ubifs
- user uploads firmware containing ubifs.img (150MB) using this CGI
- during the upload, the CGI writes the temporary file (up to 150MB)
to a fat partition on a empty microSD (a non-booting microSD has to be
always present for this to work)
- upon completion of the upload, the CGI unpacks the temporary file
and validates checksums, this of course needs more space since now
both the temporary file and unpacked results are present
- then reboot since we can't ubiformat/reflash from the running ubifs
partition and I can't detach from it for same reason.
- upon reboot, u-boot script checks for the presence of the ubifs.img
in the microSD fat partition, if it is there then it nand erases the
ubifs partition, then does nandwrite of the ubifs.img
- I realize this loses the erase counters since it is simplistic
- system boots and then removes the upgrade files so that it doesn't
repeat for each bootup

This seems clunky and I recognize that if the upgrade is interrupted,
the unit would be bricked. I was curious how other people implement
this and what the best practices are. I was thinking whether I should
have another partition for a small upgrade-only OS, so if u-boot
detects ubifs.img or a user button press, it boots into the
upgrade-only OS and then I can run ubiformat from there. I would
welcome any advice/suggestions.

Thanks,
jayakumar


From richard.genoud at gmail.com  Mon Sep  3 06:57:58 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 3 Sep 2012 12:57:58 +0200
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <1346659239.3061.17.camel@sauron.fi.intel.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346659239.3061.17.camel@sauron.fi.intel.com>
Message-ID: <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>

2012/9/3 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Fri, 2012-08-31 at 16:46 +0200, Richard Genoud wrote:
>> BUT, I ran into a bug, I don't know if it's my kernel (as I've got
>> quite a lot of patches ahead of 3.6 to get my board run), but it's
>> kind of nasty.
>
> What is your kernel? Why don't you just pull the corresponding ubifs
> backport tree?
I'm on 3.6-rc1 + specific work for my board (pinctrl, device tree and
some driver stuff) without which I can't boot

> Would you please be able to reproduce this with linux-ubi tree and also
> send be the full oops?
I rebased my work onto linux-ubi/master, I enabled only the needed
options to boot and test.
[   12.500000] UBI: attaching mtd3 to ubi0
[   12.539062] UBI: scanning is finished
[   12.539062] UBI: empty MTD device detected
[   12.562500] ------------[ cut here ]------------
[   12.562500] kernel BUG at mm/slob.c:331!
[   12.562500] Internal error: Oops - BUG: 0 [#1] ARM
[   12.562500] CPU: 0    Not tainted  (3.6.0-rc1+ #887)
[   12.562500] PC is at slob_alloc.clone.18+0x174/0x1b4
[   12.562500] LR is at slob_page_alloc+0x1a8/0x1d0
[   12.562500] pc : [<c0068130>]    lr : [<c0067c40>]    psr: 60000093
[   12.562500] sp : c7b47e08  ip : 00000000  fp : 01020014
[   12.562500] r10: 00000000  r9 : a0000013  r8 : 00007b69
[   12.562500] r7 : c0321000  r6 : 00000030  r5 : c0417d20  r4 : c02e1908
[   12.562500] r3 : 01020014  r2 : 01020013  r1 : fefdffec  r0 : 00000000
[   12.562500] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   12.562500] Control: 0005317f  Table: 27b48000  DAC: 00000015
[   12.562500] Process ubiattach (pid: 354, stack limit = 0xc7b46270)
[   12.562500] Stack: (0xc7b47e08 to 0xc7b48000)
[   12.562500] 7e00:                   00000030 000000d0 01020014
c7add1e0 c7b6a0f4 00000000
[   12.562500] 7e20: c7b6a0a0 c7add2a0 00000001 00000001 c7b6a0f0
c0068374 00000000 c7b67020
[   12.562500] 7e40: c7b6a0f4 c01798c0 00005800 c7ad7540 c7ad7540
00001000 00000001 00005800
[   12.562500] 7e60: 00000000 02000200 00000002 00000000 00005800
7fffefff 00000001 c7ad7540
[   12.562500] 7e80: c7add2a0 c7b67020 c7af79e0 c7ad7540 c7add2a0
01000000 00000000 00000000
[   12.562500] 7ea0: 00000000 c016c020 c7b67020 00000000 c7ad7540
00000000 00000000 02000000
[   12.562500] 7ec0: 00000014 c89e6000 000080d2 c7ad7540 c89e6000
c7add2a0 00000000 c89eb6ac
[   12.562500] 7ee0: c7b46000 00000000 00000003 c016cff4 c7ad7540
c7add2a0 00000000 c7a5e820
[   12.562500] 7f00: 00000014 c017a618 c7ad7540 00000000 00000000
c016fee0 c7aac2f0 c7aa8640
[   12.562500] 7f20: c7aa24b0 40186f40 40186f40 00000000 be82bb20
c7a5e820 40186f40 00000003
[   12.562500] 7f40: c0009388 c01703d8 ffffffff 00000003 00000000
00000000 00000000 00000000
[   12.562500] 7f60: be82bb20 00000003 40186f40 c0078684 c7acb6a0
00000003 40186f40 c7acb6a0
[   12.562500] 7f80: be82bb20 c00786f4 00000003 00000000 be82bb20
be82bb20 40186f40 00000003
[   12.562500] 7fa0: 00000036 c0009200 be82bb20 40186f40 00000003
40186f40 be82bb20 00000000
[   12.562500] 7fc0: be82bb20 40186f40 00000003 00000036 ffffffff
0001442c ffffffff 00000003
[   12.562500] 7fe0: b6ef5ec4 be82bae0 000098ec b6ef5f08 60000010
00000003 27ffe831 27ffec31
[   12.562500] [<c0068130>] (slob_alloc.clone.18+0x174/0x1b4) from
[<c0068374>] (kmem_cache_alloc_node+0x28/0x64)
[   12.562500] [<c0068374>] (kmem_cache_alloc_node+0x28/0x64) from
[<c01798c0>] (ubi_add_to_av+0x318/0x3fc)
[   12.562500] [<c01798c0>] (ubi_add_to_av+0x318/0x3fc) from
[<c016c020>] (create_vtbl+0x1cc/0x258)
[   12.562500] [<c016c020>] (create_vtbl+0x1cc/0x258) from
[<c016cff4>] (ubi_read_volume_table+0xe0/0x1f0)
[   12.562500] [<c016cff4>] (ubi_read_volume_table+0xe0/0x1f0) from
[<c017a618>] (ubi_attach+0x54/0xac)
[   12.562500] [<c017a618>] (ubi_attach+0x54/0xac) from [<c016fee0>]
(ubi_attach_mtd_dev+0x1bc/0x474)
[   12.562500] [<c016fee0>] (ubi_attach_mtd_dev+0x1bc/0x474) from
[<c01703d8>] (ctrl_cdev_ioctl+0xd8/0x168)
[   12.562500] [<c01703d8>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c0078684>] (do_vfs_ioctl+0x270/0x2ac)
[   12.562500] [<c0078684>] (do_vfs_ioctl+0x270/0x2ac) from
[<c00786f4>] (sys_ioctl+0x34/0x54)
[   12.562500] [<c00786f4>] (sys_ioctl+0x34/0x54) from [<c0009200>]
(ret_fast_syscall+0x0/0x2c)
[   12.562500] Code: e1a0200b ebfffe5b e250a000 1a000000 (e7f001f2)
[   12.562500] ---[ end trace 473f0aad0098fe9c ]---


>
>> After that, I can have a OOPS right away, but sometimes not.
>> but if I run someting (top for exemple) I get an oops then.
>> So, the memory is beeing corrupted somewhere, but I couldn't find out
>> exactly where.
>
> If you could somehow reproduce this with nandsim, it would make it easy
> for me to find the bug.
here it is:
[    0.921875] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.929687] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.937500] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.953125] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.960937] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.968750] [nandsim] warning: read_byte: unexpected data output
cycle, state is STATE_READY return 0x0
[    0.976562] NAND device: Manufacturer ID: 0x98, Chip ID: 0x39
(Toshiba NAND 128MiB 1,8V 8-bit), page size: 512, OOB size: 16
[    0.992187] flash size: 128 MiB
[    0.992187] page size: 512 bytes
[    0.992187] OOB area size: 16 bytes
[    1.000000] sector size: 16 KiB
[    1.000000] pages number: 262144
[    1.007812] pages per sector: 32
[    1.007812] bus width: 8
[    1.007812] bits in sector size: 14
[    1.015625] bits in page size: 9
[    1.015625] bits in OOB size: 4
[    1.023437] flash size with OOB: 135168 KiB
[    1.023437] page address bytes: 4
[    1.031250] sector address bytes: 3
[    1.031250] options: 0x42
[    1.039062] Scanning device for bad blocks
[    1.242187] Creating 1 MTD partitions on "NAND 128MiB 1,8V 8-bit":
[    1.250000] 0x000000000000-0x000008000000 : "NAND simulator partition 0"

# flash_erase /dev/mtd0 0 8192
Erasing 16 Kibyte @ 7ffc000 -- 100 % complete
# ./ubiattach -m 0
[  152.718750] UBI: attaching mtd0 to ubi0
[  153.054687] UBI: scanning is finished
[  153.062500] UBI: empty MTD device detected
[  153.078125] Internal error: Oops - undefined instruction: 0 [#1] ARM
[  153.078125] CPU: 0    Not tainted  (3.6.0-rc1+ #888)
[  153.078125] PC is at 0xc7aab444
[  153.078125] LR is at ip_local_out+0x28/0x2c
[  153.078125] pc : [<c7aab444>]    lr : [<c01bcab4>]    psr: 60000013
[  153.078125] sp : c7aefa80  ip : 0900800a  fp : c02df6fc
[  153.078125] r10: 00000068  r9 : 00000108  r8 : 00000000
[  153.078125] r7 : c7aefb3c  r6 : c7ac17e0  r5 : c7bb3464  r4 : c7bc0280
[  153.078125] r3 : c7aab308  r2 : 00000525  r1 : 00000000  r0 : c7bc029f
[  153.078125] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[  153.078125] Control: 0005317f  Table: 27b08000  DAC: 00000017
[  153.078125] Process klogd (pid: 324, stack limit = 0xc7aee270)
[  153.078125] Stack: (0xc7aefa80 to 0xc7af0000)
[  153.078125] fa80: c7bc0280 c01be694 c7bc0280 c7bb3464 c7ac17e0
c01dbbe0 c7aefa8c c7ac17e0
[  153.078125] faa0: c7aefc9c c7aefb3c c7bc0280 0900800a 6400800a
c01dd420 00000068 00000008
[  153.078125] fac0: c7aefb5c c7aefb6c 00004040 c7ac17e0 c7ad2780
000000cc 00000060 00000060
[  153.078125] fae0: 00000000 00000000 c01bdd0c 00000000 c7ac198c
00000011 c7ac17e0 00000068
[  153.078125] fb00: c7ac17e0 c7ad28a0 00000000 00000068 c7ad28b8
c0191af8 c7ad28a0 c7ac17e0
[  153.078125] fb20: 00000011 c01db548 00000000 c7ad28a0 c7adb7e4
c01de1c8 0000d203 00000002
[  153.078125] fb40: 00000001 00000000 02110000 00000000 6400800a
0900800a d2030108 0900800a
[  153.078125] fb60: 00000000 00000000 c02cce00 00000000 c7aefbcc
c7aefbb0 00000060 c7aefc9c
[  153.078125] fb80: c7ac17e0 c7ae8960 00000010 00004040 c7aefec8
c01e3bec 00000060 bf000000
[  153.078125] fba0: c7ac22a0 00000060 c7aefc9c c018e1f8 00000000
00000000 00000000 00000001
[  153.078125] fbc0: ffffffff 00000000 00000000 00000000 00000000
00000000 c7ae8960 00000000
[  153.078125] fbe0: 00000000 00000000 00000000 00000000 c7aefc30
00000000 00000000 00000000
[  153.078125] fc00: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[  153.078125] fc20: 00000000 00000000 00000000 00000000 00000000
00011200 01ffffff 00000060
[  153.078125] fc40: c7ac22a0 c02e3208 00000000 c7aefc9c c02e2c50
c004c190 00000000 00000041
[  153.078125] fc60: c02e2c50 00000000 00000001 00000000 bf000000
c7ac25cc c7aefc9c c7bb5004
[  153.078125] fc80: c7ac2ac4 c018e4b0 c7ac22a0 c01fc444 00000060
c01fe03c c7ae8ab8 c7ac25cc
[  153.078125] fca0: 00000010 c7aefcb8 00000001 00000000 00000000
00004040 c7bb5004 00000060
[  153.078125] fcc0: 00000001 c7ac2ac4 00000000 c7ac22a0 00000060
00000001 c7aabec8 c01fc4d8
[  153.078125] fce0: 00000000 00000000 c7aee000 00011200 c7acb6b8
c7ac2ac0 c7ac25c0 c7bc0200
[  153.078125] fd00: c7ac2b34 c7ac2b50 00000001 c7aabec8 c7aefec8
c01fc820 00000000 3b9aca00
[  153.078125] fd20: c7ac25c0 c7ac2ac0 c7bc0200 c01faa90 a40f89aa
00000023 c7bc0200 c7ac2ac0
[  153.078125] fd40: 00000000 00000000 c7ad0000 c01f8168 c7acb6b8
c01f803c 00000012 c7bc0200
[  153.078125] fd60: c7bc0238 c01fe95c c7bc0200 c7aefd94 c7aefdd8
c7aab880 c7ad0000 c01f9264
[  153.078125] fd80: c0229578 c7aefd94 00000000 c01f92c0 ffffffe0
00000000 c7aab880 c7aefdd8
[  153.078125] fda0: c0229578 00000000 00000000 00000000 00000060
c7aee000 c7aefdd8 c7aab880
[  153.078125] fdc0: c7acb6b8 c00c46dc c7aefdd8 c7bc0160 c7ac2020
c00c4d24 c02d48a4 c7acb6b8
[  153.078125] fde0: c7bc0160 00000000 00000020 c7acb7b0 c7bc0160
c7ac2020 c7acb6b0 c00baed4
[  153.078125] fe00: 00008000 c7acb7b0 c7ac0e38 00000000 00000101
c00b66a4 c7aeff00 c7aefec0
[  153.078125] fe20: c7aefe84 00000001 c7aab190 00000001 c7ad0000
c0073528 c7aeff00 c7aeff08
[  153.078125] fe40: c7aeff00 c7aefec0 00000000 00000000 00000000
c7aee000 c7aabec8 c0075048
[  153.078125] fe60: 0002bbb4 00000002 c7bc00c0 00000000 c7aeff78
00000024 ffffff9c 00000000
[  153.078125] fe80: 00000000 c7ac0e38 c7bb4000 c7aeff00 c7bc00c0
00000000 c7aee000 00000000
[  153.078125] fea0: c7aee000 c7aeff78 c7aefec8 c0075588 c7aefec8
00000000 b6ef8990 c02e3208
[  153.078125] fec0: 00000000 00000000 00000000 00000000 00000000
c7aeff78 00000001 ffffff9c
[  153.078125] fee0: c7aeff00 c7bb4000 c7aee000 00000000 0000000a
c00758ec 00000041 c02d2688
[  153.078125] ff00: c7aab190 c7aabec8 0002bbb4 00000002 c7bb4005
c7802800 c7aab190 c7aa9500
[  153.078125] ff20: c7ac0e38 00000101 00000000 00000000 00000000
00000000 00000000 c7af1b68
[  153.078125] ff40: c7af1b60 00000000 00000000 c007fb50 00000000
00000000 00000004 ffffff9c
[  153.078125] ff60: c7bb4000 00000001 c0009388 c00695ac c7aeff90
0000004e 00000000 becd0000
[  153.078125] ff80: 00000024 00000100 00000000 00000000 b6f04eb0
becd67d0 00000005 c0009388
[  153.078125] ffa0: 00000000 c0009200 00000000 b6f04eb0 b6ef8990
00000000 00000054 b6f04eb0
[  153.078125] ffc0: 00000000 b6f04eb0 becd67d0 00000005 b6f05040
00000fff 000a6e38 0000000a
[  153.078125] ffe0: becd6c54 becd6710 b6ebeed4 b6eee76c 60000010
b6ef8990 27ffe831 27ffec31
[  153.078125] [<c01bcab4>] (ip_local_out+0x28/0x2c) from [<c01be694>]
(ip_send_skb+0x8/0x58)
[  153.078125] [<c01be694>] (ip_send_skb+0x8/0x58) from [<c01dbbe0>]
(udp_send_skb+0x180/0x250)
[  153.078125] [<c01dbbe0>] (udp_send_skb+0x180/0x250) from
[<c01dd420>] (udp_sendmsg+0x474/0x67c)
[  153.078125] [<c01dd420>] (udp_sendmsg+0x474/0x67c) from
[<c01e3bec>] (inet_sendmsg+0x60/0x70)
[  153.078125] [<c01e3bec>] (inet_sendmsg+0x60/0x70) from [<c018e1f8>]
(sock_sendmsg+0x80/0xa0)
[  153.078125] [<c018e1f8>] (sock_sendmsg+0x80/0xa0) from [<c018e4b0>]
(kernel_sendmsg+0x3c/0x70)
[  153.078125] [<c018e4b0>] (kernel_sendmsg+0x3c/0x70) from
[<c01fc444>] (xs_send_kvec+0x98/0xa8)
[  153.078125] [<c01fc444>] (xs_send_kvec+0x98/0xa8) from [<c01fc4d8>]
(xs_sendpages+0x84/0x1e8)
[  153.078125] [<c01fc4d8>] (xs_sendpages+0x84/0x1e8) from
[<c01fc820>] (xs_udp_send_request+0x38/0xb4)
[  153.078125] [<c01fc820>] (xs_udp_send_request+0x38/0xb4) from
[<c01faa90>] (xprt_transmit+0xd0/0x1e8)
[  153.078125] [<c01faa90>] (xprt_transmit+0xd0/0x1e8) from
[<c01f8168>] (call_transmit+0x12c/0x194)
[  153.078125] [<c01f8168>] (call_transmit+0x12c/0x194) from
[<c01fe95c>] (__rpc_execute+0x4c/0xfc)
[  153.078125] [<c01fe95c>] (__rpc_execute+0x4c/0xfc) from
[<c01f9264>] (rpc_run_task+0xa4/0xb0)
[  153.078125] [<c01f9264>] (rpc_run_task+0xa4/0xb0) from [<c01f92c0>]
(rpc_call_sync+0x50/0x74)
[  153.078125] [<c01f92c0>] (rpc_call_sync+0x50/0x74) from
[<c00c46dc>] (nfs_rpc_wrapper.clone.6+0x28/0x64)
[  153.078125] [<c00c46dc>] (nfs_rpc_wrapper.clone.6+0x28/0x64) from
[<c00c4d24>] (nfs_proc_getattr+0x48/0x54)
[  153.078125] [<c00c4d24>] (nfs_proc_getattr+0x48/0x54) from
[<c00baed4>] (__nfs_revalidate_inode+0x8c/0x114)
[  153.078125] [<c00baed4>] (__nfs_revalidate_inode+0x8c/0x114) from
[<c00b66a4>] (nfs_lookup_revalidate+0x144/0x2ec)
[  153.078125] [<c00b66a4>] (nfs_lookup_revalidate+0x144/0x2ec) from
[<c0073528>] (lookup_fast+0x1b4/0x260)
[  153.078125] [<c0073528>] (lookup_fast+0x1b4/0x260) from
[<c0075048>] (do_last.clone.41+0x130/0x5cc)
[  153.078125] [<c0075048>] (do_last.clone.41+0x130/0x5cc) from
[<c0075588>] (path_openat+0xa4/0x3d8)
[  153.078125] [<c0075588>] (path_openat+0xa4/0x3d8) from [<c00758ec>]
(do_filp_open+0x30/0x7c)
[  153.078125] [<c00758ec>] (do_filp_open+0x30/0x7c) from [<c00695ac>]
(do_sys_open+0xd8/0x170)
[  153.078125] [<c00695ac>] (do_sys_open+0xd8/0x170) from [<c0009200>]
(ret_fast_syscall+0x0/0x2c)
[  153.078125] Code: 00000000 00000000 00000000 31313a30 (fdd20000)
[  153.078125] ---[ end trace ee2f60ac8ae81fb8 ]---

and another:
# flash_erase /dev/mtd0 0 8192
Erasing 16 Kibyte @ 7ffc000 -- 100 % complete
# ./ubiattach -m 0
[   97.273437] UBI: attaching mtd0 to ubi0
[   97.609375] UBI: scanning is finished
[   97.617187] UBI: empty MTD device detected
[   97.625000] ------------[ cut here ]------------
[   97.625000] kernel BUG at mm/slob.c:331!
[   97.625000] Internal error: Oops - BUG: 0 [#1] ARM
[   97.625000] CPU: 0    Not tainted  (3.6.0-rc1+ #888)
[   97.625000] PC is at slob_alloc.clone.18+0x174/0x1b4
[   97.625000] LR is at slob_page_alloc+0x1a8/0x1d0
[   97.625000] pc : [<c0068130>]    lr : [<c0067c40>]    psr: 60000093
[   97.625000] sp : c7af3e08  ip : 00000000  fp : 01620014
[   97.625000] r10: 00000000  r9 : a0000013  r8 : 00007bb3
[   97.625000] r7 : c0313000  r6 : 00000030  r5 : c040a660  r4 : c02d3908
[   97.625000] r3 : 01620014  r2 : 01620013  r1 : fe9dffec  r0 : 00000000
[   97.625000] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   97.625000] Control: 0005317f  Table: 27b4c000  DAC: 00000015
[   97.625000] Process ubiattach (pid: 351, stack limit = 0xc7af2270)
[   97.625000] Stack: (0xc7af3e08 to 0xc7af4000)
[   97.625000] 3e00:                   00000030 000000d0 01620014
c7b1c2a0 c7ba5314 00000000
[   97.625000] 3e20: c7ba52c0 c7b1c3e0 00000001 00000001 c7ba5310
c0068374 00000000 c7bae240
[   97.625000] 3e40: c7ba5314 c0174c40 00003e00 c7ad9a60 00000200
00000001 00003e00 00000000
[   97.625000] 3e60: 00000000 02000200 00000002 00000000 00003e00
7fffefff 00000001 c7ad9a60
[   97.625000] 3e80: c7b1c3e0 c7bae240 c7b1c450 c7ad9a60 c7b1c3e0
01000000 00000000 00000000
[   97.625000] 3ea0: 00000000 c01673a0 c7bae240 00000000 c7ad9a60
00000000 00000000 02000000
[   97.625000] 3ec0: 00000014 c89ca000 000080d2 c7ad9a60 c89ca000
c7b1c3e0 00000000 c89cde7c
[   97.625000] 3ee0: c7af2000 00000000 00000000 c0168374 c7ad9a60
c7b1c3e0 00000000 c79315c0
[   97.625000] 3f00: 00000014 c0175998 c7ad9a60 00000000 00000000
c016b260 c7aac3f0 c7aacc50
[   97.625000] 3f20: c7aa7020 40186f40 40186f40 00000000 bedd1b20
c79315c0 40186f40 00000003
[   97.625000] 3f40: c0009388 c016b758 ffffffff 00000000 00000000
00000000 00000000 00000000
[   97.625000] 3f60: bedd1b20 00000003 40186f40 c0078684 c7b36600
00000003 40186f40 c7b36600
[   97.625000] 3f80: bedd1b20 c00786f4 00000003 00000000 bedd1b20
bedd1b20 40186f40 00000003
[   97.625000] 3fa0: 00000036 c0009200 bedd1b20 40186f40 00000003
40186f40 bedd1b20 00000000
[   97.625000] 3fc0: bedd1b20 40186f40 00000003 00000036 ffffffff
0001442c ffffffff 00000000
[   97.625000] 3fe0: b6f7bec4 bedd1ae0 000098ec b6f7bf08 60000010
00000003 27ffe831 27ffec31
[   97.625000] [<c0068130>] (slob_alloc.clone.18+0x174/0x1b4) from
[<c0068374>] (kmem_cache_alloc_node+0x28/0x64)
[   97.625000] [<c0068374>] (kmem_cache_alloc_node+0x28/0x64) from
[<c0174c40>] (ubi_add_to_av+0x318/0x3fc)
[   97.625000] [<c0174c40>] (ubi_add_to_av+0x318/0x3fc) from
[<c01673a0>] (create_vtbl+0x1cc/0x258)
[   97.625000] [<c01673a0>] (create_vtbl+0x1cc/0x258) from
[<c0168374>] (ubi_read_volume_table+0xe0/0x1f0)
[   97.625000] [<c0168374>] (ubi_read_volume_table+0xe0/0x1f0) from
[<c0175998>] (ubi_attach+0x54/0xac)
[   97.625000] [<c0175998>] (ubi_attach+0x54/0xac) from [<c016b260>]
(ubi_attach_mtd_dev+0x1bc/0x474)
[   97.625000] [<c016b260>] (ubi_attach_mtd_dev+0x1bc/0x474) from
[<c016b758>] (ctrl_cdev_ioctl+0xd8/0x168)
[   97.625000] [<c016b758>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c0078684>] (do_vfs_ioctl+0x270/0x2ac)
[   97.625000] [<c0078684>] (do_vfs_ioctl+0x270/0x2ac) from
[<c00786f4>] (sys_ioctl+0x34/0x54)
[   97.625000] [<c00786f4>] (sys_ioctl+0x34/0x54) from [<c0009200>]
(ret_fast_syscall+0x0/0x2c)
[   97.625000] Code: e1a0200b ebfffe5b e250a000 1a000000 (e7f001f2)
[   97.625000] ---[ end trace 8743f692af56986c ]---
Segmentation fault

yet another one:
# ./ubiattach -m 0
[  159.718750] UBI: attaching mtd0 to ubi0
[  160.031250] UBI: scanning is finished
[  160.031250] UBI: empty MTD device detected
[  160.656250] UBI: attached mtd0 (name "NAND simulator partition 0",
size 128 MiB) to ubi0
[  160.664062] UBI: PEB size: 16384 bytes (16 KiB), LEB size: 15872 bytes
[  160.671875] UBI: min./max. I/O unit sizes: 512/512, sub-page size 256
[  160.679687] UBI: VID header offset: 256 (aligned 256), data offset: 512
[  160.687500] UBI: good PEBs: 8192, bad PEBs: 0, corrupted PEBs: 0
[  160.695312] UBI: user volume: 0, internal volumes: 1, max. volumes count: 92
[  160.703125] UBI: max/mean erase counter: 0/0, WL threshold: 4096,
image sequence number: 1661313839
[  160.710937] UBI: available PEBs: 8028, total reserved PEBs: 164,
PEBs reserved for bad PEB handling: 160
[  160.718750] UBI: background thread "ubi_bgt0d" started, PID 327
UBI device numb[  160.742187] Unable to handle kernel paging request
at virtual address 5af0c7b4
e[  160.750000] pgd = c0004000
r[  160.750000] [5af0c7b4] *pgd=00000000
0[  160.757812] Internal error: Oops: 5 [#1] ARM
[  160.757812] CPU: 0    Not tainted  (3.6.0-rc1+ #890)
[  160.757812] PC is at unlink_anon_vmas+0x2c/0x18c
[  160.757812] LR is at free_pgtables+0x28/0xa0
[  160.757812] pc : [<c0063a38>]    lr : [<c005b118>]    psr: 80000013
[  160.757812] sp : c7ab9eb0  ip : 00000880  fp : c0291e0f
[  160.757812] r10: b6eee000  r9 : 00100100  r8 : 5af0c7b4
[  160.757812] r7 : 6b30c7a5  r6 : c7abd8e0  r5 : 00000000  r4 : c7abfb7a
[  160.757812] r3 : c7abfb82  r2 : 00200000  r1 : 00008000  r0 : c7abd8a8
[  160.757812] Flags: Nzcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[  160.757812] Control: 0005317f  Table: 27ae4000  DAC: 00000015
[  160.757812] Process ubiattach (pid: 325, stack limit = 0xc7ab8270)
[  160.757812] Stack: (0xc7ab9eb0 to 0xc7aba000)
[  160.757812] 9ea0:                                     c7abd8a8
c7abd8a8 00200000 c7abd788
[  160.757812] 9ec0: 00000000 00001000 c7ab9f08 c7abd8a8 c7abd8a8
b6eee000 00000000 c005b118
[  160.757812] 9ee0: b6eee000 c7ad5600 c7ac82a0 c7ad5600 00000000
c7ac82d4 c0009388 c7ab8000
[  160.757812] 9f00: 00000000 c006024c c7ac82a0 00000001 00000000
c0008ea0 c78f27e0 00000000
[  160.757812] 9f20: 00000400 c7b36000 c78f27e0 c7ac82a0 00000001
c7ab8000 c78f27e0 c7ac82a0
[  160.757812] 9f40: c7ac82a0 00000000 c7ac82a0 00000000 00000000
c0014bd4 c7ac82a0 c7ac8000
[  160.757812] 9f60: 00000000 c0019914 c7ac8000 0000003d c7a46780
c7ac8000 00000000 00000001
[  160.757812] 9f80: 000000f8 c001af2c 00000000 00000000 b6f5c2ec
c001b0d0 b6f1e98c c001b10c
[  160.757812] 9fa0: 00000000 c0009200 b6f1e98c 00000000 00000000
00060d4c 00060d24 00000000
[  160.757812] 9fc0: b6f1e98c 00000000 b6f5c2ec 000000f8 00000000
00000000 b6f6ff70 00000000
[  160.757812] 9fe0: b6f5bebc be80bbf0 b6f42820 b6efb23c 60000010
00000000 00000000 00000000
[  160.757812] [<c0063a38>] (unlink_anon_vmas+0x2c/0x18c) from
[<c005b118>] (free_pgtables+0x28/0xa0)
[  160.757812] [<c005b118>] (free_pgtables+0x28/0xa0) from
[<c006024c>] (exit_mmap+0xcc/0x19c)
[  160.757812] [<c006024c>] (exit_mmap+0xcc/0x19c) from [<c0014bd4>]
(mmput+0x38/0xa8)
[  160.757812] [<c0014bd4>] (mmput+0x38/0xa8) from [<c0019914>]
(exit_mm+0xe8/0xec)
[  160.757812] [<c0019914>] (exit_mm+0xe8/0xec) from [<c001af2c>]
(do_exit+0x1d0/0x2c4)
[  160.757812] [<c001af2c>] (do_exit+0x1d0/0x2c4) from [<c001b0d0>]
(do_group_exit+0x84/0xb0)
[  160.757812] [<c001b0d0>] (do_group_exit+0x84/0xb0) from
[<c001b10c>] (sys_exit_group+0x10/0x18)
[  160.757812] [<c001b10c>] (sys_exit_group+0x10/0x18) from
[<c0009200>] (ret_fast_syscall+0x0/0x2c)
[  160.757812] Code: e59fb158 e59f9158 ea000028 e5948004 (e598a000)
,[  160.984375] ---[ end trace a5ec5c26278be2bc ]---
 [  160.992187] Fixing recursive fault but reboot is needed!
total 8192 LEBs (130023424 bytes, 124.0 MiB), available 8028 LEBs
(127420416 bytes, 121.5 MiB), LEB size 15872 bytes (15.5 KiB)

as you can see, the oops is not always at the same place, and does not
happened at the same moment
BUT something important I forgot to tell:
# flash_erase /dev/mtd0 0 8192
# ubiformat /dev/mtd0
# ubiattach -m 0
If I do a ubiformat after the flash_erase, I don't have an oops.

> We renamed all scan functions recently, so AFAICS you are not using the
> latest UBI code-base. How about picking the latest back-port tree?

Did the same thing, with the new UBI code, same result, once those are
not freed, I don't get oopses anymore.
diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index 64b9c56..6b9d6d8 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -340,8 +340,8 @@ retry:
         * of this LEB as it will be deleted and freed in 'ubi_add_to_av()'.
         */
        err = ubi_add_to_av(ubi, ai, new_aeb->pnum, new_aeb->ec, vid_hdr, 0);
-       kfree(new_aeb);
-       ubi_free_vid_hdr(ubi, vid_hdr);
+//     kfree(new_aeb);
+//     ubi_free_vid_hdr(ubi, vid_hdr);
        return err;

 write_error:

> This is strange, I think these 2 frees are all-right, I think the
> root-cause is somewhere else.
Yes, I didn't see neither the problem with those.
It's like the new_aeb and vid_hdr structs are still used after being
freed, but I couldn't find out where.

But once again, as I can't boot with a vanilla kernel or linux-ubi
kernel, I can't guarantee that this bug comes from UBI and not from
somewhere else.


here is the "minimal" .config I used:
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_GENERIC_BUG=y
CONFIG_HAVE_IRQ_WORK=y
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
CONFIG_HAVE_GENERIC_HARDIRQS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_IRQ_DOMAIN=y
CONFIG_SPARSE_IRQ=y
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_TINY_RCU=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
CONFIG_EXPERT=y
CONFIG_UID16=y
CONFIG_KALLSYMS=y
CONFIG_KALLSYMS_ALL=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_EMBEDDED=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_COMPAT_BRK=y
CONFIG_SLOB=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_RT_MUTEXES=y
CONFIG_BLOCK=y
CONFIG_MSDOS_PARTITION=y
CONFIG_IOSCHED_NOOP=y
CONFIG_DEFAULT_NOOP=y
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
CONFIG_INLINE_READ_UNLOCK=y
CONFIG_INLINE_READ_UNLOCK_IRQ=y
CONFIG_INLINE_WRITE_UNLOCK=y
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
CONFIG_MMU=y
CONFIG_ARCH_AT91=y
CONFIG_HAVE_AT91_DBGU0=y
CONFIG_AT91_SAM9_ALT_RESET=y
CONFIG_AT91_SAM9G45_RESET=y
CONFIG_SOC_AT91SAM9=y
CONFIG_SOC_AT91SAM9X5=y
CONFIG_ARCH_AT91SAM9X5=y
CONFIG_AT91_PMC_UNIT=y
CONFIG_MACH_AT91SAM_DT=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5TJ=y
CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_USE_DOMAINS=y
CONFIG_ARM_THUMB=y
CONFIG_MULTI_IRQ_HANDLER=y
CONFIG_VMSPLIT_3G=y
CONFIG_PREEMPT_NONE=y
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
CONFIG_HAVE_ARCH_PFN_VALID=y
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_VIRT_TO_BUS=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_ALIGNMENT_TRAP=y
CONFIG_UACCESS_WITH_MEMCPY=y
CONFIG_USE_OF=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_FPE_FASTFPE=y
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_HAVE_AOUT=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_INET_LRO=y
CONFIG_BQL=y
CONFIG_HAVE_BPF_JIT=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_OF_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_IDS=y
CONFIG_MTD_NAND_NANDSIM=y
CONFIG_MTD_UBI=y
CONFIG_DTC=y
CONFIG_OF=y
CONFIG_PROC_DEVICETREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_DEVICE=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
CONFIG_BLK_DEV=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_SCSI_MOD=y
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
CONFIG_MII=y
CONFIG_ETHERNET=y
CONFIG_HAVE_NET_MACB=y
CONFIG_NET_CADENCE=y
CONFIG_MACB=y
CONFIG_PHYLIB=y
CONFIG_DAVICOM_PHY=y
CONFIG_INPUT=y
CONFIG_SERIO=y
CONFIG_SERIO_SERPORT=y
CONFIG_SERIO_LIBPS2=y
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_UNIX98_PTYS=y
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_PINCTRL=y
CONFIG_PINMUX=y
CONFIG_PINCTRL_AT91=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_OF_GPIO=y
CONFIG_SSB_POSSIBLE=y
CONFIG_BCMA_POSSIBLE=y
CONFIG_HAVE_FB_ATMEL=y
CONFIG_DUMMY_CONSOLE=y
CONFIG_HID=y
CONFIG_HIDRAW=y
CONFIG_HID_GENERIC=y
CONFIG_USB_ARCH_HAS_OHCI=y
CONFIG_USB_ARCH_HAS_EHCI=y
CONFIG_RTC_LIB=y
CONFIG_CLKDEV_LOOKUP=y
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
CONFIG_FANOTIFY=y
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
CONFIG_ROOT_NFS=y
CONFIG_LOCKD=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_INFO=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_ARM_UNWIND=y
CONFIG_DEBUG_USER=y
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_CRC32=y
CONFIG_CRC32_SLICEBY8=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y


From artem.bityutskiy at linux.intel.com  Mon Sep  3 07:20:21 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 14:20:21 +0300
Subject: TR: Notification d'envoi de fichier via http://dl.free.fr
In-Reply-To: <003d01cd877e$39b71020$ad253060$@ercogener.com>
References: <20120831133153.764EC3495D9@dl.free.fr>
 <003d01cd877e$39b71020$ad253060$@ercogener.com>
Message-ID: <1346671221.3061.42.camel@sauron.fi.intel.com>

[CCing the MTD ML]

Mounts fine on nandsim + the latest UBIFS kernel (linux-ubifs), and all
files are readable - checked with rsync.

$ sudo modprobe nandsim first_id_byte=0x20 second_id_byte=0xaa third_id_byte=0x00 fourth_id_byte=0x15
$ sudo modprobe mtdchar
$ sudo dd if=~/tmp/Angstrom-fabien-image-eglibc-ipk-v2011.09-at91sam9260ek.rootfs.ubi of=/dev/mtd0 bs=2048
$ sudo modprobe ubi mtd=0
$ sudo mount -t ubifs /dev/ubi0_0  /mnt/ubifs/
$ dmesg | tail
....
[ 3980.001332] NAND device: Manufacturer ID: 0x20, Chip ID: 0xaa (ST Micro NAND 256MiB 1,8V 8-bit), page size: 2048, OOB size: 64
[ 3980.001337] flash size: 256 MiB
[ 3980.001338] page size: 2048 bytes
[ 3980.001346] OOB area size: 64 bytes
[ 3980.001347] sector size: 128 KiB
[ 3980.001348] pages number: 131072
[ 3980.001349] pages per sector: 64
[ 3980.001350] bus width: 8
[ 3980.001351] bits in sector size: 17
[ 3980.001351] bits in page size: 11
[ 3980.001352] bits in OOB size: 6
[ 3980.001353] flash size with OOB: 270336 KiB
[ 3980.001354] page address bytes: 5
[ 3980.001355] sector address bytes: 3
[ 3980.001355] options: 0x8
[ 3980.001616] Scanning device for bad blocks
[ 3980.005765] Creating 1 MTD partitions on "NAND 256MiB 1,8V 8-bit":
[ 3980.005769] 0x000000000000-0x000010000000 : "NAND simulator partition 0"
[ 4075.066153] UBI: attaching mtd0 to ubi0
[ 4075.070304] UBI: scanning is finished
[ 4075.071382] UBI: volume 0 ("at91sam9260ek-rootfs") re-sized from 543 to 2004 LEBs
[ 4075.072470] UBI: attached mtd0 (name "NAND simulator partition 0", size 256 MiB) to ubi0
[ 4075.072472] UBI: PEB size: 131072 bytes (128 KiB), LEB size: 129024 bytes
[ 4075.072473] UBI: min./max. I/O unit sizes: 2048/2048, sub-page size 512
[ 4075.072474] UBI: VID header offset: 512 (aligned 512), data offset: 2048
[ 4075.072475] UBI: good PEBs: 2048, bad PEBs: 0, corrupted PEBs: 0
[ 4075.072476] UBI: user volume: 1, internal volumes: 1, max. volumes count: 128
[ 4075.072478] UBI: max/mean erase counter: 1/0, WL threshold: 4096, image sequence number: 383215587
[ 4075.072479] UBI: available PEBs: 0, total reserved PEBs: 2048, PEBs reserved for bad PEB handling: 40
[ 4075.072528] UBI: background thread "ubi_bgt0d" started, PID 13967
[ 4091.803787] UBIFS: background thread "ubifs_bgt0_0" started, PID 13989
[ 4091.804518] UBIFS: mounted UBI device 0, volume 0, name "at91sam9260ek-rootfs"(null)
[ 4091.804521] UBIFS: LEB size: 129024 bytes (126 KiB), min./max. I/O unit sizes: 2048 bytes/2048 bytes
[ 4091.804522] UBIFS: FS size: 254564352 bytes (242 MiB, 1973 LEBs), journal size 9033728 bytes (8 MiB, 71 LEBs)
[ 4091.804524] UBIFS: reserved for root: 0 bytes (0 KiB)
[ 4091.804526] UBIFS: media format: w4/r0 (latest is w4/r0), UUID 6E97ED8D-B37E-4C41-8521-B7840B684C1B, small LPT model

$ [dedekind at np linux-ubifs (test)]$ ls -l /mnt/ubifs/
total 0
drwxrwxr-x  2 root root  9048 Sep 16  2011 bin
drwxrwxr-x  2 root root   160 Sep 16  2011 boot
drwxr-xr-x  3 root root  4896 Sep  3  2011 dev
drwxr-xr-x 39 root root  5952 Sep 16  2011 etc
drwxrwxr-x  3 root root   224 Sep 16  2011 home
drwxrwxr-x  6 root root  2760 Sep 16  2011 lib
lrwxrwxrwx  1 root root    12 Sep 16  2011 linuxrc -> /bin/busybox
drwxrwxr-x 10 root root   680 Sep 16  2011 media
drwxrwxr-x  2 root root   416 Sep 16  2011 mnt
drwxr-xr-x  2 root root   160 Sep  3  2011 proc
drwxrwxr-x  2 root root 10008 Sep 16  2011 sbin
drwxr-xr-x  2 root root   160 Sep  3  2011 sys
drwxrwxrwt  2 root root   160 Sep  3  2011 tmp
drwxrwxr-x 10 root root   672 Sep  3  2011 usr
drwxrwxr-x 10 root root  1000 Sep  3  2011 var
[dedekind at np linux-ubifs (test)]$ ls -l /mnt/ubifs/home/
total 0
drwxr-xr-x 2 root root 376 Sep 16  2011 root
[dedekind at np linux-ubifs (test)]$ ls -l /mnt/ubifs/home/root/
total 56
-rwxr-xr-x 1 root root  6640 Sep 16  2011 auto_install.sh
-rwxr-xr-x 1 root root 21868 Sep 16  2011 fw_printenv
-rwxr-xr-x 1 root root 21868 Sep 16  2011 fw_setenv

$ sudo rsync -aH --delete --devices --specials /mnt/ubifs /tmp/ubifs


Please, check yourself on ubifs-v2.6.37 if it works the same way. Weird
why it does not work for you.

Also, you never sent me the full log. Please, _before_ mounting, enable
debugging prints:

1. modprobe ubifs
2. echo 'format "UBIFS DBG" +pf' > /sys/kernel/debug/dynamic_debug/control
3. mount

then type "dmesg" and send full log please.

Thanks!


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/8829e2b7/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 07:53:00 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 14:53:00 +0300
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346659239.3061.17.camel@sauron.fi.intel.com>
 <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>
Message-ID: <1346673180.3061.44.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 12:57 +0200, Richard Genoud wrote:
> > If you could somehow reproduce this with nandsim, it would make it easy
> > for me to find the bug.
> here it is:
> [    0.921875] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.929687] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.937500] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.953125] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.960937] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.968750] [nandsim] warning: read_byte: unexpected data output
> cycle, state is STATE_READY return 0x0
> [    0.976562] NAND device: Manufacturer ID: 0x98, Chip ID: 0x39
> (Toshiba NAND 128MiB 1,8V 8-bit), page size: 512, OOB size: 16
> [    0.992187] flash size: 128 MiB
> [    0.992187] page size: 512 bytes
> [    0.992187] OOB area size: 16 bytes
> [    1.000000] sector size: 16 KiB
> [    1.000000] pages number: 262144
> [    1.007812] pages per sector: 32
> [    1.007812] bus width: 8
> [    1.007812] bits in sector size: 14
> [    1.015625] bits in page size: 9
> [    1.015625] bits in OOB size: 4
> [    1.023437] flash size with OOB: 135168 KiB
> [    1.023437] page address bytes: 4
> [    1.031250] sector address bytes: 3
> [    1.031250] options: 0x42
> [    1.039062] Scanning device for bad blocks
> [    1.242187] Creating 1 MTD partitions on "NAND 128MiB 1,8V 8-bit":
> [    1.250000] 0x000000000000-0x000008000000 : "NAND simulator partition 0"
> 
> # flash_erase /dev/mtd0 0 8192

Hmm, cannot reproduce on my x86_64.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/c26f99d5/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 07:54:45 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 14:54:45 +0300
Subject: TR: Notification d'envoi de fichier via http://dl.free.fr
In-Reply-To: <1346671221.3061.42.camel@sauron.fi.intel.com>
References: <20120831133153.764EC3495D9@dl.free.fr>
 <003d01cd877e$39b71020$ad253060$@ercogener.com>
 <1346671221.3061.42.camel@sauron.fi.intel.com>
Message-ID: <1346673285.3061.46.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 14:20 +0300, Artem Bityutskiy wrote:
> Also, you never sent me the full log. Please, _before_ mounting, enable
> debugging prints:
> 
> 1. modprobe ubifs
> 2. echo 'format "UBIFS DBG" +pf' > /sys/kernel/debug/dynamic_debug/control
> 3. mount
> 
> then type "dmesg" and send full log please.

Also note, I am using x86_64 PC.

Can you try to take the ubifs-v3.0 tree and try to reproduce the issue?

If it is reproducible, then we can find the guilty commit using git
bisect.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/3adda142/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 07:56:25 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 14:56:25 +0300
Subject: UBIFS Informations
In-Reply-To: <503F7685.8030707@gmail.com>
References: <503F7685.8030707@gmail.com>
Message-ID: <1346673385.3061.48.camel@sauron.fi.intel.com>

On Thu, 2012-08-30 at 16:19 +0200, simon widmer wrote:
> Hej,
> 
> is there any possibility to extract the compile options of a ubinized 
> UBIFS? My problem is that I have an embedded system where some UBIFS run 
> on, I have an old UBIFS which I can easily put on a volume 
> (ubiupdatevol) and which runs perfectly. I had to make a new image, 
> taking the parameters i wrote down and its now working, i end with an error
>      UBIFS error (pid 946): ubifs_read_node: bad node type (255 but 
> expected 6)
>      UBIFS error (pid 946): ubifs_read_node: bad node at LEB 0:0
> either the node is 255 either 0 instead of 6.

You are the second person complaining about this. What is the kernel
version your image worked fine with?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/d3b5083f/attachment.sig>

From akinobu.mita at gmail.com  Mon Sep  3 08:59:58 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 21:59:58 +0900
Subject: [PATCH v3 03/11] mtd: mtd_nandecctest: remove unnecessary include
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-4-git-send-email-akinobu.mita@gmail.com>

Including linux/jiffies.h was required for calling srandom32(jiffies)
that has already been removed.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index f71ed92..1051b48 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -4,7 +4,6 @@
 #include <linux/random.h>
 #include <linux/string.h>
 #include <linux/bitops.h>
-#include <linux/jiffies.h>
 #include <linux/mtd/nand_ecc.h>
 
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 08:59:57 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 21:59:57 +0900
Subject: [PATCH v3 02/11] mtd: mtd_nandecctest: make module_init() return an
 error code if test fails
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-3-git-send-email-akinobu.mita@gmail.com>

Return an error code if test fails in order to detect a test case failure
by invoking tests repeatedly like this:

while sudo modprobe mtd_nandecctest; do
	sudo modprobe -r mtd_nandecctest
done

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 4d7b171..f71ed92 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -66,10 +66,13 @@ static int nand_ecc_test(const size_t size)
 
 static int __init ecc_test_init(void)
 {
-	nand_ecc_test(256);
-	nand_ecc_test(512);
+	int err;
 
-	return 0;
+	err = nand_ecc_test(256);
+	if (err)
+		return err;
+
+	return nand_ecc_test(512);
 }
 
 static void __exit ecc_test_exit(void)
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 08:59:56 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 21:59:56 +0900
Subject: [PATCH v3 01/11] mtd: mtd_nandecctest: remove unnecessary srandom32()
 call
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-2-git-send-email-akinobu.mita@gmail.com>

It is unnecessary for this driver to call srandom32() in module_init.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 70d6d7d..4d7b171 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -66,8 +66,6 @@ static int nand_ecc_test(const size_t size)
 
 static int __init ecc_test_init(void)
 {
-	srandom32(jiffies);
-
 	nand_ecc_test(256);
 	nand_ecc_test(512);
 
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 08:59:59 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 21:59:59 +0900
Subject: [PATCH v3 04/11] mtd: mtd_nandecctest: make module_init() return
 appropriate errno
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-5-git-send-email-akinobu.mita@gmail.com>

Return -EINVAL instead of -1 (-EPERM) when test fails.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 1051b48..128547c 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -51,7 +51,7 @@ static int nand_ecc_test(const size_t size)
 	print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 4,
 			error_data, size, false);
 
-	return -1;
+	return -EINVAL;
 }
 
 #else
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 08:59:55 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 21:59:55 +0900
Subject: [PATCH v3 00/11] mtd: mtd_nandecctest: add more tests
Message-ID: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>

This patch series adds several tests cases to mtd_nandecctest module
and includes several minor changes.

Changelog
* v3
- remove unnecessary include
- split into still smaller patches

* v2
- split one patch into smaller patches

Akinobu Mita (11):
  mtd: mtd_nandecctest: remove unnecessary srandom32() call
  mtd: mtd_nandecctest: make module_init() return an error code if test
    fails
  mtd: mtd_nandecctest: remove unnecessary include
  mtd: mtd_nandecctest: make module_init() return appropriate errno
  mtd: mtd_nandecctest: improve message output
  mtd: mtd_nandecctest: ensure alignment requirement for bitops
  mtd: mtd_nandecctest: generalize injecting bit errors function for
    ecc code
  mtd: mtd_nandecctest: rewrite the test routine
  mtd: mtd_nandecctest: add no corruption test
  mtd: mtd_nandecctest: add single bit error correction test
  mtd: mtd_nandecctest: add double bit error detection tests

 drivers/mtd/tests/mtd_nandecctest.c | 280 +++++++++++++++++++++++++++++++-----
 1 file changed, 247 insertions(+), 33 deletions(-)

Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:00 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:00 +0900
Subject: [PATCH v3 05/11] mtd: mtd_nandecctest: improve message output
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-6-git-send-email-akinobu.mita@gmail.com>

This includes the message related changes:

- Use pr_* instead of printk
- Print hexdump of ECC code if test fails
- Change log level for hexdump of data from KERN_DEBUG to KERN_INFO
- Factor out the hexdump code into a separate function

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 48 ++++++++++++++++++++++---------------
 1 file changed, 29 insertions(+), 19 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 128547c..2b2d1a9 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -15,41 +15,51 @@ static void inject_single_bit_error(void *data, size_t size)
 	__change_bit(offset, data);
 }
 
-static unsigned char data[512];
+static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
+			void *correct_ecc, const size_t size)
+{
+	pr_info("hexdump of error data:\n");
+	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
+			error_data, size, false);
+	print_hex_dump(KERN_INFO, "hexdump of error ecc: ",
+			DUMP_PREFIX_NONE, 16, 1, error_ecc, 3, false);
+
+	pr_info("hexdump of correct data:\n");
+	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 4,
+			correct_data, size, false);
+	print_hex_dump(KERN_INFO, "hexdump of correct ecc: ",
+			DUMP_PREFIX_NONE, 16, 1, correct_ecc, 3, false);
+}
+
+static unsigned char correct_data[512];
 static unsigned char error_data[512];
 
 static int nand_ecc_test(const size_t size)
 {
-	unsigned char code[3];
-	unsigned char error_code[3];
+	unsigned char correct_ecc[3];
+	unsigned char error_ecc[3];
 	char testname[30];
 
-	BUG_ON(sizeof(data) < size);
+	BUG_ON(sizeof(correct_data) < size);
 
 	sprintf(testname, "nand-ecc-%zu", size);
 
-	get_random_bytes(data, size);
+	get_random_bytes(correct_data, size);
 
-	memcpy(error_data, data, size);
+	memcpy(error_data, correct_data, size);
 	inject_single_bit_error(error_data, size);
 
-	__nand_calculate_ecc(data, size, code);
-	__nand_calculate_ecc(error_data, size, error_code);
-	__nand_correct_data(error_data, code, error_code, size);
+	__nand_calculate_ecc(correct_data, size, correct_ecc);
+	__nand_calculate_ecc(error_data, size, error_ecc);
+	__nand_correct_data(error_data, correct_ecc, error_ecc, size);
 
-	if (!memcmp(data, error_data, size)) {
-		printk(KERN_INFO "mtd_nandecctest: ok - %s\n", testname);
+	if (!memcmp(correct_data, error_data, size)) {
+		pr_info("mtd_nandecctest: ok - %s\n", testname);
 		return 0;
 	}
 
-	printk(KERN_ERR "mtd_nandecctest: not ok - %s\n", testname);
-
-	printk(KERN_DEBUG "hexdump of data:\n");
-	print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 4,
-			data, size, false);
-	printk(KERN_DEBUG "hexdump of error data:\n");
-	print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 4,
-			error_data, size, false);
+	pr_err("mtd_nandecctest: not ok - %s\n", testname);
+	dump_data_ecc(error_data, error_ecc, correct_data, correct_ecc, size);
 
 	return -EINVAL;
 }
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:01 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:01 +0900
Subject: [PATCH v3 06/11] mtd: mtd_nandecctest: ensure alignment requirement
 for bitops
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-7-git-send-email-akinobu.mita@gmail.com>

Currently the data blocks which is used to test single bit error
correction is allocated statically and injecting single bit error is
implemented by using __change_bit() which must operate on the memory
aligned to the size of an "unsigned long".  But there is no such
guarantee for statically allocated array.

This fix the issue by allocating the data block dynamically by
kmalloc().  It also allocate the ecc code dynamically instead of
allocating statically on stack.

The reason to allocate the ecc code dynamically is that later change
will add tests which inject bit errors into the ecc code by bitops.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 43 +++++++++++++++++++++++++------------
 1 file changed, 29 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 2b2d1a9..d3e8873 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -4,6 +4,7 @@
 #include <linux/random.h>
 #include <linux/string.h>
 #include <linux/bitops.h>
+#include <linux/slab.h>
 #include <linux/mtd/nand_ecc.h>
 
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
@@ -31,16 +32,24 @@ static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
 			DUMP_PREFIX_NONE, 16, 1, correct_ecc, 3, false);
 }
 
-static unsigned char correct_data[512];
-static unsigned char error_data[512];
-
 static int nand_ecc_test(const size_t size)
 {
-	unsigned char correct_ecc[3];
-	unsigned char error_ecc[3];
+	int err = 0;
+	void *error_data;
+	void *error_ecc;
+	void *correct_data;
+	void *correct_ecc;
 	char testname[30];
 
-	BUG_ON(sizeof(correct_data) < size);
+	error_data = kmalloc(size, GFP_KERNEL);
+	error_ecc = kmalloc(3, GFP_KERNEL);
+	correct_data = kmalloc(size, GFP_KERNEL);
+	correct_ecc = kmalloc(3, GFP_KERNEL);
+
+	if (!error_data || !error_ecc || !correct_data || !correct_ecc) {
+		err = -ENOMEM;
+		goto error;
+	}
 
 	sprintf(testname, "nand-ecc-%zu", size);
 
@@ -53,15 +62,21 @@ static int nand_ecc_test(const size_t size)
 	__nand_calculate_ecc(error_data, size, error_ecc);
 	__nand_correct_data(error_data, correct_ecc, error_ecc, size);
 
-	if (!memcmp(correct_data, error_data, size)) {
-		pr_info("mtd_nandecctest: ok - %s\n", testname);
-		return 0;
+	if (memcmp(correct_data, error_data, size)) {
+		pr_err("mtd_nandecctest: not ok - %s\n", testname);
+		dump_data_ecc(error_data, error_ecc, correct_data, correct_ecc,
+				size);
+		err = -EINVAL;
+		goto error;
 	}
-
-	pr_err("mtd_nandecctest: not ok - %s\n", testname);
-	dump_data_ecc(error_data, error_ecc, correct_data, correct_ecc, size);
-
-	return -EINVAL;
+	pr_info("mtd_nandecctest: ok - %s\n", testname);
+error:
+	kfree(error_data);
+	kfree(error_ecc);
+	kfree(correct_data);
+	kfree(correct_ecc);
+
+	return err;
 }
 
 #else
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:02 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:02 +0900
Subject: [PATCH v3 07/11] mtd: mtd_nandecctest: generalize injecting bit
 errors function for ecc code
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-8-git-send-email-akinobu.mita@gmail.com>

In order to inject deliberate bit errors into the ecc code which only
has 3 bytes, this adjusts the bitops usage in inject_single_bit_error()
which is currently only used for injecting into the 256 or 512 bytes
data block.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index d3e8873..0274f73 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -7,13 +7,22 @@
 #include <linux/slab.h>
 #include <linux/mtd/nand_ecc.h>
 
+#include <asm/byteorder.h>
+
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
 
+#ifdef __LITTLE_ENDIAN
+#define __change_bit_le(nr, addr) __change_bit(nr, addr)
+#else
+#define __change_bit_le(nr, addr) \
+		__change_bit((nr) ^ ((BITS_PER_LONG - 1) & ~0x7), addr)
+#endif
+
 static void inject_single_bit_error(void *data, size_t size)
 {
-	unsigned long offset = random32() % (size * BITS_PER_BYTE);
+	unsigned int offset = random32() % (size * BITS_PER_BYTE);
 
-	__change_bit(offset, data);
+	__change_bit_le(offset, data);
 }
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:03 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:03 +0900
Subject: [PATCH v3 08/11] mtd: mtd_nandecctest: rewrite the test routine
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-9-git-send-email-akinobu.mita@gmail.com>

This rewrites the entire test routine in order to make it easy to add more
tests by later changes and minimize duplication of each tests as much as
possible.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/tests/mtd_nandecctest.c | 83 +++++++++++++++++++++++++++----------
 1 file changed, 60 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 0274f73..65cec2a 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -11,6 +11,12 @@
 
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
 
+struct nand_ecc_test {
+	const char *name;
+	void (*prepare)(void *, void *, void *, void *, const size_t);
+	int (*verify)(void *, void *, void *, const size_t);
+};
+
 #ifdef __LITTLE_ENDIAN
 #define __change_bit_le(nr, addr) __change_bit(nr, addr)
 #else
@@ -18,13 +24,44 @@
 		__change_bit((nr) ^ ((BITS_PER_LONG - 1) & ~0x7), addr)
 #endif
 
-static void inject_single_bit_error(void *data, size_t size)
+static void single_bit_error_data(void *error_data, void *correct_data,
+				size_t size)
 {
 	unsigned int offset = random32() % (size * BITS_PER_BYTE);
 
-	__change_bit_le(offset, data);
+	memcpy(error_data, correct_data, size);
+	__change_bit_le(offset, error_data);
+}
+
+static void single_bit_error_in_data(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	single_bit_error_data(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
 }
 
+static int single_bit_error_correct(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, calc_ecc, error_ecc, size);
+	if (ret == 1 && !memcmp(correct_data, error_data, size))
+		return 0;
+
+	return -EINVAL;
+}
+
+static const struct nand_ecc_test nand_ecc_test[] = {
+	{
+		.name = "single-bit-error-in-data-correct",
+		.prepare = single_bit_error_in_data,
+		.verify = single_bit_error_correct,
+	},
+};
+
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
 			void *correct_ecc, const size_t size)
 {
@@ -41,14 +78,14 @@ static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
 			DUMP_PREFIX_NONE, 16, 1, correct_ecc, 3, false);
 }
 
-static int nand_ecc_test(const size_t size)
+static int nand_ecc_test_run(const size_t size)
 {
+	int i;
 	int err = 0;
 	void *error_data;
 	void *error_ecc;
 	void *correct_data;
 	void *correct_ecc;
-	char testname[30];
 
 	error_data = kmalloc(size, GFP_KERNEL);
 	error_ecc = kmalloc(3, GFP_KERNEL);
@@ -60,25 +97,25 @@ static int nand_ecc_test(const size_t size)
 		goto error;
 	}
 
-	sprintf(testname, "nand-ecc-%zu", size);
-
 	get_random_bytes(correct_data, size);
-
-	memcpy(error_data, correct_data, size);
-	inject_single_bit_error(error_data, size);
-
 	__nand_calculate_ecc(correct_data, size, correct_ecc);
-	__nand_calculate_ecc(error_data, size, error_ecc);
-	__nand_correct_data(error_data, correct_ecc, error_ecc, size);
-
-	if (memcmp(correct_data, error_data, size)) {
-		pr_err("mtd_nandecctest: not ok - %s\n", testname);
-		dump_data_ecc(error_data, error_ecc, correct_data, correct_ecc,
-				size);
-		err = -EINVAL;
-		goto error;
+
+	for (i = 0; i < ARRAY_SIZE(nand_ecc_test); i++) {
+		nand_ecc_test[i].prepare(error_data, error_ecc,
+				correct_data, correct_ecc, size);
+		err = nand_ecc_test[i].verify(error_data, error_ecc,
+						correct_data, size);
+
+		if (err) {
+			pr_err("mtd_nandecctest: not ok - %s-%zd\n",
+				nand_ecc_test[i].name, size);
+			dump_data_ecc(error_data, error_ecc,
+				correct_data, correct_ecc, size);
+			break;
+		}
+		pr_info("mtd_nandecctest: ok - %s-%zd\n",
+			nand_ecc_test[i].name, size);
 	}
-	pr_info("mtd_nandecctest: ok - %s\n", testname);
 error:
 	kfree(error_data);
 	kfree(error_ecc);
@@ -90,7 +127,7 @@ error:
 
 #else
 
-static int nand_ecc_test(const size_t size)
+static int nand_ecc_test_run(const size_t size)
 {
 	return 0;
 }
@@ -101,11 +138,11 @@ static int __init ecc_test_init(void)
 {
 	int err;
 
-	err = nand_ecc_test(256);
+	err = nand_ecc_test_run(256);
 	if (err)
 		return err;
 
-	return nand_ecc_test(512);
+	return nand_ecc_test_run(512);
 }
 
 static void __exit ecc_test_exit(void)
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:04 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:04 +0900
Subject: [PATCH v3 09/11] mtd: mtd_nandecctest: add no corruption test
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-10-git-send-email-akinobu.mita@gmail.com>

This adds no corruptin test case listed below:

Prepare data block and ECC data with no corruption, and verify that
the data block is preserved by __nand_correct_data()

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 65cec2a..1d1af09 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -33,6 +33,27 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static void no_bit_error(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
+}
+
+static int no_bit_error_verify(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, calc_ecc, error_ecc, size);
+	if (ret == 0 && !memcmp(correct_data, error_data, size))
+		return 0;
+
+	return -EINVAL;
+}
+
 static void single_bit_error_in_data(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -56,6 +77,11 @@ static int single_bit_error_correct(void *error_data, void *error_ecc,
 
 static const struct nand_ecc_test nand_ecc_test[] = {
 	{
+		.name = "no-bit-error",
+		.prepare = no_bit_error,
+		.verify = no_bit_error_verify,
+	},
+	{
 		.name = "single-bit-error-in-data-correct",
 		.prepare = single_bit_error_in_data,
 		.verify = single_bit_error_correct,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:05 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:05 +0900
Subject: [PATCH v3 10/11] mtd: mtd_nandecctest: add single bit error
 correction test
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-11-git-send-email-akinobu.mita@gmail.com>

This adds the single bit error correction test case listed below:

Prepare data block without corruption and ECC data with single bit error,
and verify that the data block is preserved by __nand_correct_data().

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 1d1af09..77ba479 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -33,6 +33,31 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static unsigned int random_ecc_bit(size_t size)
+{
+	unsigned int offset = random32() % (3 * BITS_PER_BYTE);
+
+	if (size == 256) {
+		/*
+		 * Don't inject a bit error into the insignificant bits (16th
+		 * and 17th bit) in ECC code for 256 byte data block
+		 */
+		while (offset == 16 || offset == 17)
+			offset = random32() % (3 * BITS_PER_BYTE);
+	}
+
+	return offset;
+}
+
+static void single_bit_error_ecc(void *error_ecc, void *correct_ecc,
+				size_t size)
+{
+	unsigned int offset = random_ecc_bit(size);
+
+	memcpy(error_ecc, correct_ecc, 3);
+	__change_bit_le(offset, error_ecc);
+}
+
 static void no_bit_error(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -61,6 +86,13 @@ static void single_bit_error_in_data(void *error_data, void *error_ecc,
 	memcpy(error_ecc, correct_ecc, 3);
 }
 
+static void single_bit_error_in_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	single_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
 static int single_bit_error_correct(void *error_data, void *error_ecc,
 				void *correct_data, const size_t size)
 {
@@ -86,6 +118,11 @@ static const struct nand_ecc_test nand_ecc_test[] = {
 		.prepare = single_bit_error_in_data,
 		.verify = single_bit_error_correct,
 	},
+	{
+		.name = "single-bit-error-in-ecc-correct",
+		.prepare = single_bit_error_in_ecc,
+		.verify = single_bit_error_correct,
+	},
 };
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Mon Sep  3 09:00:06 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Mon,  3 Sep 2012 22:00:06 +0900
Subject: [PATCH v3 11/11] mtd: mtd_nandecctest: add double bit error detection
 tests
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346677206-13621-12-git-send-email-akinobu.mita@gmail.com>

This adds the double bit error detection test cases listed below:

* Prepare data block with double bit error and ECC data without
corruption, and verify that the uncorrectable error is detected by
__nand_correct_data().

* Prepare data block with single bit error and ECC data with single bit
error, and verify that the uncorrectable error is detected.

* Prepare data block without corruption and ECC data with double bit
error, and verify that the uncorrectable error is detected.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 80 +++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 77ba479..b2c95c7 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -33,6 +33,22 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static void double_bit_error_data(void *error_data, void *correct_data,
+				size_t size)
+{
+	unsigned int offset[2];
+
+	offset[0] = random32() % (size * BITS_PER_BYTE);
+	do {
+		offset[1] = random32() % (size * BITS_PER_BYTE);
+	} while (offset[0] == offset[1]);
+
+	memcpy(error_data, correct_data, size);
+
+	__change_bit_le(offset[0], error_data);
+	__change_bit_le(offset[1], error_data);
+}
+
 static unsigned int random_ecc_bit(size_t size)
 {
 	unsigned int offset = random32() % (3 * BITS_PER_BYTE);
@@ -58,6 +74,21 @@ static void single_bit_error_ecc(void *error_ecc, void *correct_ecc,
 	__change_bit_le(offset, error_ecc);
 }
 
+static void double_bit_error_ecc(void *error_ecc, void *correct_ecc,
+				size_t size)
+{
+	unsigned int offset[2];
+
+	offset[0] = random_ecc_bit(size);
+	do {
+		offset[1] = random_ecc_bit(size);
+	} while (offset[0] == offset[1]);
+
+	memcpy(error_ecc, correct_ecc, 3);
+	__change_bit_le(offset[0], error_ecc);
+	__change_bit_le(offset[1], error_ecc);
+}
+
 static void no_bit_error(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -107,6 +138,40 @@ static int single_bit_error_correct(void *error_data, void *error_ecc,
 	return -EINVAL;
 }
 
+static void double_bit_error_in_data(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	double_bit_error_data(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
+}
+
+static void single_bit_error_in_data_and_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	single_bit_error_data(error_data, correct_data, size);
+	single_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
+static void double_bit_error_in_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	double_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
+static int double_bit_error_detect(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, calc_ecc, error_ecc, size);
+
+	return (ret == -1) ? 0 : -EINVAL;
+}
+
 static const struct nand_ecc_test nand_ecc_test[] = {
 	{
 		.name = "no-bit-error",
@@ -123,6 +188,21 @@ static const struct nand_ecc_test nand_ecc_test[] = {
 		.prepare = single_bit_error_in_ecc,
 		.verify = single_bit_error_correct,
 	},
+	{
+		.name = "double-bit-error-in-data-detect",
+		.prepare = double_bit_error_in_data,
+		.verify = double_bit_error_detect,
+	},
+	{
+		.name = "single-bit-error-in-data-and-ecc-detect",
+		.prepare = single_bit_error_in_data_and_ecc,
+		.verify = double_bit_error_detect,
+	},
+	{
+		.name = "double-bit-error-in-ecc-detect",
+		.prepare = double_bit_error_in_ecc,
+		.verify = double_bit_error_detect,
+	},
 };
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From richard.genoud at gmail.com  Mon Sep  3 09:14:32 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 3 Sep 2012 15:14:32 +0200
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <1346673180.3061.44.camel@sauron.fi.intel.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346659239.3061.17.camel@sauron.fi.intel.com>
 <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>
 <1346673180.3061.44.camel@sauron.fi.intel.com>
Message-ID: <CACQ1gAjeNq5zNKzSbO_eeDG7ahhBc9mNvMf_s4RadrWSq-5taQ@mail.gmail.com>

I finally managed to reproduced it on linux-ubi/master + only one
patch to make my board boot:
(I thought it needed much more code than that...)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c8050b1..c6eb877 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -141,6 +141,10 @@ config ARCH_AT91SAM9G45
	bool "AT91SAM9G45"
	select SOC_AT91SAM9G45

+config ARCH_AT91SAM9X5
+	bool "AT91SAM9x5"
+	select SOC_AT91SAM9X5
+
 config ARCH_AT91X40
	bool "AT91x40"
	depends on !MMU

The 1st try was a complete hang, with no trace at all. And here are 3
differents oops:

# flash_erase /dev/mtd0 0 8192
Erasing 16 Kibyte @ 7ffc000 -- 100 % complete
# ubiattach -m 0
[  162.984375] UBI: attaching mtd0 to ubi0
[  163.273437] UBI: scanning is finished
[  163.273437] UBI: empty MTD device detected
[  163.289062] ------------[ cut here ]------------
[  163.289062] kernel BUG at mm/slob.c:331!
[  163.289062] Internal error: Oops - BUG: 0 [#1] ARM
[  163.289062] CPU: 0    Not tainted  (3.6.0-rc1+ #893)
[  163.289062] PC is at slob_alloc.clone.18+0x17c/0x1c0
[  163.289062] LR is at slob_page_alloc+0x1a8/0x1d0
[  163.289062] pc : [<c006c23c>]    lr : [<c006bd28>]    psr: 60000093
[  163.289062] sp : c740fd30  ip : 00000000  fp : 04f20014
[  163.289062] r10: 00000000  r9 : a0000013  r8 : 00007406
[  163.289062] r7 : c02a5000  r6 : 00000030  r5 : c038d0c0  r4 : c0281c70
[  163.289062] r3 : 04f20014  r2 : 04f20013  r1 : fb0dffec  r0 : 00000000
[  163.289062] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[  163.289062] Control: 0005317f  Table: 27a9c000  DAC: 00000015
[  163.289062] Process ubiattach (pid: 336, stack limit = 0xc740e270)
[  163.289062] Stack: (0xc740fd30 to 0xc7410000)
[  163.289062] fd20:                                     00000030
000000d0 04f20014 c7aac9c0
[  163.289062] fd40: 00000000 c7401060 c7aac940 c74010b4 c7ac1960
c74010b0 00000000 c006c4a8
[  163.289062] fd60: 00000000 c7b2b560 00000000 c013a6b8 00003e00
c01378dc 00003e00 c740fdac
[  163.289062] fd80: c8970000 c7b2b560 00000002 00000000 00000001
7fffefff 00000001 00000000
[  163.289062] fda0: 00000001 02000200 c7aac940 00000001 00000000
c7b2b560 c7aace08 c7ac1960
[  163.289062] fdc0: c7aac940 01000000 00000000 00000000 00000000
c012dd94 c7b2b560 00000000
[  163.289062] fde0: c7ac1960 00000000 00000000 02000000 c7a2d260
c8970000 000080d2 c7ac1960
[  163.289062] fe00: c8970000 00000000 c7aac940 c8973e7c c7aac94c
000000a0 00000000 c012e574
[  163.289062] fe20: 00000000 00000000 00000000 00002000 c7aac940
00000000 c7aac940 c7ac1960
[  163.289062] fe40: 00000199 c7a2d260 c7aac94c 000000a0 00000000
c013c00c ffffffff 00000000
[  163.289062] fe60: c7aac954 00000040 80000013 c0281c70 c7aac954
c7aac944 c7aac94c c7aac95c
[  163.289062] fe80: 00000040 000080d0 00000020 00000020 c7ac1960
c7ac1ddc 00000140 fffffe00
[  163.289062] fea0: c7ac1960 00000000 00000000 c7a2d260 00000000
000000a0 00000000 c01317d8
[  163.289062] fec0: c7a42010 c7a3bed0 00000002 00000000 00000000
c740ff78 00000001 bead4af8
[  163.289062] fee0: c7a2d260 bead4af8 c7a3e4b0 00000003 c740e000
00000000 00000000 c0131fa8
[  163.289062] ff00: ffffffff 00000000 00000000 00000000 00000000
00000000 c7ac7c00 bead4af8
[  163.289062] ff20: bead4af8 c007c5b4 00000000 00000000 00000000
00000000 00000000 00000003
[  163.289062] ff40: 00000003 c0385a20 00000000 c004f75c 00000000
00000003 c7ac7c00 c7051000
[  163.289062] ff60: c7ac7c08 c006c520 c027a224 c7ac7c00 bead4af8
40186f40 00000003 c000d9c4
[  163.289062] ff80: c740e000 c007c66c 00000003 00000000 bead4af8
bead4af8 40186f40 00000003
[  163.289062] ffa0: 00000036 c000d860 bead4af8 40186f40 00000003
40186f40 bead4af8 00000000
[  163.289062] ffc0: bead4af8 40186f40 00000003 00000036 00000003
bead4db4 00000000 00000000
[  163.289062] ffe0: b6f62ec4 bead4ab0 000098c8 b6f62f08 60000010
00000003 00000000 08000002
[  163.289062] [<c006c23c>] (slob_alloc.clone.18+0x17c/0x1c0) from
[<c006c4a8>] (kmem_cache_alloc_node+0x28/0x64)
[  163.289062] [<c006c4a8>] (kmem_cache_alloc_node+0x28/0x64) from
[<c013a6b8>] (ubi_add_to_av+0x6c0/0x7cc)
[  163.289062] [<c013a6b8>] (ubi_add_to_av+0x6c0/0x7cc) from
[<c012dd94>] (create_vtbl+0x1cc/0x258)
[  163.289062] [<c012dd94>] (create_vtbl+0x1cc/0x258) from
[<c012e574>] (ubi_read_volume_table+0xe4/0x960)
[  163.289062] [<c012e574>] (ubi_read_volume_table+0xe4/0x960) from
[<c013c00c>] (ubi_attach+0x13d0/0x147c)
[  163.289062] [<c013c00c>] (ubi_attach+0x13d0/0x147c) from
[<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20)
[  163.289062] [<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20) from
[<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168)
[  163.289062] [<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544)
[  163.289062] [<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544) from
[<c007c66c>] (sys_ioctl+0x34/0x54)
[  163.289062] [<c007c66c>] (sys_ioctl+0x34/0x54) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[  163.289062] Code: e1a0200b ebfffe52 e250a000 1a000000 (e7f001f2)
[  163.289062] ---[ end trace adca1a6dde15e0c1 ]---
Segmentation fault
#

another:
# flash_erase /dev/mtd0 0 8192
Erasing 16 Kibyte @ 7ffc000 -- 100 % complete
# ubiattach -m 0
[   61.882812] UBI: attaching mtd0 to ubi0
[   62.171875] UBI: scanning is finished
[   62.179687] UBI: empty MTD device detected
[   62.187500] Unable to handle kernel NULL pointer dereference at
virtual address 00000000
[   62.195312] pgd = c7adc000
[   62.203125] [00000000] *pgd=27ad9831, *pte=00000000, *ppte=00000000
[   62.203125] Internal error: Oops: 17 [#1] ARM
[   62.203125] CPU: 0    Not tainted  (3.6.0-rc1+ #893)
[   62.203125] PC is at ubi_wl_init+0x138/0x36c
[   62.203125] LR is at schedule_erase+0x50/0x64
[   62.203125] pc : [<c0139b18>]    lr : [<c013845c>]    psr: 60000013
[   62.203125] sp : c7acbe28  ip : 00008000  fp : 00000000
[   62.203125] r10: c7ad2890  r9 : c029ff5c  r8 : ffffffe0
[   62.203125] r7 : c7aaef00  r6 : c7aaef14  r5 : c7ad2508  r4 : c7a6e440
[   62.203125] r3 : 00000000  r2 : c7a6e838  r1 : c7ad2860  r0 : 00000000
[   62.203125] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[   62.203125] Control: 0005317f  Table: 27adc000  DAC: 00000015
[   62.203125] Process ubiattach (pid: 329, stack limit = 0xc7aca270)
[   62.203125] Stack: (0xc7acbe28 to 0xc7acc000)
[   62.203125] be20:                   00000000 c7aaef00 7fffefff
00000000 c7aaef00 c7a6e440
[   62.203125] be40: 00000199 c7a2d260 c7aaef0c 000000a0 00000000
c013c020 ffffffff 00000000
[   62.203125] be60: c7aaef14 00000040 80000013 c039a634 c7aaef14
c7aaef04 c7aaef0c c7aaef1c
[   62.203125] be80: 00000040 000080d0 00000020 00000020 c7a6e440
c7a6e8bc 00000140 fffffe00
[   62.203125] bea0: c7a6e440 00000000 00000000 c7a2d260 00000000
000000a0 00000000 c01317d8
[   62.203125] bec0: c7a42010 c7a3bed0 00000002 00000000 00000000
c7acbf78 00000001 be873af8
[   62.203125] bee0: c7a2d260 be873af8 c7a3e4b0 00000003 c7aca000
00000000 00000000 c0131fa8
[   62.203125] bf00: ffffffff 00000000 00000000 00000000 00000000
00000000 c7aadae0 be873af8
[   62.203125] bf20: be873af8 c007c5b4 00000000 00000000 00000000
00000000 00000000 00000003
[   62.203125] bf40: 00000003 c039a100 00000000 c004f75c 00000000
00000003 c7aadae0 c7a88000
[   62.203125] bf60: c7aadae8 c006c520 c027a224 c7aadae0 be873af8
40186f40 00000003 c000d9c4
[   62.203125] bf80: c7aca000 c007c66c 00000003 00000000 be873af8
be873af8 40186f40 00000003
[   62.203125] bfa0: 00000036 c000d860 be873af8 40186f40 00000003
40186f40 be873af8 00000000
[   62.203125] bfc0: be873af8 40186f40 00000003 00000036 00000003
be873db4 00000000 00000000
[   62.203125] bfe0: b6ed3ec4 be873ab0 000098c8 b6ed3f08 60000010
00000003 27ffe831 27ffec31
[   62.203125] [<c0139b18>] (ubi_wl_init+0x138/0x36c) from
[<c013c020>] (ubi_attach+0x13e4/0x147c)
[   62.203125] [<c013c020>] (ubi_attach+0x13e4/0x147c) from
[<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20)
[   62.203125] [<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20) from
[<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168)
[   62.203125] [<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544)
[   62.203125] [<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544) from
[<c007c66c>] (sys_ioctl+0x34/0x54)
[   62.203125] [<c007c66c>] (sys_ioctl+0x34/0x54) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   62.203125] Code: e1a01005 e5930000 ebfcca73 ea000074 (e5983020)
[   62.460937] ---[ end trace 41b3746085dc3822 ]---
Segmentation fault



and a big one:
# ubiattach -m 0
[   44.507812] UBI: attaching mtd0 to ubi0
[   44.796875] UBI: scanning is finished
[   44.804687] UBI: empty MTD device detected
[   44.820312] BUG: Bad page state in process klogd  pfn:27ad3
[   44.820312] page:c039aa60 count:0 mapcount:81 mapping:  (null)
index:0xc7ad3ae0
[   44.828125] page flags: 0x800(private)
[   44.835937] [<c00119e8>] (unwind_backtrace+0x0/0xe4) from
[<c004ef88>] (bad_page+0xcc/0xf8)
[   44.843750] [<c004ef88>] (bad_page+0xcc/0xf8) from [<c004fea8>]
(get_page_from_freelist+0x38c/0x4b8)
[   44.851562] [<c004fea8>] (get_page_from_freelist+0x38c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   44.859375] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   44.875000] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64)
[   44.882812] [<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64) from
[<c00762d4>] (getname_flags+0x24/0x94)
[   44.890625] [<c00762d4>] (getname_flags+0x24/0x94) from
[<c006d6a8>] (do_sys_open+0xa0/0x170)
[   44.898437] [<c006d6a8>] (do_sys_open+0xa0/0x170) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   44.906250] Disabling lock debugging due to kernel taint
[   44.914062] Unable to handle kernel paging request at virtual
address 00100104
[   44.914062] pgd = c7aa8000
[   44.914062] [00100104] *pgd=27a7e831, *pte=00000000, *ppte=00000000
[   44.914062] Internal error: Oops: 817 [#1] ARM
[   44.914062] CPU: 0    Tainted: G    B         (3.6.0-rc1+ #893)
[   44.914062] PC is at get_page_from_freelist+0x24c/0x4b8
[   44.914062] LR is at get_page_from_freelist+0x38c/0x4b8
[   44.914062] pc : [<c004fd68>]    lr : [<c004fea8>]    psr: 60000093
[   44.914062] sp : c7aa1e68  ip : 60000013  fp : 60000013
[   44.914062] r10: c039aa60  r9 : c029ad10  r8 : c0290b10
[   44.914062] r7 : b6fcd990  r6 : c0290558  r5 : c03ae04c  r4 : 00000000
[   44.914062] r3 : 00200200  r2 : 00100100  r1 : 00200200  r0 : 00000000
[   44.914062] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   44.914062] Control: 0005317f  Table: 27aa8000  DAC: 00000015
[   44.914062] Process klogd (pid: 302, stack limit = 0xc7aa0270)
[   44.914062] Stack: (0xc7aa1e68 to 0xc7aa2000)
[   44.914062] 1e60:                   00000041 00000000 c7aa1ec0
000200d0 00000001 00000008
[   44.914062] 1e80: c0290b14 00000000 ffffffff 00000000 c7aa0000
00000000 00000101 00000000
[   44.914062] 1ea0: c7b420c0 c0290558 fffffdee 000000d0 01ffffff
00000000 b6fcd990 c0290b10
[   44.914062] 1ec0: 00000000 00000000 c0290558 c00500bc 00000000
00000041 c0290558 00000000
[   44.914062] 1ee0: 00000000 00000000 c7a6f000 00000000 000200d0
c78296a0 c78296d8 c00eded0
[   44.914062] 1f00: c02809b8 c78296a0 c78296a0 c02809b8 c78296d0
c0290558 c0038dac c7802780
[   44.914062] 1f20: 00000000 00000000 b6fcd990 c000d9c4 c7aa0000
00000000 0000000a c006c084
[   44.914062] 1f40: 00000020 c006c4c4 c027a224 00000000 00000000
c00762d4 00000000 00000000
[   44.914062] 1f60: ffffff9c beefb7d0 00000001 c006d6a8 c7aa1f90
0000004e 00000000 beef0000
[   44.914062] 1f80: 00000024 00000100 00000000 00000000 b6fd9eb0
beefb7d0 00000005 c000d9c4
[   44.914062] 1fa0: 00000000 c000d860 00000000 b6fd9eb0 b6fcd990
00000000 00000054 b6fd9eb0
[   44.914062] 1fc0: 00000000 b6fd9eb0 beefb7d0 00000005 b6fda040
00000fff 000a6e38 0000000a
[   44.914062] 1fe0: beefbc54 beefb710 b6f93ed4 b6fc376c 60000010
b6fcd990 00000000 00000000
[   44.914062] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   44.914062] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   44.914062] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64)
[   44.914062] [<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64) from
[<c00762d4>] (getname_flags+0x24/0x94)
[   44.914062] [<c00762d4>] (getname_flags+0x24/0x94) from
[<c006d6a8>] (do_sys_open+0xa0/0x170)
[   44.914062] [<c006d6a8>] (do_sys_open+0xa0/0x170) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   44.914062] Code: e59f1254 e24aa014 e59a3018 e59a2014 (e5823004)
[   44.914062] ---[ end trace 4f68e63fbfe364d4 ]---
[   44.914062] Unable to handle kernel paging request at virtual
address 00100104
[   44.914062] pgd = c0004000
[   44.914062] [00100104] *pgd=00000000
[   44.914062] Internal error: Oops: 817 [#2] ARM
[   44.914062] CPU: 0    Tainted: G    B D       (3.6.0-rc1+ #893)
[   44.914062] PC is at get_page_from_freelist+0x24c/0x4b8
[   44.914062] LR is at zone_watermark_ok+0x18/0x1c
[   44.914062] pc : [<c004fd68>]    lr : [<c004dce0>]    psr: 60000093
[   44.914062] sp : c7aa1b78  ip : 00000041  fp : 60000093
[   44.914062] r10: c039aa60  r9 : c029ad10  r8 : c0290b10
[   44.914062] r7 : c7a776f4  r6 : c0290558  r5 : c03ae04c  r4 : 00000000
[   44.914062] r3 : 00200200  r2 : 00100100  r1 : 00200200  r0 : 00000001
[   44.914062] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   44.914062] Control: 0005317f  Table: 27aa8000  DAC: 00000015
[   44.914062] Process klogd (pid: 302, stack limit = 0xc7aa0270)
[   44.914062] Stack: (0xc7aa1b78 to 0xc7aa2000)
[   44.914062] 1b60:
    00000041 c0291934
[   44.914062] 1b80: c0294d50 00020200 00000001 00000008 c0290b14
00000000 ffffffff 00000000
[   44.914062] 1ba0: c7aa0000 00000000 c7aa1c08 00000000 00000001
c0290558 00000006 00000200
[   44.914062] 1bc0: 01ffffff 00000000 c7a776f4 c0290b10 00000000
00000000 c0290558 c00500bc
[   44.914062] 1be0: 00000000 00000041 c0290558 00000000 c0291934
00000000 c02815fc c0290558
[   44.914062] 1c00: 00020200 c0281618 00000001 c00530f4 000002dc
c0053b3c c02815fc c0290558
[   44.914062] 1c20: 00000001 c0290558 c02815bc c7a776c0 c7a95d20
00000000 c7a776f4 00000817
[   44.914062] 1c40: c7a776f4 60000093 00000001 c005063c c7aa1c78
c0063e08 c7a776c0 00000001
[   44.914062] 1c60: 00000000 00000001 00000093 00000000 00000008
c7aa1c78 00000006 00000004
[   44.914062] 1c80: c0291d5e 00000000 00000000 60000093 c7a776c0
00000000 c7a776c0 00000000
[   44.914062] 1ca0: 00000000 c00175a8 c7a776c0 c7a6f000 00000000
c001c5bc c7a6f000 00000000
[   44.914062] 1cc0: c7a77be0 c7a6f000 0000000b c7aa0000 c0220eac
c001db5c 00010000 c01d5d18
[   44.914062] 1ce0: c0222c31 c7aa1cfc 00000002 c7aa1e20 0000000b
c7aa0000 c0220eac 00000817
[   44.914062] 1d00: c7a776f4 60000093 00010000 c00109f4 c7aa0270
0000000b 00000817 00100104
[   44.914062] 1d20: 00000817 c7a776c0 c7aa1e20 00000000 00000029
c0012888 00100104 c7aa1e20
[   44.914062] 1d40: c7a6f000 c7a776c0 00000817 c0012ae8 00100104
00000817 c7aa1e20 00000817
[   44.914062] 1d60: 00000007 00100104 c7aa1e20 c027cfe0 c029ad10
c039aa60 60000013 c00085a0
[   44.914062] 1d80: 00000000 c0049100 c7a6f000 00000012 00000000
c000e0d8 fefff000 c001ae94
[   44.914062] 1da0: 60000013 c000d500 0000006f 00000001 c027f360
c027f360 0000002c 00000006
[   44.914062] 1dc0: 00000004 c0291d5e 00000000 00000000 60000013
00000000 60000093 c7aa1df0
[   44.914062] 1de0: c001ae90 c001ae94 60000013 ffffffff 00000000
00000000 00000000 00000000
[   44.914062] 1e00: c0291d5e 0000002c c004fd68 60000093 ffffffff
c7aa1e54 c0290b10 c000d498
[   44.914062] 1e20: 00000000 00200200 00100100 00200200 00000000
c03ae04c c0290558 b6fcd990
[   44.914062] 1e40: c0290b10 c029ad10 c039aa60 60000013 60000013
c7aa1e68 c004fea8 c004fd68
[   44.914062] 1e60: 60000093 ffffffff 00000041 00000000 c7aa1ec0
000200d0 00000001 00000008
[   44.914062] 1e80: c0290b14 00000000 ffffffff 00000000 c7aa0000
00000000 00000101 00000000
[   44.914062] 1ea0: c7b420c0 c0290558 fffffdee 000000d0 01ffffff
00000000 b6fcd990 c0290b10
[   44.914062] 1ec0: 00000000 00000000 c0290558 c00500bc 00000000
00000041 c0290558 00000000
[   44.914062] 1ee0: 00000000 00000000 c7a6f000 00000000 000200d0
c78296a0 c78296d8 c00eded0
[   44.914062] 1f00: c02809b8 c78296a0 c78296a0 c02809b8 c78296d0
c0290558 c0038dac c7802780
[   44.914062] 1f20: 00000000 00000000 b6fcd990 c000d9c4 c7aa0000
00000000 0000000a c006c084
[   44.914062] 1f40: 00000020 c006c4c4 c027a224 00000000 00000000
c00762d4 00000000 00000000
[   44.914062] 1f60: ffffff9c beefb7d0 00000001 c006d6a8 c7aa1f90
0000004e 00000000 beef0000
[   44.914062] 1f80: 00000024 00000100 00000000 00000000 b6fd9eb0
beefb7d0 00000005 c000d9c4
[   44.914062] 1fa0: 00000000 c000d860 00000000 b6fd9eb0 b6fcd990
00000000 00000054 b6fd9eb0
[   44.914062] 1fc0: 00000000 b6fd9eb0 beefb7d0 00000005 b6fda040
00000fff 000a6e38 0000000a
[   44.914062] 1fe0: beefbc54 beefb710 b6f93ed4 b6fc376c 60000010
b6fcd990 00000000 00000000
[   44.914062] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   44.914062] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c005063c>] (__get_free_pages+0x10/0x4c)
[   44.914062] [<c005063c>] (__get_free_pages+0x10/0x4c) from
[<c0063e08>] (exit_mmap+0x94/0x19c)
[   44.914062] [<c0063e08>] (exit_mmap+0x94/0x19c) from [<c00175a8>]
(mmput+0x38/0xa8)
[   44.914062] [<c00175a8>] (mmput+0x38/0xa8) from [<c001c5bc>]
(exit_mm+0xe8/0xec)
[   44.914062] [<c001c5bc>] (exit_mm+0xe8/0xec) from [<c001db5c>]
(do_exit+0x1d4/0x688)
[   44.914062] [<c001db5c>] (do_exit+0x1d4/0x688) from [<c00109f4>]
(die+0x208/0x244)
[   44.914062] [<c00109f4>] (die+0x208/0x244) from [<c0012888>]
(__do_kernel_fault+0x64/0x84)
[   44.914062] [<c0012888>] (__do_kernel_fault+0x64/0x84) from
[<c0012ae8>] (do_page_fault+0x240/0x254)
[   44.914062] [<c0012ae8>] (do_page_fault+0x240/0x254) from
[<c00085a0>] (do_DataAbort+0x30/0x98)
[   44.914062] [<c00085a0>] (do_DataAbort+0x30/0x98) from [<c000d498>]
(__dabt_svc+0x38/0x60)
[   44.914062] Exception stack(0xc7aa1e20 to 0xc7aa1e68)
[   44.914062] 1e20: 00000000 00200200 00100100 00200200 00000000
c03ae04c c0290558 b6fcd990
[   44.914062] 1e40: c0290b10 c029ad10 c039aa60 60000013 60000013
c7aa1e68 c004fea8 c004fd68
[   44.914062] 1e60: 60000093 ffffffff
[   44.914062] [<c000d498>] (__dabt_svc+0x38/0x60) from [<c004fd68>]
(get_page_from_freelist+0x24c/0x4b8)
[   44.914062] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   44.914062] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   44.914062] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64)
[   44.914062] [<c006c4c4>] (kmem_cache_alloc_node+0x44/0x64) from
[<c00762d4>] (getname_flags+0x24/0x94)
[   44.914062] [<c00762d4>] (getname_flags+0x24/0x94) from
[<c006d6a8>] (do_sys_open+0xa0/0x170)
[   44.914062] [<c006d6a8>] (do_sys_open+0xa0/0x170) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   44.914062] Code: e59f1254 e24aa014 e59a3018 e59a2014 (e5823004)
[   44.914062] ---[ end trace 4f68e63fbfe364d5 ]---
[   44.914062] Fixing recursive fault but reboot is needed!
[   45.796875] Unable to handle kernel paging request at virtual
address 00100104
[   45.796875] pgd = c7ad8000
[   45.796875] [00100104] *pgd=0000001c
[   45.796875] Unable to handle kernel paging request at virtual
address a0000400
[   45.796875] pgd = c7ad8000
[   45.796875] [a0000400] *pgd=00000000
[   45.796875] Internal error: Oops: 5 [#3] ARM
[   45.796875] CPU: 0    Tainted: G    B D       (3.6.0-rc1+ #893)
[   45.796875] PC is at show_pte+0x74/0xbc
[   45.796875] LR is at show_pte+0x3c/0xbc
[   45.796875] pc : [<c0012708>]    lr : [<c00126d0>]    psr: 60000093
[   45.796875] sp : c7ab5bb8  ip : 60000093  fp : 00010000
[   45.796875] r10: 00000029  r9 : c7ac7254  r8 : 00000000
[   45.796875] r7 : c7ab5cb0  r6 : 00000000  r5 : 00000000  r4 : 00000100
[   45.796875] r3 : a0000000  r2 : 00000000  r1 : 00000000  r0 : c0220df7
[   45.796875] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   45.796875] Control: 0005317f  Table: 27ad8000  DAC: 00000015
[   45.796875] Process ubiattach (pid: 329, stack limit = 0xc7ab4270)
[   45.796875] Stack: (0xc7ab5bb8 to 0xc7ab6000)
[   45.796875] 5ba0:
    00100104 00000817
[   45.796875] 5bc0: c7ac7220 c0012878 00100104 c7ab5cb0 c7ace780
c7ac7220 00000817 c0012ae8
[   45.796875] 5be0: 00100104 00000817 c7ab5cb0 00000817 00000007
00100104 c7ab5cb0 c027cfe0
[   45.796875] 5c00: c029ad10 c039aa60 60000013 c00085a0 00000001
c02806d8 c7ad3b80 c00369ec
[   45.796875] 5c20: c7ab0960 60000093 c7ab5c44 c0036af4 c7ac4000
00000001 0000000e c7ab0c18
[   45.796875] 5c40: 00000002 c0025984 00000001 0000000e c7ab0960
00000001 c7ab0c48 c02806d8
[   45.796875] 5c60: 00000000 c00260e0 0000000e 20000093 c02809b8
c78f54a0 c02809b8 c78f54a0
[   45.796875] 5c80: c02809b8 c78f54a0 c7ab0c48 c02806d0 00000001
c0290c1a c004fd68 60000093
[   45.796875] 5ca0: ffffffff c7ab5ce4 c0290b10 c000d498 00000001
00200200 00100100 00200200
[   45.796875] 5cc0: 00000000 c03ae04c c0290558 80000013 c0290b10
c029ad10 c039aa60 60000013
[   45.796875] 5ce0: 00000041 c7ab5cf8 c004dce0 c004fd68 60000093
ffffffff 00000041 c027e4a0
[   45.796875] 5d00: 00000000 00020050 00000001 00000008 c0290b14
00000000 ffffffff 00000000
[   45.796875] 5d20: c7ab4000 00000000 00000000 00000000 c0296184
c0290558 00000100 00000050
[   45.796875] 5d40: 01ffffff 00000000 80000013 c0290b10 00000000
00000000 c0290558 c00500bc
[   45.796875] 5d60: 00000000 00000041 c0290558 00000000 c7ab5dd4
00000000 00000000 c0049100
[   45.796875] 5d80: 00020050 00000012 00000000 c000e0d8 fefff000
c006c18c 60000013 c000d500
[   45.796875] 5da0: c7ad9f60 c0290558 ffffffe0 c0281c70 c0281c5c
0000003c 80000013 c03995f4
[   45.796875] 5dc0: 0000001e 00000000 00000020 c006c084 00000050
c006c1a4 0000003c 00000050
[   45.796875] 5de0: 00000020 0000001c ffffffff c7b42220 ffffffff
c7ae2000 c029ff5c c7ae1fc0
[   45.796875] 5e00: 00000000 c006c2b0 c7a73440 c0138430 ffffffff
c7a73440 c7b42220 c7ad2774
[   45.796875] 5e20: c7ad2760 c0139afc 00000000 c7ad2760 7fffefff
00000000 c7ad2760 c7a73440
[   45.796875] 5e40: 00000199 c7928380 c7ad276c 000000a0 00000000
c013c020 ffffffff 00000000
[   45.796875] 5e60: c7ad2774 00000040 80000013 c0281c70 c7ad2774
c7ad2764 c7ad276c c7ad277c
[   45.796875] 5e80: 00000040 000080d0 00000020 00000020 c7a73440
c7a738bc 00000140 fffffe00
[   45.796875] 5ea0: c7a73440 00000000 00000000 c7928380 00000000
000000a0 00000000 c01317d8
[   45.796875] 5ec0: c7a42bb0 c7a3bea8 00000002 00000000 00000000
c7ab5f78 00000001 bea1caf8
[   45.796875] 5ee0: c7928380 bea1caf8 c7a3f4b0 00000003 c7ab4000
00000000 00000000 c0131fa8
[   45.796875] 5f00: ffffffff 00000000 00000000 00000000 00000000
00000000 c7ad25a0 bea1caf8
[   45.796875] 5f20: bea1caf8 c007c5b4 00000000 00000000 00000000
00000000 00000000 00000003
[   45.796875] 5f40: 00000003 c039a740 00000000 c004f75c 00000000
00000003 c7ad25a0 c7aba000
[   45.796875] 5f60: c7ad25a8 c006c520 c027a224 c7ad25a0 bea1caf8
40186f40 00000003 c000d9c4
[   45.796875] 5f80: c7ab4000 c007c66c 00000003 00000000 bea1caf8
bea1caf8 40186f40 00000003
[   45.796875] 5fa0: 00000036 c000d860 bea1caf8 40186f40 00000003
40186f40 bea1caf8 00000000
[   45.796875] 5fc0: bea1caf8 40186f40 00000003 00000036 00000003
bea1cdb4 00000000 00000000
[   45.796875] 5fe0: b6f62ec4 bea1cab0 000098c8 b6f62f08 60000010
00000003 00000006 00000004
[   45.796875] [<c0012708>] (show_pte+0x74/0xbc) from [<c0012878>]
(__do_kernel_fault+0x54/0x84)
[   45.796875] [<c0012878>] (__do_kernel_fault+0x54/0x84) from
[<c0012ae8>] (do_page_fault+0x240/0x254)
[   45.796875] [<c0012ae8>] (do_page_fault+0x240/0x254) from
[<c00085a0>] (do_DataAbort+0x30/0x98)
[   45.796875] [<c00085a0>] (do_DataAbort+0x30/0x98) from [<c000d498>]
(__dabt_svc+0x38/0x60)
[   45.796875] Exception stack(0xc7ab5cb0 to 0xc7ab5cf8)
[   45.796875] 5ca0:                                     00000001
00200200 00100100 00200200
[   45.796875] 5cc0: 00000000 c03ae04c c0290558 80000013 c0290b10
c029ad10 c039aa60 60000013
[   45.796875] 5ce0: 00000041 c7ab5cf8 c004dce0 c004fd68 60000093 ffffffff
[   45.796875] [<c000d498>] (__dabt_svc+0x38/0x60) from [<c004fd68>]
(get_page_from_freelist+0x24c/0x4b8)
[   45.796875] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   45.796875] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   45.796875] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0)
[   45.796875] [<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0) from
[<c006c2b0>] (__kmalloc_node+0x30/0xa0)
[   45.796875] [<c006c2b0>] (__kmalloc_node+0x30/0xa0) from
[<c0138430>] (schedule_erase+0x24/0x64)
[   45.796875] [<c0138430>] (schedule_erase+0x24/0x64) from
[<c0139afc>] (ubi_wl_init+0x11c/0x36c)
[   45.796875] [<c0139afc>] (ubi_wl_init+0x11c/0x36c) from
[<c013c020>] (ubi_attach+0x13e4/0x147c)
[   45.796875] [<c013c020>] (ubi_attach+0x13e4/0x147c) from
[<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20)
[   45.796875] [<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20) from
[<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168)
[   45.796875] [<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544)
[   45.796875] [<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544) from
[<c007c66c>] (sys_ioctl+0x34/0x54)
[   45.796875] [<c007c66c>] (sys_ioctl+0x34/0x54) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   45.796875] Code: e3c33eff e3c3300f e59f003c e2433460 (e7932104)
[   45.796875] ---[ end trace 4f68e63fbfe364d6 ]---
[   45.796875] Unable to handle kernel paging request at virtual
address 00100104
[   45.796875] pgd = c0004000
[   45.796875] [00100104] *pgd=00000000
[   45.796875] Internal error: Oops: 817 [#4] ARM
[   45.796875] CPU: 0    Tainted: G    B D       (3.6.0-rc1+ #893)
[   45.796875] PC is at get_page_from_freelist+0x24c/0x4b8
[   45.796875] LR is at zone_watermark_ok+0x18/0x1c
[   45.796875] pc : [<c004fd68>]    lr : [<c004dce0>]    psr: 60000093
[   45.796875] sp : c7ab58c8  ip : 00000041  fp : 60000093
[   45.796875] r10: c039aa60  r9 : c029ad10  r8 : c0290b10
[   45.796875] r7 : c7ac7254  r6 : c0290558  r5 : c03ae04c  r4 : 00000000
[   45.796875] r3 : 00200200  r2 : 00100100  r1 : 00200200  r0 : 00000001
[   45.796875] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[   45.796875] Control: 0005317f  Table: 27ad8000  DAC: 00000015
[   45.796875] Process ubiattach (pid: 329, stack limit = 0xc7ab4270)
[   45.796875] Stack: (0xc7ab58c8 to 0xc7ab6000)
[   45.796875] 58c0:                   00000041 c0291934 c0294388
00020200 00000001 00000008
[   45.796875] 58e0: c0290b14 00000000 ffffffff 00000000 c7ab4000
00000000 c7ab5958 00000000
[   45.796875] 5900: 00000001 c0290558 00000006 00000200 01ffffff
00000000 c7ac7254 c0290b10
[   45.796875] 5920: 00000000 00000000 c0290558 c00500bc 00000000
00000041 c0290558 00000000
[   45.796875] 5940: c0291934 00000000 c001971c c0222c9f 00020200
00000000 00000001 c0291934
[   45.796875] 5960: c029e088 00000000 00000001 00000000 c02943c0
c0290558 c01114f0 c7ac7220
[   45.796875] 5980: c7acf668 00000000 c7ac7254 00000005 c7ac7254
60000093 00000001 c005063c
[   45.796875] 59a0: c7ab59c8 c0063e08 c7ac7220 00000001 00000000
00000001 0000012c 00000000
[   45.796875] 59c0: 00000008 c7ab59c8 00000006 00000004 c0291d5e
00000000 00000000 60000093
[   45.796875] 59e0: c7ac7220 00000000 c7ac7220 00000000 00000000
c00175a8 c7ac7220 c7ace780
[   45.796875] 5a00: 00000000 c001c5bc c7ace780 0000003d c7acea20
c7ace780 0000000b c7ab4000
[   45.796875] 5a20: c0220eac c001db5c 00010000 c01d5d18 c0222c31
c7ab5a4c 00000002 c7ab5b70
[   45.796875] 5a40: 0000000b c7ab4000 c0220eac 00000005 c7ac7254
60000093 00010000 c00109f4
[   45.796875] 5a60: c7ab4270 0000000b 00000005 a0000400 00000005
c7ac7220 c7ab5b70 00000000
[   45.796875] 5a80: 00000028 c0012888 a0000400 c7ab5b70 c7ace780
c7ac7220 00000005 c0012ae8
[   45.796875] 5aa0: a0000400 00000005 c7ab5b70 00000005 00000005
a0000400 c7ab5b70 c027cfe0
[   45.796875] 5ac0: c7ac7254 00000029 00010000 c00085a0 c0291470
c011153c c01114f0 c0287b4c
[   45.796875] 5ae0: c0291470 00000027 00000018 c001a4bc 00000027
60000093 c0291470 c001aa8c
[   45.796875] 5b00: 00000021 00000010 00000008 ffffffff 4c102108
00000000 000000e2 00000000
[   45.796875] 5b20: 00000018 00000018 00000004 00000001 c0291d5e
00000000 00000000 60000093
[   45.796875] 5b40: 00000000 c001ae90 00000000 00000000 00000000
00000000 c0012708 60000093
[   45.796875] 5b60: ffffffff c7ab5ba4 00000000 c000d498 c0220df7
00000000 00000000 a0000000
[   45.796875] 5b80: 00000100 00000000 00000000 c7ab5cb0 00000000
c7ac7254 00000029 00010000
[   45.796875] 5ba0: 60000093 c7ab5bb8 c00126d0 c0012708 60000093
ffffffff 00100104 00000817
[   45.796875] 5bc0: c7ac7220 c0012878 00100104 c7ab5cb0 c7ace780
c7ac7220 00000817 c0012ae8
[   45.796875] 5be0: 00100104 00000817 c7ab5cb0 00000817 00000007
00100104 c7ab5cb0 c027cfe0
[   45.796875] 5c00: c029ad10 c039aa60 60000013 c00085a0 00000001
c02806d8 c7ad3b80 c00369ec
[   45.796875] 5c20: c7ab0960 60000093 c7ab5c44 c0036af4 c7ac4000
00000001 0000000e c7ab0c18
[   45.796875] 5c40: 00000002 c0025984 00000001 0000000e c7ab0960
00000001 c7ab0c48 c02806d8
[   45.796875] 5c60: 00000000 c00260e0 0000000e 20000093 c02809b8
c78f54a0 c02809b8 c78f54a0
[   45.796875] 5c80: c02809b8 c78f54a0 c7ab0c48 c02806d0 00000001
c0290c1a c004fd68 60000093
[   45.796875] 5ca0: ffffffff c7ab5ce4 c0290b10 c000d498 00000001
00200200 00100100 00200200
[   45.796875] 5cc0: 00000000 c03ae04c c0290558 80000013 c0290b10
c029ad10 c039aa60 60000013
[   45.796875] 5ce0: 00000041 c7ab5cf8 c004dce0 c004fd68 60000093
ffffffff 00000041 c027e4a0
[   45.796875] 5d00: 00000000 00020050 00000001 00000008 c0290b14
00000000 ffffffff 00000000
[   45.796875] 5d20: c7ab4000 00000000 00000000 00000000 c0296184
c0290558 00000100 00000050
[   45.796875] 5d40: 01ffffff 00000000 80000013 c0290b10 00000000
00000000 c0290558 c00500bc
[   45.796875] 5d60: 00000000 00000041 c0290558 00000000 c7ab5dd4
00000000 00000000 c0049100
[   45.796875] 5d80: 00020050 00000012 00000000 c000e0d8 fefff000
c006c18c 60000013 c000d500
[   45.796875] 5da0: c7ad9f60 c0290558 ffffffe0 c0281c70 c0281c5c
0000003c 80000013 c03995f4
[   45.796875] 5dc0: 0000001e 00000000 00000020 c006c084 00000050
c006c1a4 0000003c 00000050
[   45.796875] 5de0: 00000020 0000001c ffffffff c7b42220 ffffffff
c7ae2000 c029ff5c c7ae1fc0
[   45.796875] 5e00: 00000000 c006c2b0 c7a73440 c0138430 ffffffff
c7a73440 c7b42220 c7ad2774
[   45.796875] 5e20: c7ad2760 c0139afc 00000000 c7ad2760 7fffefff
00000000 c7ad2760 c7a73440
[   45.796875] 5e40: 00000199 c7928380 c7ad276c 000000a0 00000000
c013c020 ffffffff 00000000
[   45.796875] 5e60: c7ad2774 00000040 80000013 c0281c70 c7ad2774
c7ad2764 c7ad276c c7ad277c
[   45.796875] 5e80: 00000040 000080d0 00000020 00000020 c7a73440
c7a738bc 00000140 fffffe00
[   45.796875] 5ea0: c7a73440 00000000 00000000 c7928380 00000000
000000a0 00000000 c01317d8
[   45.796875] 5ec0: c7a42bb0 c7a3bea8 00000002 00000000 00000000
c7ab5f78 00000001 bea1caf8
[   45.796875] 5ee0: c7928380 bea1caf8 c7a3f4b0 00000003 c7ab4000
00000000 00000000 c0131fa8
[   45.796875] 5f00: ffffffff 00000000 00000000 00000000 00000000
00000000 c7ad25a0 bea1caf8
[   45.796875] 5f20: bea1caf8 c007c5b4 00000000 00000000 00000000
00000000 00000000 00000003
[   45.796875] 5f40: 00000003 c039a740 00000000 c004f75c 00000000
00000003 c7ad25a0 c7aba000
[   45.796875] 5f60: c7ad25a8 c006c520 c027a224 c7ad25a0 bea1caf8
40186f40 00000003 c000d9c4
[   45.796875] 5f80: c7ab4000 c007c66c 00000003 00000000 bea1caf8
bea1caf8 40186f40 00000003
[   45.796875] 5fa0: 00000036 c000d860 bea1caf8 40186f40 00000003
40186f40 bea1caf8 00000000
[   45.796875] 5fc0: bea1caf8 40186f40 00000003 00000036 00000003
bea1cdb4 00000000 00000000
[   45.796875] 5fe0: b6f62ec4 bea1cab0 000098c8 b6f62f08 60000010
00000003 00000006 00000004
[   45.796875] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   45.796875] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c005063c>] (__get_free_pages+0x10/0x4c)
[   45.796875] [<c005063c>] (__get_free_pages+0x10/0x4c) from
[<c0063e08>] (exit_mmap+0x94/0x19c)
[   45.796875] [<c0063e08>] (exit_mmap+0x94/0x19c) from [<c00175a8>]
(mmput+0x38/0xa8)
[   45.796875] [<c00175a8>] (mmput+0x38/0xa8) from [<c001c5bc>]
(exit_mm+0xe8/0xec)
[   45.796875] [<c001c5bc>] (exit_mm+0xe8/0xec) from [<c001db5c>]
(do_exit+0x1d4/0x688)
[   45.796875] [<c001db5c>] (do_exit+0x1d4/0x688) from [<c00109f4>]
(die+0x208/0x244)
[   45.796875] [<c00109f4>] (die+0x208/0x244) from [<c0012888>]
(__do_kernel_fault+0x64/0x84)
[   45.796875] [<c0012888>] (__do_kernel_fault+0x64/0x84) from
[<c0012ae8>] (do_page_fault+0x240/0x254)
[   45.796875] [<c0012ae8>] (do_page_fault+0x240/0x254) from
[<c00085a0>] (do_DataAbort+0x30/0x98)
[   45.796875] [<c00085a0>] (do_DataAbort+0x30/0x98) from [<c000d498>]
(__dabt_svc+0x38/0x60)
[   45.796875] Exception stack(0xc7ab5b70 to 0xc7ab5bb8)
[   45.796875] 5b60:                                     c0220df7
00000000 00000000 a0000000
[   45.796875] 5b80: 00000100 00000000 00000000 c7ab5cb0 00000000
c7ac7254 00000029 00010000
[   45.796875] 5ba0: 60000093 c7ab5bb8 c00126d0 c0012708 60000093 ffffffff
[   45.796875] [<c000d498>] (__dabt_svc+0x38/0x60) from [<c0012708>]
(show_pte+0x74/0xbc)
[   45.796875] [<c0012708>] (show_pte+0x74/0xbc) from [<c0012878>]
(__do_kernel_fault+0x54/0x84)
[   45.796875] [<c0012878>] (__do_kernel_fault+0x54/0x84) from
[<c0012ae8>] (do_page_fault+0x240/0x254)
[   45.796875] [<c0012ae8>] (do_page_fault+0x240/0x254) from
[<c00085a0>] (do_DataAbort+0x30/0x98)
[   45.796875] [<c00085a0>] (do_DataAbort+0x30/0x98) from [<c000d498>]
(__dabt_svc+0x38/0x60)
[   45.796875] Exception stack(0xc7ab5cb0 to 0xc7ab5cf8)
[   45.796875] 5ca0:                                     00000001
00200200 00100100 00200200
[   45.796875] 5cc0: 00000000 c03ae04c c0290558 80000013 c0290b10
c029ad10 c039aa60 60000013
[   45.796875] 5ce0: 00000041 c7ab5cf8 c004dce0 c004fd68 60000093 ffffffff
[   45.796875] [<c000d498>] (__dabt_svc+0x38/0x60) from [<c004fd68>]
(get_page_from_freelist+0x24c/0x4b8)
[   45.796875] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   45.796875] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   45.796875] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0)
[   45.796875] [<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0) from
[<c006c2b0>] (__kmalloc_node+0x30/0xa0)
[   45.796875] [<c006c2b0>] (__kmalloc_node+0x30/0xa0) from
[<c0138430>] (schedule_erase+0x24/0x64)
[   45.796875] [<c0138430>] (schedule_erase+0x24/0x64) from
[<c0139afc>] (ubi_wl_init+0x11c/0x36c)
[   45.796875] [<c0139afc>] (ubi_wl_init+0x11c/0x36c) from
[<c013c020>] (ubi_attach+0x13e4/0x147c)
[   45.796875] [<c013c020>] (ubi_attach+0x13e4/0x147c) from
[<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20)
[   45.796875] [<c01317d8>] (ubi_attach_mtd_dev+0x58c/0xb20) from
[<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168)
[   45.796875] [<c0131fa8>] (ctrl_cdev_ioctl+0xd8/0x168) from
[<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544)
[   45.796875] [<c007c5b4>] (do_vfs_ioctl+0x4c0/0x544) from
[<c007c66c>] (sys_ioctl+0x34/0x54)
[   45.796875] [<c007c66c>] (sys_ioctl+0x34/0x54) from [<c000d860>]
(ret_fast_syscall+0x0/0x2c)
[   45.796875] Code: e59f1254 e24aa014 e59a3018 e59a2014 (e5823004)
[   45.796875] ---[ end trace 4f68e63fbfe364d7 ]---
[   45.796875] Fixing recursive fault but reboot is needed!
[   46.148437] Unable to handle kernel paging request at virtual
address 00100104
[   46.148437] pgd = c0004000
[   46.148437] [00100104] *pgd=00000000
[   46.148437] Internal error: Oops: 817 [#5] ARM
[   46.148437] CPU: 0    Tainted: G    B D       (3.6.0-rc1+ #893)
[   46.148437] PC is at get_page_from_freelist+0x24c/0x4b8
[   46.148437] LR is at zone_watermark_ok+0x18/0x1c
[   46.148437] pc : [<c004fd68>]    lr : [<c004dce0>]    psr: 60000093
[   46.148437] sp : c0273cc0  ip : 00000041  fp : 60000093
[   46.148437] r10: c039aa60  r9 : c029ad10  r8 : c0290b10
[   46.148437] r7 : 80000093  r6 : c0290558  r5 : c03ae04c  r4 : 00000000
[   46.148437] r3 : 00200200  r2 : 00100100  r1 : 00200200  r0 : 00000001
[   46.148437] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[   46.148437] Control: 0005317f  Table: 27ad8000  DAC: 00000017
[   46.148437] Process swapper (pid: 0, stack limit = 0xc0272270)
[   46.148437] Stack: (0xc0273cc0 to 0xc0274000)
[   46.148437] 3cc0: 00000041 c7acf4a0 c0272000 00020020 00000001
00000008 c0290b14 00000000
[   46.148437] 3ce0: ffffffff 00000000 c0272000 00000000 c7ace7b0
00000000 c0038dac c0290558
[   46.148437] 3d00: c7ace780 00000020 01ffffff 00000000 80000093
c0290b10 00000000 00000000
[   46.148437] 3d20: c0290558 c00500bc 00000000 00000041 c0290558
00000000 00000001 00000000
[   46.148437] 3d40: c0273d74 c00308d8 00020020 c0036604 00000000
20000013 c7a4994c c7abb900
[   46.148437] 3d60: 000000cc 00000060 c7a48a40 c0290558 fffffff8
c0281c70 c0281c5c 00000090
[   46.148437] 3d80: 80000093 c03995f4 00000048 00000000 00000008
c006c084 00000020 c006c1a4
[   46.148437] 3da0: 00000090 00000020 00000008 c7808b40 0000000e
c7ab0c18 c7ab0960 00000001
[   46.148437] 3dc0: c02806d8 00000000 00000002 c006c4a8 c0297524
c0280098 0000000e c0024abc
[   46.148437] 3de0: 00000001 00000001 0000000e c0025834 00000001
0000000e c7ab0960 00000001
[   46.148437] 3e00: c7ab0c48 c02806d8 00000000 c00260e0 0000000e
20000093 c7ab0960 c7a8bfc0
[   46.148437] 3e20: 00000001 0000000e c0280778 c00262d0 c02806d0
00000001 c0290c1a c001e6bc
[   46.148437] 3e40: c001e6a4 c0033b20 00000000 c003bb9c 00000000
00000000 00000000 00000000
[   46.148437] 3e60: 0000002e 0860173b ffc06c00 c027c058 00000000
c027e4a0 00000000 00000000
[   46.148437] 3e80: c0290c20 c7ac7220 00000001 c00240f0 c027c058
c0024124 c0290fdc 0000008f
[   46.148437] 3ea0: c027e4a0 c003ee50 c027e4a0 00000000 c0290fdc
0000008f c027e4a0 00000000
[   46.148437] 3ec0: 00000000 c0016f10 c027e6a8 c78023c0 00000012
c0044dac c78023c0 c027e6a8
[   46.148437] 3ee0: 0005d6d5 c78023c0 00000000 ffffffff c0273f64
c7ace780 c7ac7220 c7ac7220
[   46.148437] 3f00: c0273f8c c0044f40 c78023c0 c0046fc4 00000012
c004485c 00000012 c000e0d4
[   46.148437] 3f20: fefff000 c0036734 60000013 c000d500 c7ace780
00000000 00000000 60000013
[   46.148437] 3f40: c7ace780 c7ac7220 00000002 c0272000 c7ace780
c7ac7220 c7ac7220 c0273f8c
[   46.148437] 3f60: c7ab4044 c0273f78 c01d6ec0 c0036734 60000013
ffffffff c027c058 c02809b8
[   46.148437] 3f80: 00000000 c0272000 c0273fb4 c01d6ec0 c027c058
c0272000 c027cd20 c0290d48
[   46.148437] 3fa0: c03aca60 20004000 41069265 2026c3b0 00000000
c000e300 c027a090 ffffffff
[   46.148437] 3fc0: c026d5ec c02566cc ffffffff ffffffff c02561cc
00000000 00000000 c026d5ec
[   46.148437] 3fe0: 00000000 00053175 c027a01c c026d5bc c027cd14
20008040 00000000 00000000
[   46.148437] [<c004fd68>] (get_page_from_freelist+0x24c/0x4b8) from
[<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4)
[   46.148437] [<c00500bc>] (__alloc_pages_nodemask+0xe8/0x5e4) from
[<c006c084>] (slob_new_pages.clone.17+0x10/0x4c)
[   46.148437] [<c006c084>] (slob_new_pages.clone.17+0x10/0x4c) from
[<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0)
[   46.148437] [<c006c1a4>] (slob_alloc.clone.18+0xe4/0x1c0) from
[<c006c4a8>] (kmem_cache_alloc_node+0x28/0x64)
[   46.148437] [<c006c4a8>] (kmem_cache_alloc_node+0x28/0x64) from
[<c0024abc>] (__sigqueue_alloc+0x78/0x120)
[   46.148437] [<c0024abc>] (__sigqueue_alloc+0x78/0x120) from
[<c0025834>] (__send_signal.clone.23+0xa4/0x214)
[   46.148437] [<c0025834>] (__send_signal.clone.23+0xa4/0x214) from
[<c00260e0>] (do_send_sig_info+0x40/0x4c)
[   46.148437] [<c00260e0>] (do_send_sig_info+0x40/0x4c) from
[<c00262d0>] (kill_pid_info+0x30/0x44)
[   46.148437] [<c00262d0>] (kill_pid_info+0x30/0x44) from
[<c001e6bc>] (it_real_fn+0x18/0x20)
[   46.148437] [<c001e6bc>] (it_real_fn+0x18/0x20) from [<c0033b20>]
(hrtimer_run_queues+0x12c/0x1e4)
[   46.148437] [<c0033b20>] (hrtimer_run_queues+0x12c/0x1e4) from
[<c00240f0>] (run_local_timers+0x8/0x14)
[   46.148437] [<c00240f0>] (run_local_timers+0x8/0x14) from
[<c0024124>] (update_process_times+0x28/0x48)
[   46.148437] [<c0024124>] (update_process_times+0x28/0x48) from
[<c003ee50>] (tick_handle_periodic+0xc/0x74)
[   46.148437] [<c003ee50>] (tick_handle_periodic+0xc/0x74) from
[<c0016f10>] (at91sam926x_pit_interrupt+0x7c/0xa8)
[   46.148437] [<c0016f10>] (at91sam926x_pit_interrupt+0x7c/0xa8) from
[<c0044dac>] (handle_irq_event_percpu+0x30/0x19c)
[   46.148437] [<c0044dac>] (handle_irq_event_percpu+0x30/0x19c) from
[<c0044f40>] (handle_irq_event+0x28/0x38)
[   46.148437] [<c0044f40>] (handle_irq_event+0x28/0x38) from
[<c0046fc4>] (handle_fasteoi_irq+0x9c/0xdc)
[   46.148437] [<c0046fc4>] (handle_fasteoi_irq+0x9c/0xdc) from
[<c004485c>] (generic_handle_irq+0x20/0x30)
[   46.148437] [<c004485c>] (generic_handle_irq+0x20/0x30) from
[<c000e0d4>] (handle_IRQ+0x60/0x84)
[   46.148437] [<c000e0d4>] (handle_IRQ+0x60/0x84) from [<c000d500>]
(__irq_svc+0x40/0x4c)
[   46.148437] [<c000d500>] (__irq_svc+0x40/0x4c) from [<c0036734>]
(finish_task_switch.clone.52.clone.57+0x2c/0xe0)
[   46.148437] [<c0036734>]
(finish_task_switch.clone.52.clone.57+0x2c/0xe0) from [<c01d6ec0>]
(__schedule+0x300/0x338)
[   46.148437] [<c01d6ec0>] (__schedule+0x300/0x338) from [<c000e300>]
(cpu_idle+0xa4/0xb4)
[   46.148437] [<c000e300>] (cpu_idle+0xa4/0xb4) from [<c02566cc>]
(start_kernel+0x240/0x280)
[   46.148437] Code: e59f1254 e24aa014 e59a3018 e59a2014 (e5823004)
[   46.148437] ---[ end trace 4f68e63fbfe364d8 ]---
[   46.148437] Kernel panic - not syncing: Fatal exception in interrupt


I attached the .config I used


Regards,
Richard.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: .config
Type: application/octet-stream
Size: 27890 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/febe699f/attachment-0001.obj>

From dedekind1 at gmail.com  Mon Sep  3 09:31:08 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 16:31:08 +0300
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <CACQ1gAjeNq5zNKzSbO_eeDG7ahhBc9mNvMf_s4RadrWSq-5taQ@mail.gmail.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346659239.3061.17.camel@sauron.fi.intel.com>
 <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>
 <1346673180.3061.44.camel@sauron.fi.intel.com>
 <CACQ1gAjeNq5zNKzSbO_eeDG7ahhBc9mNvMf_s4RadrWSq-5taQ@mail.gmail.com>
Message-ID: <1346679068.3061.52.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 15:14 +0200, Richard Genoud wrote:
> I finally managed to reproduced it on linux-ubi/master + only one
> patch to make my board boot:
> (I thought it needed much more code than that...)

Hmm, you use slob... I guess this is the reason, I do not see issues
with slub. May be there is a bug which is revealed when slob is used?
I'll need to try slob.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/68ef50cb/attachment.sig>

From richard.genoud at gmail.com  Mon Sep  3 09:37:09 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 3 Sep 2012 15:37:09 +0200
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <1346679068.3061.52.camel@sauron.fi.intel.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346659239.3061.17.camel@sauron.fi.intel.com>
 <CACQ1gAgxnrLR-NDkiw=QUZ9r6JO30AVwX6MOYX4vV9WXoBaBiA@mail.gmail.com>
 <1346673180.3061.44.camel@sauron.fi.intel.com>
 <CACQ1gAjeNq5zNKzSbO_eeDG7ahhBc9mNvMf_s4RadrWSq-5taQ@mail.gmail.com>
 <1346679068.3061.52.camel@sauron.fi.intel.com>
Message-ID: <CACQ1gAjw7s0bYd0aYiqTm7jUuB881sHFrJUuvuycbmC1fY+MaQ@mail.gmail.com>

2012/9/3 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Mon, 2012-09-03 at 15:14 +0200, Richard Genoud wrote:
>> I finally managed to reproduced it on linux-ubi/master + only one
>> patch to make my board boot:
>> (I thought it needed much more code than that...)
>
> Hmm, you use slob... I guess this is the reason, I do not see issues
> with slub. May be there is a bug which is revealed when slob is used?
> I'll need to try slob.

Good call Artem !
I switched to slub and I can't reproduce it anymore.


From fabien.comte at ercogener.com  Mon Sep  3 10:15:05 2012
From: fabien.comte at ercogener.com (Fabien Comte)
Date: Mon, 3 Sep 2012 16:15:05 +0200
Subject: TR: Notification d'envoi de fichier via http://dl.free.fr
References: <20120831133153.764EC3495D9@dl.free.fr>	
 <003d01cd877e$39b71020$ad253060$@ercogener.com>	
 <1346671221.3061.42.camel@sauron.fi.intel.com>
 <1346673285.3061.46.camel@sauron.fi.intel.com> 
Message-ID: <001d01cd89de$84659fd0$8d30df70$@ercogener.com>

Hello,

3.0, are you sure ?
http://git.infradead.org/users/dedekind/ubifs-v3.0.git
http://git.infradead.org/users/dedekind/ubifs-v3.5.git -> for 3.5 kernels, isn't it ?

Thank you.

Fabien Comte

-----Message d'origine-----
De : Artem Bityutskiy [mailto:dedekind1 at gmail.com] Envoy? : lundi 3 septembre 2012 13:55 ? : Fabien Comte Cc : linux-mtd Objet : Re: TR: Notification d'envoi de fichier via http://dl.free.fr

On Mon, 2012-09-03 at 14:20 +0300, Artem Bityutskiy wrote:
> Also, you never sent me the full log. Please, _before_ mounting, 
> enable debugging prints:
> 
> 1. modprobe ubifs
> 2. echo 'format "UBIFS DBG" +pf' >
> /sys/kernel/debug/dynamic_debug/control
> 3. mount
> 
> then type "dmesg" and send full log please.

Also note, I am using x86_64 PC.

Can you try to take the ubifs-v3.0 tree and try to reproduce the issue?

If it is reproducible, then we can find the guilty commit using git bisect.

--
Best Regards,
Artem Bityutskiy



From dedekind1 at gmail.com  Mon Sep  3 10:25:56 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon,  3 Sep 2012 17:25:56 +0300
Subject: [PATCH] UBI: fix a horrible memory deallocation bug
Message-ID: <1346682356-14997-1-git-send-email-dedekind1@gmail.com>

From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

UBI was mistakingly using 'kfree()' instead of 'kmem_cache_free()' when
freeing "attach eraseblock" structures in vtbl.c. Thankfully, this happened
only when we were doing auto-format, so many systems were unaffected. However,
there are still many users affected.

It is strange, but the system did not crash and nothing bad happened when
the SLUB memory allocator was used. However, in case of SLOB we observed an
crash right away.

This problem was introduced in 2.6.39 by commit
"6c1e875 UBI: add slab cache for ubi_scan_leb objects"

Reported-by: Richard Genoud <richard.genoud at gmail.com>
Cc: stable at vger.kernel.org [v2.6.39+]
Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/ubi/vtbl.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
index 64b9c56..926e3df 100644
--- a/drivers/mtd/ubi/vtbl.c
+++ b/drivers/mtd/ubi/vtbl.c
@@ -340,7 +340,7 @@ retry:
 	 * of this LEB as it will be deleted and freed in 'ubi_add_to_av()'.
 	 */
 	err = ubi_add_to_av(ubi, ai, new_aeb->pnum, new_aeb->ec, vid_hdr, 0);
-	kfree(new_aeb);
+	kmem_cache_free(ai->aeb_slab_cache, new_aeb);
 	ubi_free_vid_hdr(ubi, vid_hdr);
 	return err;
 
@@ -353,7 +353,7 @@ write_error:
 		list_add(&new_aeb->u.list, &ai->erase);
 		goto retry;
 	}
-	kfree(new_aeb);
+	kmem_cache_free(ai->aeb_slab_cache, new_aeb);
 out_free:
 	ubi_free_vid_hdr(ubi, vid_hdr);
 	return err;
-- 
1.7.7.6



From dedekind1 at gmail.com  Mon Sep  3 10:32:09 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 17:32:09 +0300
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
Message-ID: <1346682729.3061.55.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 16:46 +0200, Richard Genoud wrote:
> diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c
> --- a/drivers/mtd/ubi/vtbl.c
> +++ b/drivers/mtd/ubi/vtbl.c
> @@ -346,8 +346,8 @@ retry:
>          */
>         err = ubi_scan_add_used(ubi, si, new_seb->pnum, new_seb->ec,
>                                 vid_hdr, 0);
> +//     kfree(new_seb);
> +//     ubi_free_vid_hdr(ubi, vid_hdr);
>         return err;
> 
Richard, I've sent you the fix. I've tested it and it fixes the issue.
Switching to SLUB must be hiding it somehow. Thanks for reporting!
> 
-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/098e1367/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 10:33:14 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 17:33:14 +0300
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
Message-ID: <1346682794.3061.56.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 16:46 +0200, Richard Genoud wrote:
> I tested also some values at limits, it seems all right.

Thanks Richard for testing. Would you be also energetic enough to do the
last step - some documentation for mtd-www?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/1ffc565c/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 10:38:37 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 17:38:37 +0300
Subject: TR: Notification d'envoi de fichier via http://dl.free.fr
In-Reply-To: <001d01cd89de$84659fd0$8d30df70$@ercogener.com>
References: <20120831133153.764EC3495D9@dl.free.fr>
 <003d01cd877e$39b71020$ad253060$@ercogener.com>
 <1346671221.3061.42.camel@sauron.fi.intel.com>
 <1346673285.3061.46.camel@sauron.fi.intel.com>
 <001d01cd89de$84659fd0$8d30df70$@ercogener.com>
Message-ID: <1346683117.3061.61.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 16:15 +0200, Fabien Comte wrote:
> Hello,
> 
> 3.0, are you sure ?
> http://git.infradead.org/users/dedekind/ubifs-v3.0.git
> http://git.infradead.org/users/dedekind/ubifs-v3.5.git -> for 3.5 kernels, isn't it ?

Well, here is my logic.

You say that if you create an UBIFS image in v3.0, then try to mount it
in v3.4 - it fails, while it still mounts in 3.0. Correct?

Then, if you take the ubifs-v3.0.git tree, which contains v3.0 + all the
UBI/UBIFS patches, and try to mount your image, I expect it will also
fail.

If so, you will have the kernel which:

1. Works at the 'v3.0' point.
2. Fails at the 'HEAD' point.

Then you should be able to find out which commit is guilty using 'git
bisect'. Something like:

$ git bisect start
$ git bisect bad HEAD
$ git bisect good v3.0

If you manage to find the offending commit, fixing the issue should be
relatively easy, I think (and hope).

Makes sense?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/725a1031/attachment-0001.sig>

From richard.genoud at gmail.com  Mon Sep  3 10:43:45 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 3 Sep 2012 16:43:45 +0200
Subject: [PATCH] UBI: fix a horrible memory deallocation bug
In-Reply-To: <1346682356-14997-1-git-send-email-dedekind1@gmail.com>
References: <1346682356-14997-1-git-send-email-dedekind1@gmail.com>
Message-ID: <CACQ1gAj4U1QfNuyOz_+AmSkNQw+1P8VtYeCsy7THSRrHcPWvJQ@mail.gmail.com>

2012/9/3 Artem Bityutskiy <dedekind1 at gmail.com>:
> From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
>
> UBI was mistakingly using 'kfree()' instead of 'kmem_cache_free()' when
> freeing "attach eraseblock" structures in vtbl.c. Thankfully, this happened
> only when we were doing auto-format, so many systems were unaffected. However,
> there are still many users affected.
>
> It is strange, but the system did not crash and nothing bad happened when
> the SLUB memory allocator was used. However, in case of SLOB we observed an
> crash right away.
>
> This problem was introduced in 2.6.39 by commit
> "6c1e875 UBI: add slab cache for ubi_scan_leb objects"
>
> Reported-by: Richard Genoud <richard.genoud at gmail.com>
> Cc: stable at vger.kernel.org [v2.6.39+]
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> ---
>  drivers/mtd/ubi/vtbl.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
Tested ok, works like a charm !
Thanks !


From richard.genoud at gmail.com  Mon Sep  3 10:45:12 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 3 Sep 2012 16:45:12 +0200
Subject: [PATCH v3 0/6] UBI: add max_beb_per1024 parameter / ioctl
In-Reply-To: <1346682794.3061.56.camel@sauron.fi.intel.com>
References: <1345478416-23900-1-git-send-email-richard.genoud@gmail.com>
 <1345716615.2848.229.camel@sauron.fi.intel.com>
 <20120823133655.72157b18@pixies.home.jungo.com>
 <1345725030.2848.236.camel@sauron.fi.intel.com>
 <20120823154404.51e31873@pixies.home.jungo.com>
 <1345726686.2848.241.camel@sauron.fi.intel.com>
 <CACQ1gAhs6E5jHGnTy1RhbnuzKq7uAJk0DeHfi0k73jC_8noiAg@mail.gmail.com>
 <CACQ1gAiFQfAbKVRfhjy-K31MJP9YchzxmmCo4FJECoKuudeBtw@mail.gmail.com>
 <1346682794.3061.56.camel@sauron.fi.intel.com>
Message-ID: <CACQ1gAi=rrQ78dVgxR=unbh5KR870j=k9bCsipsVaQxX80GzEA@mail.gmail.com>

2012/9/3 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Fri, 2012-08-31 at 16:46 +0200, Richard Genoud wrote:
>> I tested also some values at limits, it seems all right.
>
> Thanks Richard for testing. Would you be also energetic enough to do the
> last step - some documentation for mtd-www?

yep, that's next in line !


From shijie8 at gmail.com  Mon Sep  3 11:09:26 2012
From: shijie8 at gmail.com (Huang Shijie)
Date: Mon, 3 Sep 2012 11:09:26 -0400
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <1346656701.3061.8.camel@sauron.fi.intel.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
Message-ID: <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>

On Mon, Sep 3, 2012 at 3:18 AM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> On Sun, 2012-08-26 at 13:21 -0400, Huang Shijie wrote:
>> + *
>> + * Note:
>> + * If you choose to set the @offset for the <partdef>, please set all
>> + * the partitions with the same syntax, such as:
>> + *     gpmi-nand:100m at 0(boot),100m at 100m(kernel),1g at 200m(rootfs)
>> + *
>> + * Please do _NOT_ set the partitions like this:
>> + *     gpmi-nand:100m at 0(boot),100m(kernel),1g at 200m(rootfs)
>> + * The `kernel` partition does not set with the @offset, this is not permitted.
>>   */
>
> I guess it is indeed OK to sort the partitions, just makes things a lot
> simpler. But we probably then should also do the following:
>
> 1. Make sure there is only one partition without offset. If there are
> several - error out.

 Why allow `only one partition without offset`?

Take the following unsorted partitions as an example:
     #gpmi-nand:1g at 200m(rootfs),100m(boot),100m at 100m(kernel)

The current code will parses out the following partitions:
      rootfs: < size = 1g, offset=200m>
      boot:   < size = 100m, offset= OFFSET_CONTINOUS>
      kernel: <size = 100m, offset = 100m>

If we sort the partitions by the offset, we get the following result:
     "kernel" , "rootfs", "boot"

In actually, we expect the following result:
    "boot", "kernel", "rootfs"

What's your idea about this issue?
In my opinion, we should forbid the mixed type.

thanks
Huang Shijie







> 2. Check that partitions do not intersect - I did not notice that we do
> this in the code.
>
> So AFAICS, this patch is not needed and we better have the following
> patches:
>
> 1. Add sorting
> 2. Add a check that partitions do not overlap and there is only one
> offset-less partition.
>
> How does this sound?
>
> --
> Best Regards,
> Artem Bityutskiy


From dedekind1 at gmail.com  Mon Sep  3 11:25:18 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 18:25:18 +0300
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 ,<1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 ,<1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
Message-ID: <1346685918.3061.66.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 08:59 +1000, Iwo Mergler wrote:
> This tests ECC biterror recovery on a single NAND page. Mostly intended
> to test ECC hardware and low-level NAND driver.
> 
> There are two test modes:
> 
>     0 - artificially inserting bit errors until the ECC fails
>         This is the default method and fairly quick. It should
>         be independent of the quality of the FLASH.
> 
>     1 - re-writing the same pattern repeatedly until the ECC fails.
>         This method relies on the physics of NAND FLASH to eventually
>         generate '0' bits if '1' has been written sufficient times. Depending
>         on the NAND, the first bit errors will appear after 1000 or
>         more writes and then will usually snowball, reaching the limits
>         of the ECC quickly.
> 
> The test stops after 10000 cycles, should your FLASH be exceptionally
> good and not generate bit errors before that. Try a different page
> offset in that case.
> 
> Please note that neither of these tests will significantly 'use up' any FLASH
> endurance. Only a maximum of two erase operations will be performed.
> 
> Signed-off-by: Iwo Mergler <Iwo.Mergler at netcommwireless.com.au>
> ---
>  drivers/mtd/tests/Makefile          |    1 +
>  drivers/mtd/tests/mtd_nandbiterrs.c |  460 +++++++++++++++++++++++++++++++++++
>  2 files changed, 461 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/mtd/tests/mtd_nandbiterrs.c
> 
> diff --git a/drivers/mtd/tests/Makefile b/drivers/mtd/tests/Makefile
> index b44dcab..bd0065c 100644
> --- a/drivers/mtd/tests/Makefile
> +++ b/drivers/mtd/tests/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_MTD_TESTS) += mtd_stresstest.o
>  obj-$(CONFIG_MTD_TESTS) += mtd_subpagetest.o
>  obj-$(CONFIG_MTD_TESTS) += mtd_torturetest.o
>  obj-$(CONFIG_MTD_TESTS) += mtd_nandecctest.o
> +obj-$(CONFIG_MTD_TESTS) += mtd_nandbiterrs.o
> diff --git a/drivers/mtd/tests/mtd_nandbiterrs.c b/drivers/mtd/tests/mtd_nandbiterrs.c
> new file mode 100644
> index 0000000..94e908e
> --- /dev/null
> +++ b/drivers/mtd/tests/mtd_nandbiterrs.c
> @@ -0,0 +1,460 @@
> +/*
> + * (C)2012 NetCommWireless
> + * Iwo Mergler <Iwo.Mergler at netcommwireless.com.au>
> + *
> + * Test for multi-bit error recovery on a NAND page This mostly tests the
> + * ECC controller / driver.
> + *
> + * There are two test modes:
> + *
> + *	0 - artificially inserting bit errors until the ECC fails
> + *	    This is the default method and fairly quick. It should
> + *	    be independent of the quality of the FLASH.
> + *
> + *	1 - re-writing the same pattern repeatedly until the ECC fails.
> + *	    This method relies on the physics of NAND FLASH to eventually
> + *	    generate '0' bits if '1' has been written sufficient times.
> + *	    Depending on the NAND, the first bit errors will appear after
> + *	    1000 or more writes and then will usually snowball, reaching the
> + *	    limits of the ECC quickly.
> + *
> + *	    The test stops after 10000 cycles, should your FLASH be
> + *	    exceptionally good and not generate bit errors before that. Try
> + *	    a different page in that case.

So basically you test that ECC works, and you are trying to be
independent on the NAND HW and the ECC type. Right?

How about mtd_nandecc test? How is it different? Do we need 2 tests?
Why?

Akinobu - you recently sent a large patch-set for mtd_nandecctest, could
you please also comment on the above questions?

Basically, I would like to understand why we need 2 tests, and if we
really need 2, have the differences be documented, at least in the
commentaries.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/323436ba/attachment.sig>

From dedekind1 at gmail.com  Mon Sep  3 11:35:44 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 03 Sep 2012 18:35:44 +0300
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
Message-ID: <1346686544.3061.75.camel@sauron.fi.intel.com>

[Dropped extra CCs - let's spam less]

On Mon, 2012-09-03 at 11:09 -0400, Huang Shijie wrote:
> On Mon, Sep 3, 2012 at 3:18 AM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> > On Sun, 2012-08-26 at 13:21 -0400, Huang Shijie wrote:
> >> + *
> >> + * Note:
> >> + * If you choose to set the @offset for the <partdef>, please set all
> >> + * the partitions with the same syntax, such as:
> >> + *     gpmi-nand:100m at 0(boot),100m at 100m(kernel),1g at 200m(rootfs)
> >> + *
> >> + * Please do _NOT_ set the partitions like this:
> >> + *     gpmi-nand:100m at 0(boot),100m(kernel),1g at 200m(rootfs)
> >> + * The `kernel` partition does not set with the @offset, this is not permitted.
> >>   */
> >
> > I guess it is indeed OK to sort the partitions, just makes things a lot
> > simpler. But we probably then should also do the following:
> >
> > 1. Make sure there is only one partition without offset. If there are
> > several - error out.
> 
>  Why allow `only one partition without offset`?

E.g.,

gpmi-nand:1g at 200m(rootfs),100m(boot),100m at 100m(kernel),200m(ququ)

how would "boot" and "ququ" look like?

What I basically say is that we should refuse lines like this. Which
means checking that there is only one "OFFSET_CONTINOUS" partition.

> Take the following unsorted partitions as an example:
>      #gpmi-nand:1g at 200m(rootfs),100m(boot),100m at 100m(kernel)
> 
> The current code will parses out the following partitions:
>       rootfs: < size = 1g, offset=200m>
>       boot:   < size = 100m, offset= OFFSET_CONTINOUS>
>       kernel: <size = 100m, offset = 100m>
> 
> If we sort the partitions by the offset, we get the following result:
>      "kernel" , "rootfs", "boot"

Yeah, for some reason I assumed that if you do not specify offset then
you mean the partition must be the _last_ and span the rest of flash. I
assume other usage is bogus. So from this POW the example is bogus and
lines like this would be rejected.

I guess the criteria is that this sting contains a "gap" (0-100m).

With the logic I suggested, for this case what I said would basically:

1. Sort. This leads to

100m at 100m(kernel)
1g at 200m(rootfs)
100m(boot)

"OFFSET_CONTINOUS" is always the largest and will be at the end when
sorting.

2. Verification.

We verify for overlaps and gaps. And refuse this one.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120903/dfe21cf4/attachment.sig>

From ccano at interfaceconcept.com  Mon Sep  3 11:58:13 2012
From: ccano at interfaceconcept.com (=?ISO-8859-1?Q?C=E9dric_Cano?=)
Date: Mon, 03 Sep 2012 17:58:13 +0200
Subject: [PATCH 1/2] drivers/mtd/devices/m25p80.c: Fix return code of
 read/write mtd callbacks
Message-ID: <5044D395.9050607@ic.fr>

From: C?dric Cano <ccano at interfaceconcept.com>

For SPI Flash devices, MTD read and write functions returns "1" if Flash 
is busy (this status is returned by "wait_till_ready" fnuction). This 
return code is not an error code: if device is busy, MTD read or write 
are successful with 1 byte length.

This patch fixes code returned by "wait_till_ready", "m25p80_erase", 
"m25p80_read", "m25p80_write" and "sst_write" functions: the error code 
is -EBUSY now.

C. Cano

Signed-off-by: C?dric Cano <ccano at interfaceconcept.com>

---
--- linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-08-26 
04:32:13.000000000 +0200
+++ linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-09-03 
17:35:16.159741656 +0200
@@ -199,7 +199,7 @@

      } while (!time_after_eq(jiffies, deadline));

-    return 1;
+    return -EBUSY;
  }

  /*
@@ -209,12 +209,15 @@
   */
  static int erase_chip(struct m25p *flash)
  {
+    int    ret;
+
      pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
              (long long)(flash->mtd.size >> 10));

      /* Wait until finished previous write command. */
-    if (wait_till_ready(flash))
-        return 1;
+    ret = wait_till_ready(flash);
+    if (ret)
+        return ret;

      /* Send write enable, then erase commands. */
      write_enable(flash);
@@ -249,12 +252,15 @@
   */
  static int erase_sector(struct m25p *flash, u32 offset)
  {
+    int    ret;
+
      pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
              __func__, flash->mtd.erasesize / 1024, offset);

      /* Wait until finished previous write command. */
-    if (wait_till_ready(flash))
-        return 1;
+    ret = wait_till_ready(flash);
+    if (ret)
+        return ret;

      /* Send write enable, then erase commands. */
      write_enable(flash);
@@ -283,6 +289,7 @@
      struct m25p *flash = mtd_to_m25p(mtd);
      u32 addr,len;
      uint32_t rem;
+    int ret;

      pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
              __func__, (long long)instr->addr,
@@ -299,10 +306,11 @@

      /* whole-chip erase? */
      if (len == flash->mtd.size) {
-        if (erase_chip(flash)) {
+        ret = erase_chip(flash);
+        if (ret) {
              instr->state = MTD_ERASE_FAILED;
              mutex_unlock(&flash->lock);
-            return -EIO;
+            return ret;
          }

      /* REVISIT in some cases we could speed up erasing large regions
@@ -313,10 +321,11 @@
      /* "sector"-at-a-time erase */
      } else {
          while (len) {
-            if (erase_sector(flash, addr)) {
+            ret = erase_sector(flash, addr);
+            if (ret) {
                  instr->state = MTD_ERASE_FAILED;
                  mutex_unlock(&flash->lock);
-                return -EIO;
+                return ret;
              }

              addr += mtd->erasesize;
@@ -339,6 +348,7 @@
  static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
      size_t *retlen, u_char *buf)
  {
+    int ret;
      struct m25p *flash = mtd_to_m25p(mtd);
      struct spi_transfer t[2];
      struct spi_message m;
@@ -364,10 +374,11 @@
      mutex_lock(&flash->lock);

      /* Wait till previous write/erase is done. */
-    if (wait_till_ready(flash)) {
+    ret = wait_till_ready(flash);
+    if (ret) {
          /* REVISIT status return?? */
          mutex_unlock(&flash->lock);
-        return 1;
+        return ret;
      }

      /* FIXME switch to OPCODE_FAST_READ.  It's required for higher
@@ -396,6 +407,7 @@
  static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
      size_t *retlen, const u_char *buf)
  {
+    int ret;
      struct m25p *flash = mtd_to_m25p(mtd);
      u32 page_offset, page_size;
      struct spi_transfer t[2];
@@ -417,9 +429,10 @@
      mutex_lock(&flash->lock);

      /* Wait until finished previous write command. */
-    if (wait_till_ready(flash)) {
+    ret = wait_till_ready(flash);
+    if (ret) {
          mutex_unlock(&flash->lock);
-        return 1;
+        return ret;
      }

      write_enable(flash);
---



From simonxwidmer at gmail.com  Mon Sep  3 12:16:57 2012
From: simonxwidmer at gmail.com (simon widmer)
Date: Mon, 03 Sep 2012 18:16:57 +0200
Subject: UBIFS Informations
In-Reply-To: <1346673385.3061.48.camel@sauron.fi.intel.com>
References: <503F7685.8030707@gmail.com>
 <1346673385.3061.48.camel@sauron.fi.intel.com>
Message-ID: <5044D7F9.2070906@gmail.com>

On 09/03/2012 01:56 PM, Artem Bityutskiy wrote:
> You are the second person complaining about this. What is the kernel 
> version your image worked fine with? 
I am working on custom target kernel (running on an arm based embedded 
system) which did not change version (i only changed compile options) 
->  2.6.31
The kernel on which I build the ubifs did in fact change -> from ubuntu 
8.4 (2.6.24) to ubuntu 10.04 (2.6.33)
I have to check if I still have the virtual machine image of the old 
building system that i could countercheck if I can reproduce a working 
image. I will do that tomorrow.




From ccano at interfaceconcept.com  Mon Sep  3 12:19:27 2012
From: ccano at interfaceconcept.com (=?ISO-8859-1?Q?C=E9dric_Cano?=)
Date: Mon, 03 Sep 2012 18:19:27 +0200
Subject: [PATCH 2/2] drivers/mtd/devices/m25p80.c: Fix whole device erase
Message-ID: <5044D88F.2060003@ic.fr>

From: C?dric Cano <ccano at interfaceconcept.com>

There are two ways to erase SPI Flash devices: sector per sector or the 
entire Flash (used when MTD partition is the whole Flash).

When the whole Flash is erased, the SPI command is sent to the device 
and the erase function ends. Then, when another access (read, write or 
erase) is done, a  wait of busy is performed that fails because of Flash 
erase time (can be more than 30s in case of whole erase).

This patch removes chip erase and use only sector per sector erase to 
erase the chip. When erase is performed, Flash accesses can be done.

C. Cano

Signed-off-by: C?dric Cano <ccano at interfaceconcept.com>
---

--- linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-09-03 
18:03:35.787723207 +0200
+++ linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-09-03 
18:01:17.455724709 +0200
@@ -202,31 +202,6 @@
      return -EBUSY;
  }

-/*
- * Erase the whole flash memory
- *
- * Returns 0 if successful, non-zero otherwise.
- */
-static int erase_chip(struct m25p *flash)
-{
-    pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
-            (long long)(flash->mtd.size >> 10));
-
-    /* Wait until finished previous write command. */
-    if (wait_till_ready(flash))
-        return 1;
-
-    /* Send write enable, then erase commands. */
-    write_enable(flash);
-
-    /* Set up command buffer. */
-    flash->command[0] = OPCODE_CHIP_ERASE;
-
-    spi_write(flash->spi, flash->command, 1);
-
-    return 0;
-}
-
  static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
  {
      /* opcode is in cmd[0] */
@@ -301,33 +276,17 @@

      mutex_lock(&flash->lock);

-    /* whole-chip erase? */
-    if (len == flash->mtd.size) {
-        ret = erase_chip(flash);
+    /* "sector"-at-a-time erase */
+    while (len) {
+        ret = erase_sector(flash, addr);
          if (ret) {
              instr->state = MTD_ERASE_FAILED;
              mutex_unlock(&flash->lock);
              return ret;
          }

-    /* REVISIT in some cases we could speed up erasing large regions
-     * by using OPCODE_SE instead of OPCODE_BE_4K.  We may have set up
-     * to use "small sector erase", but that's not always optimal.
-     */
-
-    /* "sector"-at-a-time erase */
-    } else {
-        while (len) {
-            ret = erase_sector(flash, addr)
-            if (ret) {
-                instr->state = MTD_ERASE_FAILED;
-                mutex_unlock(&flash->lock);
-                return ret;
-            }
-
-            addr += mtd->erasesize;
-            len -= mtd->erasesize;
-        }
+        addr += mtd->erasesize;
+        len -= mtd->erasesize;
      }

      mutex_unlock(&flash->lock);
---


From cernekee at gmail.com  Mon Sep  3 14:26:29 2012
From: cernekee at gmail.com (Kevin Cernekee)
Date: Mon, 3 Sep 2012 11:26:29 -0700
Subject: [PATCH 1/2] drivers/mtd/devices/m25p80.c: Fix return code of
 read/write mtd callbacks
In-Reply-To: <5044D395.9050607@ic.fr>
References: <5044D395.9050607@ic.fr>
Message-ID: <CAJiQ=7AwRnbtDtTd9u-j5xqOCqYx89R8CfK7MpQCYG3OossY0A@mail.gmail.com>

On Mon, Sep 3, 2012 at 8:58 AM, C?dric Cano <ccano at interfaceconcept.com> wrote:
> For SPI Flash devices, MTD read and write functions returns "1" if Flash is
> busy (this status is returned by "wait_till_ready" fnuction). This return

"function"

It is usually a good idea to wrap the commit text around 72-74
characters so that it is readable in "git log" on an 80-column
terminal.

> code is not an error code: if device is busy, MTD read or write are
> successful with 1 byte length.

Looking at mtd_read() - typically the transfer length is passed back
through the "size_t *retlen" pointer, not the function's return value.

In Linux 3.5, if m25p80_read() returns 1, mtd_read() will interpret it
as a bitflip count not a byte count.  That isn't the correct behavior
for a NOR device, but it probably wouldn't cause the symptom you are
reporting.

In Linux 3.4 and older, some functions like mtdchar_read() could
interpret the '1' as an error code and pass it back as-is to the
caller (who is expecting either a negative error code or a positive
length).  Is this the case you are running into?

Side note - it would be helpful to add kerneldoc markup to
include/linux/mtd/mtd.h for struct mtd_info and the new mtd_* wrapper
functions, so we have a clear definition of what the parameters and
return values should look like.

> --- linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-08-26
> 04:32:13.000000000 +0200
> +++ linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-09-03
> 17:35:16.159741656 +0200
> @@ -199,7 +199,7 @@

Could you please use "git format-patch" for your submissions, and base
them on the current head of tree?

Thanks.


From zajec5 at gmail.com  Mon Sep  3 15:07:17 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Mon,  3 Sep 2012 21:07:17 +0200
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
Message-ID: <1346699237-414-1-git-send-email-zajec5@gmail.com>

This registers MTD driver for serial flash platform device. Right now it
supports reading only, writing still has to be implemented.
At this point it's marked as BROKEN, because it requires code present in
net tree that wasn't mainlined yet.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
V2: fix mem leak (add failure path in init)
    signed-off-by
---
 drivers/mtd/devices/Kconfig         |    8 ++
 drivers/mtd/devices/Makefile        |    1 +
 drivers/mtd/devices/bcm47xxsflash.c |  132 +++++++++++++++++++++++++++++++++++
 3 files changed, 141 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/devices/bcm47xxsflash.c

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 4cdb2af..4b4f7d2 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -120,6 +120,14 @@ config MTD_SST25L
 	  Set up your spi devices with the right board-specific platform data,
 	  if you want to specify device partitioning.
 
+config MTD_BCM47XXSFLASH
+	tristate "Support for serial flash on BCMA bus"
+	depends on BCMA_SFLASH && BROKEN
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  serial flash memories.
+
 config MTD_SLRAM
 	tristate "Uncached system RAM"
 	help
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index a4dd1d8..395733a 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
 obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
 obj-$(CONFIG_MTD_SPEAR_SMI)	+= spear_smi.o
 obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
+obj-$(CONFIG_MTD_BCM47XXSFLASH)	+= bcm47xxsflash.o
 
 CFLAGS_docg3.o			+= -I$(src)
\ No newline at end of file
diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
new file mode 100644
index 0000000..0283138
--- /dev/null
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -0,0 +1,132 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+			      size_t *retlen, u_char *buf)
+{
+	struct bcma_sflash *sflash = mtd->priv;
+	size_t bytes_read = 0;
+	u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
+	int i;
+	size_t unaligned_before, unaligned_after;
+
+	/* Check address range */
+	if ((from + len) > mtd->size)
+		return -EINVAL;
+
+	unaligned_before = from & 0x3;
+	unaligned_after = (from + len) & 0x3;
+
+	for (i = 0; i < unaligned_before; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+	for (i = from - unaligned_before; i < from + len - unaligned_after;
+	     i += 4) {
+		*(u32 *)buf = readl((u32 *)src);
+		buf += 4;
+		src += 4;
+		bytes_read += 4;
+	}
+	for (i = 0; i < unaligned_after; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+
+	*retlen = bytes_read;
+
+	return 0;
+}
+
+static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
+				   struct mtd_info *mtd)
+{
+	mtd->priv = sflash;
+	mtd->name = "bcm47xxsflash";
+	mtd->owner = THIS_MODULE;
+	mtd->type = MTD_ROM;
+	mtd->size = sflash->size;
+	mtd->_read = bcm47xxsflash_read;
+	mtd->writesize = 1; /* FIXME */
+}
+
+static int bcm47xxsflash_probe(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+	int err;
+
+	sflash->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
+	if (!sflash->mtd) {
+		err = -ENOMEM;
+		goto out;
+	}
+	bcm47xxsflash_fill_mtd(sflash, sflash->mtd);
+
+	err = mtd_device_parse_register(sflash->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		goto err_dev_reg;
+	}
+
+	return 0;
+
+err_dev_reg:
+	kfree(sflash->mtd);
+out:
+	return err;
+}
+
+static int __devexit bcm47xxsflash_remove(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+
+	if (!sflash->mtd) {
+		WARN_ON(1);
+		return -ENODEV;
+	}
+
+	mtd_device_unregister(sflash->mtd);
+	kfree(sflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcma_sflash_driver = {
+	.remove = __devexit_p(bcm47xxsflash_remove),
+	.driver = {
+		.name = "bcma_sflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxsflash_init(void)
+{
+	int err;
+
+	err = platform_driver_probe(&bcma_sflash_driver, bcm47xxsflash_probe);
+	if (err)
+		pr_err("Failed to register BCMA serial flash driver: %d\n", err);
+
+	return err;
+}
+
+static void __exit bcm47xxsflash_exit(void)
+{
+	platform_driver_unregister(&bcma_sflash_driver);
+}
+
+module_init(bcm47xxsflash_init);
+module_exit(bcm47xxsflash_exit);
-- 
1.7.7



From marex at denx.de  Mon Sep  3 20:04:09 2012
From: marex at denx.de (Marek Vasut)
Date: Tue, 4 Sep 2012 02:04:09 +0200
Subject: [PATCH V5] mtd: m25p80: Make fast read configurable via DT
In-Reply-To: <1345923416-9293-1-git-send-email-marex@denx.de>
References: <1345923416-9293-1-git-send-email-marex@denx.de>
Message-ID: <201209040204.09537.marex@denx.de>

Hi Artem,

> Add DT property "m25p,fast-read" that signalises the particular
> chip supports "fast read" opcode.

Do you think it's aplicable now ?

> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Cc: David Woodhouse <david.woodhouse at intel.com>

[...]

Best regards,
Marek Vasut


From yw100.lee at samsung.com  Mon Sep  3 22:16:48 2012
From: yw100.lee at samsung.com (=?euc-kr?B?wMy+57/s?=)
Date: Tue, 04 Sep 2012 02:16:48 +0000 (GMT)
Subject: Fwd: ubifs crash with two cases( switched to readonly, recover fail )
Message-ID: <0M9S00ISLZO0NEE0@mailout1.samsung.com>

An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/8887785a/attachment-0001.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: 201209041117600_BEI0XT4N.gif
Type: image/gif
Size: 14036 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/8887785a/attachment-0001.gif>

From b32955 at freescale.com  Mon Sep  3 23:23:24 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 11:23:24 +0800
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <1346686544.3061.75.camel@sauron.fi.intel.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
 <1346686544.3061.75.camel@sauron.fi.intel.com>
Message-ID: <5045742C.9000608@freescale.com>

? 2012?09?03? 23:35, Artem Bityutskiy ??:
> 1. Sort. This leads to
>
> 100m at 100m(kernel)
> 1g at 200m(rootfs)
> 100m(boot)
>
> "OFFSET_CONTINOUS" is always the largest and will be at the end when
> sorting.
>
ok.
> 2. Verification.
>
> We verify for overlaps and gaps. And refuse this one.
>
It's really necessary to check the overlaps.

I will try to send out the new patch set.


Best Regards
Huang Shijie




From marex at denx.de  Mon Sep  3 23:31:36 2012
From: marex at denx.de (Marek Vasut)
Date: Tue,  4 Sep 2012 05:31:36 +0200
Subject: [PATCH] mtd: m25p80: Disable 4K erase for s25sl032p, s25sl064p
Message-ID: <1346729496-3303-1-git-send-email-marex@denx.de>

Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011,
section 9.17:

A 64 kB sector erase (D8h) command issued on 4 kB or 8 kB erase
sectors will erase all sectors in the specified 64 kB region.
However, please note that a 4 kB sector erase (20h) or 8 kB
sector erase (40h) command will not work on a 64 kB sector.

Refering further to Table 8.1 and Table 8.2, it is clearly seen
that most of the sectors are 64kB, therefore disable this 4K
erase support since it's valid only on first/last sectors.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: David Woodhouse <david.woodhouse at intel.com>
---
 drivers/mtd/devices/m25p80.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c433051..9930e23 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -661,8 +661,8 @@ static const struct spi_device_id m25p_ids[] = {
 	/* Spansion -- single (large) sector size only, at least
 	 * for the chips listed here (without boot sectors).
 	 */
-	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SECT_4K) },
-	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SECT_4K) },
+	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, 0) },
+	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, 0) },
 	{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
 	{ "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, 0) },
 	{ "s25fl512s",  INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
-- 
1.7.10.4



From dedekind1 at gmail.com  Tue Sep  4 02:55:17 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 09:55:17 +0300
Subject: [GIT PULL] UBI fix for v3.6-rc5
Message-ID: <1346741717.12610.2.camel@sauron.fi.intel.com>

The following changes since commit 4cbe5a555fa58a79b6ecbb6c531b8bab0650778d:

  Linux 3.6-rc4 (2012-09-01 10:39:58 -0700)

are available in the git repository at:

  git://git.infradead.org/linux-ubi.git tags/upstream-3.6-rc5

for you to fetch changes up to 78b495c39add820ab66ab897af9bd77a5f2e91f6:

  UBI: fix a horrible memory deallocation bug (2012-09-04 09:40:26 +0300)

----------------------------------------------------------------
A single small fix for memory deallocation: we allocated memory using
'kmem_cache_alloc()' but were freeing it using 'kfree()' in some cases.
Now we fix this by using 'kmem_cache_free()' instead.

----------------------------------------------------------------
Artem Bityutskiy (1):
      UBI: fix a horrible memory deallocation bug

 drivers/mtd/ubi/vtbl.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/78c5c2f3/attachment.sig>

From dedekind1 at gmail.com  Tue Sep  4 03:20:00 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 10:20:00 +0300
Subject: [PATCH] UBI: fix trivial typo 'it' => 'is'
In-Reply-To: <1346449421-22067-1-git-send-email-computersforpeace@gmail.com>
References: <1346449421-22067-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1346743200.12610.3.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 14:43 -0700, Brian Norris wrote:
> Signed-off-by: Brian Norris <computersforpeace at gmail.com>
> ---
>  drivers/mtd/ubi/attach.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Pushed to linux-ubi, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/80652783/attachment.sig>

From dedekind1 at gmail.com  Tue Sep  4 03:46:36 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 10:46:36 +0300
Subject: RCU warning during UBI file system mount
In-Reply-To: <5042EC5D.1010207@grid-net.com>
References: <5042EC5D.1010207@grid-net.com>
Message-ID: <1346744796.12610.6.camel@sauron.fi.intel.com>

Let's CC LKML and Paul.

 
On Sat, 2012-09-01 at 22:19 -0700, Subodh Nijsure wrote:
> Hello,
> 
> I am running 3.6-rc4 kernel on my MX28 based board and every time I 
> mount UBI file system I see following warning.
> Anybody else seen this errors, particularly those running it on MXS 
> platform?
> 
> I haven't debugged RCU warnings before any clues as to what is the 
> source of this warning is, should I be looking at 
> start_dma_without_bch_irq() code? Would appreciate any pointers in 
> fixing this...
> 
> [    4.280000] WARNING: at /opt/git/kernel-mainline/kernel/rcutiny.c:75 
> rcu_idle_enter_common.clone.7+0x90/0xac()
> [    4.280000] Current pid: 1 comm: swapper / Idle pid: 0 comm: swapper
> [    4.280000] Modules linked in:
> [    4.280000] [<c0014eec>] (unwind_backtrace+0x0/0x130) from 
> [<c001dd94>] (warn_slowpath_common+0x4c/0x64)
> [    4.280000] [<c001dd94>] (warn_slowpath_common+0x4c/0x64) from 
> [<c001de40>] (warn_slowpath_fmt+0x30/0x40)
> [    4.280000] [<c001de40>] (warn_slowpath_fmt+0x30/0x40) from 
> [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
> [    4.280000] [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac) 
> from [<c0061670>] (rcu_irq_exit+0x3c/0x78)
> [    4.280000] [<c0061670>] (rcu_irq_exit+0x3c/0x78) from [<c000fe90>] 
> (handle_IRQ+0x34/0x84)
> [    4.280000] [<c000fe90>] (handle_IRQ+0x34/0x84) from [<c000ec34>] 
> (__irq_svc+0x34/0x58)
> [    4.280000] [<c000ec34>] (__irq_svc+0x34/0x58) from [<c0394c4c>] 
> (schedule_timeout+0xdc/0x16c)
> [    4.280000] [<c0394c4c>] (schedule_timeout+0xdc/0x16c) from 
> [<c0395f34>] (wait_for_common+0xb4/0x160)
> [    4.280000] [<c0395f34>] (wait_for_common+0xb4/0x160) from 
> [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8)
> [    4.280000] [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8) from 
> [<c0258660>] (gpmi_send_command+0x120/0x154)
> [    4.280000] [<c0258660>] (gpmi_send_command+0x120/0x154) from 
> [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c)
> [    4.280000] [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c) from [<c024f8e0>] 
> (nand_command_lp+0xe8/0x270)
> [    4.280000] [<c024f8e0>] (nand_command_lp+0xe8/0x270) from 
> [<c0251e00>] (nand_do_read_ops+0x124/0x444)
> [    4.280000] [<c0251e00>] (nand_do_read_ops+0x124/0x444) from 
> [<c0252558>] (nand_read+0x54/0x78)
> [    4.280000] [<c0252558>] (nand_read+0x54/0x78) from [<c02499a4>] 
> (part_read+0x48/0x80)
> [    4.280000] [<c02499a4>] (part_read+0x48/0x80) from [<c0246910>] 
> (mtd_read+0x88/0xb4)
> [    4.280000] [<c0246910>] (mtd_read+0x88/0xb4) from [<c026b188>] 
> (ubi_io_read+0xb0/0x3e8)
> [    4.280000] [<c026b188>] (ubi_io_read+0xb0/0x3e8) from [<c026740c>] 
> (ubi_eba_read_leb+0x198/0x4bc)
> [    4.280000] [<c026740c>] (ubi_eba_read_leb+0x198/0x4bc) from 
> [<c0266800>] (ubi_leb_read+0xf4/0x16c)
> [    4.280000] [<c0266800>] (ubi_leb_read+0xf4/0x16c) from [<c0155550>] 
> (ubifs_leb_read+0x24/0x88)
> [    4.280000] [<c0155550>] (ubifs_leb_read+0x24/0x88) from [<c01572f8>] 
> (ubifs_read_node+0xa8/0x2e4)
> [    4.280000] [<c01572f8>] (ubifs_read_node+0xa8/0x2e4) from 
> [<c0153c50>] (ubifs_read_sb_node+0x54/0x78)
> [    4.280000] [<c0153c50>] (ubifs_read_sb_node+0x54/0x78) from 
> [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c)
> [    4.280000] [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c) from 
> [<c01520ac>] (ubifs_mount+0x73c/0x1bc0)
> [    4.280000] [<c01520ac>] (ubifs_mount+0x73c/0x1bc0) from [<c00a49ec>] 
> (mount_fs+0x44/0x184)
> [    4.280000] [<c00a49ec>] (mount_fs+0x44/0x184) from [<c00baf90>] 
> (vfs_kern_mount+0x4c/0xc0)
> [    4.280000] [<c00baf90>] (vfs_kern_mount+0x4c/0xc0) from [<c00bb1a0>] 
> (do_kern_mount+0x34/0xd0)
> [    4.280000] [<c00bb1a0>] (do_kern_mount+0x34/0xd0) from [<c00bc93c>] 
> (do_mount+0x15c/0x73c)
> [    4.280000] [<c00bc93c>] (do_mount+0x15c/0x73c) from [<c00bcfa0>] 
> (sys_mount+0x84/0xc4)
> [    4.280000] [<c00bcfa0>] (sys_mount+0x84/0xc4) from [<c04e4a04>] 
> (do_mount_root+0x24/0xb0)
> [    4.280000] [<c04e4a04>] (do_mount_root+0x24/0xb0) from [<c04e4b78>] 
> (mount_block_root+0xe8/0x214)
> [    4.280000] [<c04e4b78>] (mount_block_root+0xe8/0x214) from 
> [<c04e4e28>] (prepare_namespace+0x8c/0x180)
> [    4.280000] [<c04e4e28>] (prepare_namespace+0x8c/0x180) from 
> [<c04e4894>] (kernel_init+0x16c/0x1b4)
> [    4.280000] [<c04e4894>] (kernel_init+0x16c/0x1b4) from [<c000ff70>] 
> (kernel_thread_exit+0x0/0x8)
> [    4.280000] ---[ end trace 4d36b722759fdc4f ]---
> [    4.950000] UBIFS DBG (pid 58): ubifs_bg_thread: background thread 
> "ubifs_bgt0_0" started, PID 58
> 
> -Subodh
> 
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/8f2e02d3/attachment.sig>

From dedekind1 at gmail.com  Tue Sep  4 03:47:33 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 10:47:33 +0300
Subject: FW: UBIFS tools and latest 2.6.33 kernel from
 http://git.infradead.org/users/dedekind/ubifs-v2.6.33.git
In-Reply-To: <504448B1.4050205@gmail.com>
References: <886EEBE3AFFFB144AA8169C199AB4E6AA7BC4D5FB8@BBMBX.backbone.local>
 <1346416026.9709.47.camel@sauron.fi.intel.com>
 <CAN8TOE8j9gxpXAmL51gqaW8=TFLQLPhp03inryx_-uZv4901Ng@mail.gmail.com>
 <1346583467.2533.1.camel@kyv> <504448B1.4050205@gmail.com>
Message-ID: <1346744853.12610.7.camel@sauron.fi.intel.com>

On Sun, 2012-09-02 at 23:05 -0700, Brian Norris wrote:
> On 09/02/2012 03:57 AM, Artem Bityutskiy wrote:
> > On Fri, 2012-08-31 at 15:18 -0700, Brian Norris wrote:
> >> There was a series of 'writebufsize' fixes that may be missing from
> >> multiple backport trees. I can help you track them down, if you'd like
> >> the help.
> >
> > Sure, go ahead, I can them put them to the backport trees.
> 
> OK, I just put up my own github backport tree, with branches for v2.6.32 
> through v3.3. I think your v3.4+ repos are fine. URL:
> 
>    git://github.com/computersforpeace/UBIFS-backports.git
>    https://github.com/computersforpeace/UBIFS-backports.git

Thanks Brian, pulled all the branches.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/54719e36/attachment-0001.sig>

From dedekind1 at gmail.com  Tue Sep  4 03:50:25 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 10:50:25 +0300
Subject: [PATCH 3/4] drivers/mtd/maps/autcpu12-nvram.c: drop frees of
 devm_ alloc'd data
In-Reply-To: <1346517191-8794-5-git-send-email-Julia.Lawall@lip6.fr>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
 <1346517191-8794-5-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1346745025.12610.8.camel@sauron.fi.intel.com>

On Sat, 2012-09-01 at 18:33 +0200, Julia Lawall wrote:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> devm free functions should not have to be explicitly used.
> 
> A semantic match that finds this problem is as follows:
> (http://coccinelle.lip6.fr/)

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/b079ad6d/attachment.sig>

From ccano at interfaceconcept.com  Tue Sep  4 03:54:43 2012
From: ccano at interfaceconcept.com (=?UTF-8?B?Q8OpZHJpYyBDYW5v?=)
Date: Tue, 04 Sep 2012 09:54:43 +0200
Subject: [PATCH 1/2] drivers/mtd/devices/m25p80.c: Fix return code of
 read/write mtd callbacks
In-Reply-To: <CAJiQ=7AwRnbtDtTd9u-j5xqOCqYx89R8CfK7MpQCYG3OossY0A@mail.gmail.com>
References: <5044D395.9050607@ic.fr>
 <CAJiQ=7AwRnbtDtTd9u-j5xqOCqYx89R8CfK7MpQCYG3OossY0A@mail.gmail.com>
Message-ID: <5045B3C3.8020500@interfaceconcept.com>

Le 03/09/2012 20:26, Kevin Cernekee a ?crit :
> On Mon, Sep 3, 2012 at 8:58 AM, C?dric Cano <ccano at interfaceconcept.com> wrote:
>> For SPI Flash devices, MTD read and write functions returns "1" if Flash is
>> busy (this status is returned by "wait_till_ready" fnuction). This return
> "function"
>
> It is usually a good idea to wrap the commit text around 72-74
> characters so that it is readable in "git log" on an 80-column
> terminal.
>
>> code is not an error code: if device is busy, MTD read or write are
>> successful with 1 byte length.
> Looking at mtd_read() - typically the transfer length is passed back
> through the "size_t *retlen" pointer, not the function's return value.
>
> In Linux 3.5, if m25p80_read() returns 1, mtd_read() will interpret it
> as a bitflip count not a byte count.  That isn't the correct behavior
> for a NOR device, but it probably wouldn't cause the symptom you are
> reporting.
>
> In Linux 3.4 and older, some functions like mtdchar_read() could
> interpret the '1' as an error code and pass it back as-is to the
> caller (who is expecting either a negative error code or a positive
> length).  Is this the case you are running into?

You're alright: I'm doing my test on kernel 3.4. In this case, '1' is
the return code of mtd_read() that is considered as a length, not an
error.
In kernel 3.5, it should work without this patch (I can't test it).

>
> Side note - it would be helpful to add kerneldoc markup to
> include/linux/mtd/mtd.h for struct mtd_info and the new mtd_* wrapper
> functions, so we have a clear definition of what the parameters and
> return values should look like.
>
>> --- linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-08-26
>> 04:32:13.000000000 +0200
>> +++ linux-3.5.3/drivers/mtd/devices/m25p80.c    2012-09-03
>> 17:35:16.159741656 +0200
>> @@ -199,7 +199,7 @@
> Could you please use "git format-patch" for your submissions, and base
> them on the current head of tree?
>
> Thanks.
>
OK, I will repost my second patch with this method.

Thanks.



From dedekind1 at gmail.com  Tue Sep  4 04:03:23 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 11:03:23 +0300
Subject: [PATCH] jffs2: don't fail on bitflips in OOB
In-Reply-To: <1346450479-22400-1-git-send-email-computersforpeace@gmail.com>
References: <1346450479-22400-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1346745803.12610.9.camel@sauron.fi.intel.com>

On Fri, 2012-08-31 at 15:01 -0700, Brian Norris wrote:
> JFFS2 was designed without thought for OOB bitflips, it seems, but they
> can occur and will be reported to JFFS2 via mtd_read_oob()[1]. We don't
> want to fail on these transactions, since the data was corrected.
> 
> [1] Few drivers report bitflips for OOB-only transactions. With such
>     drivers, this patch should have no effect.
> 
> Signed-off-by: Brian Norris <computersforpeace at gmail.com>
> Cc: stable at vger.kernel.org

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/eb9eff08/attachment.sig>

From b32955 at freescale.com  Tue Sep  4 03:43:46 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 15:43:46 +0800
Subject: [PATCH v2 1/3] mtd: cmdlinepart: sort the unsorted partitions
Message-ID: <1346744628-13840-1-git-send-email-b32955@freescale.com>

Assume we have a 1GB(8Gb) nand chip.
It is legit if we set the partitions as the following:
    gpmi-nand:1g at 200m(rootfs),100m at 0(boot),100m at 100m(kernel)

Unfortunately, the current code can not parse out any partition with this
cmdline. The parse_cmdline_partitions() will meet the
truncated partition `rootfs` firstly. But the parse_cmdline_partitions()
will break its `for` loop with the following line when the truncating occurs.

       ...........................
	part->num_parts = i;
       ...........................

What's worse is that this line has a bug in it. It accidently misses
the truncated partitions. So we can not parse out any partition.

In this case, we should parse out the `boot` and `kernel` partitions at least.
So we need to sort the unsorted partitions. With the sorted partitions, the
parse_cmdline_partitions() can parse out the `boot` and `kernel` successfully.

This patch sorts the unsorted partitions by the @offset.
For there are maybe only several partitions, so the Bubble sort algorithm
is enough.

We also need another patch to fix the missed truncated partition issue.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/cmdlinepart.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 17b0bd4..dde8e84 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -205,6 +205,26 @@ static struct mtd_partition * newpart(char *s,
 	return parts;
 }
 
+/* There are only several partitions, so the Bubble sort is enough. */
+static inline void sort_partitons(struct mtd_partition *parts, int num_parts)
+{
+	int i, j;
+
+	/* sort by the offset */
+	for (i = 0; i < num_parts - 1; i++) {
+		for (j = 1; j < num_parts - i; j++) {
+			if (parts[j - 1].offset > parts[j].offset) {
+				struct mtd_partition tmp;
+
+				tmp = parts[j - 1];
+				parts[j - 1] = parts[j];
+				parts[j] = tmp;
+			}
+		}
+	}
+	return;
+}
+
 /*
  * Parse the command line.
  */
@@ -262,6 +282,9 @@ static int mtdpart_setup_real(char *s)
 		this_mtd->mtd_id = (char*)(this_mtd + 1);
 		strlcpy(this_mtd->mtd_id, mtd_id, mtd_id_len + 1);
 
+		/* sort the partitions */
+		sort_partitons(parts, num_parts);
+
 		/* link into chain */
 		this_mtd->next = partitions;
 		partitions = this_mtd;
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep  4 03:43:48 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 15:43:48 +0800
Subject: [PATCH v2 3/3] mtd: cmdlinepart: check the partitions
In-Reply-To: <1346744628-13840-1-git-send-email-b32955@freescale.com>
References: <1346744628-13840-1-git-send-email-b32955@freescale.com>
Message-ID: <1346744628-13840-3-git-send-email-b32955@freescale.com>

The partitions are all sorted well by the @offset.
But we should check if there are errors in the partitions.

The following cases are regarded as errors:
  [1] There is a hole in the partitions, such as
      #gpmi-nand:100m(boot),100m at 100m(kernel),1g at 200m(rootfs)

  [2] There is a overlap in the partitions, such as
      #gpmi-nand:100m at 0(boot),100m at 50m(kernel),1g at 150m(rootfs)

  [3] Not all the partitions are set with @offset, and there are
      more then one partion whose offset is OFFSET_CONTINUOUS.
      #gpmi-nand:100m at 0(boot),100m(kernel),-(usr)

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/cmdlinepart.c |   82 ++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 77 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index edd17e0..3473af5 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -225,6 +225,53 @@ static inline void sort_partitons(struct mtd_partition *parts, int num_parts)
 	return;
 }
 
+enum partition_check_result {
+	PARTITION_GOOD,
+	PARTITION_OVERLAPPED,
+	PARTITION_HOLE,
+	PARTITION_TOO_MUCH_CONT,
+};
+
+/* The partitions have been sorted well by the @offset. */
+static inline int check_partitions(struct mtd_partition *parts, int num_parts)
+{
+	int i;
+	uint64_t offset = 0;
+	int offset_continuous_cnt = 0;
+
+	for (i = 0; i < num_parts; i++) {
+		if (parts[i].offset == OFFSET_CONTINUOUS) {
+			offset_continuous_cnt++;
+			continue;
+		}
+
+		/* find a hole. */
+		if (parts[i].offset > offset)
+			return PARTITION_HOLE;
+
+		/* find an overlapped partition. */
+		if (parts[i].offset < offset)
+			return PARTITION_OVERLAPPED;
+
+		offset += parts[i].size;
+	}
+
+	if (offset_continuous_cnt) {
+		/* We do not set partitions with the @offset in the cmdline. */
+		if (offset_continuous_cnt == num_parts)
+			return PARTITION_GOOD;
+
+		/* It's ok if there is only one OFFSET_CONTINUOUS partition. */
+		if (offset_continuous_cnt == 1)
+			return PARTITION_GOOD;
+
+		return PARTITION_TOO_MUCH_CONT;
+	}
+
+	/* We set with @offset for all the partitions in the cmdline. */
+	return PARTITION_GOOD;
+}
+
 /*
  * Parse the command line.
  */
@@ -238,6 +285,7 @@ static int mtdpart_setup_real(char *s)
 		struct mtd_partition *parts;
 		int mtd_id_len, num_parts;
 		char *p, *mtd_id;
+		enum partition_check_result ret;
 
 		mtd_id = s;
 
@@ -285,13 +333,37 @@ static int mtdpart_setup_real(char *s)
 		/* sort the partitions */
 		sort_partitons(parts, num_parts);
 
-		/* link into chain */
-		this_mtd->next = partitions;
-		partitions = this_mtd;
+		/* check the partitions */
+		ret = check_partitions(parts, num_parts);
+		switch (ret) {
+		case PARTITION_GOOD:
+			/* link into chain */
+			this_mtd->next = partitions;
+			partitions = this_mtd;
 
-		dbg(("mtdid=<%s> num_parts=<%d>\n",
-		     this_mtd->mtd_id, this_mtd->num_parts));
+			dbg(("mtdid=<%s> num_parts=<%d>\n",
+			     this_mtd->mtd_id, this_mtd->num_parts));
+			break;
 
+		case PARTITION_OVERLAPPED:
+			printk(KERN_ERR ERRP "%s:The partitions overlap,"
+				"please check the cmdline, and fix it.\n",
+				this_mtd->mtd_id);
+			break;
+
+		case PARTITION_HOLE:
+			printk(KERN_ERR ERRP "%s:There is a hole in the "
+				"partitions, please check the cmdline, "
+				"and fix it.\n",
+				this_mtd->mtd_id);
+			break;
+
+		case PARTITION_TOO_MUCH_CONT:
+			printk(KERN_ERR ERRP "%s:The offset is not right,"
+				"please check the cmdline, and fix it.\n",
+				this_mtd->mtd_id);
+			break;
+		}
 
 		/* EOS - we're done */
 		if (*s == 0)
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep  4 03:43:47 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 15:43:47 +0800
Subject: [PATCH v2 2/3] mtd: cmdlinepart: fix the wrong partitions number when
 truncating occurs
In-Reply-To: <1346744628-13840-1-git-send-email-b32955@freescale.com>
References: <1346744628-13840-1-git-send-email-b32955@freescale.com>
Message-ID: <1346744628-13840-2-git-send-email-b32955@freescale.com>

This patch is based on the assumption that all the partitions are
in the right offset order.

Assume we have a 1GB(8Gb) nand chip, and we set the partitions
in the command line like this:
    #gpmi-nand:100m(boot),100m(kernel),1g(rootfs)

In this case, the partition truncating occurs. The current code will
get the following result:

     ----------------------------------
	root at freescale ~$ cat /proc/mtd
	dev:    size   erasesize  name
	mtd0: 06400000 00040000 "boot"
	mtd1: 06400000 00040000 "kernel"
     ----------------------------------

It is obvious that we lost the truncated partition `rootfs` which should
be 824M in this case.

Why? The old code sets the wrong partitions number when the truncating
occurs. This patch fixes it. Alao add a `break` to shortcut the code in this
case.

After apply this patch, the result becomes:
     ----------------------------------
	root at freescale ~$ cat /proc/mtd
	dev:    size   erasesize  name
	mtd0: 06400000 00040000 "boot"
	mtd1: 06400000 00040000 "kernel"
	mtd2: 33800000 00040000 "rootfs"
     ----------------------------------

We get the right result.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/cmdlinepart.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index dde8e84..edd17e0 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -347,7 +347,8 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 					       "%s: partitioning exceeds flash size, truncating\n",
 					       part->mtd_id);
 					part->parts[i].size = master->size - offset;
-					part->num_parts = i;
+					part->num_parts = i + 1;
+					break;
 				}
 				offset += part->parts[i].size;
 			}
-- 
1.7.0.4




From dedekind1 at gmail.com  Tue Sep  4 04:19:45 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 11:19:45 +0300
Subject: [PATCH v2 3/3] mtd: cmdlinepart: check the partitions
In-Reply-To: <1346744628-13840-3-git-send-email-b32955@freescale.com>
References: <1346744628-13840-1-git-send-email-b32955@freescale.com>
 <1346744628-13840-3-git-send-email-b32955@freescale.com>
Message-ID: <1346746785.12610.12.camel@sauron.fi.intel.com>

On Tue, 2012-09-04 at 15:43 +0800, Huang Shijie wrote:
> +enum partition_check_result {
> +	PARTITION_GOOD,
> +	PARTITION_OVERLAPPED,
> +	PARTITION_HOLE,
> +	PARTITION_TOO_MUCH_CONT,
> +};

Could you please kill these constants, they are not really needed I
think.

> +/* The partitions have been sorted well by the @offset. */
> +static inline int check_partitions(struct mtd_partition *parts, int num_parts)
> +{
> +	int i;
> +	uint64_t offset = 0;
> +	int offset_continuous_cnt = 0;
> +
> +	for (i = 0; i < num_parts; i++) {
> +		if (parts[i].offset == OFFSET_CONTINUOUS) {
> +			offset_continuous_cnt++;
> +			continue;
> +		}
> +
> +		/* find a hole. */
> +		if (parts[i].offset > offset)
> +			return PARTITION_HOLE;

Just print the error messages in this function and return -EINVAL.


> @@ -285,13 +333,37 @@ static int mtdpart_setup_real(char *s)
>  		/* sort the partitions */
>  		sort_partitons(parts, num_parts);
>  
> -		/* link into chain */
> -		this_mtd->next = partitions;
> -		partitions = this_mtd;
> +		/* check the partitions */
> +		ret = check_partitions(parts, num_parts);

Just do

if (ret)
	return ret;


and kill the huge 'switch' that you added.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/293eb97b/attachment.sig>

From akinobu.mita at gmail.com  Tue Sep  4 04:16:52 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Tue, 4 Sep 2012 17:16:52 +0900
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <1346685918.3061.66.camel@sauron.fi.intel.com>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 <1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 <1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
 <1346685918.3061.66.camel@sauron.fi.intel.com>
Message-ID: <CAC5umyhakuTz=d5Gr6DiUZQSvuefo6S86KR55qQbQ_x+LUiDbA@mail.gmail.com>

2012/9/4 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Fri, 2012-08-31 at 08:59 +1000, Iwo Mergler wrote:
>> This tests ECC biterror recovery on a single NAND page. Mostly intended
>> to test ECC hardware and low-level NAND driver.
>>
>> There are two test modes:
>>
>>     0 - artificially inserting bit errors until the ECC fails
>>         This is the default method and fairly quick. It should
>>         be independent of the quality of the FLASH.
>>
>>     1 - re-writing the same pattern repeatedly until the ECC fails.
>>         This method relies on the physics of NAND FLASH to eventually
>>         generate '0' bits if '1' has been written sufficient times. Depending
>>         on the NAND, the first bit errors will appear after 1000 or
>>         more writes and then will usually snowball, reaching the limits
>>         of the ECC quickly.
>>
>> The test stops after 10000 cycles, should your FLASH be exceptionally
>> good and not generate bit errors before that. Try a different page
>> offset in that case.
>>
>> Please note that neither of these tests will significantly 'use up' any FLASH
>> endurance. Only a maximum of two erase operations will be performed.
>>
>> Signed-off-by: Iwo Mergler <Iwo.Mergler at netcommwireless.com.au>
>> ---
>>  drivers/mtd/tests/Makefile          |    1 +
>>  drivers/mtd/tests/mtd_nandbiterrs.c |  460 +++++++++++++++++++++++++++++++++++
>>  2 files changed, 461 insertions(+), 0 deletions(-)
>>  create mode 100644 drivers/mtd/tests/mtd_nandbiterrs.c
>>
>> diff --git a/drivers/mtd/tests/Makefile b/drivers/mtd/tests/Makefile
>> index b44dcab..bd0065c 100644
>> --- a/drivers/mtd/tests/Makefile
>> +++ b/drivers/mtd/tests/Makefile
>> @@ -6,3 +6,4 @@ obj-$(CONFIG_MTD_TESTS) += mtd_stresstest.o
>>  obj-$(CONFIG_MTD_TESTS) += mtd_subpagetest.o
>>  obj-$(CONFIG_MTD_TESTS) += mtd_torturetest.o
>>  obj-$(CONFIG_MTD_TESTS) += mtd_nandecctest.o
>> +obj-$(CONFIG_MTD_TESTS) += mtd_nandbiterrs.o
>> diff --git a/drivers/mtd/tests/mtd_nandbiterrs.c b/drivers/mtd/tests/mtd_nandbiterrs.c
>> new file mode 100644
>> index 0000000..94e908e
>> --- /dev/null
>> +++ b/drivers/mtd/tests/mtd_nandbiterrs.c
>> @@ -0,0 +1,460 @@
>> +/*
>> + * (C)2012 NetCommWireless
>> + * Iwo Mergler <Iwo.Mergler at netcommwireless.com.au>
>> + *
>> + * Test for multi-bit error recovery on a NAND page This mostly tests the
>> + * ECC controller / driver.
>> + *
>> + * There are two test modes:
>> + *
>> + *   0 - artificially inserting bit errors until the ECC fails
>> + *       This is the default method and fairly quick. It should
>> + *       be independent of the quality of the FLASH.
>> + *
>> + *   1 - re-writing the same pattern repeatedly until the ECC fails.
>> + *       This method relies on the physics of NAND FLASH to eventually
>> + *       generate '0' bits if '1' has been written sufficient times.
>> + *       Depending on the NAND, the first bit errors will appear after
>> + *       1000 or more writes and then will usually snowball, reaching the
>> + *       limits of the ECC quickly.
>> + *
>> + *       The test stops after 10000 cycles, should your FLASH be
>> + *       exceptionally good and not generate bit errors before that. Try
>> + *       a different page in that case.
>
> So basically you test that ECC works, and you are trying to be
> independent on the NAND HW and the ECC type. Right?
>
> How about mtd_nandecc test? How is it different? Do we need 2 tests?
> Why?
>
> Akinobu - you recently sent a large patch-set for mtd_nandecctest, could
> you please also comment on the above questions?

I think the test mtd_nandbiterrs is trying to do is useful and it is
different from mtd_nandecctest.  So they can coexist.

The mtd_nandecctest tests ECC function itself in nand_ecc.ko without
actual mtd devices.  Tests for nand_bch.ko may be added to
mtd_nandecctest in the future. But it should be done without actual
device as it has been.  It doesn't need to warry about losing important
data by human error.  BTW, my patch set for mtd_nandecctest attempts to
cover all type of corruption patterns.

On the other hand, mtd_nandbiterrs tests ECC functionality by poking
real mtd devices which may not be using ECC functions provided by
nand_ecc.ko.  It is more realistic and its test coverage spreads wider
range of mtd code than mtd_nandecctest can.

> Basically, I would like to understand why we need 2 tests, and if we
> really need 2, have the differences be documented, at least in the
> commentaries.

I'll add commentaries described above in nandecctest.c.


From b32955 at freescale.com  Tue Sep  4 04:25:24 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 16:25:24 +0800
Subject: [PATCH v2 3/3] mtd: cmdlinepart: check the partitions
In-Reply-To: <1346746785.12610.12.camel@sauron.fi.intel.com>
References: <1346744628-13840-1-git-send-email-b32955@freescale.com>	
 <1346744628-13840-3-git-send-email-b32955@freescale.com>
 <1346746785.12610.12.camel@sauron.fi.intel.com>
Message-ID: <5045BAF4.9090308@freescale.com>

? 2012?09?04? 16:19, Artem Bityutskiy ??:
> Just do
>
> if (ret)
> 	return ret;
>
>
> and kill the huge 'switch' that you added.
If the cmdline have two mtd-ids such as:
   
gpmi-nand:100m(root),100m at 100m(kernel),1g at 200m(rootfs);edb7212-nand:-(home)

The `return` will also bypass the `edb7212-nand`.

Is it acceptable?

Best Regards
Huang Shijie



From ccano at interfaceconcept.com  Tue Sep  4 04:32:41 2012
From: ccano at interfaceconcept.com (=?ISO-8859-1?Q?C=E9dric_Cano?=)
Date: Tue, 04 Sep 2012 10:32:41 +0200
Subject: [PATCH 1/1] drivers/mtd/devices/m25p80.c: Fix whole device erase
Message-ID: <5045BCA9.5040401@ic.fr>

From: C?dric Cano<ccano at interfaceconcept.com>

There are two ways to erase SPI Flash devices: sector per sector or the
entire Flash (used when MTD partition is the whole Flash).

When the whole Flash is erased, the SPI command is sent to the device
and the erase function exits. Then, when another access (read, write or
erase) is done, a  wait of busy is performed that fails because of Flash
erase time (can be more than 30s in case of whole erase).

This patch removes chip erase and use only sector per sector erase to
erase the chip. When erase is performed, Flash accesses can be done.

C. Cano

Signed-off-by: C?dric Cano<ccano at interfaceconcept.com>
---
  drivers/mtd/devices/m25p80.c |   50 +++++-------------------------------------
  1 file changed, 5 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 5257345..b8956df 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -202,31 +202,6 @@ static int wait_till_ready(struct m25p *flash)
  	return 1;
  }
  
-/*
- * Erase the whole flash memory
- *
- * Returns 0 if successful, non-zero otherwise.
- */
-static int erase_chip(struct m25p *flash)
-{
-	pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
-			(long long)(flash->mtd.size >> 10));
-
-	/* Wait until finished previous write command. */
-	if (wait_till_ready(flash))
-		return 1;
-
-	/* Send write enable, then erase commands. */
-	write_enable(flash);
-
-	/* Set up command buffer. */
-	flash->command[0] = OPCODE_CHIP_ERASE;
-
-	spi_write(flash->spi, flash->command, 1);
-
-	return 0;
-}
-
  static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
  {
  	/* opcode is in cmd[0] */
@@ -297,31 +272,16 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
  
  	mutex_lock(&flash->lock);
  
-	/* whole-chip erase? */
-	if (len == flash->mtd.size) {
-		if (erase_chip(flash)) {
+	/* "sector"-at-a-time erase */
+	while (len) {
+		if (erase_sector(flash, addr)) {
  			instr->state = MTD_ERASE_FAILED;
  			mutex_unlock(&flash->lock);
  			return -EIO;
  		}
  
-	/* REVISIT in some cases we could speed up erasing large regions
-	 * by using OPCODE_SE instead of OPCODE_BE_4K.  We may have set up
-	 * to use "small sector erase", but that's not always optimal.
-	 */
-
-	/* "sector"-at-a-time erase */
-	} else {
-		while (len) {
-			if (erase_sector(flash, addr)) {
-				instr->state = MTD_ERASE_FAILED;
-				mutex_unlock(&flash->lock);
-				return -EIO;
-			}
-
-			addr += mtd->erasesize;
-			len -= mtd->erasesize;
-		}
+		addr += mtd->erasesize;
+		len -= mtd->erasesize;
  	}
  
  	mutex_unlock(&flash->lock);
-- 



From dedekind1 at gmail.com  Tue Sep  4 04:42:51 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 11:42:51 +0300
Subject: [PATCH 4/4] drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
In-Reply-To: <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
 <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>
Message-ID: <1346748171.12610.22.camel@sauron.fi.intel.com>

Aiaiai! :-) [1] [2]

I've build-tested this using aiaiai and it reports that this change breaks the build:

dedekind at blue:~/git/maintaining$ ./verify ../l2-mtd/ mpc5121_nfc < ~/tmp/julia2.mbox 
Tested the patch(es) on top of the following commits:
ba64756 Quick fixes - applied by aiaiai
651c6fa JFFS2: don't fail on bitflips in OOB
e22ac84 mtd: autcpu12-nvram: drop frees of devm_ alloc'd data
ea9d312 mtd: cmdlinepart: minor cleanups

--------------------------------------------------------------------------------
Failed to build the following commit for configuration "powerpc-mpc512x_defconfig" (architecture powerpc)":

0fe13ab drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups

...
drivers/mtd/nand/mpc5121_nfc.c: In function 'mpc5121_nfc_probe':
drivers/mtd/nand/mpc5121_nfc.c:622:28: warning: variable 'regs_size' set but not used [-Wunused-but-set-variable]
drivers/mtd/nand/mpc5121_nfc.c:622:16: warning: variable 'regs_paddr' set but not used [-Wunused-but-set-variable]
drivers/built-in.o: In function `mpc5121_nfc_probe':
mpc5121_nfc.c:(.devinit.text+0x2a14): undefined reference to `devm_clk_get'
make[1]: *** [vmlinux] Error 1

--------------------------------------------------------------------------------

I do not really know why, but it seems that clock framework is not supported for powerpc. CCing the PPC mailing list. Preserved the context below for the PPC people.

So, not taking this patch.

References:

1. http://git.infradead.org/users/dedekind/aiaiai.git
2. http://git.infradead.org/users/dedekind/maintaining.git

On Sat, 2012-09-01 at 18:33 +0200, Julia Lawall wrote:
> From: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> devm free functions should not have to be explicitly used.
> 
> The only thing left that is useful in the function mpc5121_nfc_free is the
> call to clk_disable, which is moved to the call sites.
> 
> This function also incorrectly called iounmap on devm_ioremap allocated
> data.
> 
> Use devm_request_and_ioremap in place of devm_request_mem_region and
> devm_ioremap.
> 
> Use devm_clk_get.
> 
> A semantic match that finds the first problem is as follows:
> (http://coccinelle.lip6.fr/)
> 
> // <smpl>
> @@
> @@
> 
> (
> * devm_kfree(...);
> |
> * devm_free_irq(...);
> |
> * devm_iounmap(...);
> |
> * devm_release_region(...);
> |
> * devm_release_mem_region(...);
> )
> // </smpl>
> 
> Signed-off-by: Julia Lawall <Julia.Lawall at lip6.fr>
> 
> ---
>  drivers/mtd/nand/mpc5121_nfc.c |   35 +++++------------------------------
>  1 file changed, 5 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
> index c259c24..45183ba 100644
> --- a/drivers/mtd/nand/mpc5121_nfc.c
> +++ b/drivers/mtd/nand/mpc5121_nfc.c
> @@ -632,21 +632,6 @@ out:
>  	return ret;
>  }
>  
> -/* Free driver resources */
> -static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
> -{
> -	struct nand_chip *chip = mtd->priv;
> -	struct mpc5121_nfc_prv *prv = chip->priv;
> -
> -	if (prv->clk) {
> -		clk_disable(prv->clk);
> -		clk_put(prv->clk);
> -	}
> -
> -	if (prv->csreg)
> -		iounmap(prv->csreg);
> -}
> -
>  static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  {
>  	struct device_node *rootnode, *dn = op->dev.of_node;
> @@ -713,12 +698,7 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  	regs_paddr = res.start;
>  	regs_size = resource_size(&res);
>  
> -	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
> -		dev_err(dev, "Error requesting memory region!\n");
> -		return -EBUSY;
> -	}
> -
> -	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
> +	prv->regs = devm_request_and_ioremap(dev, &res);
>  	if (!prv->regs) {
>  		dev_err(dev, "Error mapping memory region!\n");
>  		return -ENOMEM;
> @@ -752,11 +732,10 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  	of_node_put(rootnode);
>  
>  	/* Enable NFC clock */
> -	prv->clk = clk_get(dev, "nfc_clk");
> +	prv->clk = devm_clk_get(dev, "nfc_clk");
>  	if (IS_ERR(prv->clk)) {
>  		dev_err(dev, "Unable to acquire NFC clock!\n");
> -		retval = PTR_ERR(prv->clk);
> -		goto error;
> +		return PTR_ERR(prv->clk);
>  	}
>  
>  	clk_enable(prv->clk);
> @@ -803,7 +782,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  	/* Detect NAND chips */
>  	if (nand_scan(mtd, be32_to_cpup(chips_no))) {
>  		dev_err(dev, "NAND Flash not found !\n");
> -		devm_free_irq(dev, prv->irq, mtd);
>  		retval = -ENXIO;
>  		goto error;
>  	}
> @@ -828,7 +806,6 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  
>  	default:
>  		dev_err(dev, "Unsupported NAND flash!\n");
> -		devm_free_irq(dev, prv->irq, mtd);
>  		retval = -ENXIO;
>  		goto error;
>  	}
> @@ -839,13 +816,12 @@ static int __devinit mpc5121_nfc_probe(struct platform_device *op)
>  	retval = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>  	if (retval) {
>  		dev_err(dev, "Error adding MTD device!\n");
> -		devm_free_irq(dev, prv->irq, mtd);
>  		goto error;
>  	}
>  
>  	return 0;
>  error:
> -	mpc5121_nfc_free(dev, mtd);
> +	clk_disable(prv->clk);
>  	return retval;
>  }
>  
> @@ -857,8 +833,7 @@ static int __devexit mpc5121_nfc_remove(struct platform_device *op)
>  	struct mpc5121_nfc_prv *prv = chip->priv;
>  
>  	nand_release(mtd);
> -	devm_free_irq(dev, prv->irq, mtd);
> -	mpc5121_nfc_free(dev, mtd);
> +	clk_disable(prv->clk);
>  
>  	return 0;
>  }
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/87c034c5/attachment-0001.sig>

From dedekind1 at gmail.com  Tue Sep  4 04:50:31 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 11:50:31 +0300
Subject: [PATCH v2 3/3] mtd: cmdlinepart: check the partitions
In-Reply-To: <5045BAF4.9090308@freescale.com>
References: <1346744628-13840-1-git-send-email-b32955@freescale.com>
 <1346744628-13840-3-git-send-email-b32955@freescale.com>
 <1346746785.12610.12.camel@sauron.fi.intel.com>
 <5045BAF4.9090308@freescale.com>
Message-ID: <1346748631.12610.27.camel@sauron.fi.intel.com>

On Tue, 2012-09-04 at 16:25 +0800, Huang Shijie wrote:
> ? 2012?09?04? 16:19, Artem Bityutskiy ??:
> > Just do
> >
> > if (ret)
> > 	return ret;
> >
> >
> > and kill the huge 'switch' that you added.
> If the cmdline have two mtd-ids such as:
>    
> gpmi-nand:100m(root),100m at 100m(kernel),1g at 200m(rootfs);edb7212-nand:-(home)
> 
> The `return` will also bypass the `edb7212-nand`.
> 
> Is it acceptable?

I thought the whole idea is to refuse command lines which are ambiguous
or make no sense, no?

You could actually do this in two step and split your 3rd patch:

1. Add 'check_partitions' which prints an error messages and returns
-EINVAL if the command line has overlaps or gaps or other bad things.
But ignore the return code in 'mtdpart_setup_real()'

2. Make 'mtdpart_setup_real()' check for the error code and propagate it
up, so we'll have a prink + real refusal.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/4110a0cc/attachment.sig>

From lars at metafoo.de  Tue Sep  4 04:53:46 2012
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Tue, 04 Sep 2012 10:53:46 +0200
Subject: [PATCH 4/4] drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
In-Reply-To: <1346748171.12610.22.camel@sauron.fi.intel.com>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
 <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>
 <1346748171.12610.22.camel@sauron.fi.intel.com>
Message-ID: <5045C19A.7000705@metafoo.de>

On 09/04/2012 10:42 AM, Artem Bityutskiy wrote:
> Aiaiai! :-) [1] [2]
> 
> I've build-tested this using aiaiai and it reports that this change breaks the build:
> 
> dedekind at blue:~/git/maintaining$ ./verify ../l2-mtd/ mpc5121_nfc < ~/tmp/julia2.mbox 
> Tested the patch(es) on top of the following commits:
> ba64756 Quick fixes - applied by aiaiai
> 651c6fa JFFS2: don't fail on bitflips in OOB
> e22ac84 mtd: autcpu12-nvram: drop frees of devm_ alloc'd data
> ea9d312 mtd: cmdlinepart: minor cleanups
> 
> --------------------------------------------------------------------------------
> Failed to build the following commit for configuration "powerpc-mpc512x_defconfig" (architecture powerpc)":
> 
> 0fe13ab drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
> 
> ...
> drivers/mtd/nand/mpc5121_nfc.c: In function 'mpc5121_nfc_probe':
> drivers/mtd/nand/mpc5121_nfc.c:622:28: warning: variable 'regs_size' set but not used [-Wunused-but-set-variable]
> drivers/mtd/nand/mpc5121_nfc.c:622:16: warning: variable 'regs_paddr' set but not used [-Wunused-but-set-variable]
> drivers/built-in.o: In function `mpc5121_nfc_probe':
> mpc5121_nfc.c:(.devinit.text+0x2a14): undefined reference to `devm_clk_get'
> make[1]: *** [vmlinux] Error 1
> 
> --------------------------------------------------------------------------------
> 
> I do not really know why, but it seems that clock framework is not supported for powerpc. CCing the PPC mailing list. Preserved the context below for the PPC people.
> 

I've been bitten by the same issue recently, also cause by one of these
cocci devm patches. devm_clk_get is only available if the generic
clk_get/clk_put implementation is used. Not all architectures do this and
some implement their own clk_get/clk_put, etc functions. Since devm_clk_get
is merely a wrapper around clk_get/clk_put there is no reason why it should
depend CLKDEV_LOOKUP. I've prepared a patch which makes them generically
available if the clk_get/clk_put are implemented (i.e. if HAVE_CLK is set),
but it is on a different machine right now, will try to submit it later today.

- Lars



From dedekind1 at gmail.com  Tue Sep  4 05:31:54 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 12:31:54 +0300
Subject: Problems after 2nd bootup with NAND and ubifs/ubi
In-Reply-To: <CADqH6Vw4FtGjLF-oPVwg0YcwOoQxk90whB6YoYh4mt=1D2SGmw@mail.gmail.com>
References: <CADqH6Vx_doWcOFP6N8qSV-h+KdZi8cqdxyHCROf-SKFvUiYNhg@mail.gmail.com>
 <1345810383.2848.304.camel@sauron.fi.intel.com>
 <CADqH6Vw4FtGjLF-oPVwg0YcwOoQxk90whB6YoYh4mt=1D2SGmw@mail.gmail.com>
Message-ID: <1346751114.12610.29.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 18:31 +0800, Jaya Kumar wrote:
> Would I be correct in assuming that the mtd_oobtest failure can be
> ignored since ubi does not use OOB? 

If you only care about UBI/UBIFS, then yes, you can ignore this. But in
general - it is asking for troubles.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/5b1ba92f/attachment.sig>

From b32955 at freescale.com  Tue Sep  4 05:07:50 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 4 Sep 2012 17:07:50 +0800
Subject: [PATCH v3] mtd: cmdlinepart: check the partitions
In-Reply-To: <1346746785.12610.12.camel@sauron.fi.intel.com>
References: <1346746785.12610.12.camel@sauron.fi.intel.com>
Message-ID: <1346749670-23944-1-git-send-email-b32955@freescale.com>

The partitions are all sorted well by the @offset.
But we should check if there are errors in the partitions.

The following cases are regarded as errors:
  [1] There is a hole in the partitions, such as
      #gpmi-nand:100m(boot),100m at 100m(kernel),1g at 200m(rootfs)

  [2] There is a overlap in the partitions, such as
      #gpmi-nand:100m at 0(boot),100m at 50m(kernel),1g at 150m(rootfs)

  [3] Not all the partitions are set with @offset, and there are
      more then one partion whose offset is OFFSET_CONTINUOUS.
      #gpmi-nand:100m at 0(boot),100m(kernel),-(usr)

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/cmdlinepart.c |   55 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 55 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index edd17e0..5a603d1 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -225,6 +225,55 @@ static inline void sort_partitons(struct mtd_partition *parts, int num_parts)
 	return;
 }
 
+/* The partitions have been sorted well by the @offset. */
+static inline int check_partitions(struct mtd_partition *parts, int num_parts)
+{
+	int i;
+	uint64_t offset = 0;
+	int offset_continuous_cnt = 0;
+
+	for (i = 0; i < num_parts; i++) {
+		if (parts[i].offset == OFFSET_CONTINUOUS) {
+			offset_continuous_cnt++;
+			continue;
+		}
+
+		/* find a hole. */
+		if (parts[i].offset > offset) {
+			printk(KERN_ERR ERRP "There is a hole in the "
+				"partitions, please check the cmdline, "
+				"and fix it.\n");
+			return -EINVAL;
+		}
+
+		/* find an overlapped partition. */
+		if (parts[i].offset < offset) {
+			printk(KERN_ERR ERRP "The partitions overlap,"
+				"please check the cmdline, and fix it.\n");
+			return -EINVAL;
+		}
+
+		offset += parts[i].size;
+	}
+
+	if (offset_continuous_cnt) {
+		/* We do not set partitions with the @offset in the cmdline. */
+		if (offset_continuous_cnt == num_parts)
+			return 0;
+
+		/* It's ok if there is only one OFFSET_CONTINUOUS partition. */
+		if (offset_continuous_cnt == 1)
+			return 0;
+
+		printk(KERN_ERR ERRP "The offset is not right,"
+			"please check the cmdline, and fix it.\n");
+		return -EINVAL;
+	}
+
+	/* We set with @offset for all the partitions in the cmdline. */
+	return 0;
+}
+
 /*
  * Parse the command line.
  */
@@ -238,6 +287,7 @@ static int mtdpart_setup_real(char *s)
 		struct mtd_partition *parts;
 		int mtd_id_len, num_parts;
 		char *p, *mtd_id;
+		int ret;
 
 		mtd_id = s;
 
@@ -285,6 +335,11 @@ static int mtdpart_setup_real(char *s)
 		/* sort the partitions */
 		sort_partitons(parts, num_parts);
 
+		/* check the partitions */
+		ret = check_partitions(parts, num_parts);
+		if (ret)
+			return ret;
+
 		/* link into chain */
 		this_mtd->next = partitions;
 		partitions = this_mtd;
-- 
1.7.0.4




From dedekind1 at gmail.com  Tue Sep  4 05:40:20 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 12:40:20 +0300
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
Message-ID: <1346751620.12610.35.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 18:45 +0800, Jaya Kumar wrote:
> Hi mtd friends,
> 
> Sorry, I have a somewhat offtopic question. I'm using ubifs, and I'm
> trying to figure out what would be a good way to handle browser based
> firmware upgrades. I've implemented the following:
> 
> - NAND is partitioned into bootloader, kernel, ubifs
> - system is running from ubifs
> - httpd with CGI is running from ubifs
> - user uploads firmware containing ubifs.img (150MB) using this CGI
> - during the upload, the CGI writes the temporary file (up to 150MB)
> to a fat partition on a empty microSD (a non-booting microSD has to be
> always present for this to work)
> - upon completion of the upload, the CGI unpacks the temporary file
> and validates checksums, this of course needs more space since now
> both the temporary file and unpacked results are present
> - then reboot since we can't ubiformat/reflash from the running ubifs
> partition and I can't detach from it for same reason.
> - upon reboot, u-boot script checks for the presence of the ubifs.img
> in the microSD fat partition, if it is there then it nand erases the
> ubifs partition, then does nandwrite of the ubifs.img
> - I realize this loses the erase counters since it is simplistic

If you use ubiformat for erasing, then the erasecounters are preserved.

> - system boots and then removes the upgrade files so that it doesn't
> repeat for each bootup

> This seems clunky and I recognize that if the upgrade is interrupted,
> the unit would be bricked. I was curious how other people implement
> this and what the best practices are. I was thinking whether I should
> have another partition for a small upgrade-only OS, so if u-boot
> detects ubifs.img or a user button press, it boots into the
> upgrade-only OS and then I can run ubiformat from there. I would
> welcome any advice/suggestions.

Well, if you use mSD, you may have space to save the contents of the
partitions which you are trying to update, which would allow to
roll-back to the old system should something go wrong.

Another approach people use is that they have "mirror" UBI volume of the
same size, like "ubifs-reserve". Then the update image is put to
ubifs-reserve, and after this you use the UBI volume rename feature and
rename "ubifs-reserve into" "ubifs". This will kill the old "ubifs"
volume. After this you may resize "ubifs" to something larger, and
create a new "ubifs-reserve" volume.

See "Volume update" here:
http://www.linux-mtd.infradead.org/doc/ubi.html

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/8f530ca8/attachment.sig>

From artem.bityutskiy at linux.intel.com  Tue Sep  4 05:46:06 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 12:46:06 +0300
Subject: [PATCH v3 01/11] mtd: mtd_nandecctest: remove unnecessary
 srandom32() call
In-Reply-To: <1346677206-13621-2-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
 <1346677206-13621-2-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346751966.12610.36.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 21:59 +0900, Akinobu Mita wrote:
> It is unnecessary for this driver to call srandom32() in module_init.
> 
> Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>

Just FYI, patches 1 and 2 are already in l2-mtd.git, no need to re-send
patches which are in the l2 tree again.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/e6bfe52f/attachment-0001.sig>

From julia.lawall at lip6.fr  Tue Sep  4 05:44:34 2012
From: julia.lawall at lip6.fr (Julia Lawall)
Date: Tue, 4 Sep 2012 11:44:34 +0200 (CEST)
Subject: [PATCH 4/4] drivers/mtd/nand/mpc5121_nfc.c: some devm_
 cleanups
In-Reply-To: <5045C19A.7000705@metafoo.de>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
 <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>
 <1346748171.12610.22.camel@sauron.fi.intel.com> <5045C19A.7000705@metafoo.de>
Message-ID: <alpine.DEB.2.02.1209041142130.2759@hadrien>

On Tue, 4 Sep 2012, Lars-Peter Clausen wrote:

> On 09/04/2012 10:42 AM, Artem Bityutskiy wrote:
> > Aiaiai! :-) [1] [2]
> >
> > I've build-tested this using aiaiai and it reports that this change breaks the build:
> >
> > dedekind at blue:~/git/maintaining$ ./verify ../l2-mtd/ mpc5121_nfc < ~/tmp/julia2.mbox
> > Tested the patch(es) on top of the following commits:
> > ba64756 Quick fixes - applied by aiaiai
> > 651c6fa JFFS2: don't fail on bitflips in OOB
> > e22ac84 mtd: autcpu12-nvram: drop frees of devm_ alloc'd data
> > ea9d312 mtd: cmdlinepart: minor cleanups
> >
> > --------------------------------------------------------------------------------
> > Failed to build the following commit for configuration "powerpc-mpc512x_defconfig" (architecture powerpc)":
> >
> > 0fe13ab drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
> >
> > ...
> > drivers/mtd/nand/mpc5121_nfc.c: In function 'mpc5121_nfc_probe':
> > drivers/mtd/nand/mpc5121_nfc.c:622:28: warning: variable 'regs_size' set but not used [-Wunused-but-set-variable]
> > drivers/mtd/nand/mpc5121_nfc.c:622:16: warning: variable 'regs_paddr' set but not used [-Wunused-but-set-variable]
> > drivers/built-in.o: In function `mpc5121_nfc_probe':
> > mpc5121_nfc.c:(.devinit.text+0x2a14): undefined reference to `devm_clk_get'
> > make[1]: *** [vmlinux] Error 1
> >
> > --------------------------------------------------------------------------------
> >
> > I do not really know why, but it seems that clock framework is not supported for powerpc. CCing the PPC mailing list. Preserved the context below for the PPC people.
> >
>
> I've been bitten by the same issue recently, also cause by one of these
> cocci devm patches. devm_clk_get is only available if the generic
> clk_get/clk_put implementation is used. Not all architectures do this and
> some implement their own clk_get/clk_put, etc functions. Since devm_clk_get
> is merely a wrapper around clk_get/clk_put there is no reason why it should
> depend CLKDEV_LOOKUP. I've prepared a patch which makes them generically
> available if the clk_get/clk_put are implemented (i.e. if HAVE_CLK is set),
> but it is on a different machine right now, will try to submit it later today.

Sorry about this.  I wasn't aware that devm_clk_get wasn't supported by
all architectures, and I have no way of compiling code for these
architectures...  But I wonder why it is not, since devm-ness doesn't seem
to have anything to do with architecture-specific details?  It would be
really nice to have it for all architectures, because the clock functions
are just as (or at least almost as) common as kzalloc, ioremap, etc.

thanks,
julia


From dedekind1 at gmail.com  Tue Sep  4 05:54:13 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 12:54:13 +0300
Subject: [PATCH 4/4] drivers/mtd/nand/mpc5121_nfc.c: some devm_ cleanups
In-Reply-To: <alpine.DEB.2.02.1209041142130.2759@hadrien>
References: <1346517191-8794-1-git-send-email-Julia.Lawall@lip6.fr>
 <1346517191-8794-4-git-send-email-Julia.Lawall@lip6.fr>
 <1346748171.12610.22.camel@sauron.fi.intel.com>
 <5045C19A.7000705@metafoo.de> <alpine.DEB.2.02.1209041142130.2759@hadrien>
Message-ID: <1346752453.12610.39.camel@sauron.fi.intel.com>

On Tue, 2012-09-04 at 11:44 +0200, Julia Lawall wrote:
> > I've been bitten by the same issue recently, also cause by one of these
> > cocci devm patches. devm_clk_get is only available if the generic
> > clk_get/clk_put implementation is used. Not all architectures do this and
> > some implement their own clk_get/clk_put, etc functions. Since devm_clk_get
> > is merely a wrapper around clk_get/clk_put there is no reason why it should
> > depend CLKDEV_LOOKUP. I've prepared a patch which makes them generically
> > available if the clk_get/clk_put are implemented (i.e. if HAVE_CLK is set),
> > but it is on a different machine right now, will try to submit it later today.
> 
> Sorry about this.  I wasn't aware that devm_clk_get wasn't supported by
> all architectures, and I have no way of compiling code for these
> architectures...  But I wonder why it is not, since devm-ness doesn't seem
> to have anything to do with architecture-specific details?  It would be
> really nice to have it for all architectures, because the clock functions
> are just as (or at least almost as) common as kzalloc, ioremap, etc.

It looks like Lars is going to fix this.

I am personally fine if you send patches without build-testing them.
Your patches are generally of good quality and you send many of them, so
build-testing each would be too much for you. And at least for MTD, I
can build-test myself.


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/f3c90116/attachment.sig>

From artem.bityutskiy at linux.intel.com  Tue Sep  4 06:06:35 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 13:06:35 +0300
Subject: [PATCH v3 07/11] mtd: mtd_nandecctest: generalize injecting bit
 errors function for ecc code
In-Reply-To: <1346677206-13621-8-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
 <1346677206-13621-8-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346753195.12610.43.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 22:00 +0900, Akinobu Mita wrote:
> In order to inject deliberate bit errors into the ecc code which only
> has 3 bytes, this adjusts the bitops usage in inject_single_bit_error()
> which is currently only used for injecting into the 256 or 512 bytes
> data block.
> 
> Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
> Cc: David Woodhouse <dwmw2 at infradead.org>
> Cc: linux-mtd at lists.infradead.org
> Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

I do not understand the commit message and the patch.
> ---
>  drivers/mtd/tests/mtd_nandecctest.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
> index d3e8873..0274f73 100644
> --- a/drivers/mtd/tests/mtd_nandecctest.c
> +++ b/drivers/mtd/tests/mtd_nandecctest.c
> @@ -7,13 +7,22 @@
>  #include <linux/slab.h>
>  #include <linux/mtd/nand_ecc.h>
>  
> +#include <asm/byteorder.h>

I think you do not need to include this.

> +
>  #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
>  
> +#ifdef __LITTLE_ENDIAN
> +#define __change_bit_le(nr, addr) __change_bit(nr, addr)
> +#else
> +#define __change_bit_le(nr, addr) \
> +		__change_bit((nr) ^ ((BITS_PER_LONG - 1) & ~0x7), addr)
> +#endif

Why is this "#ifdef" needed? Can you please add a comment explaining
this? Which problem do you solve by adding '__change_bit_le()' ?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/6c30559d/attachment.sig>

From artem.bityutskiy at linux.intel.com  Tue Sep  4 06:20:26 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Tue, 04 Sep 2012 13:20:26 +0300
Subject: [PATCH v3 00/11] mtd: mtd_nandecctest: add more tests
In-Reply-To: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1346754026.12610.48.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 21:59 +0900, Akinobu Mita wrote:
> This patch series adds several tests cases to mtd_nandecctest module
> and includes several minor changes.

I've pushed patches 3-6 to the l2-mtd.git, thanks! Please, do not
re-send patches 1-6 since I already have them, and David will find them
in my tree.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120904/c16d5fc5/attachment.sig>

From shmulik.ladkani at gmail.com  Tue Sep  4 07:48:26 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Tue, 4 Sep 2012 14:48:26 +0300
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <1346686544.3061.75.camel@sauron.fi.intel.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
 <1346686544.3061.75.camel@sauron.fi.intel.com>
Message-ID: <20120904144826.7b9b7518@halley>

On Mon, 03 Sep 2012 18:35:44 +0300 Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> With the logic I suggested, for this case what I said would basically:
> 
> 1. Sort. This leads to
> 
> 100m at 100m(kernel)
> 1g at 200m(rootfs)
> 100m(boot)
> 
> "OFFSET_CONTINOUS" is always the largest and will be at the end when
> sorting.
> 
> 2. Verification.
> 
> We verify for overlaps and gaps. And refuse this one.

Artem, Huang,

Sorry for the long delay, got busy with urgent matters (found out I need
to go thru some surgery), I will probably not be available in the
upcoming days, but I've read the correspondance and wanted to share my
two cents...

My POV is that sorting and verification is not needed, is troublesome,
and might affect users in ways they don't expect.

So far, mtdparts commandline parsing has been very lenient and liberal.
I think we should keep this approach; give the user the flexibility,
he'll be responsible to provide meaningful cmdline parts for his
system.

Actually, Huang's initial complaint was that 'parse_cmdline_partitions'
was too strict - the truncated partition was not registered!

Now, philosophy aside, let's talk about some usecases that might break.

I remember overlapping partitions (more precisely, partition that is a
subset of another) being common in some embedded systems, where the
"rootfs" and "kernel" partitions are a subset of the "overall image"
partition.
Why break this? if users enjoy the flexibility, and careful not to
create silly partitions, I'm in favor of keeping the flexibility.

Same goes for sorting.
If one has a system hacked to work with mtd0 hardcodedly, but mtd0's
physical location is somewhere at the end of the device, why reorder the
partitions enumeration affecting this system?

I'd say keep it simple and flexible.
I trust the user to provide meaningful partitions in the cmdline.

Anyways, please consider this approach.

My patch suggestion might look as (and might need some rework):

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 17b0bd4..f5df613 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -324,7 +324,6 @@ static int parse_cmdline_partitions(struct mtd_info *master,
                                               "%s: partitioning exceeds flash size, truncating\n",
                                               part->mtd_id);
                                        part->parts[i].size = master->size - offset;
-                                       part->num_parts = i;
                                }
                                offset += part->parts[i].size;
                        }

Regards,
Shmulik


From richard.genoud at gmail.com  Tue Sep  4 09:56:09 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue,  4 Sep 2012 15:56:09 +0200
Subject: [MTD website] UBI: now we reserve 20/1024 PEB for bad block handling
Message-ID: <1346766969-13490-1-git-send-email-richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 doc/ubi.xml |   84 +++++++++++++++++++++++++++++++++--------------------------
 faq/ubi.xml |    9 ++++--
 2 files changed, 53 insertions(+), 40 deletions(-)

diff --git a/doc/ubi.xml b/doc/ubi.xml
index dea14e6..90a9508 100644
--- a/doc/ubi.xml
+++ b/doc/ubi.xml
@@ -516,9 +516,10 @@ amount of flash space available for UBI users. Namely:</p>
 	<li>1 PEB is reserved for wear-leveling purposes;</li>
 	<li>1 PEB is reserved for the
 	<a href="ubi.html#L_lebchange">atomic LEB change</a> operation;</li>
-	<li>some amount of PEBs is reserved for bad PEB handling; this is
-	applicable for NAND flash, but not for NOR flash; the percentage of
-	reserved PEBs is configurable and is 2% by default;</li>
+	<li>some <a href="ubi.html#L_max_beb">amount of PEBs</a> is reserved
+	for bad PEB handling; this is applicable for NAND flash, but not for
+	NOR flash; the amount of reserved PEBs is configurable and is equal
+	to 20 blocks per 1024 blocks by default;</li>
 	<li>UBI stores the EC and VID
 	<a href="ubi.html#L_ubi_headers">headers</a> at the beginning of each
 	PEB; the amount of bytes used for these purposes depends on the flash
@@ -528,13 +529,17 @@ amount of flash space available for UBI users. Namely:</p>
 <p>Lets introduce symbols:</p>
 
 <ul>
+	<li><i>W</i> - total number of physical eraseblocks on the flash
+	device (NB: the whole device, not the MTD partition);</li>
 	<li><i>P</i> - total number of physical eraseblocks on the MTD
-	device;</li>
+	partition);</li>
 	<li><i>S<sub>P</sub></i> - physical eraseblock size;</li>
 	<li><i>S<sub>L</sub></i> - logical eraseblock size;</li>
-	<li><i>B</i> - number of PEBs reserved for bad PEB handling; it is
-	2% of <i>P</i> for NAND by default, and 0 for NOR and other flash types
-	which do not have bad PEBs;</li>
+	<li><i>B<sub>B</sub></i> - number of bad blocks on the MTD partition;</li>
+	<li><i>B<sub>R</sub></i> - number of PEBs reserved for bad PEB
+	handling. it is 20 * <i>W</i>/1024 for NAND by default, and 0 for NOR
+	and other flash types which do not have bad PEBs;</li>
+	<li><i>B</i> - MAX(<i>B<sub>R</sub></i>,<i>B<sub>B</sub></i>);</li>
 	<li><i>O</i> - the overhead related to storing EC and VID headers in
 	bytes, i.e. <i>O</i> = <i>S<sub>P</sub></i> - <i>S<sub>L</sub></i>.</li>
 </ul>
@@ -564,6 +569,9 @@ different for different flashes:</p>
 	64 bytes aligned to the min. I/O unit size if the min. I/O unit size
 	is less than 64 bytes.</li>
 </ul>
+<p>N.B.: the formula above counts bad blocks as a UBI overhead. The <i>real</i>
+UBI overhead is: (<i>B</i> - <i>B<sub>B</sub></i> + 4) * <i>S<sub>P</sub></i> +
+<i>O</i> * (<i>P</i> - <i>B</i> - 4)</p>
 
 
 
@@ -833,44 +841,46 @@ UBI.</p>
 
 
 
-<h2><a name="L_autoresize">Volume auto-resize</a></h2>
+<h2><a name="L_max_beb">Reserved blocks for bad block handling (only for NAND chips)</a></h2>
 
 <p>It is well-known that NAND chips have some amount of physical eraseblocks
-marked as bad by the manufacturer. The bad PEBs are distributed randomly
-and their number is different, although manufacturers usually guarantee that
+marked as bad by the manufacturer. During the lifetime of the NAND device,
+other bad blocks may appear. Although, manufacturers usually guarantee that
 the first few physical eraseblocks are not bad and the total amount of bad PEBs
-does not exceed certain number. For example, a new 256MiB Samsung OneNAND chip
-is guaranteed to have not more than 40 128KiB PEBs (but of course, more
-physical eraseblock will become bad over time). This is about 2% of flash
-size.</p>
+will not exceed certain number. For example, a 256MiB (2048 128KiB PEBs)
+Samsung OneNAND chip is guaranteed to have not more than 40 128KiB PEBs during
+its endurance lifetime. This is a very common value for NAND devices:
+20/1024 PEB, which is about 2% of flash size.</p>
+
+<p>This ratio of 20/1024 is the default number of blocks that UBI reserves for
+a UBI device. It means that if there's 2 UBI devices on a 4096 PEB NAND, 80 PEB
+for <b>each</b> UBI device will be reserved. This may appear as a waste of
+space, but as far as bad blocks can appear everywhere on the NAND flash, and
+are not equally disposed on the whole device, it's the safer way. So instead of
+using several UBI devices on a NAND flash, it's more space efficient to use only
+one UBI device and several UBI volumes.</p>
+<p>The default value of 20 PEB reserved per 1024 PEB is a kernel config option.
+For each UBI device, this value can be adjusted via a kernel parameter or an
+ubiattach parameter (since kernel 3.7).</p>
+
+
+
+
+<h2><a name="L_autoresize">Volume auto-resize</a></h2>
 
 <p>When it is needed to create an UBI image which will be flashed to the end
 user devices in production line, you should define exact sizes of all volumes
-(the sizes are stored in the UBI volume table). But it is difficult to do
-because the total flash chip size may vary depending on the amount of the
-initially bad PEBs.</p>
-
-<p>One obvious way to solve the problem is to assume the worst case, when all
-chips would have maximum amount of bad PEBs. But in practice, most of the chips
-will have only few bad PEBs which is far less than the maximum. In general, it
-is fine - this will increase reliability, because UBI anyway uses all PEBs of
-the device. On the other hand UBI anyway reserves some amount of physical
-eraseblocks for bad PEB handling which is 2% of PEBs by default. So in case of
-the above mentioned OneNAND chip the result would be that 2% of PEBs would be
-reserved by UBI, and 0-2% of PEBs would not be used (they would be seen as
-available LEBs to the UBI users).</p>
-
-<p>But there is an alternative approach - one of the volume may have the
-<b>auto-resize</b> mark, which means that its size has to be enlarged when UBI
+(the sizes are stored in the UBI volume table). But usually, in the embedded
+world, we like to have one (read only) volume for the root file system and
+one read write volume for the rest (logs, user data, etc.). If the size of the
+root file system is fixed, the size of the second one can vary from one product
+to another (different flash sizes) and we just want all space left.</p>
+
+<p>That what the auto-resize is about. If the volume has the <b>auto-resize</b>
+mark, its size will be enlarged when UBI
 is run for the first time. After the volume size is adjusted, UBI removes the
 auto-resize mark and the volume is not re-sized anymore. The auto-resize flag is
-stored in the volume table and only one volume may be marked as auto-resize.
-For example, if there is a volume which is intended to have the root
-file-system, it may be reasonable to mark it with the auto-resize flag.</p>
-
-<p>In the example with OneNAND chip, if one of the UBI volumes is be marked
-as auto-re-sized, it will be enlarged by 0-2% on the first UBI boot, but 2% of
-PEBs will anyway be reserved for bad PEB handling.</p>
+stored in the volume table and only one volume may be marked as auto-resize.</p>
 
 <p>Note, the auto-resize feature exists in the Linux kernel starting from
 version <code>2.6.25</code>.</p>
diff --git a/faq/ubi.xml b/faq/ubi.xml
index 02f8146..68aeaa4 100644
--- a/faq/ubi.xml
+++ b/faq/ubi.xml
@@ -459,10 +459,13 @@ must be an issue for UBI as well.</p>
 
 <h2><a name="L_bad_blocks_exceeded">What happens when the PEBs reserved for bad block handling run out?</a></h2>
 
-By default, 2% of the available PEBs are reserved for handling bad blocks.
-
+<p>By default, about 2% of the whole flash size (20/1024 PEB) are reserved for
+<a href="ubi.html#L_max_beb">handling bad blocks.</a>
 If the number of blocks that turn bad exceeds that allocation, an error
-message will be printed and UBI will switch to read-only mode.
+message will be printed and UBI will switch to read-only mode.</p>
+<p>Note: If at attach time, there's already more bad blocks than reserved PEBs,
+UBI will stay in read-write mode. The switching to read-only mode only occurs
+when a new bad block appears.</p>
 
 
 
-- 
1.7.2.5



From richard.genoud at gmail.com  Tue Sep  4 10:01:07 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 4 Sep 2012 16:01:07 +0200
Subject: [MTD website] UBI: now we reserve 20/1024 PEB for bad block
 handling
In-Reply-To: <1346766969-13490-1-git-send-email-richard.genoud@gmail.com>
References: <1346766969-13490-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <CACQ1gAj1cEJwTQ3ZVw14iWSz2Qay9Qbk++78t167h3TvepyJ5A@mail.gmail.com>

2012/9/4 Richard Genoud <richard.genoud at gmail.com>:
> +
> +<h2><a name="L_autoresize">Volume auto-resize</a></h2>
>
>  <p>When it is needed to create an UBI image which will be flashed to the end
>  user devices in production line, you should define exact sizes of all volumes
> -(the sizes are stored in the UBI volume table). But it is difficult to do
> -because the total flash chip size may vary depending on the amount of the
> -initially bad PEBs.</p>
> -
> -<p>One obvious way to solve the problem is to assume the worst case, when all
> -chips would have maximum amount of bad PEBs. But in practice, most of the chips
> -will have only few bad PEBs which is far less than the maximum. In general, it
> -is fine - this will increase reliability, because UBI anyway uses all PEBs of
> -the device. On the other hand UBI anyway reserves some amount of physical
> -eraseblocks for bad PEB handling which is 2% of PEBs by default. So in case of
> -the above mentioned OneNAND chip the result would be that 2% of PEBs would be
> -reserved by UBI, and 0-2% of PEBs would not be used (they would be seen as
> -available LEBs to the UBI users).</p>
> -
> -<p>But there is an alternative approach - one of the volume may have the
> -<b>auto-resize</b> mark, which means that its size has to be enlarged when UBI
> +(the sizes are stored in the UBI volume table). But usually, in the embedded
> +world, we like to have one (read only) volume for the root file system and
> +one read write volume for the rest (logs, user data, etc.). If the size of the
> +root file system is fixed, the size of the second one can vary from one product
> +to another (different flash sizes) and we just want all space left.</p>
> +
> +<p>That what the auto-resize is about. If the volume has the <b>auto-resize</b>
> +mark, its size will be enlarged when UBI
>  is run for the first time. After the volume size is adjusted, UBI removes the
>  auto-resize mark and the volume is not re-sized anymore. The auto-resize flag is
> -stored in the volume table and only one volume may be marked as auto-resize.
> -For example, if there is a volume which is intended to have the root
> -file-system, it may be reasonable to mark it with the auto-resize flag.</p>
> -
> -<p>In the example with OneNAND chip, if one of the UBI volumes is be marked
> -as auto-re-sized, it will be enlarged by 0-2% on the first UBI boot, but 2% of
> -PEBs will anyway be reserved for bad PEB handling.</p>
> +stored in the volume table and only one volume may be marked as auto-resize.</p>
>
>  <p>Note, the auto-resize feature exists in the Linux kernel starting from
>  version <code>2.6.25</code>.</p>
I change this because I think there was a misunderstanding, the
manufacturer guarantees that there won't be more than xxx bad block on
the device during its "endurance lifetime" not at shipping time.
So I gave another example, but fill free to change it !

Best regards,
Richard.


From paulmck at linux.vnet.ibm.com  Tue Sep  4 10:48:13 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Tue, 4 Sep 2012 07:48:13 -0700
Subject: RCU warning during UBI file system mount
In-Reply-To: <1346744796.12610.6.camel@sauron.fi.intel.com>
References: <5042EC5D.1010207@grid-net.com>
 <1346744796.12610.6.camel@sauron.fi.intel.com>
Message-ID: <20120904144813.GC2593@linux.vnet.ibm.com>

On Tue, Sep 04, 2012 at 10:46:36AM +0300, Artem Bityutskiy wrote:
> Let's CC LKML and Paul.
> 
>  
> On Sat, 2012-09-01 at 22:19 -0700, Subodh Nijsure wrote:
> > Hello,
> > 
> > I am running 3.6-rc4 kernel on my MX28 based board and every time I 
> > mount UBI file system I see following warning.
> > Anybody else seen this errors, particularly those running it on MXS 
> > platform?
> > 
> > I haven't debugged RCU warnings before any clues as to what is the 
> > source of this warning is, should I be looking at 
> > start_dma_without_bch_irq() code? Would appreciate any pointers in 
> > fixing this...

RCU is upset because what it believes to be a non-idle task is telling
RCU that it is entering the idle loop.

Does the MX28 kernel have any unusual idle features?  (This is a subarch
of ARM, correct?)

							Thanx, Paul

> > [    4.280000] WARNING: at /opt/git/kernel-mainline/kernel/rcutiny.c:75 
> > rcu_idle_enter_common.clone.7+0x90/0xac()
> > [    4.280000] Current pid: 1 comm: swapper / Idle pid: 0 comm: swapper
> > [    4.280000] Modules linked in:
> > [    4.280000] [<c0014eec>] (unwind_backtrace+0x0/0x130) from 
> > [<c001dd94>] (warn_slowpath_common+0x4c/0x64)
> > [    4.280000] [<c001dd94>] (warn_slowpath_common+0x4c/0x64) from 
> > [<c001de40>] (warn_slowpath_fmt+0x30/0x40)
> > [    4.280000] [<c001de40>] (warn_slowpath_fmt+0x30/0x40) from 
> > [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
> > [    4.280000] [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac) 
> > from [<c0061670>] (rcu_irq_exit+0x3c/0x78)
> > [    4.280000] [<c0061670>] (rcu_irq_exit+0x3c/0x78) from [<c000fe90>] 
> > (handle_IRQ+0x34/0x84)
> > [    4.280000] [<c000fe90>] (handle_IRQ+0x34/0x84) from [<c000ec34>] 
> > (__irq_svc+0x34/0x58)
> > [    4.280000] [<c000ec34>] (__irq_svc+0x34/0x58) from [<c0394c4c>] 
> > (schedule_timeout+0xdc/0x16c)
> > [    4.280000] [<c0394c4c>] (schedule_timeout+0xdc/0x16c) from 
> > [<c0395f34>] (wait_for_common+0xb4/0x160)
> > [    4.280000] [<c0395f34>] (wait_for_common+0xb4/0x160) from 
> > [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8)
> > [    4.280000] [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8) from 
> > [<c0258660>] (gpmi_send_command+0x120/0x154)
> > [    4.280000] [<c0258660>] (gpmi_send_command+0x120/0x154) from 
> > [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c)
> > [    4.280000] [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c) from [<c024f8e0>] 
> > (nand_command_lp+0xe8/0x270)
> > [    4.280000] [<c024f8e0>] (nand_command_lp+0xe8/0x270) from 
> > [<c0251e00>] (nand_do_read_ops+0x124/0x444)
> > [    4.280000] [<c0251e00>] (nand_do_read_ops+0x124/0x444) from 
> > [<c0252558>] (nand_read+0x54/0x78)
> > [    4.280000] [<c0252558>] (nand_read+0x54/0x78) from [<c02499a4>] 
> > (part_read+0x48/0x80)
> > [    4.280000] [<c02499a4>] (part_read+0x48/0x80) from [<c0246910>] 
> > (mtd_read+0x88/0xb4)
> > [    4.280000] [<c0246910>] (mtd_read+0x88/0xb4) from [<c026b188>] 
> > (ubi_io_read+0xb0/0x3e8)
> > [    4.280000] [<c026b188>] (ubi_io_read+0xb0/0x3e8) from [<c026740c>] 
> > (ubi_eba_read_leb+0x198/0x4bc)
> > [    4.280000] [<c026740c>] (ubi_eba_read_leb+0x198/0x4bc) from 
> > [<c0266800>] (ubi_leb_read+0xf4/0x16c)
> > [    4.280000] [<c0266800>] (ubi_leb_read+0xf4/0x16c) from [<c0155550>] 
> > (ubifs_leb_read+0x24/0x88)
> > [    4.280000] [<c0155550>] (ubifs_leb_read+0x24/0x88) from [<c01572f8>] 
> > (ubifs_read_node+0xa8/0x2e4)
> > [    4.280000] [<c01572f8>] (ubifs_read_node+0xa8/0x2e4) from 
> > [<c0153c50>] (ubifs_read_sb_node+0x54/0x78)
> > [    4.280000] [<c0153c50>] (ubifs_read_sb_node+0x54/0x78) from 
> > [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c)
> > [    4.280000] [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c) from 
> > [<c01520ac>] (ubifs_mount+0x73c/0x1bc0)
> > [    4.280000] [<c01520ac>] (ubifs_mount+0x73c/0x1bc0) from [<c00a49ec>] 
> > (mount_fs+0x44/0x184)
> > [    4.280000] [<c00a49ec>] (mount_fs+0x44/0x184) from [<c00baf90>] 
> > (vfs_kern_mount+0x4c/0xc0)
> > [    4.280000] [<c00baf90>] (vfs_kern_mount+0x4c/0xc0) from [<c00bb1a0>] 
> > (do_kern_mount+0x34/0xd0)
> > [    4.280000] [<c00bb1a0>] (do_kern_mount+0x34/0xd0) from [<c00bc93c>] 
> > (do_mount+0x15c/0x73c)
> > [    4.280000] [<c00bc93c>] (do_mount+0x15c/0x73c) from [<c00bcfa0>] 
> > (sys_mount+0x84/0xc4)
> > [    4.280000] [<c00bcfa0>] (sys_mount+0x84/0xc4) from [<c04e4a04>] 
> > (do_mount_root+0x24/0xb0)
> > [    4.280000] [<c04e4a04>] (do_mount_root+0x24/0xb0) from [<c04e4b78>] 
> > (mount_block_root+0xe8/0x214)
> > [    4.280000] [<c04e4b78>] (mount_block_root+0xe8/0x214) from 
> > [<c04e4e28>] (prepare_namespace+0x8c/0x180)
> > [    4.280000] [<c04e4e28>] (prepare_namespace+0x8c/0x180) from 
> > [<c04e4894>] (kernel_init+0x16c/0x1b4)
> > [    4.280000] [<c04e4894>] (kernel_init+0x16c/0x1b4) from [<c000ff70>] 
> > (kernel_thread_exit+0x0/0x8)
> > [    4.280000] ---[ end trace 4d36b722759fdc4f ]---
> > [    4.950000] UBIFS DBG (pid 58): ubifs_bg_thread: background thread 
> > "ubifs_bgt0_0" started, PID 58
> > 
> > -Subodh
> > 
> > ______________________________________________________
> > Linux MTD discussion mailing list
> > http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 
> -- 
> Best Regards,
> Artem Bityutskiy




From snijsure at grid-net.com  Tue Sep  4 11:43:12 2012
From: snijsure at grid-net.com (Subodh Nijsure)
Date: Tue, 4 Sep 2012 08:43:12 -0700
Subject: RCU warning during UBI file system mount
In-Reply-To: <20120904144813.GC2593@linux.vnet.ibm.com>
References: <5042EC5D.1010207@grid-net.com>
 <1346744796.12610.6.camel@sauron.fi.intel.com>
 <20120904144813.GC2593@linux.vnet.ibm.com>
Message-ID: <50462190.7090702@grid-net.com>

Hello Paul,

On 09/04/2012 07:48 AM, Paul E. McKenney wrote:
> On Tue, Sep 04, 2012 at 10:46:36AM +0300, Artem Bityutskiy wrote:
>> Let's CC LKML and Paul.
>>
>>   
>> On Sat, 2012-09-01 at 22:19 -0700, Subodh Nijsure wrote:
>>> Hello,
>>>
>>> I am running 3.6-rc4 kernel on my MX28 based board and every time I
>>> mount UBI file system I see following warning.
>>> Anybody else seen this errors, particularly those running it on MXS
>>> platform?
>>>
>>> I haven't debugged RCU warnings before any clues as to what is the
>>> source of this warning is, should I be looking at
>>> start_dma_without_bch_irq() code? Would appreciate any pointers in
>>> fixing this...
> RCU is upset because what it believes to be a non-idle task is telling
> RCU that it is entering the idle loop.
>
> Does the MX28 kernel have any unusual idle features?  (This is a subarch
> of ARM, correct?)
>
> 							Thanx, Paul

MX28 is ARM device. I removed following from my config and these 
warnings went away.

CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y

I have attached the kernel configuration file I used.

It doesn't affect specific hw I am working with as device is not 
required to enter idle mode.
I am Cc-ing linux-arm folks,  in case someone on arm platform requires 
CPU idele &, RCU to work.

-Subodh
>>> [    4.280000] WARNING: at /opt/git/kernel-mainline/kernel/rcutiny.c:75
>>> rcu_idle_enter_common.clone.7+0x90/0xac()
>>> [    4.280000] Current pid: 1 comm: swapper / Idle pid: 0 comm: swapper
>>> [    4.280000] Modules linked in:
>>> [    4.280000] [<c0014eec>] (unwind_backtrace+0x0/0x130) from
>>> [<c001dd94>] (warn_slowpath_common+0x4c/0x64)
>>> [    4.280000] [<c001dd94>] (warn_slowpath_common+0x4c/0x64) from
>>> [<c001de40>] (warn_slowpath_fmt+0x30/0x40)
>>> [    4.280000] [<c001de40>] (warn_slowpath_fmt+0x30/0x40) from
>>> [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
>>> [    4.280000] [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
>>> from [<c0061670>] (rcu_irq_exit+0x3c/0x78)
>>> [    4.280000] [<c0061670>] (rcu_irq_exit+0x3c/0x78) from [<c000fe90>]
>>> (handle_IRQ+0x34/0x84)
>>> [    4.280000] [<c000fe90>] (handle_IRQ+0x34/0x84) from [<c000ec34>]
>>> (__irq_svc+0x34/0x58)
>>> [    4.280000] [<c000ec34>] (__irq_svc+0x34/0x58) from [<c0394c4c>]
>>> (schedule_timeout+0xdc/0x16c)
>>> [    4.280000] [<c0394c4c>] (schedule_timeout+0xdc/0x16c) from
>>> [<c0395f34>] (wait_for_common+0xb4/0x160)
>>> [    4.280000] [<c0395f34>] (wait_for_common+0xb4/0x160) from
>>> [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8)
>>> [    4.280000] [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8) from
>>> [<c0258660>] (gpmi_send_command+0x120/0x154)
>>> [    4.280000] [<c0258660>] (gpmi_send_command+0x120/0x154) from
>>> [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c)
>>> [    4.280000] [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c) from [<c024f8e0>]
>>> (nand_command_lp+0xe8/0x270)
>>> [    4.280000] [<c024f8e0>] (nand_command_lp+0xe8/0x270) from
>>> [<c0251e00>] (nand_do_read_ops+0x124/0x444)
>>> [    4.280000] [<c0251e00>] (nand_do_read_ops+0x124/0x444) from
>>> [<c0252558>] (nand_read+0x54/0x78)
>>> [    4.280000] [<c0252558>] (nand_read+0x54/0x78) from [<c02499a4>]
>>> (part_read+0x48/0x80)
>>> [    4.280000] [<c02499a4>] (part_read+0x48/0x80) from [<c0246910>]
>>> (mtd_read+0x88/0xb4)
>>> [    4.280000] [<c0246910>] (mtd_read+0x88/0xb4) from [<c026b188>]
>>> (ubi_io_read+0xb0/0x3e8)
>>> [    4.280000] [<c026b188>] (ubi_io_read+0xb0/0x3e8) from [<c026740c>]
>>> (ubi_eba_read_leb+0x198/0x4bc)
>>> [    4.280000] [<c026740c>] (ubi_eba_read_leb+0x198/0x4bc) from
>>> [<c0266800>] (ubi_leb_read+0xf4/0x16c)
>>> [    4.280000] [<c0266800>] (ubi_leb_read+0xf4/0x16c) from [<c0155550>]
>>> (ubifs_leb_read+0x24/0x88)
>>> [    4.280000] [<c0155550>] (ubifs_leb_read+0x24/0x88) from [<c01572f8>]
>>> (ubifs_read_node+0xa8/0x2e4)
>>> [    4.280000] [<c01572f8>] (ubifs_read_node+0xa8/0x2e4) from
>>> [<c0153c50>] (ubifs_read_sb_node+0x54/0x78)
>>> [    4.280000] [<c0153c50>] (ubifs_read_sb_node+0x54/0x78) from
>>> [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c)
>>> [    4.280000] [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c) from
>>> [<c01520ac>] (ubifs_mount+0x73c/0x1bc0)
>>> [    4.280000] [<c01520ac>] (ubifs_mount+0x73c/0x1bc0) from [<c00a49ec>]
>>> (mount_fs+0x44/0x184)
>>> [    4.280000] [<c00a49ec>] (mount_fs+0x44/0x184) from [<c00baf90>]
>>> (vfs_kern_mount+0x4c/0xc0)
>>> [    4.280000] [<c00baf90>] (vfs_kern_mount+0x4c/0xc0) from [<c00bb1a0>]
>>> (do_kern_mount+0x34/0xd0)
>>> [    4.280000] [<c00bb1a0>] (do_kern_mount+0x34/0xd0) from [<c00bc93c>]
>>> (do_mount+0x15c/0x73c)
>>> [    4.280000] [<c00bc93c>] (do_mount+0x15c/0x73c) from [<c00bcfa0>]
>>> (sys_mount+0x84/0xc4)
>>> [    4.280000] [<c00bcfa0>] (sys_mount+0x84/0xc4) from [<c04e4a04>]
>>> (do_mount_root+0x24/0xb0)
>>> [    4.280000] [<c04e4a04>] (do_mount_root+0x24/0xb0) from [<c04e4b78>]
>>> (mount_block_root+0xe8/0x214)
>>> [    4.280000] [<c04e4b78>] (mount_block_root+0xe8/0x214) from
>>> [<c04e4e28>] (prepare_namespace+0x8c/0x180)
>>> [    4.280000] [<c04e4e28>] (prepare_namespace+0x8c/0x180) from
>>> [<c04e4894>] (kernel_init+0x16c/0x1b4)
>>> [    4.280000] [<c04e4894>] (kernel_init+0x16c/0x1b4) from [<c000ff70>]
>>> (kernel_thread_exit+0x0/0x8)
>>> [    4.280000] ---[ end trace 4d36b722759fdc4f ]---
>>> [    4.950000] UBIFS DBG (pid 58): ubifs_bg_thread: background thread
>>> "ubifs_bgt0_0" started, PID 58
>>>
>>> -Subodh
>>>
>>> ______________________________________________________
>>> Linux MTD discussion mailing list
>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>> -- 
>> Best Regards,
>> Artem Bityutskiy
>

-------------- next part --------------
#
# Automatically generated file; DO NOT EDIT.
# Linux/arm 3.6.0-rc4 Kernel Configuration
#
CONFIG_ARM=y
CONFIG_HAVE_PWM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_HAVE_PROC_CPU=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_ARM_PATCH_PHYS_VIRT=y
CONFIG_GENERIC_BUG=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_HAVE_IRQ_WORK=y
CONFIG_IRQ_WORK=y

#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_CROSS_COMPILE="/opt/tools/cs-2009q1/bin/arm-none-linux-gnueabi-"
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_HAVE_KERNEL_GZIP=y
CONFIG_HAVE_KERNEL_LZMA=y
CONFIG_HAVE_KERNEL_XZ=y
CONFIG_HAVE_KERNEL_LZO=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_LZMA is not set
# CONFIG_KERNEL_XZ is not set
# CONFIG_KERNEL_LZO is not set
CONFIG_DEFAULT_HOSTNAME="(none)"
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_FHANDLE is not set
# CONFIG_TASKSTATS is not set
CONFIG_AUDIT=y
CONFIG_AUDIT_LOGINUID_IMMUTABLE=y
CONFIG_HAVE_GENERIC_HARDIRQS=y

#
# IRQ subsystem
#
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_IRQ_DOMAIN=y
# CONFIG_IRQ_DOMAIN_DEBUG is not set
CONFIG_KTIME_SCALAR=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y

#
# Timers subsystem
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y

#
# RCU Subsystem
#
CONFIG_TINY_RCU=y
# CONFIG_PREEMPT_RCU is not set
# CONFIG_TREE_RCU_TRACE is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_CHECKPOINT_RESTORE is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_IPC_NS is not set
# CONFIG_PID_NS is not set
# CONFIG_NET_NS is not set
# CONFIG_SCHED_AUTOGROUP is not set
# CONFIG_SYSFS_DEPRECATED is not set
CONFIG_RELAY=y
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
# CONFIG_EXPERT is not set
CONFIG_UID16=y
# CONFIG_SYSCTL_SYSCALL is not set
CONFIG_KALLSYMS=y
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
# CONFIG_EMBEDDED is not set
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_PERF_USE_VMALLOC=y

#
# Kernel Performance Events And Counters
#
CONFIG_PERF_EVENTS=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_JUMP_LABEL is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y

#
# GCOV-based kernel profiling
#
# CONFIG_GCOV_KERNEL is not set
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_BLOCK=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_BSGLIB is not set
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_FREEZER is not set

#
# System Type
#
CONFIG_MMU=y
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_VEXPRESS is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_BCMRING is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CNS3XXX is not set
# CONFIG_ARCH_GEMINI is not set
# CONFIG_ARCH_PRIMA2 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_MXC is not set
CONFIG_ARCH_MXS=y
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_ARCH_DOVE is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_MV78XX0 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_MMP is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_W90X900 is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_ARCH_PICOXCELL is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_MSM is not set
# CONFIG_ARCH_SHMOBILE is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C24XX is not set
# CONFIG_ARCH_S3C64XX is not set
# CONFIG_ARCH_S5P64X0 is not set
# CONFIG_ARCH_S5PC100 is not set
# CONFIG_ARCH_S5PV210 is not set
# CONFIG_ARCH_EXYNOS is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_U300 is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_NOMADIK is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_PLAT_SPEAR is not set
# CONFIG_ARCH_VT8500 is not set
# CONFIG_ARCH_ZYNQ is not set
# CONFIG_GPIO_PCA953X is not set
CONFIG_MXS_HAVE_AMBA_DUART=y
CONFIG_MXS_HAVE_PLATFORM_AUART=y
CONFIG_MXS_HAVE_PLATFORM_FEC=y
CONFIG_MXS_HAVE_PLATFORM_FLEXCAN=y
CONFIG_MXS_HAVE_PLATFORM_MXS_I2C=y
CONFIG_MXS_HAVE_PLATFORM_MXS_MMC=y
CONFIG_MXS_HAVE_PLATFORM_MXSFB=y
CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF=y
CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX=y
CONFIG_SOC_IMX23=y
CONFIG_SOC_IMX28=y

#
# MXS platforms:
#
CONFIG_MACH_MXS_DT=y
# CONFIG_MACH_STMP378X_DEVB is not set
# CONFIG_MACH_MX23EVK is not set
CONFIG_MACH_MX28EVK=y
# CONFIG_MACH_TX28 is not set
# CONFIG_MACH_M28EVK is not set
# CONFIG_MACH_APX4DEVKIT is not set

#
# Processor Type
#
CONFIG_CPU_ARM926T=y
CONFIG_CPU_32v5=y
CONFIG_CPU_ABRT_EV5TJ=y
CONFIG_CPU_PABRT_LEGACY=y
CONFIG_CPU_CACHE_VIVT=y
CONFIG_CPU_COPY_V4WB=y
CONFIG_CPU_TLB_V4WBI=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_USE_DOMAINS=y

#
# Processor Features
#
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
# CONFIG_CACHE_L2X0 is not set
CONFIG_ARM_L1_CACHE_SHIFT=5
CONFIG_ARM_NR_BANKS=8

#
# Bus support
#
CONFIG_ARM_AMBA=y
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set

#
# Kernel Features
#
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_ARCH_NR_GPIO=0
# CONFIG_PREEMPT_NONE is not set
CONFIG_PREEMPT_VOLUNTARY=y
# CONFIG_PREEMPT is not set
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_OABI_COMPAT=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_HAVE_ARCH_PFN_VALID=y
# CONFIG_HIGHMEM is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=999999
# CONFIG_COMPACTION is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_NEED_PER_CPU_KM=y
# CONFIG_CLEANCACHE is not set
# CONFIG_FRONTSWAP is not set
CONFIG_FORCE_MAX_ZONEORDER=11
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_UACCESS_WITH_MEMCPY is not set
# CONFIG_SECCOMP is not set
# CONFIG_CC_STACKPROTECTOR is not set
# CONFIG_DEPRECATED_PARAM_STRUCT is not set

#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ARM_APPENDED_DTB=y
# CONFIG_ARM_ATAG_DTB_COMPAT is not set
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
CONFIG_KEXEC=y
CONFIG_ATAGS_PROC=y
CONFIG_CRASH_DUMP=y
CONFIG_AUTO_ZRELADDR=y

#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set

#
# Floating point emulation
#

#
# At least one emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set

#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set

#
# Power management options
#
# CONFIG_SUSPEND is not set
# CONFIG_PM_RUNTIME is not set
CONFIG_ARCH_HAS_OPP=y
# CONFIG_PM_OPP is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
# CONFIG_ARM_CPU_SUSPEND is not set
CONFIG_NET=y

#
# Networking options
#
CONFIG_PACKET=y
CONFIG_UNIX=y
# CONFIG_UNIX_DIAG is not set
CONFIG_XFRM=y
CONFIG_XFRM_ALGO=y
# CONFIG_XFRM_USER is not set
# CONFIG_XFRM_SUB_POLICY is not set
# CONFIG_XFRM_MIGRATE is not set
# CONFIG_XFRM_STATISTICS is not set
CONFIG_XFRM_IPCOMP=y
CONFIG_NET_KEY=y
# CONFIG_NET_KEY_MIGRATE is not set
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE_DEMUX is not set
# CONFIG_IP_MROUTE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_NET_IPVTI is not set
# CONFIG_INET_AH is not set
CONFIG_INET_ESP=y
CONFIG_INET_IPCOMP=y
CONFIG_INET_XFRM_TUNNEL=y
CONFIG_INET_TUNNEL=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_INET_UDP_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETLABEL is not set
CONFIG_NETWORK_SECMARK=y
# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
CONFIG_NETFILTER=y
# CONFIG_NETFILTER_DEBUG is not set
CONFIG_NETFILTER_ADVANCED=y

#
# Core Netfilter Configuration
#
CONFIG_NETFILTER_NETLINK=y
CONFIG_NETFILTER_NETLINK_ACCT=y
# CONFIG_NETFILTER_NETLINK_QUEUE is not set
# CONFIG_NETFILTER_NETLINK_LOG is not set
CONFIG_NF_CONNTRACK=y
CONFIG_NF_CONNTRACK_MARK=y
CONFIG_NF_CONNTRACK_SECMARK=y
CONFIG_NF_CONNTRACK_PROCFS=y
# CONFIG_NF_CONNTRACK_EVENTS is not set
CONFIG_NF_CONNTRACK_TIMEOUT=y
CONFIG_NF_CONNTRACK_TIMESTAMP=y
# CONFIG_NF_CT_PROTO_DCCP is not set
# CONFIG_NF_CT_PROTO_SCTP is not set
# CONFIG_NF_CT_PROTO_UDPLITE is not set
# CONFIG_NF_CONNTRACK_AMANDA is not set
# CONFIG_NF_CONNTRACK_FTP is not set
# CONFIG_NF_CONNTRACK_H323 is not set
# CONFIG_NF_CONNTRACK_IRC is not set
# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
# CONFIG_NF_CONNTRACK_SNMP is not set
# CONFIG_NF_CONNTRACK_PPTP is not set
# CONFIG_NF_CONNTRACK_SANE is not set
# CONFIG_NF_CONNTRACK_SIP is not set
# CONFIG_NF_CONNTRACK_TFTP is not set
# CONFIG_NF_CT_NETLINK is not set
CONFIG_NF_CT_NETLINK_TIMEOUT=y
CONFIG_NETFILTER_XTABLES=y

#
# Xtables combined modules
#
CONFIG_NETFILTER_XT_MARK=y
CONFIG_NETFILTER_XT_CONNMARK=y

#
# Xtables targets
#
# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set
# CONFIG_NETFILTER_XT_TARGET_CT is not set
# CONFIG_NETFILTER_XT_TARGET_HMARK is not set
# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
# CONFIG_NETFILTER_XT_TARGET_LED is not set
CONFIG_NETFILTER_XT_TARGET_LOG=y
CONFIG_NETFILTER_XT_TARGET_MARK=y
# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
# CONFIG_NETFILTER_XT_TARGET_TEE is not set
CONFIG_NETFILTER_XT_TARGET_TRACE=y
CONFIG_NETFILTER_XT_TARGET_SECMARK=y
# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set

#
# Xtables matches
#
# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
# CONFIG_NETFILTER_XT_MATCH_CPU is not set
# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
CONFIG_NETFILTER_XT_MATCH_ECN=y
# CONFIG_NETFILTER_XT_MATCH_ESP is not set
# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
# CONFIG_NETFILTER_XT_MATCH_HL is not set
# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
CONFIG_NETFILTER_XT_MATCH_LIMIT=y
# CONFIG_NETFILTER_XT_MATCH_MAC is not set
CONFIG_NETFILTER_XT_MATCH_MARK=y
CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
CONFIG_NETFILTER_XT_MATCH_NFACCT=y
CONFIG_NETFILTER_XT_MATCH_OSF=y
# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
# CONFIG_NETFILTER_XT_MATCH_REALM is not set
CONFIG_NETFILTER_XT_MATCH_RECENT=y
# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
CONFIG_NETFILTER_XT_MATCH_STATE=y
# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
# CONFIG_NETFILTER_XT_MATCH_STRING is not set
# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
CONFIG_NETFILTER_XT_MATCH_TIME=y
# CONFIG_NETFILTER_XT_MATCH_U32 is not set
# CONFIG_IP_SET is not set
# CONFIG_IP_VS is not set

#
# IP: Netfilter Configuration
#
CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_CONNTRACK_IPV4=y
# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
# CONFIG_IP_NF_QUEUE is not set
CONFIG_IP_NF_IPTABLES=y
# CONFIG_IP_NF_MATCH_AH is not set
# CONFIG_IP_NF_MATCH_ECN is not set
# CONFIG_IP_NF_MATCH_RPFILTER is not set
# CONFIG_IP_NF_MATCH_TTL is not set
CONFIG_IP_NF_FILTER=y
CONFIG_IP_NF_TARGET_REJECT=y
CONFIG_IP_NF_TARGET_ULOG=y
# CONFIG_NF_NAT is not set
# CONFIG_IP_NF_MANGLE is not set
CONFIG_IP_NF_RAW=y
# CONFIG_IP_NF_SECURITY is not set
CONFIG_IP_NF_ARPTABLES=y
CONFIG_IP_NF_ARPFILTER=y
# CONFIG_IP_NF_ARP_MANGLE is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_RDS is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_L2TP is not set
# CONFIG_BRIDGE is not set
# CONFIG_NET_DSA is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_PHONET is not set
# CONFIG_IEEE802154 is not set
# CONFIG_NET_SCHED is not set
# CONFIG_DCB is not set
CONFIG_DNS_RESOLVER=y
# CONFIG_BATMAN_ADV is not set
# CONFIG_OPENVSWITCH is not set
CONFIG_BQL=y
# CONFIG_BPF_JIT is not set

#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
# CONFIG_WIRELESS is not set
# CONFIG_WIMAX is not set
# CONFIG_RFKILL is not set
# CONFIG_RFKILL_REGULATOR is not set
# CONFIG_NET_9P is not set
# CONFIG_CAIF is not set
# CONFIG_CEPH_LIB is not set
# CONFIG_NFC is not set
CONFIG_HAVE_BPF_JIT=y

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_DEVTMPFS=y
# CONFIG_DEVTMPFS_MOUNT is not set
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_GENERIC_CPU_DEVICES is not set
# CONFIG_DMA_SHARED_BUFFER is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_TESTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_OF_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set

#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=m
# CONFIG_MTD_BLOCK is not set
# CONFIG_MTD_BLOCK_RO is not set
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_SM_FTL is not set
# CONFIG_MTD_OOPS is not set
# CONFIG_MTD_SWAP is not set

#
# RAM/ROM/Flash chip drivers
#
# CONFIG_MTD_CFI is not set
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set

#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PLATRAM is not set

#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set

#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_DOCG3 is not set
CONFIG_MTD_NAND_ECC=y
# CONFIG_MTD_NAND_ECC_SMC is not set
CONFIG_MTD_NAND=y
# CONFIG_MTD_NAND_VERIFY_WRITE is not set
CONFIG_MTD_NAND_BCH=y
CONFIG_MTD_NAND_ECC_BCH=y
# CONFIG_MTD_SM_COMMON is not set
CONFIG_MTD_NAND_MUSEUM_IDS=y
# CONFIG_MTD_NAND_GPIO is not set
CONFIG_MTD_NAND_IDS=y
# CONFIG_MTD_NAND_DISKONCHIP is not set
# CONFIG_MTD_NAND_DOCG4 is not set
# CONFIG_MTD_NAND_NANDSIM is not set
CONFIG_MTD_NAND_GPMI_NAND=y
CONFIG_MTD_NAND_PLATFORM=y
# CONFIG_MTD_ALAUDA is not set
CONFIG_MTD_ONENAND=y
# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
# CONFIG_MTD_ONENAND_GENERIC is not set
# CONFIG_MTD_ONENAND_OTP is not set
# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
# CONFIG_MTD_ONENAND_SIM is not set

#
# LPDDR flash memory drivers
#
# CONFIG_MTD_LPDDR is not set
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_RESERVE=1
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_DTC=y
CONFIG_OF=y

#
# Device Tree and Open Firmware support
#
CONFIG_PROC_DEVICETREE=y
CONFIG_OF_SELFTEST=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_IRQ=y
CONFIG_OF_DEVICE=y
CONFIG_OF_I2C=y
CONFIG_OF_NET=y
CONFIG_OF_MDIO=y
CONFIG_OF_MTD=y
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set

#
# Misc devices
#
# CONFIG_SENSORS_LIS3LV02D is not set
# CONFIG_AD525X_DPOT is not set
# CONFIG_ATMEL_PWM is not set
# CONFIG_ICS932S401 is not set
# CONFIG_ENCLOSURE_SERVICES is not set
# CONFIG_APDS9802ALS is not set
# CONFIG_ISL29003 is not set
# CONFIG_ISL29020 is not set
# CONFIG_SENSORS_TSL2550 is not set
# CONFIG_SENSORS_BH1780 is not set
# CONFIG_SENSORS_BH1770 is not set
# CONFIG_SENSORS_APDS990X is not set
# CONFIG_HMC6352 is not set
# CONFIG_DS1682 is not set
# CONFIG_BMP085_I2C is not set
# CONFIG_USB_SWITCH_FSA9480 is not set
CONFIG_MMA7660=y
CONFIG_MXS_PERSISTENT=y
# CONFIG_C2PORT is not set

#
# EEPROM support
#
CONFIG_EEPROM_AT24=y
# CONFIG_EEPROM_LEGACY is not set
# CONFIG_EEPROM_MAX6875 is not set
# CONFIG_EEPROM_93CX6 is not set

#
# Texas Instruments shared transport line discipline
#
# CONFIG_TI_ST is not set
# CONFIG_SENSORS_LIS3_I2C is not set

#
# Altera FPGA firmware download module
#
# CONFIG_ALTERA_STAPL is not set

#
# SCSI device support
#
CONFIG_SCSI_MOD=y
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
CONFIG_NET_CORE=y
# CONFIG_BONDING is not set
# CONFIG_DUMMY is not set
# CONFIG_EQUALIZER is not set
# CONFIG_MII is not set
# CONFIG_NET_TEAM is not set
# CONFIG_MACVLAN is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set

#
# CAIF transport drivers
#
CONFIG_ETHERNET=y
CONFIG_NET_VENDOR_BROADCOM=y
# CONFIG_B44 is not set
# CONFIG_NET_CALXEDA_XGMAC is not set
CONFIG_NET_VENDOR_CHELSIO=y
CONFIG_NET_VENDOR_CIRRUS=y
# CONFIG_CS89x0 is not set
# CONFIG_DM9000 is not set
# CONFIG_DNET is not set
CONFIG_NET_VENDOR_FARADAY=y
# CONFIG_FTMAC100 is not set
# CONFIG_FTGMAC100 is not set
CONFIG_NET_VENDOR_FREESCALE=y
CONFIG_FEC=y
CONFIG_NET_VENDOR_INTEL=y
CONFIG_NET_VENDOR_I825XX=y
CONFIG_NET_VENDOR_MARVELL=y
CONFIG_NET_VENDOR_MICREL=y
# CONFIG_KS8842 is not set
# CONFIG_KS8851_MLL is not set
CONFIG_NET_VENDOR_NATSEMI=y
CONFIG_NET_VENDOR_8390=y
# CONFIG_AX88796 is not set
# CONFIG_ETHOC is not set
CONFIG_NET_VENDOR_SEEQ=y
# CONFIG_SEEQ8005 is not set
CONFIG_NET_VENDOR_SMSC=y
# CONFIG_SMC91X is not set
# CONFIG_SMC911X is not set
# CONFIG_SMSC911X is not set
CONFIG_NET_VENDOR_STMICRO=y
# CONFIG_STMMAC_ETH is not set
CONFIG_NET_VENDOR_WIZNET=y
# CONFIG_WIZNET_W5100 is not set
# CONFIG_WIZNET_W5300 is not set
CONFIG_PHYLIB=y

#
# MII PHY device drivers
#
# CONFIG_AMD_PHY is not set
# CONFIG_MARVELL_PHY is not set
# CONFIG_DAVICOM_PHY is not set
# CONFIG_QSEMI_PHY is not set
# CONFIG_LXT_PHY is not set
# CONFIG_CICADA_PHY is not set
# CONFIG_VITESSE_PHY is not set
# CONFIG_SMSC_PHY is not set
# CONFIG_BROADCOM_PHY is not set
# CONFIG_BCM87XX_PHY is not set
# CONFIG_ICPLUS_PHY is not set
# CONFIG_REALTEK_PHY is not set
# CONFIG_NATIONAL_PHY is not set
# CONFIG_STE10XP is not set
# CONFIG_LSI_ET1011C_PHY is not set
# CONFIG_MICREL_PHY is not set
# CONFIG_FIXED_PHY is not set
# CONFIG_MDIO_BITBANG is not set
# CONFIG_MDIO_BUS_MUX_GPIO is not set
CONFIG_PPP=m
CONFIG_PPP_BSDCOMP=m
CONFIG_PPP_DEFLATE=m
CONFIG_PPP_FILTER=y
CONFIG_PPP_MPPE=m
# CONFIG_PPP_MULTILINK is not set
# CONFIG_PPPOE is not set
CONFIG_PPP_ASYNC=m
# CONFIG_PPP_SYNC_TTY is not set
# CONFIG_SLIP is not set
CONFIG_SLHC=m

#
# USB Network Adapters
#
# CONFIG_USB_CATC is not set
# CONFIG_USB_KAWETH is not set
# CONFIG_USB_PEGASUS is not set
# CONFIG_USB_RTL8150 is not set
# CONFIG_USB_USBNET is not set
# CONFIG_USB_IPHETH is not set
# CONFIG_WLAN is not set

#
# Enable WiMAX (Networking options) to see the WiMAX drivers
#
# CONFIG_WAN is not set
# CONFIG_ISDN is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_MATRIXKMAP is not set

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
CONFIG_INPUT_EVDEV=m
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
CONFIG_TOUCHSCREEN_TSC2007=m
# CONFIG_TOUCHSCREEN_W90X900 is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_INPUT_MISC is not set

#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_UNIX98_PTYS=y
CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_SERIAL_NONSTANDARD is not set
# CONFIG_N_GSM is not set
# CONFIG_TRACE_SINK is not set
# CONFIG_DEVKMEM is not set

#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set

#
# Non-8250 serial port support
#
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
# CONFIG_SERIAL_TIMBERDALE is not set
# CONFIG_SERIAL_ALTERA_JTAGUART is not set
# CONFIG_SERIAL_ALTERA_UART is not set
CONFIG_SERIAL_MXS_AUART=y
CONFIG_SERIAL_MXS_AUART_CONSOLE=y
# CONFIG_SERIAL_XILINX_PS_UART is not set
# CONFIG_HVC_DCC is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_MUX is not set
CONFIG_I2C_HELPER_AUTO=y

#
# I2C Hardware Bus support
#

#
# I2C system bus drivers (mostly embedded / system-on-chip)
#
# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
# CONFIG_I2C_GPIO is not set
CONFIG_I2C_MXS=y
# CONFIG_I2C_NOMADIK is not set
# CONFIG_I2C_OCORES is not set
# CONFIG_I2C_PCA_PLATFORM is not set
# CONFIG_I2C_PXA_PCI is not set
# CONFIG_I2C_SIMTEC is not set
# CONFIG_I2C_XILINX is not set

#
# External I2C/SMBus adapter drivers
#
# CONFIG_I2C_DIOLAN_U2C is not set
# CONFIG_I2C_PARPORT_LIGHT is not set
# CONFIG_I2C_TAOS_EVM is not set
# CONFIG_I2C_TINY_USB is not set

#
# Other I2C/SMBus bus drivers
#
# CONFIG_I2C_STUB is not set
# CONFIG_I2C_DEBUG_CORE is not set
# CONFIG_I2C_DEBUG_ALGO is not set
# CONFIG_I2C_DEBUG_BUS is not set
# CONFIG_SPI is not set
# CONFIG_HSI is not set

#
# PPS support
#
# CONFIG_PPS is not set

#
# PPS generators support
#

#
# PTP clock support
#

#
# Enable Device Drivers -> PPS to see the PTP clock options.
#
CONFIG_PINCTRL=y

#
# Pin controllers
#
CONFIG_PINMUX=y
CONFIG_PINCONF=y
CONFIG_PINCTRL_MXS=y
CONFIG_PINCTRL_IMX23=y
CONFIG_PINCTRL_IMX28=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
CONFIG_OF_GPIO=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_GENERIC=y

#
# Memory mapped GPIO drivers:
#
# CONFIG_GPIO_GENERIC_PLATFORM is not set
# CONFIG_GPIO_EM is not set
CONFIG_GPIO_MXS=y
# CONFIG_GPIO_PL061 is not set

#
# I2C GPIO expanders:
#
# CONFIG_GPIO_MAX7300 is not set
# CONFIG_GPIO_MAX732X is not set
# CONFIG_GPIO_PCF857X is not set
# CONFIG_GPIO_SX150X is not set
# CONFIG_GPIO_ADP5588 is not set

#
# PCI GPIO expanders:
#

#
# SPI GPIO expanders:
#
# CONFIG_GPIO_MCP23S08 is not set

#
# AC97 GPIO expanders:
#

#
# MODULbus GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_POWER_AVS is not set
CONFIG_HWMON=y
# CONFIG_HWMON_VID is not set
# CONFIG_HWMON_DEBUG_CHIP is not set

#
# Native drivers
#
# CONFIG_SENSORS_AD7414 is not set
# CONFIG_SENSORS_AD7418 is not set
CONFIG_SENSORS_LRADC=y
# CONFIG_SENSORS_ADM1021 is not set
# CONFIG_SENSORS_ADM1025 is not set
# CONFIG_SENSORS_ADM1026 is not set
# CONFIG_SENSORS_ADM1029 is not set
# CONFIG_SENSORS_ADM1031 is not set
# CONFIG_SENSORS_ADM9240 is not set
# CONFIG_SENSORS_ADT7411 is not set
# CONFIG_SENSORS_ADT7462 is not set
# CONFIG_SENSORS_ADT7470 is not set
# CONFIG_SENSORS_ADT7475 is not set
# CONFIG_SENSORS_ASC7621 is not set
# CONFIG_SENSORS_ATXP1 is not set
# CONFIG_SENSORS_DS620 is not set
# CONFIG_SENSORS_DS1621 is not set
# CONFIG_SENSORS_F71805F is not set
# CONFIG_SENSORS_F71882FG is not set
# CONFIG_SENSORS_F75375S is not set
# CONFIG_SENSORS_G760A is not set
# CONFIG_SENSORS_GL518SM is not set
# CONFIG_SENSORS_GL520SM is not set
# CONFIG_SENSORS_GPIO_FAN is not set
# CONFIG_SENSORS_HIH6130 is not set
# CONFIG_SENSORS_IT87 is not set
# CONFIG_SENSORS_JC42 is not set
# CONFIG_SENSORS_LINEAGE is not set
# CONFIG_SENSORS_LM63 is not set
# CONFIG_SENSORS_LM73 is not set
# CONFIG_SENSORS_LM75 is not set
# CONFIG_SENSORS_LM77 is not set
# CONFIG_SENSORS_LM78 is not set
# CONFIG_SENSORS_LM80 is not set
# CONFIG_SENSORS_LM83 is not set
# CONFIG_SENSORS_LM85 is not set
# CONFIG_SENSORS_LM87 is not set
# CONFIG_SENSORS_LM90 is not set
# CONFIG_SENSORS_LM92 is not set
# CONFIG_SENSORS_LM93 is not set
# CONFIG_SENSORS_LTC4151 is not set
# CONFIG_SENSORS_LTC4215 is not set
# CONFIG_SENSORS_LTC4245 is not set
# CONFIG_SENSORS_LTC4261 is not set
# CONFIG_SENSORS_LM95241 is not set
# CONFIG_SENSORS_LM95245 is not set
# CONFIG_SENSORS_MAX16065 is not set
# CONFIG_SENSORS_MAX1619 is not set
# CONFIG_SENSORS_MAX1668 is not set
# CONFIG_SENSORS_MAX6639 is not set
# CONFIG_SENSORS_MAX6642 is not set
# CONFIG_SENSORS_MAX6650 is not set
CONFIG_SENSORS_MAX7500=y
# CONFIG_SENSORS_MCP3021 is not set
# CONFIG_SENSORS_NTC_THERMISTOR is not set
# CONFIG_SENSORS_PC87360 is not set
# CONFIG_SENSORS_PC87427 is not set
# CONFIG_SENSORS_PCF8591 is not set
# CONFIG_PMBUS is not set
# CONFIG_SENSORS_SHT15 is not set
# CONFIG_SENSORS_SHT21 is not set
# CONFIG_SENSORS_SMM665 is not set
# CONFIG_SENSORS_DME1737 is not set
# CONFIG_SENSORS_EMC1403 is not set
# CONFIG_SENSORS_EMC2103 is not set
# CONFIG_SENSORS_EMC6W201 is not set
# CONFIG_SENSORS_SMSC47M1 is not set
# CONFIG_SENSORS_SMSC47M192 is not set
# CONFIG_SENSORS_SMSC47B397 is not set
# CONFIG_SENSORS_SCH56XX_COMMON is not set
# CONFIG_SENSORS_SCH5627 is not set
# CONFIG_SENSORS_SCH5636 is not set
# CONFIG_SENSORS_ADS1015 is not set
# CONFIG_SENSORS_ADS7828 is not set
# CONFIG_SENSORS_AMC6821 is not set
# CONFIG_SENSORS_INA2XX is not set
# CONFIG_SENSORS_THMC50 is not set
# CONFIG_SENSORS_TMP102 is not set
# CONFIG_SENSORS_TMP401 is not set
# CONFIG_SENSORS_TMP421 is not set
# CONFIG_SENSORS_VT1211 is not set
# CONFIG_SENSORS_W83781D is not set
# CONFIG_SENSORS_W83791D is not set
# CONFIG_SENSORS_W83792D is not set
# CONFIG_SENSORS_W83793 is not set
# CONFIG_SENSORS_W83795 is not set
# CONFIG_SENSORS_W83L785TS is not set
# CONFIG_SENSORS_W83L786NG is not set
# CONFIG_SENSORS_W83627HF is not set
# CONFIG_SENSORS_W83627EHF is not set
# CONFIG_THERMAL is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_CORE=y
# CONFIG_WATCHDOG_NOWAYOUT is not set

#
# Watchdog Device Drivers
#
# CONFIG_SOFT_WATCHDOG is not set
# CONFIG_ARM_SP805_WATCHDOG is not set
CONFIG_MXS_WATCHDOG=y
# CONFIG_DW_WATCHDOG is not set
# CONFIG_MAX63XX_WATCHDOG is not set

#
# USB-based Watchdog Cards
#
# CONFIG_USBPCWATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set
CONFIG_BCMA_POSSIBLE=y

#
# Broadcom specific AMBA
#
# CONFIG_BCMA is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_88PM860X is not set
# CONFIG_MFD_88PM800 is not set
# CONFIG_MFD_88PM805 is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_HTC_I2CPLD is not set
# CONFIG_MFD_LM3533 is not set
# CONFIG_TPS6105X is not set
# CONFIG_TPS65010 is not set
# CONFIG_TPS6507X is not set
# CONFIG_MFD_TPS65217 is not set
# CONFIG_MFD_TPS6586X is not set
# CONFIG_MFD_TPS65910 is not set
# CONFIG_MFD_TPS65912_I2C is not set
# CONFIG_TWL4030_CORE is not set
# CONFIG_TWL6040_CORE is not set
# CONFIG_MFD_STMPE is not set
# CONFIG_MFD_TC3589X is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_MFD_DA9052_I2C is not set
# CONFIG_PMIC_ADP5520 is not set
# CONFIG_MFD_MAX77686 is not set
# CONFIG_MFD_MAX77693 is not set
# CONFIG_MFD_MAX8925 is not set
# CONFIG_MFD_MAX8997 is not set
# CONFIG_MFD_MAX8998 is not set
# CONFIG_MFD_SEC_CORE is not set
# CONFIG_MFD_ARIZONA_I2C is not set
# CONFIG_MFD_WM8400 is not set
# CONFIG_MFD_WM831X_I2C is not set
# CONFIG_MFD_WM8350_I2C is not set
# CONFIG_MFD_WM8994 is not set
# CONFIG_MFD_PCF50633 is not set
# CONFIG_MFD_MC13XXX_I2C is not set
# CONFIG_ABX500_CORE is not set
# CONFIG_MFD_WL1273_CORE is not set
# CONFIG_MFD_TPS65090 is not set
# CONFIG_MFD_AAT2870_CORE is not set
# CONFIG_MFD_RC5T583 is not set
# CONFIG_MFD_PALMAS is not set
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_DEBUG is not set
# CONFIG_REGULATOR_DUMMY is not set
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
# CONFIG_REGULATOR_GPIO is not set
# CONFIG_REGULATOR_AD5398 is not set
CONFIG_REGULATOR_MXS=y
# CONFIG_REGULATOR_ISL6271A is not set
# CONFIG_REGULATOR_MAX1586 is not set
# CONFIG_REGULATOR_MAX8649 is not set
# CONFIG_REGULATOR_MAX8660 is not set
# CONFIG_REGULATOR_MAX8952 is not set
# CONFIG_REGULATOR_LP3971 is not set
# CONFIG_REGULATOR_LP3972 is not set
# CONFIG_REGULATOR_LP872X is not set
# CONFIG_REGULATOR_TPS62360 is not set
# CONFIG_REGULATOR_TPS65023 is not set
# CONFIG_REGULATOR_TPS6507X is not set
# CONFIG_MEDIA_SUPPORT is not set

#
# Graphics support
#
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_EXYNOS_VIDEO is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

#
# Console display driver support
#
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set

#
# HID support
#
CONFIG_HID=y
# CONFIG_HIDRAW is not set
# CONFIG_UHID is not set
CONFIG_HID_GENERIC=y

#
# Special HID drivers
#
CONFIG_HID_A4TECH=y
# CONFIG_HID_ACRUX is not set
CONFIG_HID_APPLE=y
# CONFIG_HID_AUREAL is not set
CONFIG_HID_BELKIN=y
CONFIG_HID_CHERRY=y
CONFIG_HID_CHICONY=y
CONFIG_HID_CYPRESS=y
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_EMS_FF is not set
CONFIG_HID_EZKEY=y
# CONFIG_HID_HOLTEK is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_UCLOGIC is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_TWINHAN is not set
CONFIG_HID_KENSINGTON=y
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO_TPKBD is not set
CONFIG_HID_LOGITECH=y
# CONFIG_HID_LOGITECH_DJ is not set
# CONFIG_LOGITECH_FF is not set
# CONFIG_LOGIRUMBLEPAD2_FF is not set
# CONFIG_LOGIG940_FF is not set
# CONFIG_LOGIWHEELS_FF is not set
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NTRIG is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_ROCCAT is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SAMSUNG is not set
# CONFIG_HID_SONY is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set

#
# USB HID support
#
CONFIG_USB_HID=y
# CONFIG_HID_PID is not set
# CONFIG_USB_HIDDEV is not set
# CONFIG_USB_ARCH_HAS_OHCI is not set
# CONFIG_USB_ARCH_HAS_EHCI is not set
# CONFIG_USB_ARCH_HAS_XHCI is not set
CONFIG_USB_SUPPORT=y
CONFIG_USB_COMMON=y
CONFIG_USB_ARCH_HAS_HCD=y
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y

#
# Miscellaneous USB options
#
# CONFIG_USB_DYNAMIC_MINORS is not set
# CONFIG_USB_MON is not set
# CONFIG_USB_WUSB_CBAF is not set

#
# USB Host Controller Drivers
#
# CONFIG_USB_C67X00_HCD is not set
CONFIG_USB_EHCI_ROOT_HUB_TT=y
CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_OXU210HP_HCD is not set
# CONFIG_USB_ISP116X_HCD is not set
# CONFIG_USB_ISP1760_HCD is not set
# CONFIG_USB_ISP1362_HCD is not set
# CONFIG_USB_SL811_HCD is not set
# CONFIG_USB_R8A66597_HCD is not set
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_HOST=y
# CONFIG_USB_CHIPIDEA_DEBUG is not set

#
# USB Device Class drivers
#
CONFIG_USB_ACM=y
# CONFIG_USB_PRINTER is not set
# CONFIG_USB_WDM is not set
# CONFIG_USB_TMC is not set

#
# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
#

#
# also be needed; see USB_STORAGE Help for more info
#
# CONFIG_USB_LIBUSUAL is not set

#
# USB Imaging devices
#
# CONFIG_USB_MDC800 is not set

#
# USB port drivers
#
CONFIG_USB_SERIAL=y
# CONFIG_USB_SERIAL_CONSOLE is not set
# CONFIG_USB_EZUSB is not set
CONFIG_USB_SERIAL_GENERIC=y
# CONFIG_USB_SERIAL_AIRCABLE is not set
# CONFIG_USB_SERIAL_ARK3116 is not set
# CONFIG_USB_SERIAL_BELKIN is not set
# CONFIG_USB_SERIAL_CH341 is not set
# CONFIG_USB_SERIAL_WHITEHEAT is not set
# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
# CONFIG_USB_SERIAL_CP210X is not set
# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
# CONFIG_USB_SERIAL_EMPEG is not set
# CONFIG_USB_SERIAL_FTDI_SIO is not set
# CONFIG_USB_SERIAL_FUNSOFT is not set
# CONFIG_USB_SERIAL_VISOR is not set
# CONFIG_USB_SERIAL_IPAQ is not set
# CONFIG_USB_SERIAL_IR is not set
# CONFIG_USB_SERIAL_EDGEPORT is not set
# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
# CONFIG_USB_SERIAL_F81232 is not set
# CONFIG_USB_SERIAL_GARMIN is not set
# CONFIG_USB_SERIAL_IPW is not set
# CONFIG_USB_SERIAL_IUU is not set
# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
# CONFIG_USB_SERIAL_KEYSPAN is not set
# CONFIG_USB_SERIAL_KLSI is not set
# CONFIG_USB_SERIAL_KOBIL_SCT is not set
# CONFIG_USB_SERIAL_MCT_U232 is not set
# CONFIG_USB_SERIAL_METRO is not set
# CONFIG_USB_SERIAL_MOS7720 is not set
# CONFIG_USB_SERIAL_MOS7840 is not set
# CONFIG_USB_SERIAL_MOTOROLA is not set
# CONFIG_USB_SERIAL_NAVMAN is not set
# CONFIG_USB_SERIAL_PL2303 is not set
# CONFIG_USB_SERIAL_OTI6858 is not set
# CONFIG_USB_SERIAL_QCAUX is not set
# CONFIG_USB_SERIAL_QUALCOMM is not set
# CONFIG_USB_SERIAL_SPCP8X5 is not set
# CONFIG_USB_SERIAL_HP4X is not set
# CONFIG_USB_SERIAL_SAFE is not set
# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
CONFIG_USB_SERIAL_SIERRAWIRELESS=y
# CONFIG_USB_SERIAL_SYMBOL is not set
# CONFIG_USB_SERIAL_TI is not set
# CONFIG_USB_SERIAL_CYBERJACK is not set
# CONFIG_USB_SERIAL_XIRCOM is not set
CONFIG_USB_SERIAL_WWAN=y
CONFIG_USB_SERIAL_OPTION=y
# CONFIG_USB_SERIAL_OMNINET is not set
# CONFIG_USB_SERIAL_OPTICON is not set
# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
# CONFIG_USB_SERIAL_ZIO is not set
# CONFIG_USB_SERIAL_SSU100 is not set
# CONFIG_USB_SERIAL_QT2 is not set
# CONFIG_USB_SERIAL_DEBUG is not set

#
# USB Miscellaneous drivers
#
# CONFIG_USB_EMI62 is not set
# CONFIG_USB_EMI26 is not set
# CONFIG_USB_ADUTUX is not set
# CONFIG_USB_SEVSEG is not set
# CONFIG_USB_RIO500 is not set
# CONFIG_USB_LEGOTOWER is not set
# CONFIG_USB_LCD is not set
# CONFIG_USB_LED is not set
# CONFIG_USB_CYPRESS_CY7C63 is not set
# CONFIG_USB_CYTHERM is not set
# CONFIG_USB_IDMOUSE is not set
# CONFIG_USB_FTDI_ELAN is not set
# CONFIG_USB_APPLEDISPLAY is not set
# CONFIG_USB_LD is not set
# CONFIG_USB_TRANCEVIBRATOR is not set
# CONFIG_USB_IOWARRIOR is not set
# CONFIG_USB_TEST is not set
# CONFIG_USB_ISIGHTFW is not set
# CONFIG_USB_YUREX is not set

#
# USB Physical Layer drivers
#
# CONFIG_USB_ISP1301 is not set
# CONFIG_USB_GADGET is not set

#
# OTG and related infrastructure
#
CONFIG_USB_OTG_UTILS=y
# CONFIG_USB_GPIO_VBUS is not set
# CONFIG_USB_ULPI is not set
# CONFIG_NOP_USB_XCEIV is not set
CONFIG_USB_MXS_PHY=y
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
CONFIG_LEDS_GPIO_REGISTER=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y

#
# LED drivers
#
# CONFIG_LEDS_LM3530 is not set
# CONFIG_LEDS_PCA9532 is not set
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_LP3944 is not set
# CONFIG_LEDS_LP5521 is not set
# CONFIG_LEDS_LP5523 is not set
# CONFIG_LEDS_PCA955X is not set
# CONFIG_LEDS_PCA9633 is not set
# CONFIG_LEDS_PWM is not set
CONFIG_LEDS_REGULATOR=y
# CONFIG_LEDS_BD2802 is not set
# CONFIG_LEDS_LT3593 is not set
# CONFIG_LEDS_RENESAS_TPU is not set
# CONFIG_LEDS_TCA6507 is not set
# CONFIG_LEDS_LM3556 is not set
# CONFIG_LEDS_OT200 is not set
# CONFIG_LEDS_BLINKM is not set
CONFIG_LEDS_TRIGGERS=y

#
# LED Triggers
#
CONFIG_LEDS_TRIGGER_TIMER=y
# CONFIG_LEDS_TRIGGER_ONESHOT is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y

#
# iptables trigger is under Netfilter config (LED target)
#
CONFIG_LEDS_TRIGGER_TRANSIENT=y
# CONFIG_ACCESSIBILITY is not set
# CONFIG_EDAC is not set
CONFIG_RTC_LIB=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_HCTOSYS=y
CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
# CONFIG_RTC_DEBUG is not set

#
# RTC interfaces
#
CONFIG_RTC_INTF_SYSFS=y
CONFIG_RTC_INTF_PROC=y
CONFIG_RTC_INTF_DEV=y
# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
# CONFIG_RTC_DRV_TEST is not set

#
# I2C RTC drivers
#
CONFIG_RTC_DRV_DS1307=m
# CONFIG_RTC_DRV_DS1374 is not set
# CONFIG_RTC_DRV_DS1672 is not set
# CONFIG_RTC_DRV_DS3232 is not set
# CONFIG_RTC_DRV_MAX6900 is not set
# CONFIG_RTC_DRV_RS5C372 is not set
# CONFIG_RTC_DRV_ISL1208 is not set
# CONFIG_RTC_DRV_ISL12022 is not set
# CONFIG_RTC_DRV_X1205 is not set
# CONFIG_RTC_DRV_PCF8563 is not set
# CONFIG_RTC_DRV_PCF8583 is not set
# CONFIG_RTC_DRV_M41T80 is not set
# CONFIG_RTC_DRV_BQ32K is not set
# CONFIG_RTC_DRV_S35390A is not set
# CONFIG_RTC_DRV_FM3130 is not set
# CONFIG_RTC_DRV_RX8581 is not set
# CONFIG_RTC_DRV_RX8025 is not set
# CONFIG_RTC_DRV_EM3027 is not set
# CONFIG_RTC_DRV_RV3029C2 is not set

#
# SPI RTC drivers
#

#
# Platform RTC drivers
#
# CONFIG_RTC_DRV_CMOS is not set
# CONFIG_RTC_DRV_DS1286 is not set
# CONFIG_RTC_DRV_DS1511 is not set
# CONFIG_RTC_DRV_DS1553 is not set
# CONFIG_RTC_DRV_DS1742 is not set
# CONFIG_RTC_DRV_STK17TA8 is not set
# CONFIG_RTC_DRV_M48T86 is not set
# CONFIG_RTC_DRV_M48T35 is not set
# CONFIG_RTC_DRV_M48T59 is not set
# CONFIG_RTC_DRV_MSM6242 is not set
# CONFIG_RTC_DRV_BQ4802 is not set
# CONFIG_RTC_DRV_RP5C01 is not set
# CONFIG_RTC_DRV_V3020 is not set

#
# on-CPU RTC drivers
#
# CONFIG_RTC_DRV_PL030 is not set
# CONFIG_RTC_DRV_PL031 is not set
# CONFIG_RTC_DRV_STMP is not set
CONFIG_DMADEVICES=y
# CONFIG_DMADEVICES_DEBUG is not set

#
# DMA Devices
#
# CONFIG_AMBA_PL08X is not set
# CONFIG_DW_DMAC is not set
# CONFIG_TIMB_DMA is not set
# CONFIG_PL330_DMA is not set
CONFIG_MXS_DMA=y
CONFIG_DMA_ENGINE=y

#
# DMA Clients
#
# CONFIG_NET_DMA is not set
# CONFIG_ASYNC_TX_DMA is not set
# CONFIG_DMATEST is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set

#
# Virtio drivers
#
# CONFIG_VIRTIO_BALLOON is not set
# CONFIG_VIRTIO_MMIO is not set

#
# Microsoft Hyper-V guest support
#
# CONFIG_STAGING is not set
CONFIG_CLKDEV_LOOKUP=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_COMMON_CLK=y

#
# Common Clock Framework
#
# CONFIG_COMMON_CLK_DEBUG is not set

#
# Hardware Spinlock drivers
#
CONFIG_CLKSRC_MMIO=y
CONFIG_IOMMU_SUPPORT=y
CONFIG_OF_IOMMU=y

#
# Remoteproc drivers (EXPERIMENTAL)
#

#
# Rpmsg drivers (EXPERIMENTAL)
#
# CONFIG_VIRT_DRIVERS is not set
# CONFIG_PM_DEVFREQ is not set
# CONFIG_EXTCON is not set
# CONFIG_MEMORY is not set
# CONFIG_IIO is not set
# CONFIG_PWM is not set
CONFIG_GNET_DRIVER_CLASS=y
CONFIG_GNET_PROC=y
CONFIG_GNET_PROC_DEBUG=y
CONFIG_GNET_ZIGBEE_DRIVER=y
CONFIG_GNET_ZIGBEE_DEBUG=y
CONFIG_GNET_OTP=y

#
# File systems
#
# CONFIG_EXT2_FS is not set
CONFIG_EXT3_FS=y
CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
CONFIG_EXT3_FS_XATTR=y
# CONFIG_EXT3_FS_POSIX_ACL is not set
# CONFIG_EXT3_FS_SECURITY is not set
# CONFIG_EXT4_FS is not set
CONFIG_JBD=y
# CONFIG_JBD_DEBUG is not set
CONFIG_FS_MBCACHE=y
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_BTRFS_FS is not set
# CONFIG_NILFS2_FS is not set
CONFIG_FS_POSIX_ACL=y
CONFIG_FILE_LOCKING=y
CONFIG_FSNOTIFY=y
CONFIG_DNOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_FANOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_QUOTACTL is not set
# CONFIG_AUTOFS4_FS is not set
CONFIG_FUSE_FS=y
CONFIG_CUSE=y
CONFIG_GENERIC_ACL=y

#
# Caches
#
CONFIG_FSCACHE=m
CONFIG_FSCACHE_STATS=y
# CONFIG_FSCACHE_HISTOGRAM is not set
# CONFIG_FSCACHE_DEBUG is not set
# CONFIG_FSCACHE_OBJECT_LIST is not set
CONFIG_CACHEFILES=m
# CONFIG_CACHEFILES_DEBUG is not set
# CONFIG_CACHEFILES_HISTOGRAM is not set

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_VMCORE=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_TMPFS_XATTR=y
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS2_FS is not set
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_LOGFS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_PSTORE is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V2 is not set
CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
# CONFIG_NFS_SWAP is not set
# CONFIG_NFS_V4_1 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
CONFIG_NFS_USE_KERNEL_DNS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_LOCKD_V4=y
CONFIG_NFS_ACL_SUPPORT=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
CONFIG_SUNRPC_GSS=y
# CONFIG_SUNRPC_DEBUG is not set
# CONFIG_CEPH_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
CONFIG_NLS=y
CONFIG_NLS_DEFAULT="iso8859-1"
# CONFIG_NLS_CODEPAGE_437 is not set
# CONFIG_NLS_CODEPAGE_737 is not set
# CONFIG_NLS_CODEPAGE_775 is not set
# CONFIG_NLS_CODEPAGE_850 is not set
# CONFIG_NLS_CODEPAGE_852 is not set
# CONFIG_NLS_CODEPAGE_855 is not set
# CONFIG_NLS_CODEPAGE_857 is not set
# CONFIG_NLS_CODEPAGE_860 is not set
# CONFIG_NLS_CODEPAGE_861 is not set
# CONFIG_NLS_CODEPAGE_862 is not set
# CONFIG_NLS_CODEPAGE_863 is not set
# CONFIG_NLS_CODEPAGE_864 is not set
# CONFIG_NLS_CODEPAGE_865 is not set
# CONFIG_NLS_CODEPAGE_866 is not set
# CONFIG_NLS_CODEPAGE_869 is not set
# CONFIG_NLS_CODEPAGE_936 is not set
# CONFIG_NLS_CODEPAGE_950 is not set
# CONFIG_NLS_CODEPAGE_932 is not set
# CONFIG_NLS_CODEPAGE_949 is not set
# CONFIG_NLS_CODEPAGE_874 is not set
# CONFIG_NLS_ISO8859_8 is not set
# CONFIG_NLS_CODEPAGE_1250 is not set
# CONFIG_NLS_CODEPAGE_1251 is not set
# CONFIG_NLS_ASCII is not set
# CONFIG_NLS_ISO8859_1 is not set
# CONFIG_NLS_ISO8859_2 is not set
# CONFIG_NLS_ISO8859_3 is not set
# CONFIG_NLS_ISO8859_4 is not set
# CONFIG_NLS_ISO8859_5 is not set
# CONFIG_NLS_ISO8859_6 is not set
# CONFIG_NLS_ISO8859_7 is not set
# CONFIG_NLS_ISO8859_9 is not set
# CONFIG_NLS_ISO8859_13 is not set
# CONFIG_NLS_ISO8859_14 is not set
# CONFIG_NLS_ISO8859_15 is not set
# CONFIG_NLS_KOI8_R is not set
# CONFIG_NLS_KOI8_U is not set
# CONFIG_NLS_MAC_ROMAN is not set
# CONFIG_NLS_MAC_CELTIC is not set
# CONFIG_NLS_MAC_CENTEURO is not set
# CONFIG_NLS_MAC_CROATIAN is not set
# CONFIG_NLS_MAC_CYRILLIC is not set
# CONFIG_NLS_MAC_GAELIC is not set
# CONFIG_NLS_MAC_GREEK is not set
# CONFIG_NLS_MAC_ICELAND is not set
# CONFIG_NLS_MAC_INUIT is not set
# CONFIG_NLS_MAC_ROMANIAN is not set
# CONFIG_NLS_MAC_TURKISH is not set
# CONFIG_NLS_UTF8 is not set

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=2048
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
CONFIG_DEBUG_FS=y
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_SECTION_MISMATCH is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_HARDLOCKUP_DETECTOR is not set
# CONFIG_PANIC_ON_OOPS is not set
CONFIG_PANIC_ON_OOPS_VALUE=0
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
# CONFIG_SPARSE_RCU_POINTER is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_LKDTM is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
CONFIG_DYNAMIC_DEBUG=y
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_ATOMIC64_SELFTEST is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_TEST_KSTRTOX is not set
# CONFIG_STRICT_DEVMEM is not set
CONFIG_ARM_UNWIND=y
CONFIG_DEBUG_USER=y
# CONFIG_OC_ETM is not set

#
# Security options
#
CONFIG_KEYS=y
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEYS_DEBUG_PROC_KEYS=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
CONFIG_SECURITY_NETWORK_XFRM=y
CONFIG_SECURITY_PATH=y
CONFIG_LSM_MMAP_MIN_ADDR=32768
CONFIG_SECURITY_SELINUX=y
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
CONFIG_SECURITY_SELINUX_DISABLE=y
CONFIG_SECURITY_SELINUX_DEVELOP=y
CONFIG_SECURITY_SELINUX_AVC_STATS=y
CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
# CONFIG_SECURITY_YAMA is not set
# CONFIG_IMA is not set
# CONFIG_EVM is not set
CONFIG_DEFAULT_SECURITY_SELINUX=y
# CONFIG_DEFAULT_SECURITY_DAC is not set
CONFIG_DEFAULT_SECURITY="selinux"
CONFIG_CRYPTO=y

#
# Crypto core or helper
#
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_BLKCIPHER=y
CONFIG_CRYPTO_BLKCIPHER2=y
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_PCOMP2=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
# CONFIG_CRYPTO_GF128MUL is not set
# CONFIG_CRYPTO_NULL is not set
CONFIG_CRYPTO_WORKQUEUE=y
# CONFIG_CRYPTO_CRYPTD is not set
CONFIG_CRYPTO_AUTHENC=y
# CONFIG_CRYPTO_TEST is not set

#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set

#
# Block modes
#
CONFIG_CRYPTO_CBC=y
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
CONFIG_CRYPTO_ECB=m
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_XTS is not set

#
# Hash modes
#
CONFIG_CRYPTO_HMAC=y
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_VMAC is not set

#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_GHASH is not set
# CONFIG_CRYPTO_MD4 is not set
CONFIG_CRYPTO_MD5=y
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set

#
# Ciphers
#
CONFIG_CRYPTO_AES=y
# CONFIG_CRYPTO_ANUBIS is not set
CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
CONFIG_CRYPTO_DES=y
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set

#
# Compression
#
CONFIG_CRYPTO_DEFLATE=y
# CONFIG_CRYPTO_ZLIB is not set
CONFIG_CRYPTO_LZO=y

#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_BITREVERSE=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_IO=y
CONFIG_STMP_DEVICE=y
CONFIG_CRC_CCITT=m
CONFIG_CRC16=y
# CONFIG_CRC_T10DIF is not set
CONFIG_CRC_ITU_T=m
CONFIG_CRC32=y
# CONFIG_CRC32_SELFTEST is not set
CONFIG_CRC32_SLICEBY8=y
# CONFIG_CRC32_SLICEBY4 is not set
# CONFIG_CRC32_SARWATE is not set
# CONFIG_CRC32_BIT is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
# CONFIG_CRC8 is not set
CONFIG_AUDIT_GENERIC=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
# CONFIG_XZ_DEC is not set
# CONFIG_XZ_DEC_BCJ is not set
CONFIG_BCH=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_DQL=y
CONFIG_NLATTR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
# CONFIG_AVERAGE is not set
# CONFIG_CORDIC is not set
# CONFIG_DDR is not set

From paulmck at linux.vnet.ibm.com  Tue Sep  4 15:54:42 2012
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Tue, 4 Sep 2012 12:54:42 -0700
Subject: RCU warning during UBI file system mount
In-Reply-To: <50462190.7090702@grid-net.com>
References: <5042EC5D.1010207@grid-net.com>
 <1346744796.12610.6.camel@sauron.fi.intel.com>
 <20120904144813.GC2593@linux.vnet.ibm.com>
 <50462190.7090702@grid-net.com>
Message-ID: <20120904195442.GF2593@linux.vnet.ibm.com>

On Tue, Sep 04, 2012 at 08:43:12AM -0700, Subodh Nijsure wrote:
> Hello Paul,
> 
> On 09/04/2012 07:48 AM, Paul E. McKenney wrote:
> >On Tue, Sep 04, 2012 at 10:46:36AM +0300, Artem Bityutskiy wrote:
> >>Let's CC LKML and Paul.
> >>
> >>On Sat, 2012-09-01 at 22:19 -0700, Subodh Nijsure wrote:
> >>>Hello,
> >>>
> >>>I am running 3.6-rc4 kernel on my MX28 based board and every time I
> >>>mount UBI file system I see following warning.
> >>>Anybody else seen this errors, particularly those running it on MXS
> >>>platform?
> >>>
> >>>I haven't debugged RCU warnings before any clues as to what is the
> >>>source of this warning is, should I be looking at
> >>>start_dma_without_bch_irq() code? Would appreciate any pointers in
> >>>fixing this...
> >RCU is upset because what it believes to be a non-idle task is telling
> >RCU that it is entering the idle loop.
> >
> >Does the MX28 kernel have any unusual idle features?  (This is a subarch
> >of ARM, correct?)
> >
> >							Thanx, Paul
> 
> MX28 is ARM device. I removed following from my config and these
> warnings went away.
> 
> CONFIG_CPU_IDLE=y
> CONFIG_CPU_IDLE_GOV_LADDER=y
> CONFIG_CPU_IDLE_GOV_MENU=y
> 
> I have attached the kernel configuration file I used.
> 
> It doesn't affect specific hw I am working with as device is not
> required to enter idle mode.
> I am Cc-ing linux-arm folks,  in case someone on arm platform
> requires CPU idele &, RCU to work.

I do look forward to some linux-arm enlightenment on this situation.  ;-)

							Thanx, Paul

> -Subodh
> >>>[    4.280000] WARNING: at /opt/git/kernel-mainline/kernel/rcutiny.c:75
> >>>rcu_idle_enter_common.clone.7+0x90/0xac()
> >>>[    4.280000] Current pid: 1 comm: swapper / Idle pid: 0 comm: swapper
> >>>[    4.280000] Modules linked in:
> >>>[    4.280000] [<c0014eec>] (unwind_backtrace+0x0/0x130) from
> >>>[<c001dd94>] (warn_slowpath_common+0x4c/0x64)
> >>>[    4.280000] [<c001dd94>] (warn_slowpath_common+0x4c/0x64) from
> >>>[<c001de40>] (warn_slowpath_fmt+0x30/0x40)
> >>>[    4.280000] [<c001de40>] (warn_slowpath_fmt+0x30/0x40) from
> >>>[<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
> >>>[    4.280000] [<c0061618>] (rcu_idle_enter_common.clone.7+0x90/0xac)
> >>>from [<c0061670>] (rcu_irq_exit+0x3c/0x78)
> >>>[    4.280000] [<c0061670>] (rcu_irq_exit+0x3c/0x78) from [<c000fe90>]
> >>>(handle_IRQ+0x34/0x84)
> >>>[    4.280000] [<c000fe90>] (handle_IRQ+0x34/0x84) from [<c000ec34>]
> >>>(__irq_svc+0x34/0x58)
> >>>[    4.280000] [<c000ec34>] (__irq_svc+0x34/0x58) from [<c0394c4c>]
> >>>(schedule_timeout+0xdc/0x16c)
> >>>[    4.280000] [<c0394c4c>] (schedule_timeout+0xdc/0x16c) from
> >>>[<c0395f34>] (wait_for_common+0xb4/0x160)
> >>>[    4.280000] [<c0395f34>] (wait_for_common+0xb4/0x160) from
> >>>[<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8)
> >>>[    4.280000] [<c02579d0>] (start_dma_without_bch_irq+0x6c/0xa8) from
> >>>[<c0258660>] (gpmi_send_command+0x120/0x154)
> >>>[    4.280000] [<c0258660>] (gpmi_send_command+0x120/0x154) from
> >>>[<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c)
> >>>[    4.280000] [<c0256fb4>] (gpmi_cmd_ctrl+0x44/0x6c) from [<c024f8e0>]
> >>>(nand_command_lp+0xe8/0x270)
> >>>[    4.280000] [<c024f8e0>] (nand_command_lp+0xe8/0x270) from
> >>>[<c0251e00>] (nand_do_read_ops+0x124/0x444)
> >>>[    4.280000] [<c0251e00>] (nand_do_read_ops+0x124/0x444) from
> >>>[<c0252558>] (nand_read+0x54/0x78)
> >>>[    4.280000] [<c0252558>] (nand_read+0x54/0x78) from [<c02499a4>]
> >>>(part_read+0x48/0x80)
> >>>[    4.280000] [<c02499a4>] (part_read+0x48/0x80) from [<c0246910>]
> >>>(mtd_read+0x88/0xb4)
> >>>[    4.280000] [<c0246910>] (mtd_read+0x88/0xb4) from [<c026b188>]
> >>>(ubi_io_read+0xb0/0x3e8)
> >>>[    4.280000] [<c026b188>] (ubi_io_read+0xb0/0x3e8) from [<c026740c>]
> >>>(ubi_eba_read_leb+0x198/0x4bc)
> >>>[    4.280000] [<c026740c>] (ubi_eba_read_leb+0x198/0x4bc) from
> >>>[<c0266800>] (ubi_leb_read+0xf4/0x16c)
> >>>[    4.280000] [<c0266800>] (ubi_leb_read+0xf4/0x16c) from [<c0155550>]
> >>>(ubifs_leb_read+0x24/0x88)
> >>>[    4.280000] [<c0155550>] (ubifs_leb_read+0x24/0x88) from [<c01572f8>]
> >>>(ubifs_read_node+0xa8/0x2e4)
> >>>[    4.280000] [<c01572f8>] (ubifs_read_node+0xa8/0x2e4) from
> >>>[<c0153c50>] (ubifs_read_sb_node+0x54/0x78)
> >>>[    4.280000] [<c0153c50>] (ubifs_read_sb_node+0x54/0x78) from
> >>>[<c0154940>] (ubifs_read_superblock+0xc8c/0x133c)
> >>>[    4.280000] [<c0154940>] (ubifs_read_superblock+0xc8c/0x133c) from
> >>>[<c01520ac>] (ubifs_mount+0x73c/0x1bc0)
> >>>[    4.280000] [<c01520ac>] (ubifs_mount+0x73c/0x1bc0) from [<c00a49ec>]
> >>>(mount_fs+0x44/0x184)
> >>>[    4.280000] [<c00a49ec>] (mount_fs+0x44/0x184) from [<c00baf90>]
> >>>(vfs_kern_mount+0x4c/0xc0)
> >>>[    4.280000] [<c00baf90>] (vfs_kern_mount+0x4c/0xc0) from [<c00bb1a0>]
> >>>(do_kern_mount+0x34/0xd0)
> >>>[    4.280000] [<c00bb1a0>] (do_kern_mount+0x34/0xd0) from [<c00bc93c>]
> >>>(do_mount+0x15c/0x73c)
> >>>[    4.280000] [<c00bc93c>] (do_mount+0x15c/0x73c) from [<c00bcfa0>]
> >>>(sys_mount+0x84/0xc4)
> >>>[    4.280000] [<c00bcfa0>] (sys_mount+0x84/0xc4) from [<c04e4a04>]
> >>>(do_mount_root+0x24/0xb0)
> >>>[    4.280000] [<c04e4a04>] (do_mount_root+0x24/0xb0) from [<c04e4b78>]
> >>>(mount_block_root+0xe8/0x214)
> >>>[    4.280000] [<c04e4b78>] (mount_block_root+0xe8/0x214) from
> >>>[<c04e4e28>] (prepare_namespace+0x8c/0x180)
> >>>[    4.280000] [<c04e4e28>] (prepare_namespace+0x8c/0x180) from
> >>>[<c04e4894>] (kernel_init+0x16c/0x1b4)
> >>>[    4.280000] [<c04e4894>] (kernel_init+0x16c/0x1b4) from [<c000ff70>]
> >>>(kernel_thread_exit+0x0/0x8)
> >>>[    4.280000] ---[ end trace 4d36b722759fdc4f ]---
> >>>[    4.950000] UBIFS DBG (pid 58): ubifs_bg_thread: background thread
> >>>"ubifs_bgt0_0" started, PID 58
> >>>
> >>>-Subodh
> >>>
> >>>______________________________________________________
> >>>Linux MTD discussion mailing list
> >>>http://lists.infradead.org/mailman/listinfo/linux-mtd/
> >>-- 
> >>Best Regards,
> >>Artem Bityutskiy
> >
> 

> #
> # Automatically generated file; DO NOT EDIT.
> # Linux/arm 3.6.0-rc4 Kernel Configuration
> #
> CONFIG_ARM=y
> CONFIG_HAVE_PWM=y
> CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> CONFIG_GENERIC_GPIO=y
> CONFIG_HAVE_PROC_CPU=y
> CONFIG_STACKTRACE_SUPPORT=y
> CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> CONFIG_LOCKDEP_SUPPORT=y
> CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> CONFIG_RWSEM_GENERIC_SPINLOCK=y
> CONFIG_GENERIC_HWEIGHT=y
> CONFIG_GENERIC_CALIBRATE_DELAY=y
> CONFIG_NEED_DMA_MAP_STATE=y
> CONFIG_VECTORS_BASE=0xffff0000
> CONFIG_ARM_PATCH_PHYS_VIRT=y
> CONFIG_GENERIC_BUG=y
> CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> CONFIG_HAVE_IRQ_WORK=y
> CONFIG_IRQ_WORK=y
> 
> #
> # General setup
> #
> CONFIG_EXPERIMENTAL=y
> CONFIG_BROKEN_ON_SMP=y
> CONFIG_INIT_ENV_ARG_LIMIT=32
> CONFIG_CROSS_COMPILE="/opt/tools/cs-2009q1/bin/arm-none-linux-gnueabi-"
> CONFIG_LOCALVERSION=""
> CONFIG_LOCALVERSION_AUTO=y
> CONFIG_HAVE_KERNEL_GZIP=y
> CONFIG_HAVE_KERNEL_LZMA=y
> CONFIG_HAVE_KERNEL_XZ=y
> CONFIG_HAVE_KERNEL_LZO=y
> CONFIG_KERNEL_GZIP=y
> # CONFIG_KERNEL_LZMA is not set
> # CONFIG_KERNEL_XZ is not set
> # CONFIG_KERNEL_LZO is not set
> CONFIG_DEFAULT_HOSTNAME="(none)"
> CONFIG_SWAP=y
> CONFIG_SYSVIPC=y
> CONFIG_SYSVIPC_SYSCTL=y
> # CONFIG_POSIX_MQUEUE is not set
> # CONFIG_BSD_PROCESS_ACCT is not set
> # CONFIG_FHANDLE is not set
> # CONFIG_TASKSTATS is not set
> CONFIG_AUDIT=y
> CONFIG_AUDIT_LOGINUID_IMMUTABLE=y
> CONFIG_HAVE_GENERIC_HARDIRQS=y
> 
> #
> # IRQ subsystem
> #
> CONFIG_GENERIC_HARDIRQS=y
> CONFIG_GENERIC_IRQ_PROBE=y
> CONFIG_GENERIC_IRQ_SHOW=y
> CONFIG_HARDIRQS_SW_RESEND=y
> CONFIG_GENERIC_IRQ_CHIP=y
> CONFIG_IRQ_DOMAIN=y
> # CONFIG_IRQ_DOMAIN_DEBUG is not set
> CONFIG_KTIME_SCALAR=y
> CONFIG_GENERIC_CLOCKEVENTS=y
> CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> 
> #
> # Timers subsystem
> #
> CONFIG_TICK_ONESHOT=y
> CONFIG_NO_HZ=y
> CONFIG_HIGH_RES_TIMERS=y
> 
> #
> # RCU Subsystem
> #
> CONFIG_TINY_RCU=y
> # CONFIG_PREEMPT_RCU is not set
> # CONFIG_TREE_RCU_TRACE is not set
> CONFIG_IKCONFIG=y
> CONFIG_IKCONFIG_PROC=y
> CONFIG_LOG_BUF_SHIFT=17
> # CONFIG_CGROUPS is not set
> # CONFIG_CHECKPOINT_RESTORE is not set
> CONFIG_NAMESPACES=y
> # CONFIG_UTS_NS is not set
> # CONFIG_IPC_NS is not set
> # CONFIG_PID_NS is not set
> # CONFIG_NET_NS is not set
> # CONFIG_SCHED_AUTOGROUP is not set
> # CONFIG_SYSFS_DEPRECATED is not set
> CONFIG_RELAY=y
> # CONFIG_BLK_DEV_INITRD is not set
> # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> CONFIG_SYSCTL=y
> CONFIG_ANON_INODES=y
> # CONFIG_EXPERT is not set
> CONFIG_UID16=y
> # CONFIG_SYSCTL_SYSCALL is not set
> CONFIG_KALLSYMS=y
> CONFIG_HOTPLUG=y
> CONFIG_PRINTK=y
> CONFIG_BUG=y
> CONFIG_ELF_CORE=y
> CONFIG_BASE_FULL=y
> CONFIG_FUTEX=y
> CONFIG_EPOLL=y
> CONFIG_SIGNALFD=y
> CONFIG_TIMERFD=y
> CONFIG_EVENTFD=y
> CONFIG_SHMEM=y
> CONFIG_AIO=y
> # CONFIG_EMBEDDED is not set
> CONFIG_HAVE_PERF_EVENTS=y
> CONFIG_PERF_USE_VMALLOC=y
> 
> #
> # Kernel Performance Events And Counters
> #
> CONFIG_PERF_EVENTS=y
> CONFIG_VM_EVENT_COUNTERS=y
> CONFIG_SLUB_DEBUG=y
> # CONFIG_COMPAT_BRK is not set
> # CONFIG_SLAB is not set
> CONFIG_SLUB=y
> # CONFIG_PROFILING is not set
> CONFIG_HAVE_OPROFILE=y
> # CONFIG_KPROBES is not set
> # CONFIG_JUMP_LABEL is not set
> CONFIG_HAVE_KPROBES=y
> CONFIG_HAVE_KRETPROBES=y
> CONFIG_HAVE_ARCH_TRACEHOOK=y
> CONFIG_HAVE_DMA_ATTRS=y
> CONFIG_GENERIC_SMP_IDLE_THREAD=y
> CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
> CONFIG_HAVE_CLK=y
> CONFIG_HAVE_DMA_API_DEBUG=y
> CONFIG_HAVE_ARCH_JUMP_LABEL=y
> CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
> 
> #
> # GCOV-based kernel profiling
> #
> # CONFIG_GCOV_KERNEL is not set
> CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> CONFIG_SLABINFO=y
> CONFIG_RT_MUTEXES=y
> CONFIG_BASE_SMALL=0
> CONFIG_MODULES=y
> CONFIG_MODULE_FORCE_LOAD=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_MODULE_FORCE_UNLOAD=y
> CONFIG_MODVERSIONS=y
> # CONFIG_MODULE_SRCVERSION_ALL is not set
> CONFIG_BLOCK=y
> # CONFIG_LBDAF is not set
> # CONFIG_BLK_DEV_BSG is not set
> # CONFIG_BLK_DEV_BSGLIB is not set
> # CONFIG_BLK_DEV_INTEGRITY is not set
> 
> #
> # Partition Types
> #
> # CONFIG_PARTITION_ADVANCED is not set
> CONFIG_MSDOS_PARTITION=y
> 
> #
> # IO Schedulers
> #
> CONFIG_IOSCHED_NOOP=y
> # CONFIG_IOSCHED_DEADLINE is not set
> # CONFIG_IOSCHED_CFQ is not set
> CONFIG_DEFAULT_NOOP=y
> CONFIG_DEFAULT_IOSCHED="noop"
> # CONFIG_INLINE_SPIN_TRYLOCK is not set
> # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> # CONFIG_INLINE_SPIN_LOCK is not set
> # CONFIG_INLINE_SPIN_LOCK_BH is not set
> # CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> # CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
> # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> # CONFIG_INLINE_READ_TRYLOCK is not set
> # CONFIG_INLINE_READ_LOCK is not set
> # CONFIG_INLINE_READ_LOCK_BH is not set
> # CONFIG_INLINE_READ_LOCK_IRQ is not set
> # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> CONFIG_INLINE_READ_UNLOCK=y
> # CONFIG_INLINE_READ_UNLOCK_BH is not set
> CONFIG_INLINE_READ_UNLOCK_IRQ=y
> # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> # CONFIG_INLINE_WRITE_TRYLOCK is not set
> # CONFIG_INLINE_WRITE_LOCK is not set
> # CONFIG_INLINE_WRITE_LOCK_BH is not set
> # CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> CONFIG_INLINE_WRITE_UNLOCK=y
> # CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
> # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> # CONFIG_MUTEX_SPIN_ON_OWNER is not set
> # CONFIG_FREEZER is not set
> 
> #
> # System Type
> #
> CONFIG_MMU=y
> # CONFIG_ARCH_SOCFPGA is not set
> # CONFIG_ARCH_INTEGRATOR is not set
> # CONFIG_ARCH_REALVIEW is not set
> # CONFIG_ARCH_VERSATILE is not set
> # CONFIG_ARCH_VEXPRESS is not set
> # CONFIG_ARCH_AT91 is not set
> # CONFIG_ARCH_BCMRING is not set
> # CONFIG_ARCH_HIGHBANK is not set
> # CONFIG_ARCH_CLPS711X is not set
> # CONFIG_ARCH_CNS3XXX is not set
> # CONFIG_ARCH_GEMINI is not set
> # CONFIG_ARCH_PRIMA2 is not set
> # CONFIG_ARCH_EBSA110 is not set
> # CONFIG_ARCH_EP93XX is not set
> # CONFIG_ARCH_FOOTBRIDGE is not set
> # CONFIG_ARCH_MXC is not set
> CONFIG_ARCH_MXS=y
> # CONFIG_ARCH_NETX is not set
> # CONFIG_ARCH_H720X is not set
> # CONFIG_ARCH_IOP13XX is not set
> # CONFIG_ARCH_IOP32X is not set
> # CONFIG_ARCH_IOP33X is not set
> # CONFIG_ARCH_IXP4XX is not set
> # CONFIG_ARCH_MVEBU is not set
> # CONFIG_ARCH_DOVE is not set
> # CONFIG_ARCH_KIRKWOOD is not set
> # CONFIG_ARCH_LPC32XX is not set
> # CONFIG_ARCH_MV78XX0 is not set
> # CONFIG_ARCH_ORION5X is not set
> # CONFIG_ARCH_MMP is not set
> # CONFIG_ARCH_KS8695 is not set
> # CONFIG_ARCH_W90X900 is not set
> # CONFIG_ARCH_TEGRA is not set
> # CONFIG_ARCH_PICOXCELL is not set
> # CONFIG_ARCH_PNX4008 is not set
> # CONFIG_ARCH_PXA is not set
> # CONFIG_ARCH_MSM is not set
> # CONFIG_ARCH_SHMOBILE is not set
> # CONFIG_ARCH_RPC is not set
> # CONFIG_ARCH_SA1100 is not set
> # CONFIG_ARCH_S3C24XX is not set
> # CONFIG_ARCH_S3C64XX is not set
> # CONFIG_ARCH_S5P64X0 is not set
> # CONFIG_ARCH_S5PC100 is not set
> # CONFIG_ARCH_S5PV210 is not set
> # CONFIG_ARCH_EXYNOS is not set
> # CONFIG_ARCH_SHARK is not set
> # CONFIG_ARCH_U300 is not set
> # CONFIG_ARCH_U8500 is not set
> # CONFIG_ARCH_NOMADIK is not set
> # CONFIG_ARCH_DAVINCI is not set
> # CONFIG_ARCH_OMAP is not set
> # CONFIG_PLAT_SPEAR is not set
> # CONFIG_ARCH_VT8500 is not set
> # CONFIG_ARCH_ZYNQ is not set
> # CONFIG_GPIO_PCA953X is not set
> CONFIG_MXS_HAVE_AMBA_DUART=y
> CONFIG_MXS_HAVE_PLATFORM_AUART=y
> CONFIG_MXS_HAVE_PLATFORM_FEC=y
> CONFIG_MXS_HAVE_PLATFORM_FLEXCAN=y
> CONFIG_MXS_HAVE_PLATFORM_MXS_I2C=y
> CONFIG_MXS_HAVE_PLATFORM_MXS_MMC=y
> CONFIG_MXS_HAVE_PLATFORM_MXSFB=y
> CONFIG_MXS_HAVE_PLATFORM_MXS_SAIF=y
> CONFIG_MXS_HAVE_PLATFORM_RTC_STMP3XXX=y
> CONFIG_SOC_IMX23=y
> CONFIG_SOC_IMX28=y
> 
> #
> # MXS platforms:
> #
> CONFIG_MACH_MXS_DT=y
> # CONFIG_MACH_STMP378X_DEVB is not set
> # CONFIG_MACH_MX23EVK is not set
> CONFIG_MACH_MX28EVK=y
> # CONFIG_MACH_TX28 is not set
> # CONFIG_MACH_M28EVK is not set
> # CONFIG_MACH_APX4DEVKIT is not set
> 
> #
> # Processor Type
> #
> CONFIG_CPU_ARM926T=y
> CONFIG_CPU_32v5=y
> CONFIG_CPU_ABRT_EV5TJ=y
> CONFIG_CPU_PABRT_LEGACY=y
> CONFIG_CPU_CACHE_VIVT=y
> CONFIG_CPU_COPY_V4WB=y
> CONFIG_CPU_TLB_V4WBI=y
> CONFIG_CPU_CP15=y
> CONFIG_CPU_CP15_MMU=y
> CONFIG_CPU_USE_DOMAINS=y
> 
> #
> # Processor Features
> #
> # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
> CONFIG_ARM_THUMB=y
> # CONFIG_CPU_ICACHE_DISABLE is not set
> # CONFIG_CPU_DCACHE_DISABLE is not set
> # CONFIG_CPU_DCACHE_WRITETHROUGH is not set
> # CONFIG_CPU_CACHE_ROUND_ROBIN is not set
> # CONFIG_CACHE_L2X0 is not set
> CONFIG_ARM_L1_CACHE_SHIFT=5
> CONFIG_ARM_NR_BANKS=8
> 
> #
> # Bus support
> #
> CONFIG_ARM_AMBA=y
> # CONFIG_PCI_SYSCALL is not set
> # CONFIG_ARCH_SUPPORTS_MSI is not set
> # CONFIG_PCCARD is not set
> 
> #
> # Kernel Features
> #
> CONFIG_VMSPLIT_3G=y
> # CONFIG_VMSPLIT_2G is not set
> # CONFIG_VMSPLIT_1G is not set
> CONFIG_PAGE_OFFSET=0xC0000000
> CONFIG_ARCH_NR_GPIO=0
> # CONFIG_PREEMPT_NONE is not set
> CONFIG_PREEMPT_VOLUNTARY=y
> # CONFIG_PREEMPT is not set
> CONFIG_HZ=100
> CONFIG_AEABI=y
> CONFIG_OABI_COMPAT=y
> # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> CONFIG_HAVE_ARCH_PFN_VALID=y
> # CONFIG_HIGHMEM is not set
> CONFIG_SELECT_MEMORY_MODEL=y
> CONFIG_FLATMEM_MANUAL=y
> CONFIG_FLATMEM=y
> CONFIG_FLAT_NODE_MEM_MAP=y
> CONFIG_HAVE_MEMBLOCK=y
> CONFIG_PAGEFLAGS_EXTENDED=y
> CONFIG_SPLIT_PTLOCK_CPUS=999999
> # CONFIG_COMPACTION is not set
> # CONFIG_PHYS_ADDR_T_64BIT is not set
> CONFIG_ZONE_DMA_FLAG=0
> CONFIG_VIRT_TO_BUS=y
> # CONFIG_KSM is not set
> CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
> # CONFIG_CROSS_MEMORY_ATTACH is not set
> CONFIG_NEED_PER_CPU_KM=y
> # CONFIG_CLEANCACHE is not set
> # CONFIG_FRONTSWAP is not set
> CONFIG_FORCE_MAX_ZONEORDER=11
> CONFIG_ALIGNMENT_TRAP=y
> # CONFIG_UACCESS_WITH_MEMCPY is not set
> # CONFIG_SECCOMP is not set
> # CONFIG_CC_STACKPROTECTOR is not set
> # CONFIG_DEPRECATED_PARAM_STRUCT is not set
> 
> #
> # Boot options
> #
> CONFIG_USE_OF=y
> CONFIG_ZBOOT_ROM_TEXT=0
> CONFIG_ZBOOT_ROM_BSS=0
> CONFIG_ARM_APPENDED_DTB=y
> # CONFIG_ARM_ATAG_DTB_COMPAT is not set
> CONFIG_CMDLINE=""
> # CONFIG_XIP_KERNEL is not set
> CONFIG_KEXEC=y
> CONFIG_ATAGS_PROC=y
> CONFIG_CRASH_DUMP=y
> CONFIG_AUTO_ZRELADDR=y
> 
> #
> # CPU Power Management
> #
> # CONFIG_CPU_IDLE is not set
> # CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
> 
> #
> # Floating point emulation
> #
> 
> #
> # At least one emulation must be selected
> #
> CONFIG_FPE_NWFPE=y
> # CONFIG_FPE_NWFPE_XP is not set
> # CONFIG_FPE_FASTFPE is not set
> # CONFIG_VFP is not set
> 
> #
> # Userspace binary formats
> #
> CONFIG_BINFMT_ELF=y
> CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
> CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
> CONFIG_HAVE_AOUT=y
> # CONFIG_BINFMT_AOUT is not set
> # CONFIG_BINFMT_MISC is not set
> 
> #
> # Power management options
> #
> # CONFIG_SUSPEND is not set
> # CONFIG_PM_RUNTIME is not set
> CONFIG_ARCH_HAS_OPP=y
> # CONFIG_PM_OPP is not set
> CONFIG_ARCH_SUSPEND_POSSIBLE=y
> # CONFIG_ARM_CPU_SUSPEND is not set
> CONFIG_NET=y
> 
> #
> # Networking options
> #
> CONFIG_PACKET=y
> CONFIG_UNIX=y
> # CONFIG_UNIX_DIAG is not set
> CONFIG_XFRM=y
> CONFIG_XFRM_ALGO=y
> # CONFIG_XFRM_USER is not set
> # CONFIG_XFRM_SUB_POLICY is not set
> # CONFIG_XFRM_MIGRATE is not set
> # CONFIG_XFRM_STATISTICS is not set
> CONFIG_XFRM_IPCOMP=y
> CONFIG_NET_KEY=y
> # CONFIG_NET_KEY_MIGRATE is not set
> CONFIG_INET=y
> CONFIG_IP_MULTICAST=y
> # CONFIG_IP_ADVANCED_ROUTER is not set
> CONFIG_IP_PNP=y
> CONFIG_IP_PNP_DHCP=y
> CONFIG_IP_PNP_BOOTP=y
> # CONFIG_IP_PNP_RARP is not set
> # CONFIG_NET_IPIP is not set
> # CONFIG_NET_IPGRE_DEMUX is not set
> # CONFIG_IP_MROUTE is not set
> # CONFIG_ARPD is not set
> # CONFIG_SYN_COOKIES is not set
> # CONFIG_NET_IPVTI is not set
> # CONFIG_INET_AH is not set
> CONFIG_INET_ESP=y
> CONFIG_INET_IPCOMP=y
> CONFIG_INET_XFRM_TUNNEL=y
> CONFIG_INET_TUNNEL=y
> # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> CONFIG_INET_XFRM_MODE_TUNNEL=y
> CONFIG_INET_XFRM_MODE_BEET=y
> # CONFIG_INET_LRO is not set
> CONFIG_INET_DIAG=y
> CONFIG_INET_TCP_DIAG=y
> # CONFIG_INET_UDP_DIAG is not set
> # CONFIG_TCP_CONG_ADVANCED is not set
> CONFIG_TCP_CONG_CUBIC=y
> CONFIG_DEFAULT_TCP_CONG="cubic"
> # CONFIG_TCP_MD5SIG is not set
> # CONFIG_IPV6 is not set
> # CONFIG_NETLABEL is not set
> CONFIG_NETWORK_SECMARK=y
> # CONFIG_NETWORK_PHY_TIMESTAMPING is not set
> CONFIG_NETFILTER=y
> # CONFIG_NETFILTER_DEBUG is not set
> CONFIG_NETFILTER_ADVANCED=y
> 
> #
> # Core Netfilter Configuration
> #
> CONFIG_NETFILTER_NETLINK=y
> CONFIG_NETFILTER_NETLINK_ACCT=y
> # CONFIG_NETFILTER_NETLINK_QUEUE is not set
> # CONFIG_NETFILTER_NETLINK_LOG is not set
> CONFIG_NF_CONNTRACK=y
> CONFIG_NF_CONNTRACK_MARK=y
> CONFIG_NF_CONNTRACK_SECMARK=y
> CONFIG_NF_CONNTRACK_PROCFS=y
> # CONFIG_NF_CONNTRACK_EVENTS is not set
> CONFIG_NF_CONNTRACK_TIMEOUT=y
> CONFIG_NF_CONNTRACK_TIMESTAMP=y
> # CONFIG_NF_CT_PROTO_DCCP is not set
> # CONFIG_NF_CT_PROTO_SCTP is not set
> # CONFIG_NF_CT_PROTO_UDPLITE is not set
> # CONFIG_NF_CONNTRACK_AMANDA is not set
> # CONFIG_NF_CONNTRACK_FTP is not set
> # CONFIG_NF_CONNTRACK_H323 is not set
> # CONFIG_NF_CONNTRACK_IRC is not set
> # CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
> # CONFIG_NF_CONNTRACK_SNMP is not set
> # CONFIG_NF_CONNTRACK_PPTP is not set
> # CONFIG_NF_CONNTRACK_SANE is not set
> # CONFIG_NF_CONNTRACK_SIP is not set
> # CONFIG_NF_CONNTRACK_TFTP is not set
> # CONFIG_NF_CT_NETLINK is not set
> CONFIG_NF_CT_NETLINK_TIMEOUT=y
> CONFIG_NETFILTER_XTABLES=y
> 
> #
> # Xtables combined modules
> #
> CONFIG_NETFILTER_XT_MARK=y
> CONFIG_NETFILTER_XT_CONNMARK=y
> 
> #
> # Xtables targets
> #
> # CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
> # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
> CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
> # CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set
> # CONFIG_NETFILTER_XT_TARGET_CT is not set
> # CONFIG_NETFILTER_XT_TARGET_HMARK is not set
> # CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
> # CONFIG_NETFILTER_XT_TARGET_LED is not set
> CONFIG_NETFILTER_XT_TARGET_LOG=y
> CONFIG_NETFILTER_XT_TARGET_MARK=y
> # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
> # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
> # CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
> # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
> # CONFIG_NETFILTER_XT_TARGET_TEE is not set
> CONFIG_NETFILTER_XT_TARGET_TRACE=y
> CONFIG_NETFILTER_XT_TARGET_SECMARK=y
> # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
> 
> #
> # Xtables matches
> #
> # CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
> # CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
> # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
> # CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
> # CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
> CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
> CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
> # CONFIG_NETFILTER_XT_MATCH_CPU is not set
> # CONFIG_NETFILTER_XT_MATCH_DCCP is not set
> # CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
> # CONFIG_NETFILTER_XT_MATCH_DSCP is not set
> CONFIG_NETFILTER_XT_MATCH_ECN=y
> # CONFIG_NETFILTER_XT_MATCH_ESP is not set
> # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
> # CONFIG_NETFILTER_XT_MATCH_HELPER is not set
> # CONFIG_NETFILTER_XT_MATCH_HL is not set
> # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
> # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
> CONFIG_NETFILTER_XT_MATCH_LIMIT=y
> # CONFIG_NETFILTER_XT_MATCH_MAC is not set
> CONFIG_NETFILTER_XT_MATCH_MARK=y
> CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> CONFIG_NETFILTER_XT_MATCH_NFACCT=y
> CONFIG_NETFILTER_XT_MATCH_OSF=y
> # CONFIG_NETFILTER_XT_MATCH_OWNER is not set
> # CONFIG_NETFILTER_XT_MATCH_POLICY is not set
> CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
> # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
> # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
> # CONFIG_NETFILTER_XT_MATCH_REALM is not set
> CONFIG_NETFILTER_XT_MATCH_RECENT=y
> # CONFIG_NETFILTER_XT_MATCH_SCTP is not set
> CONFIG_NETFILTER_XT_MATCH_STATE=y
> # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
> # CONFIG_NETFILTER_XT_MATCH_STRING is not set
> # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
> CONFIG_NETFILTER_XT_MATCH_TIME=y
> # CONFIG_NETFILTER_XT_MATCH_U32 is not set
> # CONFIG_IP_SET is not set
> # CONFIG_IP_VS is not set
> 
> #
> # IP: Netfilter Configuration
> #
> CONFIG_NF_DEFRAG_IPV4=y
> CONFIG_NF_CONNTRACK_IPV4=y
> # CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
> # CONFIG_IP_NF_QUEUE is not set
> CONFIG_IP_NF_IPTABLES=y
> # CONFIG_IP_NF_MATCH_AH is not set
> # CONFIG_IP_NF_MATCH_ECN is not set
> # CONFIG_IP_NF_MATCH_RPFILTER is not set
> # CONFIG_IP_NF_MATCH_TTL is not set
> CONFIG_IP_NF_FILTER=y
> CONFIG_IP_NF_TARGET_REJECT=y
> CONFIG_IP_NF_TARGET_ULOG=y
> # CONFIG_NF_NAT is not set
> # CONFIG_IP_NF_MANGLE is not set
> CONFIG_IP_NF_RAW=y
> # CONFIG_IP_NF_SECURITY is not set
> CONFIG_IP_NF_ARPTABLES=y
> CONFIG_IP_NF_ARPFILTER=y
> # CONFIG_IP_NF_ARP_MANGLE is not set
> # CONFIG_IP_DCCP is not set
> # CONFIG_IP_SCTP is not set
> # CONFIG_RDS is not set
> # CONFIG_TIPC is not set
> # CONFIG_ATM is not set
> # CONFIG_L2TP is not set
> # CONFIG_BRIDGE is not set
> # CONFIG_NET_DSA is not set
> # CONFIG_VLAN_8021Q is not set
> # CONFIG_DECNET is not set
> # CONFIG_LLC2 is not set
> # CONFIG_IPX is not set
> # CONFIG_ATALK is not set
> # CONFIG_X25 is not set
> # CONFIG_LAPB is not set
> # CONFIG_WAN_ROUTER is not set
> # CONFIG_PHONET is not set
> # CONFIG_IEEE802154 is not set
> # CONFIG_NET_SCHED is not set
> # CONFIG_DCB is not set
> CONFIG_DNS_RESOLVER=y
> # CONFIG_BATMAN_ADV is not set
> # CONFIG_OPENVSWITCH is not set
> CONFIG_BQL=y
> # CONFIG_BPF_JIT is not set
> 
> #
> # Network testing
> #
> # CONFIG_NET_PKTGEN is not set
> # CONFIG_HAMRADIO is not set
> # CONFIG_CAN is not set
> # CONFIG_IRDA is not set
> # CONFIG_BT is not set
> # CONFIG_AF_RXRPC is not set
> # CONFIG_WIRELESS is not set
> # CONFIG_WIMAX is not set
> # CONFIG_RFKILL is not set
> # CONFIG_RFKILL_REGULATOR is not set
> # CONFIG_NET_9P is not set
> # CONFIG_CAIF is not set
> # CONFIG_CEPH_LIB is not set
> # CONFIG_NFC is not set
> CONFIG_HAVE_BPF_JIT=y
> 
> #
> # Device Drivers
> #
> 
> #
> # Generic Driver Options
> #
> CONFIG_UEVENT_HELPER_PATH=""
> CONFIG_DEVTMPFS=y
> # CONFIG_DEVTMPFS_MOUNT is not set
> CONFIG_STANDALONE=y
> CONFIG_PREVENT_FIRMWARE_BUILD=y
> CONFIG_FW_LOADER=y
> # CONFIG_FIRMWARE_IN_KERNEL is not set
> CONFIG_EXTRA_FIRMWARE=""
> # CONFIG_SYS_HYPERVISOR is not set
> # CONFIG_GENERIC_CPU_DEVICES is not set
> # CONFIG_DMA_SHARED_BUFFER is not set
> # CONFIG_CONNECTOR is not set
> CONFIG_MTD=y
> # CONFIG_MTD_TESTS is not set
> # CONFIG_MTD_REDBOOT_PARTS is not set
> CONFIG_MTD_CMDLINE_PARTS=y
> # CONFIG_MTD_AFS_PARTS is not set
> # CONFIG_MTD_OF_PARTS is not set
> # CONFIG_MTD_AR7_PARTS is not set
> 
> #
> # User Modules And Translation Layers
> #
> CONFIG_MTD_CHAR=y
> CONFIG_MTD_BLKDEVS=m
> # CONFIG_MTD_BLOCK is not set
> # CONFIG_MTD_BLOCK_RO is not set
> # CONFIG_FTL is not set
> # CONFIG_NFTL is not set
> # CONFIG_INFTL is not set
> # CONFIG_RFD_FTL is not set
> # CONFIG_SSFDC is not set
> # CONFIG_SM_FTL is not set
> # CONFIG_MTD_OOPS is not set
> # CONFIG_MTD_SWAP is not set
> 
> #
> # RAM/ROM/Flash chip drivers
> #
> # CONFIG_MTD_CFI is not set
> # CONFIG_MTD_JEDECPROBE is not set
> CONFIG_MTD_MAP_BANK_WIDTH_1=y
> CONFIG_MTD_MAP_BANK_WIDTH_2=y
> CONFIG_MTD_MAP_BANK_WIDTH_4=y
> # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> CONFIG_MTD_CFI_I1=y
> CONFIG_MTD_CFI_I2=y
> # CONFIG_MTD_CFI_I4 is not set
> # CONFIG_MTD_CFI_I8 is not set
> # CONFIG_MTD_RAM is not set
> # CONFIG_MTD_ROM is not set
> # CONFIG_MTD_ABSENT is not set
> 
> #
> # Mapping drivers for chip access
> #
> # CONFIG_MTD_COMPLEX_MAPPINGS is not set
> # CONFIG_MTD_PLATRAM is not set
> 
> #
> # Self-contained MTD device drivers
> #
> # CONFIG_MTD_SLRAM is not set
> # CONFIG_MTD_PHRAM is not set
> # CONFIG_MTD_MTDRAM is not set
> # CONFIG_MTD_BLOCK2MTD is not set
> 
> #
> # Disk-On-Chip Device Drivers
> #
> # CONFIG_MTD_DOC2000 is not set
> # CONFIG_MTD_DOC2001 is not set
> # CONFIG_MTD_DOC2001PLUS is not set
> # CONFIG_MTD_DOCG3 is not set
> CONFIG_MTD_NAND_ECC=y
> # CONFIG_MTD_NAND_ECC_SMC is not set
> CONFIG_MTD_NAND=y
> # CONFIG_MTD_NAND_VERIFY_WRITE is not set
> CONFIG_MTD_NAND_BCH=y
> CONFIG_MTD_NAND_ECC_BCH=y
> # CONFIG_MTD_SM_COMMON is not set
> CONFIG_MTD_NAND_MUSEUM_IDS=y
> # CONFIG_MTD_NAND_GPIO is not set
> CONFIG_MTD_NAND_IDS=y
> # CONFIG_MTD_NAND_DISKONCHIP is not set
> # CONFIG_MTD_NAND_DOCG4 is not set
> # CONFIG_MTD_NAND_NANDSIM is not set
> CONFIG_MTD_NAND_GPMI_NAND=y
> CONFIG_MTD_NAND_PLATFORM=y
> # CONFIG_MTD_ALAUDA is not set
> CONFIG_MTD_ONENAND=y
> # CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
> # CONFIG_MTD_ONENAND_GENERIC is not set
> # CONFIG_MTD_ONENAND_OTP is not set
> # CONFIG_MTD_ONENAND_2X_PROGRAM is not set
> # CONFIG_MTD_ONENAND_SIM is not set
> 
> #
> # LPDDR flash memory drivers
> #
> # CONFIG_MTD_LPDDR is not set
> CONFIG_MTD_UBI=y
> CONFIG_MTD_UBI_WL_THRESHOLD=4096
> CONFIG_MTD_UBI_BEB_RESERVE=1
> CONFIG_MTD_UBI_GLUEBI=y
> CONFIG_DTC=y
> CONFIG_OF=y
> 
> #
> # Device Tree and Open Firmware support
> #
> CONFIG_PROC_DEVICETREE=y
> CONFIG_OF_SELFTEST=y
> CONFIG_OF_FLATTREE=y
> CONFIG_OF_EARLY_FLATTREE=y
> CONFIG_OF_ADDRESS=y
> CONFIG_OF_IRQ=y
> CONFIG_OF_DEVICE=y
> CONFIG_OF_I2C=y
> CONFIG_OF_NET=y
> CONFIG_OF_MDIO=y
> CONFIG_OF_MTD=y
> # CONFIG_PARPORT is not set
> # CONFIG_BLK_DEV is not set
> 
> #
> # Misc devices
> #
> # CONFIG_SENSORS_LIS3LV02D is not set
> # CONFIG_AD525X_DPOT is not set
> # CONFIG_ATMEL_PWM is not set
> # CONFIG_ICS932S401 is not set
> # CONFIG_ENCLOSURE_SERVICES is not set
> # CONFIG_APDS9802ALS is not set
> # CONFIG_ISL29003 is not set
> # CONFIG_ISL29020 is not set
> # CONFIG_SENSORS_TSL2550 is not set
> # CONFIG_SENSORS_BH1780 is not set
> # CONFIG_SENSORS_BH1770 is not set
> # CONFIG_SENSORS_APDS990X is not set
> # CONFIG_HMC6352 is not set
> # CONFIG_DS1682 is not set
> # CONFIG_BMP085_I2C is not set
> # CONFIG_USB_SWITCH_FSA9480 is not set
> CONFIG_MMA7660=y
> CONFIG_MXS_PERSISTENT=y
> # CONFIG_C2PORT is not set
> 
> #
> # EEPROM support
> #
> CONFIG_EEPROM_AT24=y
> # CONFIG_EEPROM_LEGACY is not set
> # CONFIG_EEPROM_MAX6875 is not set
> # CONFIG_EEPROM_93CX6 is not set
> 
> #
> # Texas Instruments shared transport line discipline
> #
> # CONFIG_TI_ST is not set
> # CONFIG_SENSORS_LIS3_I2C is not set
> 
> #
> # Altera FPGA firmware download module
> #
> # CONFIG_ALTERA_STAPL is not set
> 
> #
> # SCSI device support
> #
> CONFIG_SCSI_MOD=y
> # CONFIG_RAID_ATTRS is not set
> # CONFIG_SCSI is not set
> # CONFIG_SCSI_DMA is not set
> # CONFIG_SCSI_NETLINK is not set
> # CONFIG_ATA is not set
> # CONFIG_MD is not set
> CONFIG_NETDEVICES=y
> CONFIG_NET_CORE=y
> # CONFIG_BONDING is not set
> # CONFIG_DUMMY is not set
> # CONFIG_EQUALIZER is not set
> # CONFIG_MII is not set
> # CONFIG_NET_TEAM is not set
> # CONFIG_MACVLAN is not set
> # CONFIG_NETCONSOLE is not set
> # CONFIG_NETPOLL is not set
> # CONFIG_NET_POLL_CONTROLLER is not set
> # CONFIG_TUN is not set
> # CONFIG_VETH is not set
> 
> #
> # CAIF transport drivers
> #
> CONFIG_ETHERNET=y
> CONFIG_NET_VENDOR_BROADCOM=y
> # CONFIG_B44 is not set
> # CONFIG_NET_CALXEDA_XGMAC is not set
> CONFIG_NET_VENDOR_CHELSIO=y
> CONFIG_NET_VENDOR_CIRRUS=y
> # CONFIG_CS89x0 is not set
> # CONFIG_DM9000 is not set
> # CONFIG_DNET is not set
> CONFIG_NET_VENDOR_FARADAY=y
> # CONFIG_FTMAC100 is not set
> # CONFIG_FTGMAC100 is not set
> CONFIG_NET_VENDOR_FREESCALE=y
> CONFIG_FEC=y
> CONFIG_NET_VENDOR_INTEL=y
> CONFIG_NET_VENDOR_I825XX=y
> CONFIG_NET_VENDOR_MARVELL=y
> CONFIG_NET_VENDOR_MICREL=y
> # CONFIG_KS8842 is not set
> # CONFIG_KS8851_MLL is not set
> CONFIG_NET_VENDOR_NATSEMI=y
> CONFIG_NET_VENDOR_8390=y
> # CONFIG_AX88796 is not set
> # CONFIG_ETHOC is not set
> CONFIG_NET_VENDOR_SEEQ=y
> # CONFIG_SEEQ8005 is not set
> CONFIG_NET_VENDOR_SMSC=y
> # CONFIG_SMC91X is not set
> # CONFIG_SMC911X is not set
> # CONFIG_SMSC911X is not set
> CONFIG_NET_VENDOR_STMICRO=y
> # CONFIG_STMMAC_ETH is not set
> CONFIG_NET_VENDOR_WIZNET=y
> # CONFIG_WIZNET_W5100 is not set
> # CONFIG_WIZNET_W5300 is not set
> CONFIG_PHYLIB=y
> 
> #
> # MII PHY device drivers
> #
> # CONFIG_AMD_PHY is not set
> # CONFIG_MARVELL_PHY is not set
> # CONFIG_DAVICOM_PHY is not set
> # CONFIG_QSEMI_PHY is not set
> # CONFIG_LXT_PHY is not set
> # CONFIG_CICADA_PHY is not set
> # CONFIG_VITESSE_PHY is not set
> # CONFIG_SMSC_PHY is not set
> # CONFIG_BROADCOM_PHY is not set
> # CONFIG_BCM87XX_PHY is not set
> # CONFIG_ICPLUS_PHY is not set
> # CONFIG_REALTEK_PHY is not set
> # CONFIG_NATIONAL_PHY is not set
> # CONFIG_STE10XP is not set
> # CONFIG_LSI_ET1011C_PHY is not set
> # CONFIG_MICREL_PHY is not set
> # CONFIG_FIXED_PHY is not set
> # CONFIG_MDIO_BITBANG is not set
> # CONFIG_MDIO_BUS_MUX_GPIO is not set
> CONFIG_PPP=m
> CONFIG_PPP_BSDCOMP=m
> CONFIG_PPP_DEFLATE=m
> CONFIG_PPP_FILTER=y
> CONFIG_PPP_MPPE=m
> # CONFIG_PPP_MULTILINK is not set
> # CONFIG_PPPOE is not set
> CONFIG_PPP_ASYNC=m
> # CONFIG_PPP_SYNC_TTY is not set
> # CONFIG_SLIP is not set
> CONFIG_SLHC=m
> 
> #
> # USB Network Adapters
> #
> # CONFIG_USB_CATC is not set
> # CONFIG_USB_KAWETH is not set
> # CONFIG_USB_PEGASUS is not set
> # CONFIG_USB_RTL8150 is not set
> # CONFIG_USB_USBNET is not set
> # CONFIG_USB_IPHETH is not set
> # CONFIG_WLAN is not set
> 
> #
> # Enable WiMAX (Networking options) to see the WiMAX drivers
> #
> # CONFIG_WAN is not set
> # CONFIG_ISDN is not set
> 
> #
> # Input device support
> #
> CONFIG_INPUT=y
> # CONFIG_INPUT_FF_MEMLESS is not set
> # CONFIG_INPUT_POLLDEV is not set
> # CONFIG_INPUT_SPARSEKMAP is not set
> # CONFIG_INPUT_MATRIXKMAP is not set
> 
> #
> # Userland interfaces
> #
> CONFIG_INPUT_MOUSEDEV=y
> # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> # CONFIG_INPUT_JOYDEV is not set
> CONFIG_INPUT_EVDEV=m
> # CONFIG_INPUT_EVBUG is not set
> 
> #
> # Input Device Drivers
> #
> # CONFIG_INPUT_KEYBOARD is not set
> # CONFIG_INPUT_MOUSE is not set
> # CONFIG_INPUT_JOYSTICK is not set
> # CONFIG_INPUT_TABLET is not set
> CONFIG_INPUT_TOUCHSCREEN=y
> # CONFIG_TOUCHSCREEN_AD7879 is not set
> # CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
> # CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
> # CONFIG_TOUCHSCREEN_BU21013 is not set
> # CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
> # CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
> # CONFIG_TOUCHSCREEN_DYNAPRO is not set
> # CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
> # CONFIG_TOUCHSCREEN_EETI is not set
> # CONFIG_TOUCHSCREEN_EGALAX is not set
> # CONFIG_TOUCHSCREEN_FUJITSU is not set
> # CONFIG_TOUCHSCREEN_ILI210X is not set
> # CONFIG_TOUCHSCREEN_GUNZE is not set
> # CONFIG_TOUCHSCREEN_ELO is not set
> # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> # CONFIG_TOUCHSCREEN_WACOM_I2C is not set
> # CONFIG_TOUCHSCREEN_MAX11801 is not set
> # CONFIG_TOUCHSCREEN_MCS5000 is not set
> # CONFIG_TOUCHSCREEN_MMS114 is not set
> # CONFIG_TOUCHSCREEN_MTOUCH is not set
> # CONFIG_TOUCHSCREEN_INEXIO is not set
> # CONFIG_TOUCHSCREEN_MK712 is not set
> # CONFIG_TOUCHSCREEN_PENMOUNT is not set
> # CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
> # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> # CONFIG_TOUCHSCREEN_PIXCIR is not set
> # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> # CONFIG_TOUCHSCREEN_TSC_SERIO is not set
> CONFIG_TOUCHSCREEN_TSC2007=m
> # CONFIG_TOUCHSCREEN_W90X900 is not set
> # CONFIG_TOUCHSCREEN_ST1232 is not set
> # CONFIG_TOUCHSCREEN_TPS6507X is not set
> # CONFIG_INPUT_MISC is not set
> 
> #
> # Hardware I/O ports
> #
> # CONFIG_SERIO is not set
> # CONFIG_GAMEPORT is not set
> 
> #
> # Character devices
> #
> CONFIG_VT=y
> CONFIG_CONSOLE_TRANSLATIONS=y
> CONFIG_VT_CONSOLE=y
> CONFIG_HW_CONSOLE=y
> CONFIG_VT_HW_CONSOLE_BINDING=y
> CONFIG_UNIX98_PTYS=y
> CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
> # CONFIG_LEGACY_PTYS is not set
> # CONFIG_SERIAL_NONSTANDARD is not set
> # CONFIG_N_GSM is not set
> # CONFIG_TRACE_SINK is not set
> # CONFIG_DEVKMEM is not set
> 
> #
> # Serial drivers
> #
> # CONFIG_SERIAL_8250 is not set
> 
> #
> # Non-8250 serial port support
> #
> CONFIG_SERIAL_AMBA_PL010=y
> CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
> CONFIG_SERIAL_AMBA_PL011=y
> CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> CONFIG_SERIAL_CORE=y
> CONFIG_SERIAL_CORE_CONSOLE=y
> # CONFIG_SERIAL_TIMBERDALE is not set
> # CONFIG_SERIAL_ALTERA_JTAGUART is not set
> # CONFIG_SERIAL_ALTERA_UART is not set
> CONFIG_SERIAL_MXS_AUART=y
> CONFIG_SERIAL_MXS_AUART_CONSOLE=y
> # CONFIG_SERIAL_XILINX_PS_UART is not set
> # CONFIG_HVC_DCC is not set
> # CONFIG_IPMI_HANDLER is not set
> # CONFIG_HW_RANDOM is not set
> # CONFIG_R3964 is not set
> # CONFIG_RAW_DRIVER is not set
> # CONFIG_TCG_TPM is not set
> CONFIG_I2C=y
> CONFIG_I2C_BOARDINFO=y
> # CONFIG_I2C_COMPAT is not set
> CONFIG_I2C_CHARDEV=y
> # CONFIG_I2C_MUX is not set
> CONFIG_I2C_HELPER_AUTO=y
> 
> #
> # I2C Hardware Bus support
> #
> 
> #
> # I2C system bus drivers (mostly embedded / system-on-chip)
> #
> # CONFIG_I2C_DESIGNWARE_PLATFORM is not set
> # CONFIG_I2C_GPIO is not set
> CONFIG_I2C_MXS=y
> # CONFIG_I2C_NOMADIK is not set
> # CONFIG_I2C_OCORES is not set
> # CONFIG_I2C_PCA_PLATFORM is not set
> # CONFIG_I2C_PXA_PCI is not set
> # CONFIG_I2C_SIMTEC is not set
> # CONFIG_I2C_XILINX is not set
> 
> #
> # External I2C/SMBus adapter drivers
> #
> # CONFIG_I2C_DIOLAN_U2C is not set
> # CONFIG_I2C_PARPORT_LIGHT is not set
> # CONFIG_I2C_TAOS_EVM is not set
> # CONFIG_I2C_TINY_USB is not set
> 
> #
> # Other I2C/SMBus bus drivers
> #
> # CONFIG_I2C_STUB is not set
> # CONFIG_I2C_DEBUG_CORE is not set
> # CONFIG_I2C_DEBUG_ALGO is not set
> # CONFIG_I2C_DEBUG_BUS is not set
> # CONFIG_SPI is not set
> # CONFIG_HSI is not set
> 
> #
> # PPS support
> #
> # CONFIG_PPS is not set
> 
> #
> # PPS generators support
> #
> 
> #
> # PTP clock support
> #
> 
> #
> # Enable Device Drivers -> PPS to see the PTP clock options.
> #
> CONFIG_PINCTRL=y
> 
> #
> # Pin controllers
> #
> CONFIG_PINMUX=y
> CONFIG_PINCONF=y
> CONFIG_PINCTRL_MXS=y
> CONFIG_PINCTRL_IMX23=y
> CONFIG_PINCTRL_IMX28=y
> # CONFIG_PINCTRL_SINGLE is not set
> CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
> CONFIG_ARCH_REQUIRE_GPIOLIB=y
> CONFIG_GPIOLIB=y
> CONFIG_OF_GPIO=y
> CONFIG_GPIO_SYSFS=y
> CONFIG_GPIO_GENERIC=y
> 
> #
> # Memory mapped GPIO drivers:
> #
> # CONFIG_GPIO_GENERIC_PLATFORM is not set
> # CONFIG_GPIO_EM is not set
> CONFIG_GPIO_MXS=y
> # CONFIG_GPIO_PL061 is not set
> 
> #
> # I2C GPIO expanders:
> #
> # CONFIG_GPIO_MAX7300 is not set
> # CONFIG_GPIO_MAX732X is not set
> # CONFIG_GPIO_PCF857X is not set
> # CONFIG_GPIO_SX150X is not set
> # CONFIG_GPIO_ADP5588 is not set
> 
> #
> # PCI GPIO expanders:
> #
> 
> #
> # SPI GPIO expanders:
> #
> # CONFIG_GPIO_MCP23S08 is not set
> 
> #
> # AC97 GPIO expanders:
> #
> 
> #
> # MODULbus GPIO expanders:
> #
> # CONFIG_W1 is not set
> # CONFIG_POWER_SUPPLY is not set
> # CONFIG_POWER_AVS is not set
> CONFIG_HWMON=y
> # CONFIG_HWMON_VID is not set
> # CONFIG_HWMON_DEBUG_CHIP is not set
> 
> #
> # Native drivers
> #
> # CONFIG_SENSORS_AD7414 is not set
> # CONFIG_SENSORS_AD7418 is not set
> CONFIG_SENSORS_LRADC=y
> # CONFIG_SENSORS_ADM1021 is not set
> # CONFIG_SENSORS_ADM1025 is not set
> # CONFIG_SENSORS_ADM1026 is not set
> # CONFIG_SENSORS_ADM1029 is not set
> # CONFIG_SENSORS_ADM1031 is not set
> # CONFIG_SENSORS_ADM9240 is not set
> # CONFIG_SENSORS_ADT7411 is not set
> # CONFIG_SENSORS_ADT7462 is not set
> # CONFIG_SENSORS_ADT7470 is not set
> # CONFIG_SENSORS_ADT7475 is not set
> # CONFIG_SENSORS_ASC7621 is not set
> # CONFIG_SENSORS_ATXP1 is not set
> # CONFIG_SENSORS_DS620 is not set
> # CONFIG_SENSORS_DS1621 is not set
> # CONFIG_SENSORS_F71805F is not set
> # CONFIG_SENSORS_F71882FG is not set
> # CONFIG_SENSORS_F75375S is not set
> # CONFIG_SENSORS_G760A is not set
> # CONFIG_SENSORS_GL518SM is not set
> # CONFIG_SENSORS_GL520SM is not set
> # CONFIG_SENSORS_GPIO_FAN is not set
> # CONFIG_SENSORS_HIH6130 is not set
> # CONFIG_SENSORS_IT87 is not set
> # CONFIG_SENSORS_JC42 is not set
> # CONFIG_SENSORS_LINEAGE is not set
> # CONFIG_SENSORS_LM63 is not set
> # CONFIG_SENSORS_LM73 is not set
> # CONFIG_SENSORS_LM75 is not set
> # CONFIG_SENSORS_LM77 is not set
> # CONFIG_SENSORS_LM78 is not set
> # CONFIG_SENSORS_LM80 is not set
> # CONFIG_SENSORS_LM83 is not set
> # CONFIG_SENSORS_LM85 is not set
> # CONFIG_SENSORS_LM87 is not set
> # CONFIG_SENSORS_LM90 is not set
> # CONFIG_SENSORS_LM92 is not set
> # CONFIG_SENSORS_LM93 is not set
> # CONFIG_SENSORS_LTC4151 is not set
> # CONFIG_SENSORS_LTC4215 is not set
> # CONFIG_SENSORS_LTC4245 is not set
> # CONFIG_SENSORS_LTC4261 is not set
> # CONFIG_SENSORS_LM95241 is not set
> # CONFIG_SENSORS_LM95245 is not set
> # CONFIG_SENSORS_MAX16065 is not set
> # CONFIG_SENSORS_MAX1619 is not set
> # CONFIG_SENSORS_MAX1668 is not set
> # CONFIG_SENSORS_MAX6639 is not set
> # CONFIG_SENSORS_MAX6642 is not set
> # CONFIG_SENSORS_MAX6650 is not set
> CONFIG_SENSORS_MAX7500=y
> # CONFIG_SENSORS_MCP3021 is not set
> # CONFIG_SENSORS_NTC_THERMISTOR is not set
> # CONFIG_SENSORS_PC87360 is not set
> # CONFIG_SENSORS_PC87427 is not set
> # CONFIG_SENSORS_PCF8591 is not set
> # CONFIG_PMBUS is not set
> # CONFIG_SENSORS_SHT15 is not set
> # CONFIG_SENSORS_SHT21 is not set
> # CONFIG_SENSORS_SMM665 is not set
> # CONFIG_SENSORS_DME1737 is not set
> # CONFIG_SENSORS_EMC1403 is not set
> # CONFIG_SENSORS_EMC2103 is not set
> # CONFIG_SENSORS_EMC6W201 is not set
> # CONFIG_SENSORS_SMSC47M1 is not set
> # CONFIG_SENSORS_SMSC47M192 is not set
> # CONFIG_SENSORS_SMSC47B397 is not set
> # CONFIG_SENSORS_SCH56XX_COMMON is not set
> # CONFIG_SENSORS_SCH5627 is not set
> # CONFIG_SENSORS_SCH5636 is not set
> # CONFIG_SENSORS_ADS1015 is not set
> # CONFIG_SENSORS_ADS7828 is not set
> # CONFIG_SENSORS_AMC6821 is not set
> # CONFIG_SENSORS_INA2XX is not set
> # CONFIG_SENSORS_THMC50 is not set
> # CONFIG_SENSORS_TMP102 is not set
> # CONFIG_SENSORS_TMP401 is not set
> # CONFIG_SENSORS_TMP421 is not set
> # CONFIG_SENSORS_VT1211 is not set
> # CONFIG_SENSORS_W83781D is not set
> # CONFIG_SENSORS_W83791D is not set
> # CONFIG_SENSORS_W83792D is not set
> # CONFIG_SENSORS_W83793 is not set
> # CONFIG_SENSORS_W83795 is not set
> # CONFIG_SENSORS_W83L785TS is not set
> # CONFIG_SENSORS_W83L786NG is not set
> # CONFIG_SENSORS_W83627HF is not set
> # CONFIG_SENSORS_W83627EHF is not set
> # CONFIG_THERMAL is not set
> CONFIG_WATCHDOG=y
> CONFIG_WATCHDOG_CORE=y
> # CONFIG_WATCHDOG_NOWAYOUT is not set
> 
> #
> # Watchdog Device Drivers
> #
> # CONFIG_SOFT_WATCHDOG is not set
> # CONFIG_ARM_SP805_WATCHDOG is not set
> CONFIG_MXS_WATCHDOG=y
> # CONFIG_DW_WATCHDOG is not set
> # CONFIG_MAX63XX_WATCHDOG is not set
> 
> #
> # USB-based Watchdog Cards
> #
> # CONFIG_USBPCWATCHDOG is not set
> CONFIG_SSB_POSSIBLE=y
> 
> #
> # Sonics Silicon Backplane
> #
> # CONFIG_SSB is not set
> CONFIG_BCMA_POSSIBLE=y
> 
> #
> # Broadcom specific AMBA
> #
> # CONFIG_BCMA is not set
> 
> #
> # Multifunction device drivers
> #
> # CONFIG_MFD_CORE is not set
> # CONFIG_MFD_88PM860X is not set
> # CONFIG_MFD_88PM800 is not set
> # CONFIG_MFD_88PM805 is not set
> # CONFIG_MFD_SM501 is not set
> # CONFIG_MFD_ASIC3 is not set
> # CONFIG_HTC_EGPIO is not set
> # CONFIG_HTC_PASIC3 is not set
> # CONFIG_HTC_I2CPLD is not set
> # CONFIG_MFD_LM3533 is not set
> # CONFIG_TPS6105X is not set
> # CONFIG_TPS65010 is not set
> # CONFIG_TPS6507X is not set
> # CONFIG_MFD_TPS65217 is not set
> # CONFIG_MFD_TPS6586X is not set
> # CONFIG_MFD_TPS65910 is not set
> # CONFIG_MFD_TPS65912_I2C is not set
> # CONFIG_TWL4030_CORE is not set
> # CONFIG_TWL6040_CORE is not set
> # CONFIG_MFD_STMPE is not set
> # CONFIG_MFD_TC3589X is not set
> # CONFIG_MFD_TMIO is not set
> # CONFIG_MFD_T7L66XB is not set
> # CONFIG_MFD_TC6387XB is not set
> # CONFIG_MFD_TC6393XB is not set
> # CONFIG_PMIC_DA903X is not set
> # CONFIG_MFD_DA9052_I2C is not set
> # CONFIG_PMIC_ADP5520 is not set
> # CONFIG_MFD_MAX77686 is not set
> # CONFIG_MFD_MAX77693 is not set
> # CONFIG_MFD_MAX8925 is not set
> # CONFIG_MFD_MAX8997 is not set
> # CONFIG_MFD_MAX8998 is not set
> # CONFIG_MFD_SEC_CORE is not set
> # CONFIG_MFD_ARIZONA_I2C is not set
> # CONFIG_MFD_WM8400 is not set
> # CONFIG_MFD_WM831X_I2C is not set
> # CONFIG_MFD_WM8350_I2C is not set
> # CONFIG_MFD_WM8994 is not set
> # CONFIG_MFD_PCF50633 is not set
> # CONFIG_MFD_MC13XXX_I2C is not set
> # CONFIG_ABX500_CORE is not set
> # CONFIG_MFD_WL1273_CORE is not set
> # CONFIG_MFD_TPS65090 is not set
> # CONFIG_MFD_AAT2870_CORE is not set
> # CONFIG_MFD_RC5T583 is not set
> # CONFIG_MFD_PALMAS is not set
> CONFIG_REGULATOR=y
> # CONFIG_REGULATOR_DEBUG is not set
> # CONFIG_REGULATOR_DUMMY is not set
> CONFIG_REGULATOR_FIXED_VOLTAGE=y
> # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
> # CONFIG_REGULATOR_GPIO is not set
> # CONFIG_REGULATOR_AD5398 is not set
> CONFIG_REGULATOR_MXS=y
> # CONFIG_REGULATOR_ISL6271A is not set
> # CONFIG_REGULATOR_MAX1586 is not set
> # CONFIG_REGULATOR_MAX8649 is not set
> # CONFIG_REGULATOR_MAX8660 is not set
> # CONFIG_REGULATOR_MAX8952 is not set
> # CONFIG_REGULATOR_LP3971 is not set
> # CONFIG_REGULATOR_LP3972 is not set
> # CONFIG_REGULATOR_LP872X is not set
> # CONFIG_REGULATOR_TPS62360 is not set
> # CONFIG_REGULATOR_TPS65023 is not set
> # CONFIG_REGULATOR_TPS6507X is not set
> # CONFIG_MEDIA_SUPPORT is not set
> 
> #
> # Graphics support
> #
> # CONFIG_DRM is not set
> # CONFIG_VGASTATE is not set
> # CONFIG_VIDEO_OUTPUT_CONTROL is not set
> # CONFIG_FB is not set
> # CONFIG_EXYNOS_VIDEO is not set
> # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> 
> #
> # Console display driver support
> #
> CONFIG_DUMMY_CONSOLE=y
> # CONFIG_SOUND is not set
> 
> #
> # HID support
> #
> CONFIG_HID=y
> # CONFIG_HIDRAW is not set
> # CONFIG_UHID is not set
> CONFIG_HID_GENERIC=y
> 
> #
> # Special HID drivers
> #
> CONFIG_HID_A4TECH=y
> # CONFIG_HID_ACRUX is not set
> CONFIG_HID_APPLE=y
> # CONFIG_HID_AUREAL is not set
> CONFIG_HID_BELKIN=y
> CONFIG_HID_CHERRY=y
> CONFIG_HID_CHICONY=y
> CONFIG_HID_CYPRESS=y
> # CONFIG_HID_DRAGONRISE is not set
> # CONFIG_HID_EMS_FF is not set
> CONFIG_HID_EZKEY=y
> # CONFIG_HID_HOLTEK is not set
> # CONFIG_HID_KEYTOUCH is not set
> # CONFIG_HID_KYE is not set
> # CONFIG_HID_UCLOGIC is not set
> # CONFIG_HID_WALTOP is not set
> # CONFIG_HID_GYRATION is not set
> # CONFIG_HID_TWINHAN is not set
> CONFIG_HID_KENSINGTON=y
> # CONFIG_HID_LCPOWER is not set
> # CONFIG_HID_LENOVO_TPKBD is not set
> CONFIG_HID_LOGITECH=y
> # CONFIG_HID_LOGITECH_DJ is not set
> # CONFIG_LOGITECH_FF is not set
> # CONFIG_LOGIRUMBLEPAD2_FF is not set
> # CONFIG_LOGIG940_FF is not set
> # CONFIG_LOGIWHEELS_FF is not set
> CONFIG_HID_MICROSOFT=y
> CONFIG_HID_MONTEREY=y
> # CONFIG_HID_MULTITOUCH is not set
> # CONFIG_HID_NTRIG is not set
> # CONFIG_HID_ORTEK is not set
> # CONFIG_HID_PANTHERLORD is not set
> # CONFIG_HID_PETALYNX is not set
> # CONFIG_HID_PICOLCD is not set
> # CONFIG_HID_PRIMAX is not set
> # CONFIG_HID_ROCCAT is not set
> # CONFIG_HID_SAITEK is not set
> # CONFIG_HID_SAMSUNG is not set
> # CONFIG_HID_SONY is not set
> # CONFIG_HID_SPEEDLINK is not set
> # CONFIG_HID_SUNPLUS is not set
> # CONFIG_HID_GREENASIA is not set
> # CONFIG_HID_SMARTJOYPLUS is not set
> # CONFIG_HID_TIVO is not set
> # CONFIG_HID_TOPSEED is not set
> # CONFIG_HID_THRUSTMASTER is not set
> # CONFIG_HID_ZEROPLUS is not set
> # CONFIG_HID_ZYDACRON is not set
> 
> #
> # USB HID support
> #
> CONFIG_USB_HID=y
> # CONFIG_HID_PID is not set
> # CONFIG_USB_HIDDEV is not set
> # CONFIG_USB_ARCH_HAS_OHCI is not set
> # CONFIG_USB_ARCH_HAS_EHCI is not set
> # CONFIG_USB_ARCH_HAS_XHCI is not set
> CONFIG_USB_SUPPORT=y
> CONFIG_USB_COMMON=y
> CONFIG_USB_ARCH_HAS_HCD=y
> CONFIG_USB=y
> CONFIG_USB_DEBUG=y
> CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
> 
> #
> # Miscellaneous USB options
> #
> # CONFIG_USB_DYNAMIC_MINORS is not set
> # CONFIG_USB_MON is not set
> # CONFIG_USB_WUSB_CBAF is not set
> 
> #
> # USB Host Controller Drivers
> #
> # CONFIG_USB_C67X00_HCD is not set
> CONFIG_USB_EHCI_ROOT_HUB_TT=y
> CONFIG_USB_EHCI_TT_NEWSCHED=y
> # CONFIG_USB_OXU210HP_HCD is not set
> # CONFIG_USB_ISP116X_HCD is not set
> # CONFIG_USB_ISP1760_HCD is not set
> # CONFIG_USB_ISP1362_HCD is not set
> # CONFIG_USB_SL811_HCD is not set
> # CONFIG_USB_R8A66597_HCD is not set
> CONFIG_USB_CHIPIDEA=y
> CONFIG_USB_CHIPIDEA_HOST=y
> # CONFIG_USB_CHIPIDEA_DEBUG is not set
> 
> #
> # USB Device Class drivers
> #
> CONFIG_USB_ACM=y
> # CONFIG_USB_PRINTER is not set
> # CONFIG_USB_WDM is not set
> # CONFIG_USB_TMC is not set
> 
> #
> # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> #
> 
> #
> # also be needed; see USB_STORAGE Help for more info
> #
> # CONFIG_USB_LIBUSUAL is not set
> 
> #
> # USB Imaging devices
> #
> # CONFIG_USB_MDC800 is not set
> 
> #
> # USB port drivers
> #
> CONFIG_USB_SERIAL=y
> # CONFIG_USB_SERIAL_CONSOLE is not set
> # CONFIG_USB_EZUSB is not set
> CONFIG_USB_SERIAL_GENERIC=y
> # CONFIG_USB_SERIAL_AIRCABLE is not set
> # CONFIG_USB_SERIAL_ARK3116 is not set
> # CONFIG_USB_SERIAL_BELKIN is not set
> # CONFIG_USB_SERIAL_CH341 is not set
> # CONFIG_USB_SERIAL_WHITEHEAT is not set
> # CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> # CONFIG_USB_SERIAL_CP210X is not set
> # CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> # CONFIG_USB_SERIAL_EMPEG is not set
> # CONFIG_USB_SERIAL_FTDI_SIO is not set
> # CONFIG_USB_SERIAL_FUNSOFT is not set
> # CONFIG_USB_SERIAL_VISOR is not set
> # CONFIG_USB_SERIAL_IPAQ is not set
> # CONFIG_USB_SERIAL_IR is not set
> # CONFIG_USB_SERIAL_EDGEPORT is not set
> # CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> # CONFIG_USB_SERIAL_F81232 is not set
> # CONFIG_USB_SERIAL_GARMIN is not set
> # CONFIG_USB_SERIAL_IPW is not set
> # CONFIG_USB_SERIAL_IUU is not set
> # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> # CONFIG_USB_SERIAL_KEYSPAN is not set
> # CONFIG_USB_SERIAL_KLSI is not set
> # CONFIG_USB_SERIAL_KOBIL_SCT is not set
> # CONFIG_USB_SERIAL_MCT_U232 is not set
> # CONFIG_USB_SERIAL_METRO is not set
> # CONFIG_USB_SERIAL_MOS7720 is not set
> # CONFIG_USB_SERIAL_MOS7840 is not set
> # CONFIG_USB_SERIAL_MOTOROLA is not set
> # CONFIG_USB_SERIAL_NAVMAN is not set
> # CONFIG_USB_SERIAL_PL2303 is not set
> # CONFIG_USB_SERIAL_OTI6858 is not set
> # CONFIG_USB_SERIAL_QCAUX is not set
> # CONFIG_USB_SERIAL_QUALCOMM is not set
> # CONFIG_USB_SERIAL_SPCP8X5 is not set
> # CONFIG_USB_SERIAL_HP4X is not set
> # CONFIG_USB_SERIAL_SAFE is not set
> # CONFIG_USB_SERIAL_SIEMENS_MPI is not set
> CONFIG_USB_SERIAL_SIERRAWIRELESS=y
> # CONFIG_USB_SERIAL_SYMBOL is not set
> # CONFIG_USB_SERIAL_TI is not set
> # CONFIG_USB_SERIAL_CYBERJACK is not set
> # CONFIG_USB_SERIAL_XIRCOM is not set
> CONFIG_USB_SERIAL_WWAN=y
> CONFIG_USB_SERIAL_OPTION=y
> # CONFIG_USB_SERIAL_OMNINET is not set
> # CONFIG_USB_SERIAL_OPTICON is not set
> # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
> # CONFIG_USB_SERIAL_ZIO is not set
> # CONFIG_USB_SERIAL_SSU100 is not set
> # CONFIG_USB_SERIAL_QT2 is not set
> # CONFIG_USB_SERIAL_DEBUG is not set
> 
> #
> # USB Miscellaneous drivers
> #
> # CONFIG_USB_EMI62 is not set
> # CONFIG_USB_EMI26 is not set
> # CONFIG_USB_ADUTUX is not set
> # CONFIG_USB_SEVSEG is not set
> # CONFIG_USB_RIO500 is not set
> # CONFIG_USB_LEGOTOWER is not set
> # CONFIG_USB_LCD is not set
> # CONFIG_USB_LED is not set
> # CONFIG_USB_CYPRESS_CY7C63 is not set
> # CONFIG_USB_CYTHERM is not set
> # CONFIG_USB_IDMOUSE is not set
> # CONFIG_USB_FTDI_ELAN is not set
> # CONFIG_USB_APPLEDISPLAY is not set
> # CONFIG_USB_LD is not set
> # CONFIG_USB_TRANCEVIBRATOR is not set
> # CONFIG_USB_IOWARRIOR is not set
> # CONFIG_USB_TEST is not set
> # CONFIG_USB_ISIGHTFW is not set
> # CONFIG_USB_YUREX is not set
> 
> #
> # USB Physical Layer drivers
> #
> # CONFIG_USB_ISP1301 is not set
> # CONFIG_USB_GADGET is not set
> 
> #
> # OTG and related infrastructure
> #
> CONFIG_USB_OTG_UTILS=y
> # CONFIG_USB_GPIO_VBUS is not set
> # CONFIG_USB_ULPI is not set
> # CONFIG_NOP_USB_XCEIV is not set
> CONFIG_USB_MXS_PHY=y
> # CONFIG_MMC is not set
> # CONFIG_MEMSTICK is not set
> CONFIG_LEDS_GPIO_REGISTER=y
> CONFIG_NEW_LEDS=y
> CONFIG_LEDS_CLASS=y
> 
> #
> # LED drivers
> #
> # CONFIG_LEDS_LM3530 is not set
> # CONFIG_LEDS_PCA9532 is not set
> CONFIG_LEDS_GPIO=y
> # CONFIG_LEDS_LP3944 is not set
> # CONFIG_LEDS_LP5521 is not set
> # CONFIG_LEDS_LP5523 is not set
> # CONFIG_LEDS_PCA955X is not set
> # CONFIG_LEDS_PCA9633 is not set
> # CONFIG_LEDS_PWM is not set
> CONFIG_LEDS_REGULATOR=y
> # CONFIG_LEDS_BD2802 is not set
> # CONFIG_LEDS_LT3593 is not set
> # CONFIG_LEDS_RENESAS_TPU is not set
> # CONFIG_LEDS_TCA6507 is not set
> # CONFIG_LEDS_LM3556 is not set
> # CONFIG_LEDS_OT200 is not set
> # CONFIG_LEDS_BLINKM is not set
> CONFIG_LEDS_TRIGGERS=y
> 
> #
> # LED Triggers
> #
> CONFIG_LEDS_TRIGGER_TIMER=y
> # CONFIG_LEDS_TRIGGER_ONESHOT is not set
> CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> CONFIG_LEDS_TRIGGER_CPU=y
> CONFIG_LEDS_TRIGGER_GPIO=y
> CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> 
> #
> # iptables trigger is under Netfilter config (LED target)
> #
> CONFIG_LEDS_TRIGGER_TRANSIENT=y
> # CONFIG_ACCESSIBILITY is not set
> # CONFIG_EDAC is not set
> CONFIG_RTC_LIB=y
> CONFIG_RTC_CLASS=y
> CONFIG_RTC_HCTOSYS=y
> CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> # CONFIG_RTC_DEBUG is not set
> 
> #
> # RTC interfaces
> #
> CONFIG_RTC_INTF_SYSFS=y
> CONFIG_RTC_INTF_PROC=y
> CONFIG_RTC_INTF_DEV=y
> # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> # CONFIG_RTC_DRV_TEST is not set
> 
> #
> # I2C RTC drivers
> #
> CONFIG_RTC_DRV_DS1307=m
> # CONFIG_RTC_DRV_DS1374 is not set
> # CONFIG_RTC_DRV_DS1672 is not set
> # CONFIG_RTC_DRV_DS3232 is not set
> # CONFIG_RTC_DRV_MAX6900 is not set
> # CONFIG_RTC_DRV_RS5C372 is not set
> # CONFIG_RTC_DRV_ISL1208 is not set
> # CONFIG_RTC_DRV_ISL12022 is not set
> # CONFIG_RTC_DRV_X1205 is not set
> # CONFIG_RTC_DRV_PCF8563 is not set
> # CONFIG_RTC_DRV_PCF8583 is not set
> # CONFIG_RTC_DRV_M41T80 is not set
> # CONFIG_RTC_DRV_BQ32K is not set
> # CONFIG_RTC_DRV_S35390A is not set
> # CONFIG_RTC_DRV_FM3130 is not set
> # CONFIG_RTC_DRV_RX8581 is not set
> # CONFIG_RTC_DRV_RX8025 is not set
> # CONFIG_RTC_DRV_EM3027 is not set
> # CONFIG_RTC_DRV_RV3029C2 is not set
> 
> #
> # SPI RTC drivers
> #
> 
> #
> # Platform RTC drivers
> #
> # CONFIG_RTC_DRV_CMOS is not set
> # CONFIG_RTC_DRV_DS1286 is not set
> # CONFIG_RTC_DRV_DS1511 is not set
> # CONFIG_RTC_DRV_DS1553 is not set
> # CONFIG_RTC_DRV_DS1742 is not set
> # CONFIG_RTC_DRV_STK17TA8 is not set
> # CONFIG_RTC_DRV_M48T86 is not set
> # CONFIG_RTC_DRV_M48T35 is not set
> # CONFIG_RTC_DRV_M48T59 is not set
> # CONFIG_RTC_DRV_MSM6242 is not set
> # CONFIG_RTC_DRV_BQ4802 is not set
> # CONFIG_RTC_DRV_RP5C01 is not set
> # CONFIG_RTC_DRV_V3020 is not set
> 
> #
> # on-CPU RTC drivers
> #
> # CONFIG_RTC_DRV_PL030 is not set
> # CONFIG_RTC_DRV_PL031 is not set
> # CONFIG_RTC_DRV_STMP is not set
> CONFIG_DMADEVICES=y
> # CONFIG_DMADEVICES_DEBUG is not set
> 
> #
> # DMA Devices
> #
> # CONFIG_AMBA_PL08X is not set
> # CONFIG_DW_DMAC is not set
> # CONFIG_TIMB_DMA is not set
> # CONFIG_PL330_DMA is not set
> CONFIG_MXS_DMA=y
> CONFIG_DMA_ENGINE=y
> 
> #
> # DMA Clients
> #
> # CONFIG_NET_DMA is not set
> # CONFIG_ASYNC_TX_DMA is not set
> # CONFIG_DMATEST is not set
> # CONFIG_AUXDISPLAY is not set
> # CONFIG_UIO is not set
> 
> #
> # Virtio drivers
> #
> # CONFIG_VIRTIO_BALLOON is not set
> # CONFIG_VIRTIO_MMIO is not set
> 
> #
> # Microsoft Hyper-V guest support
> #
> # CONFIG_STAGING is not set
> CONFIG_CLKDEV_LOOKUP=y
> CONFIG_HAVE_CLK_PREPARE=y
> CONFIG_COMMON_CLK=y
> 
> #
> # Common Clock Framework
> #
> # CONFIG_COMMON_CLK_DEBUG is not set
> 
> #
> # Hardware Spinlock drivers
> #
> CONFIG_CLKSRC_MMIO=y
> CONFIG_IOMMU_SUPPORT=y
> CONFIG_OF_IOMMU=y
> 
> #
> # Remoteproc drivers (EXPERIMENTAL)
> #
> 
> #
> # Rpmsg drivers (EXPERIMENTAL)
> #
> # CONFIG_VIRT_DRIVERS is not set
> # CONFIG_PM_DEVFREQ is not set
> # CONFIG_EXTCON is not set
> # CONFIG_MEMORY is not set
> # CONFIG_IIO is not set
> # CONFIG_PWM is not set
> CONFIG_GNET_DRIVER_CLASS=y
> CONFIG_GNET_PROC=y
> CONFIG_GNET_PROC_DEBUG=y
> CONFIG_GNET_ZIGBEE_DRIVER=y
> CONFIG_GNET_ZIGBEE_DEBUG=y
> CONFIG_GNET_OTP=y
> 
> #
> # File systems
> #
> # CONFIG_EXT2_FS is not set
> CONFIG_EXT3_FS=y
> CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
> CONFIG_EXT3_FS_XATTR=y
> # CONFIG_EXT3_FS_POSIX_ACL is not set
> # CONFIG_EXT3_FS_SECURITY is not set
> # CONFIG_EXT4_FS is not set
> CONFIG_JBD=y
> # CONFIG_JBD_DEBUG is not set
> CONFIG_FS_MBCACHE=y
> # CONFIG_REISERFS_FS is not set
> # CONFIG_JFS_FS is not set
> # CONFIG_XFS_FS is not set
> # CONFIG_BTRFS_FS is not set
> # CONFIG_NILFS2_FS is not set
> CONFIG_FS_POSIX_ACL=y
> CONFIG_FILE_LOCKING=y
> CONFIG_FSNOTIFY=y
> CONFIG_DNOTIFY=y
> CONFIG_INOTIFY_USER=y
> # CONFIG_FANOTIFY is not set
> # CONFIG_QUOTA is not set
> # CONFIG_QUOTACTL is not set
> # CONFIG_AUTOFS4_FS is not set
> CONFIG_FUSE_FS=y
> CONFIG_CUSE=y
> CONFIG_GENERIC_ACL=y
> 
> #
> # Caches
> #
> CONFIG_FSCACHE=m
> CONFIG_FSCACHE_STATS=y
> # CONFIG_FSCACHE_HISTOGRAM is not set
> # CONFIG_FSCACHE_DEBUG is not set
> # CONFIG_FSCACHE_OBJECT_LIST is not set
> CONFIG_CACHEFILES=m
> # CONFIG_CACHEFILES_DEBUG is not set
> # CONFIG_CACHEFILES_HISTOGRAM is not set
> 
> #
> # CD-ROM/DVD Filesystems
> #
> # CONFIG_ISO9660_FS is not set
> # CONFIG_UDF_FS is not set
> 
> #
> # DOS/FAT/NT Filesystems
> #
> # CONFIG_MSDOS_FS is not set
> # CONFIG_VFAT_FS is not set
> # CONFIG_NTFS_FS is not set
> 
> #
> # Pseudo filesystems
> #
> CONFIG_PROC_FS=y
> CONFIG_PROC_VMCORE=y
> CONFIG_PROC_SYSCTL=y
> CONFIG_PROC_PAGE_MONITOR=y
> CONFIG_SYSFS=y
> CONFIG_TMPFS=y
> CONFIG_TMPFS_POSIX_ACL=y
> CONFIG_TMPFS_XATTR=y
> # CONFIG_HUGETLB_PAGE is not set
> # CONFIG_CONFIGFS_FS is not set
> CONFIG_MISC_FILESYSTEMS=y
> # CONFIG_ADFS_FS is not set
> # CONFIG_AFFS_FS is not set
> # CONFIG_ECRYPT_FS is not set
> # CONFIG_HFS_FS is not set
> # CONFIG_HFSPLUS_FS is not set
> # CONFIG_BEFS_FS is not set
> # CONFIG_BFS_FS is not set
> # CONFIG_EFS_FS is not set
> # CONFIG_JFFS2_FS is not set
> CONFIG_UBIFS_FS=y
> CONFIG_UBIFS_FS_ADVANCED_COMPR=y
> CONFIG_UBIFS_FS_LZO=y
> CONFIG_UBIFS_FS_ZLIB=y
> # CONFIG_LOGFS is not set
> # CONFIG_CRAMFS is not set
> # CONFIG_SQUASHFS is not set
> # CONFIG_VXFS_FS is not set
> # CONFIG_MINIX_FS is not set
> # CONFIG_OMFS_FS is not set
> # CONFIG_HPFS_FS is not set
> # CONFIG_QNX4FS_FS is not set
> # CONFIG_QNX6FS_FS is not set
> # CONFIG_ROMFS_FS is not set
> # CONFIG_PSTORE is not set
> # CONFIG_SYSV_FS is not set
> # CONFIG_UFS_FS is not set
> CONFIG_NETWORK_FILESYSTEMS=y
> CONFIG_NFS_FS=y
> # CONFIG_NFS_V2 is not set
> CONFIG_NFS_V3=y
> CONFIG_NFS_V3_ACL=y
> CONFIG_NFS_V4=y
> # CONFIG_NFS_SWAP is not set
> # CONFIG_NFS_V4_1 is not set
> CONFIG_ROOT_NFS=y
> # CONFIG_NFS_USE_LEGACY_DNS is not set
> CONFIG_NFS_USE_KERNEL_DNS=y
> # CONFIG_NFSD is not set
> CONFIG_LOCKD=y
> CONFIG_LOCKD_V4=y
> CONFIG_NFS_ACL_SUPPORT=y
> CONFIG_NFS_COMMON=y
> CONFIG_SUNRPC=y
> CONFIG_SUNRPC_GSS=y
> # CONFIG_SUNRPC_DEBUG is not set
> # CONFIG_CEPH_FS is not set
> # CONFIG_CIFS is not set
> # CONFIG_NCP_FS is not set
> # CONFIG_CODA_FS is not set
> # CONFIG_AFS_FS is not set
> CONFIG_NLS=y
> CONFIG_NLS_DEFAULT="iso8859-1"
> # CONFIG_NLS_CODEPAGE_437 is not set
> # CONFIG_NLS_CODEPAGE_737 is not set
> # CONFIG_NLS_CODEPAGE_775 is not set
> # CONFIG_NLS_CODEPAGE_850 is not set
> # CONFIG_NLS_CODEPAGE_852 is not set
> # CONFIG_NLS_CODEPAGE_855 is not set
> # CONFIG_NLS_CODEPAGE_857 is not set
> # CONFIG_NLS_CODEPAGE_860 is not set
> # CONFIG_NLS_CODEPAGE_861 is not set
> # CONFIG_NLS_CODEPAGE_862 is not set
> # CONFIG_NLS_CODEPAGE_863 is not set
> # CONFIG_NLS_CODEPAGE_864 is not set
> # CONFIG_NLS_CODEPAGE_865 is not set
> # CONFIG_NLS_CODEPAGE_866 is not set
> # CONFIG_NLS_CODEPAGE_869 is not set
> # CONFIG_NLS_CODEPAGE_936 is not set
> # CONFIG_NLS_CODEPAGE_950 is not set
> # CONFIG_NLS_CODEPAGE_932 is not set
> # CONFIG_NLS_CODEPAGE_949 is not set
> # CONFIG_NLS_CODEPAGE_874 is not set
> # CONFIG_NLS_ISO8859_8 is not set
> # CONFIG_NLS_CODEPAGE_1250 is not set
> # CONFIG_NLS_CODEPAGE_1251 is not set
> # CONFIG_NLS_ASCII is not set
> # CONFIG_NLS_ISO8859_1 is not set
> # CONFIG_NLS_ISO8859_2 is not set
> # CONFIG_NLS_ISO8859_3 is not set
> # CONFIG_NLS_ISO8859_4 is not set
> # CONFIG_NLS_ISO8859_5 is not set
> # CONFIG_NLS_ISO8859_6 is not set
> # CONFIG_NLS_ISO8859_7 is not set
> # CONFIG_NLS_ISO8859_9 is not set
> # CONFIG_NLS_ISO8859_13 is not set
> # CONFIG_NLS_ISO8859_14 is not set
> # CONFIG_NLS_ISO8859_15 is not set
> # CONFIG_NLS_KOI8_R is not set
> # CONFIG_NLS_KOI8_U is not set
> # CONFIG_NLS_MAC_ROMAN is not set
> # CONFIG_NLS_MAC_CELTIC is not set
> # CONFIG_NLS_MAC_CENTEURO is not set
> # CONFIG_NLS_MAC_CROATIAN is not set
> # CONFIG_NLS_MAC_CYRILLIC is not set
> # CONFIG_NLS_MAC_GAELIC is not set
> # CONFIG_NLS_MAC_GREEK is not set
> # CONFIG_NLS_MAC_ICELAND is not set
> # CONFIG_NLS_MAC_INUIT is not set
> # CONFIG_NLS_MAC_ROMANIAN is not set
> # CONFIG_NLS_MAC_TURKISH is not set
> # CONFIG_NLS_UTF8 is not set
> 
> #
> # Kernel hacking
> #
> CONFIG_PRINTK_TIME=y
> CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
> CONFIG_ENABLE_WARN_DEPRECATED=y
> CONFIG_ENABLE_MUST_CHECK=y
> CONFIG_FRAME_WARN=2048
> # CONFIG_MAGIC_SYSRQ is not set
> # CONFIG_STRIP_ASM_SYMS is not set
> # CONFIG_UNUSED_SYMBOLS is not set
> CONFIG_DEBUG_FS=y
> # CONFIG_HEADERS_CHECK is not set
> # CONFIG_DEBUG_SECTION_MISMATCH is not set
> # CONFIG_DEBUG_KERNEL is not set
> # CONFIG_HARDLOCKUP_DETECTOR is not set
> # CONFIG_PANIC_ON_OOPS is not set
> CONFIG_PANIC_ON_OOPS_VALUE=0
> # CONFIG_SLUB_DEBUG_ON is not set
> # CONFIG_SLUB_STATS is not set
> # CONFIG_SPARSE_RCU_POINTER is not set
> CONFIG_DEBUG_BUGVERBOSE=y
> CONFIG_DEBUG_MEMORY_INIT=y
> # CONFIG_LKDTM is not set
> CONFIG_HAVE_FUNCTION_TRACER=y
> CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
> CONFIG_HAVE_DYNAMIC_FTRACE=y
> CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
> CONFIG_HAVE_C_RECORDMCOUNT=y
> CONFIG_TRACING_SUPPORT=y
> # CONFIG_FTRACE is not set
> CONFIG_DYNAMIC_DEBUG=y
> # CONFIG_DMA_API_DEBUG is not set
> # CONFIG_ATOMIC64_SELFTEST is not set
> # CONFIG_SAMPLES is not set
> CONFIG_HAVE_ARCH_KGDB=y
> # CONFIG_TEST_KSTRTOX is not set
> # CONFIG_STRICT_DEVMEM is not set
> CONFIG_ARM_UNWIND=y
> CONFIG_DEBUG_USER=y
> # CONFIG_OC_ETM is not set
> 
> #
> # Security options
> #
> CONFIG_KEYS=y
> CONFIG_ENCRYPTED_KEYS=y
> CONFIG_KEYS_DEBUG_PROC_KEYS=y
> # CONFIG_SECURITY_DMESG_RESTRICT is not set
> CONFIG_SECURITY=y
> CONFIG_SECURITYFS=y
> CONFIG_SECURITY_NETWORK=y
> CONFIG_SECURITY_NETWORK_XFRM=y
> CONFIG_SECURITY_PATH=y
> CONFIG_LSM_MMAP_MIN_ADDR=32768
> CONFIG_SECURITY_SELINUX=y
> CONFIG_SECURITY_SELINUX_BOOTPARAM=y
> CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
> CONFIG_SECURITY_SELINUX_DISABLE=y
> CONFIG_SECURITY_SELINUX_DEVELOP=y
> CONFIG_SECURITY_SELINUX_AVC_STATS=y
> CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
> # CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
> # CONFIG_SECURITY_TOMOYO is not set
> # CONFIG_SECURITY_APPARMOR is not set
> # CONFIG_SECURITY_YAMA is not set
> # CONFIG_IMA is not set
> # CONFIG_EVM is not set
> CONFIG_DEFAULT_SECURITY_SELINUX=y
> # CONFIG_DEFAULT_SECURITY_DAC is not set
> CONFIG_DEFAULT_SECURITY="selinux"
> CONFIG_CRYPTO=y
> 
> #
> # Crypto core or helper
> #
> CONFIG_CRYPTO_ALGAPI=y
> CONFIG_CRYPTO_ALGAPI2=y
> CONFIG_CRYPTO_AEAD=y
> CONFIG_CRYPTO_AEAD2=y
> CONFIG_CRYPTO_BLKCIPHER=y
> CONFIG_CRYPTO_BLKCIPHER2=y
> CONFIG_CRYPTO_HASH=y
> CONFIG_CRYPTO_HASH2=y
> CONFIG_CRYPTO_RNG=y
> CONFIG_CRYPTO_RNG2=y
> CONFIG_CRYPTO_PCOMP2=y
> CONFIG_CRYPTO_MANAGER=y
> CONFIG_CRYPTO_MANAGER2=y
> # CONFIG_CRYPTO_USER is not set
> # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
> # CONFIG_CRYPTO_GF128MUL is not set
> # CONFIG_CRYPTO_NULL is not set
> CONFIG_CRYPTO_WORKQUEUE=y
> # CONFIG_CRYPTO_CRYPTD is not set
> CONFIG_CRYPTO_AUTHENC=y
> # CONFIG_CRYPTO_TEST is not set
> 
> #
> # Authenticated Encryption with Associated Data
> #
> # CONFIG_CRYPTO_CCM is not set
> # CONFIG_CRYPTO_GCM is not set
> # CONFIG_CRYPTO_SEQIV is not set
> 
> #
> # Block modes
> #
> CONFIG_CRYPTO_CBC=y
> # CONFIG_CRYPTO_CTR is not set
> # CONFIG_CRYPTO_CTS is not set
> CONFIG_CRYPTO_ECB=m
> # CONFIG_CRYPTO_LRW is not set
> # CONFIG_CRYPTO_PCBC is not set
> # CONFIG_CRYPTO_XTS is not set
> 
> #
> # Hash modes
> #
> CONFIG_CRYPTO_HMAC=y
> # CONFIG_CRYPTO_XCBC is not set
> # CONFIG_CRYPTO_VMAC is not set
> 
> #
> # Digest
> #
> # CONFIG_CRYPTO_CRC32C is not set
> # CONFIG_CRYPTO_GHASH is not set
> # CONFIG_CRYPTO_MD4 is not set
> CONFIG_CRYPTO_MD5=y
> # CONFIG_CRYPTO_MICHAEL_MIC is not set
> # CONFIG_CRYPTO_RMD128 is not set
> # CONFIG_CRYPTO_RMD160 is not set
> # CONFIG_CRYPTO_RMD256 is not set
> # CONFIG_CRYPTO_RMD320 is not set
> CONFIG_CRYPTO_SHA1=y
> CONFIG_CRYPTO_SHA256=y
> # CONFIG_CRYPTO_SHA512 is not set
> # CONFIG_CRYPTO_TGR192 is not set
> # CONFIG_CRYPTO_WP512 is not set
> 
> #
> # Ciphers
> #
> CONFIG_CRYPTO_AES=y
> # CONFIG_CRYPTO_ANUBIS is not set
> CONFIG_CRYPTO_ARC4=m
> # CONFIG_CRYPTO_BLOWFISH is not set
> # CONFIG_CRYPTO_CAMELLIA is not set
> # CONFIG_CRYPTO_CAST5 is not set
> # CONFIG_CRYPTO_CAST6 is not set
> CONFIG_CRYPTO_DES=y
> # CONFIG_CRYPTO_FCRYPT is not set
> # CONFIG_CRYPTO_KHAZAD is not set
> # CONFIG_CRYPTO_SALSA20 is not set
> # CONFIG_CRYPTO_SEED is not set
> # CONFIG_CRYPTO_SERPENT is not set
> # CONFIG_CRYPTO_TEA is not set
> # CONFIG_CRYPTO_TWOFISH is not set
> 
> #
> # Compression
> #
> CONFIG_CRYPTO_DEFLATE=y
> # CONFIG_CRYPTO_ZLIB is not set
> CONFIG_CRYPTO_LZO=y
> 
> #
> # Random Number Generation
> #
> # CONFIG_CRYPTO_ANSI_CPRNG is not set
> # CONFIG_CRYPTO_USER_API_HASH is not set
> # CONFIG_CRYPTO_USER_API_SKCIPHER is not set
> # CONFIG_CRYPTO_HW is not set
> # CONFIG_BINARY_PRINTF is not set
> 
> #
> # Library routines
> #
> CONFIG_BITREVERSE=y
> CONFIG_GENERIC_STRNCPY_FROM_USER=y
> CONFIG_GENERIC_STRNLEN_USER=y
> CONFIG_GENERIC_PCI_IOMAP=y
> CONFIG_GENERIC_IO=y
> CONFIG_STMP_DEVICE=y
> CONFIG_CRC_CCITT=m
> CONFIG_CRC16=y
> # CONFIG_CRC_T10DIF is not set
> CONFIG_CRC_ITU_T=m
> CONFIG_CRC32=y
> # CONFIG_CRC32_SELFTEST is not set
> CONFIG_CRC32_SLICEBY8=y
> # CONFIG_CRC32_SLICEBY4 is not set
> # CONFIG_CRC32_SARWATE is not set
> # CONFIG_CRC32_BIT is not set
> # CONFIG_CRC7 is not set
> # CONFIG_LIBCRC32C is not set
> # CONFIG_CRC8 is not set
> CONFIG_AUDIT_GENERIC=y
> CONFIG_ZLIB_INFLATE=y
> CONFIG_ZLIB_DEFLATE=y
> CONFIG_LZO_COMPRESS=y
> CONFIG_LZO_DECOMPRESS=y
> # CONFIG_XZ_DEC is not set
> # CONFIG_XZ_DEC_BCJ is not set
> CONFIG_BCH=y
> CONFIG_HAS_IOMEM=y
> CONFIG_HAS_IOPORT=y
> CONFIG_HAS_DMA=y
> CONFIG_DQL=y
> CONFIG_NLATTR=y
> CONFIG_GENERIC_ATOMIC64=y
> CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
> # CONFIG_AVERAGE is not set
> # CONFIG_CORDIC is not set
> # CONFIG_DDR is not set



From b32955 at freescale.com  Tue Sep  4 22:12:20 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 5 Sep 2012 10:12:20 +0800
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <20120904144826.7b9b7518@halley>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
 <1346686544.3061.75.camel@sauron.fi.intel.com>
 <20120904144826.7b9b7518@halley>
Message-ID: <5046B504.6000608@freescale.com>

? 2012?09?04? 19:48, Shmulik Ladkani ??:
> On Mon, 03 Sep 2012 18:35:44 +0300 Artem Bityutskiy<dedekind1 at gmail.com>  wrote:
>> With the logic I suggested, for this case what I said would basically:
>>
>> 1. Sort. This leads to
>>
>> 100m at 100m(kernel)
>> 1g at 200m(rootfs)
>> 100m(boot)
>>
>> "OFFSET_CONTINOUS" is always the largest and will be at the end when
>> sorting.
>>
>> 2. Verification.
>>
>> We verify for overlaps and gaps. And refuse this one.
> Artem, Huang,
>
> Sorry for the long delay, got busy with urgent matters (found out I need
> to go thru some surgery), I will probably not be available in the
> upcoming days, but I've read the correspondance and wanted to share my
> two cents...
>
> My POV is that sorting and verification is not needed, is troublesome,
> and might affect users in ways they don't expect.
>
> So far, mtdparts commandline parsing has been very lenient and liberal.
> I think we should keep this approach; give the user the flexibility,
> he'll be responsible to provide meaningful cmdline parts for his
> system.
>
> Actually, Huang's initial complaint was that 'parse_cmdline_partitions'
> was too strict - the truncated partition was not registered!
>
> Now, philosophy aside, let's talk about some usecases that might break.
>
> I remember overlapping partitions (more precisely, partition that is a
> subset of another) being common in some embedded systems, where the
> "rootfs" and "kernel" partitions are a subset of the "overall image"
> partition.
> Why break this? if users enjoy the flexibility, and careful not to
> create silly partitions, I'm in favor of keeping the flexibility.
>
> Same goes for sorting.
> If one has a system hacked to work with mtd0 hardcodedly, but mtd0's
> physical location is somewhere at the end of the device, why reorder the
> partitions enumeration affecting this system?
>
> I'd say keep it simple and flexible.
yes, it's really simple and flexible.
But I think it's not wise to export the 0-size partition to user.
The user may confused at this.

And the mtd-utils, such as mtd-info/mtd-debug, do they can work with a 
0-size partition?

thanks
Huang Shijie

> I trust the user to provide meaningful partitions in the cmdline.
>
> Anyways, please consider this approach.
>
> My patch suggestion might look as (and might need some rework):
>
> diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
> index 17b0bd4..f5df613 100644
> --- a/drivers/mtd/cmdlinepart.c
> +++ b/drivers/mtd/cmdlinepart.c
> @@ -324,7 +324,6 @@ static int parse_cmdline_partitions(struct mtd_info *master,
>                                                 "%s: partitioning exceeds flash size, truncating\n",
>                                                 part->mtd_id);
>                                          part->parts[i].size = master->size - offset;
> -                                       part->num_parts = i;
>                                  }
>                                  offset += part->parts[i].size;
>                          }
>
> Regards,
> Shmulik
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>




From shawn.guo at linaro.org  Tue Sep  4 23:51:10 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Wed, 5 Sep 2012 11:51:10 +0800
Subject: RCU warning during UBI file system mount
In-Reply-To: <50462190.7090702@grid-net.com>
References: <5042EC5D.1010207@grid-net.com>
 <1346744796.12610.6.camel@sauron.fi.intel.com>
 <20120904144813.GC2593@linux.vnet.ibm.com>
 <50462190.7090702@grid-net.com>
Message-ID: <20120905035108.GV2362@S2101-09.ap.freescale.net>

On Tue, Sep 04, 2012 at 08:43:12AM -0700, Subodh Nijsure wrote:
> MX28 is ARM device. I removed following from my config and these
> warnings went away.
> 
> CONFIG_CPU_IDLE=y
> CONFIG_CPU_IDLE_GOV_LADDER=y
> CONFIG_CPU_IDLE_GOV_MENU=y
> 
There is no cpuidle implemented on imx28.  I do not understand how
these options influence the result here.

> I have attached the kernel configuration file I used.
> 
> It doesn't affect specific hw I am working with as device is not
> required to enter idle mode.
> I am Cc-ing linux-arm folks,  in case someone on arm platform
> requires CPU idele &, RCU to work.
> 
I just ran a case with CONFIG_CPU_IDLE and RCU support and failed
to reproduce the warning.  Is this something specific to gpmi-nand
or we can see it with any other imx28 drivers/cases?  Sorry, I do
not have NAND flash set up on my imx28 board.

-- 
Regards,
Shawn


From shmulik.ladkani at gmail.com  Wed Sep  5 01:30:20 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Wed, 5 Sep 2012 08:30:20 +0300
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <5046B504.6000608@freescale.com>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
 <1346686544.3061.75.camel@sauron.fi.intel.com>
 <20120904144826.7b9b7518@halley> <5046B504.6000608@freescale.com>
Message-ID: <20120905083020.0bf6b0bd@halley>

On Wed, 5 Sep 2012 10:12:20 +0800 Huang Shijie <b32955 at freescale.com> wrote:
> yes, it's really simple and flexible.
> But I think it's not wise to export the 0-size partition to user.
> The user may confused at this.
> 
> And the mtd-utils, such as mtd-info/mtd-debug, do they can work with a 
> 0-size partition?

I think the 0 sized partition case is really seldom, don't worth the
trouble, the user will probably observe something went wrong in his
cmdline parts specification.

But nevertheless, if we think it's a MUST to forbid the 0 sized
partitions, then amend my patch as follows:

(sorry, didn't even compile tested this, please review and test, if the
approach is acceptible)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 17b0bd4..aed1b8a 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -319,12 +319,22 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 				if (part->parts[i].size == SIZE_REMAINING)
 					part->parts[i].size = master->size - offset;
 
+				if (part->parts[i].size == 0) {
+					printk(KERN_WARNING ERRP
+					       "%s: skipping zero sized partition\n",
+					       part->mtd_id);
+					part->num_parts--;
+					memmove(&part->parts[i],
+						&part->parts[i + 1],
+						sizeof(*part->parts) * (part->num_parts - i));
+					continue;
+				}
+
 				if (offset + part->parts[i].size > master->size) {
 					printk(KERN_WARNING ERRP
 					       "%s: partitioning exceeds flash size, truncating\n",
 					       part->mtd_id);
 					part->parts[i].size = master->size - offset;
-					part->num_parts = i;
 				}
 				offset += part->parts[i].size;
 			}

Also, I'll send a short coding cleanup patch, this loop's indent level
is horrible...

Regards,
Shmulik


From shmulik.ladkani at gmail.com  Wed Sep  5 01:58:03 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Wed, 5 Sep 2012 08:58:03 +0300
Subject: [PATCH] mtd: cmdlinepart: Simplify parse_cmdline_partitions
Message-ID: <20120905085803.4ff5b155@halley>

From: Shmulik Ladkani <shmulik.ladkani at gmail.com>

Simply 'parse_cmdline_partitions': the outer loop iterating over
'partitions' is actually a search loop, it does not execute the inner
loop for each partition, only for the matched partition.

Let's break when search is successful, and move all inner code (relevant
only for the matched partition) outside of the outer loop.

Resulting code is much more readable, and makes the indent level sane.

Signed-off-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>
---
- (should be) coding fix only, semantics aren't changed
- sorry, didn't even compile tested, please verify this is sane, thanks

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 17b0bd4..46951d7 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -308,38 +308,44 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 			return err;
 	}
 
+	/*
+	 * Search for the partition definition matching master->name.
+	 * If master->name is not set, stop at first partition definition.
+	 */
 	for (part = partitions; part; part = part->next) {
-		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id))) {
-			for (i = 0, offset = 0; i < part->num_parts; i++) {
-				if (part->parts[i].offset == OFFSET_CONTINUOUS)
-					part->parts[i].offset = offset;
-				else
-					offset = part->parts[i].offset;
-
-				if (part->parts[i].size == SIZE_REMAINING)
-					part->parts[i].size = master->size - offset;
-
-				if (offset + part->parts[i].size > master->size) {
-					printk(KERN_WARNING ERRP
-					       "%s: partitioning exceeds flash size, truncating\n",
-					       part->mtd_id);
-					part->parts[i].size = master->size - offset;
-					part->num_parts = i;
-				}
-				offset += part->parts[i].size;
-			}
-
-			*pparts = kmemdup(part->parts,
-					sizeof(*part->parts) * part->num_parts,
-					GFP_KERNEL);
-			if (!*pparts)
-				return -ENOMEM;
-
-			return part->num_parts;
+		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id)))
+			break;
+	}
+
+	if (!part)
+		return 0;
+
+	for (i = 0, offset = 0; i < part->num_parts; i++) {
+		if (part->parts[i].offset == OFFSET_CONTINUOUS)
+			part->parts[i].offset = offset;
+		else
+			offset = part->parts[i].offset;
+
+		if (part->parts[i].size == SIZE_REMAINING)
+			part->parts[i].size = master->size - offset;
+
+		if (offset + part->parts[i].size > master->size) {
+			printk(KERN_WARNING ERRP
+					"%s: partitioning exceeds flash size, truncating\n",
+					part->mtd_id);
+			part->parts[i].size = master->size - offset;
+			part->num_parts = i;
 		}
+		offset += part->parts[i].size;
 	}
 
-	return 0;
+	*pparts = kmemdup(part->parts,
+			sizeof(*part->parts) * part->num_parts,
+			GFP_KERNEL);
+	if (!*pparts)
+		return -ENOMEM;
+
+	return part->num_parts;
 }
 



From josh.wu at atmel.com  Wed Sep  5 02:00:42 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Wed,  5 Sep 2012 14:00:42 +0800
Subject: [PATCH] mtd: atmel_nand: fix the compile error which miss label
 "err_ecc_ioremap".
Message-ID: <1346824842-18875-1-git-send-email-josh.wu@atmel.com>


Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
 drivers/mtd/nand/atmel_nand.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 6a5a35b..9144557 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1399,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		res = atmel_of_init_port(host, pdev->dev.of_node);
 		if (res)
-			goto err_nand_ioremap;
+			goto err_ecc_ioremap;
 	} else {
 		memcpy(&host->board, pdev->dev.platform_data,
 		       sizeof(struct atmel_nand_data));
@@ -1560,6 +1560,7 @@ err_no_card:
 	platform_set_drvdata(pdev, NULL);
 	if (host->dma_chan)
 		dma_release_channel(host->dma_chan);
+err_ecc_ioremap:
 	iounmap(host->io_base);
 err_nand_ioremap:
 	kfree(host);
-- 
1.7.9.5



From Iwo.Mergler at netcommwireless.com  Wed Sep  5 04:28:36 2012
From: Iwo.Mergler at netcommwireless.com (Iwo Mergler)
Date: Wed, 5 Sep 2012 18:28:36 +1000
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <1346685918.3061.66.camel@sauron.fi.intel.com>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 ,<1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 ,<1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>,
 <1346685918.3061.66.camel@sauron.fi.intel.com>
Message-ID: <6871BC8982B258468985EE735D2C57524E269AFB88@ntcex01.corp.netcomm.com.au>

On Tue, 4 Sep 2012 01:25:18 +1000
Artem Bityutskiy <dedekind1 at gmail.com> wrote:
>
> So basically you test that ECC works, and you are trying to be
> independent on the NAND HW and the ECC type. Right?
> 
> How about mtd_nandecc test? How is it different? Do we need 2 tests?
> Why?
> 

Akinobu already said it - mtd_nandecc tests the implementation for
software ECC, while mtd_nandbiterrs pokes holes into real NAND
FLASH pages until the ECC (software or hardware) falls over.

It's a test for the NAND driver, rather than the ECC implementation.
The pattern I'm using is not sufficient to guarantee that all possible
error constellations are caught. There is not enough endurance
in the FLASH or indeed time in the universe to do that. :-)

But it will tell you how many '1'->'0' bit errors it could introduce into
every subpage full of random data, before the whole page comes
back as uncorrectable.

In a nutshell, I got fed up by having to fix yet another vendor-supplied
NAND driver which claimed to support BCH8 hardware ECC but in
reality considered a single bit error as 'uncorrectable'.

So I submitted my test code in the hope that NAND driver authors
can use it to validate the ECC handling.


Best regards,

Iwo

______________________________________________________________________
This communication contains information which may be confidential or privileged. The information is intended solely for the use of the individual or entity named above.  If you are not the intended recipient, be aware that any disclosure, copying, distribution or use of the contents of this information is prohibited.  If you have received this communication in error, please notify me by telephone immediately.
______________________________________________________________________


From sstuart at hrsb.ns.ca  Wed Sep  5 05:30:13 2012
From: sstuart at hrsb.ns.ca (Stuart, Sonja)
Date: Wed, 5 Sep 2012 06:30:13 -0300
Subject: 3%Loan contact us via email @ (bestleadinglnders@undgs.org 
Message-ID: <AF8116182E01AC4EB3DAB601EEB98D2124B10711@HRSBMAIL.hrsb.ns.ca>

You are welcome to BEST LEADING LENDER INC. A Home where financial needs are solved and Dreams Fulfilled to Satisfaction.This is to inform the general public that BEST LEADING LENDER INC. is currently giving out loan @3% interest with a fixed repayments of 20 to 50 years ONLY and have the funds transferred directly to your bank account in your country.

3%Loan contact us via email @ (bestleadinglnders at undgs.org ) with your informations 
FILL OUT THE BORROWER'S INFORMATION:
Best Regaed
Stuart, Sonja




From sachin.kamat at linaro.org  Wed Sep  5 06:01:32 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed,  5 Sep 2012 15:31:32 +0530
Subject: =?UTF-8?q?=5BPATCH=5D=20mtd=3A=20nand/gpio=3A=20Use=20module=5Fplatform=5Fdriver=20macro?=
Message-ID: <1346839292-31001-1-git-send-email-sachin.kamat@linaro.org>

module_platform_driver simplifies the code by eliminating
module_init and module_exit calls.

Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
---
 drivers/mtd/nand/gpio.c |   15 +--------------
 1 files changed, 1 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c
index ce6a284..bc73bc5 100644
--- a/drivers/mtd/nand/gpio.c
+++ b/drivers/mtd/nand/gpio.c
@@ -417,20 +417,7 @@ static struct platform_driver gpio_nand_driver = {
 	},
 };
 
-static int __init gpio_nand_init(void)
-{
-	printk(KERN_INFO "GPIO NAND driver, ? 2004 Simtec Electronics\n");
-
-	return platform_driver_register(&gpio_nand_driver);
-}
-
-static void __exit gpio_nand_exit(void)
-{
-	platform_driver_unregister(&gpio_nand_driver);
-}
-
-module_init(gpio_nand_init);
-module_exit(gpio_nand_exit);
+module_platform_driver(gpio_nand_driver);
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Ben Dooks <ben at simtec.co.uk>");
-- 
1.7.4.1



From josh.wu at atmel.com  Wed Sep  5 06:24:44 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Wed, 05 Sep 2012 18:24:44 +0800
Subject: [PATCH] mtd: atmel_nand: fix the compile error which miss label
 "err_ecc_ioremap".
In-Reply-To: <1346824842-18875-1-git-send-email-josh.wu@atmel.com>
References: <1346824842-18875-1-git-send-email-josh.wu@atmel.com>
Message-ID: <5047286C.4060705@atmel.com>

Hi, all

This patch is for latest l2-mtd.git tree. It fixes the compile error 
after JC's commit: b654a9a4

On 9/5/2012 2:00 PM, Josh Wu wrote:
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
>   drivers/mtd/nand/atmel_nand.c |    3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 6a5a35b..9144557 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -1399,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>   	if (pdev->dev.of_node) {
>   		res = atmel_of_init_port(host, pdev->dev.of_node);
>   		if (res)
> -			goto err_nand_ioremap;
> +			goto err_ecc_ioremap;
>   	} else {
>   		memcpy(&host->board, pdev->dev.platform_data,
>   		       sizeof(struct atmel_nand_data));
> @@ -1560,6 +1560,7 @@ err_no_card:
>   	platform_set_drvdata(pdev, NULL);
>   	if (host->dma_chan)
>   		dma_release_channel(host->dma_chan);
> +err_ecc_ioremap:
>   	iounmap(host->io_base);
>   err_nand_ioremap:
>   	kfree(host);

Best Regards,
Josh Wu


From akinobu.mita at gmail.com  Wed Sep  5 06:42:55 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Wed, 5 Sep 2012 19:42:55 +0900
Subject: [PATCH v3 07/11] mtd: mtd_nandecctest: generalize injecting bit
 errors function for ecc code
In-Reply-To: <1346753195.12610.43.camel@sauron.fi.intel.com>
References: <1346677206-13621-1-git-send-email-akinobu.mita@gmail.com>
 <1346677206-13621-8-git-send-email-akinobu.mita@gmail.com>
 <1346753195.12610.43.camel@sauron.fi.intel.com>
Message-ID: <CAC5umyjdg6B8ps20L+HeTfai-Ea8xqR0hsYBMCRkcHp6G9-0Hg@mail.gmail.com>

2012/9/4 Artem Bityutskiy <artem.bityutskiy at linux.intel.com>:
> On Mon, 2012-09-03 at 22:00 +0900, Akinobu Mita wrote:
>> In order to inject deliberate bit errors into the ecc code which only
>> has 3 bytes, this adjusts the bitops usage in inject_single_bit_error()
>> which is currently only used for injecting into the 256 or 512 bytes
>> data block.
>>
>> Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
>> Cc: David Woodhouse <dwmw2 at infradead.org>
>> Cc: linux-mtd at lists.infradead.org
>> Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
>
> I do not understand the commit message and the patch.
>> ---
>>  drivers/mtd/tests/mtd_nandecctest.c | 13 +++++++++++--
>>  1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
>> index d3e8873..0274f73 100644
>> --- a/drivers/mtd/tests/mtd_nandecctest.c
>> +++ b/drivers/mtd/tests/mtd_nandecctest.c
>> @@ -7,13 +7,22 @@
>>  #include <linux/slab.h>
>>  #include <linux/mtd/nand_ecc.h>
>>
>> +#include <asm/byteorder.h>
>
> I think you do not need to include this.

OK, I'll remove this.

>> +
>>  #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
>>
>> +#ifdef __LITTLE_ENDIAN
>> +#define __change_bit_le(nr, addr) __change_bit(nr, addr)
>> +#else
>> +#define __change_bit_le(nr, addr) \
>> +             __change_bit((nr) ^ ((BITS_PER_LONG - 1) & ~0x7), addr)
>> +#endif
>
> Why is this "#ifdef" needed? Can you please add a comment explaining
> this? Which problem do you solve by adding '__change_bit_le()' ?

Sorry for that imcomplete commit message.  I'll update with this:

mtd: mtd_nandecctest: support injecting bit error for ecc code

Currently inject_single_bit_error() is used to inject single bit error
into randomly selected bit position of the 256 or 512 bytes data block.

Later change will add tests which inject bit errors into the ecc code.
Unfortunately, inject_single_bit_error() doesn't work for the ecc code
which is not a multiple of sizeof(unsigned long).

Because bit fliping at random position is done by __change_bit().
For example, flipping bit position 0 by __change_bit(0, addr) modifies
3rd byte (32bit) or 7th byte (64bit) on big-endian systems.

Using little-endian version of bitops can fix this issue.  But
little-endian version of __change_bit is not yet available.
So this defines __change_bit_le() locally in a similar fashion to
asm-generic/bitops/le.h and use it.

...

Also I'll add this comment:

/*
 * The reason for this __change_bit_le() instead of __change_bit()
 * is to inject bit error properly within the region which is not a
 * multiple of sizeof(unsigned long) on big-endian systems
 */


From simonxwidmer at gmail.com  Wed Sep  5 08:54:59 2012
From: simonxwidmer at gmail.com (simon widmer)
Date: Wed, 05 Sep 2012 14:54:59 +0200
Subject: UBIFS Informations
In-Reply-To: <1346673385.3061.48.camel@sauron.fi.intel.com>
References: <503F7685.8030707@gmail.com>
 <1346673385.3061.48.camel@sauron.fi.intel.com>
Message-ID: <50474BA3.2070404@gmail.com>

Update: I tested on Kernel 2.6.24-24 without success. The same manner if 
i want to mount the image. What I discovered is that i noted earlier 
that i have to compile with:

$ mkfs.ubifs -q -r $PATH\/data_h -m 2048 -e 129024 -c 2047 -o temp_h.img
$ ubinize -o data_h.img -m 2048 -p 128KiB -s 512 ubinize_h.cfg

and i have no idea what option "-q" is (neither does mkfs.ubifs). so I 
just kicked it and compiled with:

$ mkfs.ubifs -r $PATH\/data_h -m 2048 -e 129024 -c 2047 -o temp_h.img
$ ubinize -o data_h.img -m 2048 -p 128KiB -s 512 ubinize_h.cfg

ubinize.cfg looks this way:

[data_h]
mode=ubi
image=temp_h.img
vol_id=0
vol_size=4MiB
vol_type=static
vol_name=data_h
vol_flags=autoresize

and the attaching procedure as follows:

UBI: attaching mtd8 to ubi0
UBI: physical eraseblock size:   131072 bytes (128 KiB)
UBI: logical eraseblock size:    129024 bytes
UBI: smallest flash I/O unit:    2048
UBI: sub-page size:              512
UBI: VID header offset:          512 (aligned 512)
UBI: data offset:                2048
UBI: attached mtd8 to ubi0
UBI: MTD device name:            "data_h"
UBI: MTD device size:            4 MiB
UBI: number of good PEBs:        32
UBI: number of bad PEBs:         0
UBI: max. allowed volumes:       128
UBI: wear-leveling threshold:    4096
UBI: number of internal volumes: 1
UBI: number of user volumes:     1
UBI: available PEBs:             0
UBI: total number of reserved PEBs: 32
UBI: number of PEBs reserved for bad PEB handling: 2
UBI: max/mean erase counter: 2/0
UBI: image sequence number: 165352633
UBI: background thread "ubi_bgt0d" started, PID 497

and finally the mounting procedure:

UBIFS error (pid 529): ubifs_read_node: bad node type (0 but expected 6)
UBIFS error (pid 529): ubifs_read_node: bad node at LEB 0:0
mount: wrong fs type, bad option, bad superblock on ubi0_0,
        missing codepage or helper program, or other error
        (UBIFS error (pid 529): ubifs_read_node: bad node type (0 but 
expected 6)
for several filesystems (e.g. nfUBIFS error (pid 529): ubifs_read_node: 
bad node at LEB 0:0
s, cifs) you might
        need a /sbin/mount.<type> helper program)
        In some cases useful info is found in syslog - try
        dmesg | tail  or so





From festevam at gmail.com  Wed Sep  5 09:27:33 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  5 Sep 2012 10:27:33 -0300
Subject: [PATCH] mtd: gpmi-nand: Improve logging style
Message-ID: <1346851653-28117-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Improve logging style by prefixing the pr_ messages with "gpmi_nand".

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index c46be6c..9493507 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -18,6 +18,9 @@
  * with this program; if not, write to the Free Software Foundation, Inc.,
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/clk.h>
 #include <linux/slab.h>
 #include <linux/interrupt.h>
@@ -114,7 +117,7 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this)
 	/* We use the same ECC strength for all chunks. */
 	geo->ecc_strength = get_ecc_strength(this);
 	if (!geo->ecc_strength) {
-		pr_err("We get a wrong ECC strength.\n");
+		pr_err("wrong ECC strength.\n");
 		return -EINVAL;
 	}
 
@@ -1685,9 +1688,9 @@ static int __init gpmi_nand_init(void)
 
 	err = platform_driver_register(&gpmi_nand_driver);
 	if (err == 0)
-		printk(KERN_INFO "GPMI NAND driver registered. (IMX)\n");
+		pr_info("driver registered.\n");
 	else
-		pr_err("i.MX GPMI NAND driver registration failed\n");
+		pr_err("driver registration failed.\n");
 	return err;
 }
 
-- 
1.7.9.5



From festevam at gmail.com  Wed Sep  5 10:35:24 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  5 Sep 2012 11:35:24 -0300
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
Message-ID: <1346855725-31726-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Using module_platform_driver() makes the code smaller and cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
This patch depends on: "mtd: gpmi-nand: Improve logging style"

 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   29 +++++++----------------------
 1 file changed, 7 insertions(+), 22 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 9493507..5999b15 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1651,6 +1651,8 @@ static int __devinit gpmi_nand_probe(struct platform_device *pdev)
 	if (ret)
 		goto exit_nfc_init;
 
+	dev_info(this->dev, "driver registered.\n");
+
 	return 0;
 
 exit_nfc_init:
@@ -1658,10 +1660,12 @@ exit_nfc_init:
 exit_acquire_resources:
 	platform_set_drvdata(pdev, NULL);
 	kfree(this);
+	dev_err(this->dev, "driver registration failed: %d\n", ret);
+
 	return ret;
 }
 
-static int __exit gpmi_nand_remove(struct platform_device *pdev)
+static int __devexit gpmi_nand_remove(struct platform_device *pdev)
 {
 	struct gpmi_nand_data *this = platform_get_drvdata(pdev);
 
@@ -1678,29 +1682,10 @@ static struct platform_driver gpmi_nand_driver = {
 		.of_match_table = gpmi_nand_id_table,
 	},
 	.probe   = gpmi_nand_probe,
-	.remove  = __exit_p(gpmi_nand_remove),
+	.remove  = __devexit_p(gpmi_nand_remove),
 	.id_table = gpmi_ids,
 };
-
-static int __init gpmi_nand_init(void)
-{
-	int err;
-
-	err = platform_driver_register(&gpmi_nand_driver);
-	if (err == 0)
-		pr_info("driver registered.\n");
-	else
-		pr_err("driver registration failed.\n");
-	return err;
-}
-
-static void __exit gpmi_nand_exit(void)
-{
-	platform_driver_unregister(&gpmi_nand_driver);
-}
-
-module_init(gpmi_nand_init);
-module_exit(gpmi_nand_exit);
+module_platform_driver(gpmi_nand_driver);
 
 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
-- 
1.7.9.5



From festevam at gmail.com  Wed Sep  5 10:35:25 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  5 Sep 2012 11:35:25 -0300
Subject: [PATCH 2/2] mtd: mxc_nand: Convert to platform driver
In-Reply-To: <1346855725-31726-1-git-send-email-festevam@gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
Message-ID: <1346855725-31726-2-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

Using module_platform_driver() makes the code smaller and cleaner.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/mtd/nand/mxc_nand.c |   18 +++---------------
 1 file changed, 3 insertions(+), 15 deletions(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index e59a45f..cc8b1e1 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1389,7 +1389,7 @@ static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
 	return 0;
 }
 
-static int __init mxcnd_probe(struct platform_device *pdev)
+static int __devinit mxcnd_probe(struct platform_device *pdev)
 {
 	struct nand_chip *this;
 	struct mtd_info *mtd;
@@ -1581,22 +1581,10 @@ static struct platform_driver mxcnd_driver = {
 		   .owner = THIS_MODULE,
 		   .of_match_table = of_match_ptr(mxcnd_dt_ids),
 	},
+	.probe = mxcnd_probe,
 	.remove = __devexit_p(mxcnd_remove),
 };
-
-static int __init mxc_nd_init(void)
-{
-	return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
-}
-
-static void __exit mxc_nd_cleanup(void)
-{
-	/* Unregister the device structure */
-	platform_driver_unregister(&mxcnd_driver);
-}
-
-module_init(mxc_nd_init);
-module_exit(mxc_nd_cleanup);
+module_platform_driver(mxcnd_driver);
 
 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 MODULE_DESCRIPTION("MXC NAND MTD driver");
-- 
1.7.9.5



From festevam at gmail.com  Wed Sep  5 10:52:27 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed,  5 Sep 2012 11:52:27 -0300
Subject: [PATCH] mtd: mxc_nand: Adapt the clock name to the new clock framework
Message-ID: <1346856747-32694-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

With the new i.mx clock framework the mxc_nand clock is registered as:
    
clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0")
    
So we do not need to pass "nfc" string and can use NULL instead.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/mtd/nand/mxc_nand.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index cc8b1e1..b0c81bf 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -1425,7 +1425,7 @@ static int __devinit mxcnd_probe(struct platform_device *pdev)
 	this->write_buf = mxc_nand_write_buf;
 	this->read_buf = mxc_nand_read_buf;
 
-	host->clk = devm_clk_get(&pdev->dev, "nfc");
+	host->clk = devm_clk_get(&pdev->dev, NULL);
 	if (IS_ERR(host->clk))
 		return PTR_ERR(host->clk);
 
-- 
1.7.9.5



From computersforpeace at gmail.com  Wed Sep  5 14:19:57 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 5 Sep 2012 11:19:57 -0700
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 <1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 <1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
Message-ID: <CAN8TOE_ax=8inGyZxS+nTfcSkskyNvHEh9ipnOTVu-moB4FqjA@mail.gmail.com>

On Thu, Aug 30, 2012 at 3:59 PM, Iwo Mergler
<Iwo.Mergler at netcommwireless.com> wrote:
> This tests ECC biterror recovery on a single NAND page. Mostly intended
> to test ECC hardware and low-level NAND driver.
>
> There are two test modes:

Why does this test even need to be in the kernel? Can't it be done
easily in userspace? I think it could even be a simple script that
utilizes flash_erase + nandwrite / nanddump with the -n (no ECC)
option. And anything that's lacking in nandwrite for this
functionality could easily be added there (for instance, support
erasure in nandwrite, rather than having to use flash_erase).

I would also note that this test doesn't explicitly test for bad
blocks, although it should fail when running the erase command.

> diff --git a/drivers/mtd/tests/mtd_nandbiterrs.c b/drivers/mtd/tests/mtd_nandbiterrs.c
> new file mode 100644
> index 0000000..94e908e
> --- /dev/null
> +++ b/drivers/mtd/tests/mtd_nandbiterrs.c
> @@ -0,0 +1,460 @@
...
> +static unsigned page_offset;
> +module_param(page_offset, uint, S_IRUGO);
> +MODULE_PARM_DESC(page_offset, "Page number relative to dev start");

Why use a page number? For erase, we'll be affecting many adjacent
pages, so this might be an unclear parameter to the user. Is there a
good reason not to use an entire eraseblock as the unit of test? Also,
is there a reason to use page number vs. eraseblock number vs. offset
as the input parameter?

> +static loff_t   offset;     /* Offset of the page we're using. */
> +static unsigned eraseblock; /* Eraseblock number for our page. */
> +
> +/* We assume that the ECC can correct up to a certain number
> + * of biterrors per subpage. */
> +static unsigned subsize;  /* Size of subpages */
> +static unsigned subcount; /* Number of subpages per page */
> +
> +static struct mtd_info *mtd;   /* MTD device */
> +
> +static uint8_t *wbuffer; /* One page write / compare buffer */
> +static uint8_t *rbuffer; /* One page read buffer */

Why are all of these globals? It seems like the read_page(),
write_page(), and rewrite_page() functions would be more sensible (and
safely extendible) if they had an extra parameter for the address. And
do you really need to represent the same value (offset) in three
different ways (offset, page offset, eraseblock)? In fact,

> +static int erase_block(void)

This isn't a very intuitive function prototype; I would normally
expect an address or block number parameter. Ditto for the following.
But this is just part of the argument of whether everything should be
provided as global variables...

> +/* Writes wbuffer to page */
> +static int write_page(int log)
...
> +/* Re-writes the data area while leaving the OOB alone. */
> +static int rewrite_page(int log)
...
> +/* Reads page into rbuffer. Returns number of corrected bit errors (>=0)
> + * or error (<0) */
> +static int read_page(int log)
...
> +/* Verifies rbuffer against random sequence */
> +static int verify_page(int log)

Brian


From marex at denx.de  Wed Sep  5 14:55:18 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 5 Sep 2012 20:55:18 +0200
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <1346855725-31726-1-git-send-email-festevam@gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
Message-ID: <201209052055.19123.marex@denx.de>

Dear Fabio Estevam,

> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Using module_platform_driver() makes the code smaller and cleaner.

You did not document the dev_info() etc. addition, dunno if it's important or 
not.

Otherwise,

Reviewed-by: Marek Vasut <marex at denx.de>

> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> This patch depends on: "mtd: gpmi-nand: Improve logging style"
> 
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   29
> +++++++---------------------- 1 file changed, 7 insertions(+), 22
> deletions(-)
> 
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 9493507..5999b15 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -1651,6 +1651,8 @@ static int __devinit gpmi_nand_probe(struct
> platform_device *pdev) if (ret)
>  		goto exit_nfc_init;
> 
> +	dev_info(this->dev, "driver registered.\n");
> +
>  	return 0;
> 
>  exit_nfc_init:
> @@ -1658,10 +1660,12 @@ exit_nfc_init:
>  exit_acquire_resources:
>  	platform_set_drvdata(pdev, NULL);
>  	kfree(this);
> +	dev_err(this->dev, "driver registration failed: %d\n", ret);
> +
>  	return ret;
>  }
> 
> -static int __exit gpmi_nand_remove(struct platform_device *pdev)
> +static int __devexit gpmi_nand_remove(struct platform_device *pdev)
>  {
>  	struct gpmi_nand_data *this = platform_get_drvdata(pdev);
> 
> @@ -1678,29 +1682,10 @@ static struct platform_driver gpmi_nand_driver = {
>  		.of_match_table = gpmi_nand_id_table,
>  	},
>  	.probe   = gpmi_nand_probe,
> -	.remove  = __exit_p(gpmi_nand_remove),
> +	.remove  = __devexit_p(gpmi_nand_remove),
>  	.id_table = gpmi_ids,
>  };
> -
> -static int __init gpmi_nand_init(void)
> -{
> -	int err;
> -
> -	err = platform_driver_register(&gpmi_nand_driver);
> -	if (err == 0)
> -		pr_info("driver registered.\n");
> -	else
> -		pr_err("driver registration failed.\n");
> -	return err;
> -}
> -
> -static void __exit gpmi_nand_exit(void)
> -{
> -	platform_driver_unregister(&gpmi_nand_driver);
> -}
> -
> -module_init(gpmi_nand_init);
> -module_exit(gpmi_nand_exit);
> +module_platform_driver(gpmi_nand_driver);
> 
>  MODULE_AUTHOR("Freescale Semiconductor, Inc.");
>  MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");

Best regards,
Marek Vasut


From festevam at gmail.com  Wed Sep  5 15:00:42 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 5 Sep 2012 16:00:42 -0300
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <201209052055.19123.marex@denx.de>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
 <201209052055.19123.marex@denx.de>
Message-ID: <CAOMZO5DD+6keJ6jkQL-AHzhdobG84=3H_r2HPOFR7apFgKYtYA@mail.gmail.com>

Hi Marek,

On Wed, Sep 5, 2012 at 3:55 PM, Marek Vasut <marex at denx.de> wrote:
> Dear Fabio Estevam,
>
>> From: Fabio Estevam <fabio.estevam at freescale.com>
>>
>> Using module_platform_driver() makes the code smaller and cleaner.
>
> You did not document the dev_info() etc. addition, dunno if it's important or
> not.

It is not an addition. I just moved  "pr_info("driver registered.\n")"
 from gpmi_nand_init, (which is removed by this patch) to the probe
function.

Regards,

Fabio Estevam


From marex at denx.de  Wed Sep  5 15:23:54 2012
From: marex at denx.de (Marek Vasut)
Date: Wed, 5 Sep 2012 21:23:54 +0200
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <CAOMZO5DD+6keJ6jkQL-AHzhdobG84=3H_r2HPOFR7apFgKYtYA@mail.gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
 <201209052055.19123.marex@denx.de>
 <CAOMZO5DD+6keJ6jkQL-AHzhdobG84=3H_r2HPOFR7apFgKYtYA@mail.gmail.com>
Message-ID: <201209052123.54695.marex@denx.de>

Dear Fabio Estevam,

> Hi Marek,
> 
> On Wed, Sep 5, 2012 at 3:55 PM, Marek Vasut <marex at denx.de> wrote:
> > Dear Fabio Estevam,
> > 
> >> From: Fabio Estevam <fabio.estevam at freescale.com>
> >> 
> >> Using module_platform_driver() makes the code smaller and cleaner.
> > 
> > You did not document the dev_info() etc. addition, dunno if it's
> > important or not.
> 
> It is not an addition. I just moved  "pr_info("driver registered.\n")"
>  from gpmi_nand_init, (which is removed by this patch) to the probe
> function.

Ah, just noticed. I'd say drop it completely then, there's now value in this 
print (or make it pr_debug() ). Besides, the init call was called only once if 
compiled in / every time if built as a module. The probe call is done per GPMI 
nand driver instance.

> Regards,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From festevam at gmail.com  Wed Sep  5 15:51:52 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Wed, 5 Sep 2012 16:51:52 -0300
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <201209052123.54695.marex@denx.de>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
 <201209052055.19123.marex@denx.de>
 <CAOMZO5DD+6keJ6jkQL-AHzhdobG84=3H_r2HPOFR7apFgKYtYA@mail.gmail.com>
 <201209052123.54695.marex@denx.de>
Message-ID: <CAOMZO5CjKaMOoc009rDC_RO58J5KO2uWmnQaAuH3SdFAtD0Esw@mail.gmail.com>

On Wed, Sep 5, 2012 at 4:23 PM, Marek Vasut <marex at denx.de> wrote:

> Ah, just noticed. I'd say drop it completely then, there's now value in this
> print (or make it pr_debug() ). Besides, the init call was called only once if

I think we can keep this info. It does not hurt and this is how the
current driver does.

> compiled in / every time if built as a module. The probe call is done per GPMI
> nand driver instance.

,which is fine too.

Regards,

Fabio Estevam


From b32955 at freescale.com  Wed Sep  5 22:12:48 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 6 Sep 2012 10:12:48 +0800
Subject: [PATCH] mtd: gpmi-nand: Improve logging style
In-Reply-To: <1346851653-28117-1-git-send-email-festevam@gmail.com>
References: <1346851653-28117-1-git-send-email-festevam@gmail.com>
Message-ID: <504806A0.6030804@freescale.com>

? 2012?09?05? 21:27, Fabio Estevam ??:
> From: Fabio Estevam <fabio.estevam at freescale.com>
>
> Improve logging style by prefixing the pr_ messages with "gpmi_nand".
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
>  drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> index c46be6c..9493507 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> @@ -18,6 +18,9 @@
>   * with this program; if not, write to the Free Software Foundation, Inc.,
>   * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
>   */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
>  #include <linux/clk.h>
>  #include <linux/slab.h>
>  #include <linux/interrupt.h>
> @@ -114,7 +117,7 @@ int common_nfc_set_geometry(struct gpmi_nand_data *this)
>  	/* We use the same ECC strength for all chunks. */
>  	geo->ecc_strength = get_ecc_strength(this);
>  	if (!geo->ecc_strength) {
> -		pr_err("We get a wrong ECC strength.\n");
> +		pr_err("wrong ECC strength.\n");
>  		return -EINVAL;
>  	}
>  
> @@ -1685,9 +1688,9 @@ static int __init gpmi_nand_init(void)
>  
>  	err = platform_driver_register(&gpmi_nand_driver);
>  	if (err == 0)
> -		printk(KERN_INFO "GPMI NAND driver registered. (IMX)\n");
> +		pr_info("driver registered.\n");
>  	else
> -		pr_err("i.MX GPMI NAND driver registration failed\n");
> +		pr_err("driver registration failed.\n");
>  	return err;
>  }
>  
thanks.

Acked-by: Huang Shijie <b32955 at freescale.com>

Huang Shijie



From Iwo.Mergler at netcommwireless.com  Wed Sep  5 23:37:13 2012
From: Iwo.Mergler at netcommwireless.com (Iwo Mergler)
Date: Thu, 6 Sep 2012 13:37:13 +1000
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <CAN8TOE_ax=8inGyZxS+nTfcSkskyNvHEh9ipnOTVu-moB4FqjA@mail.gmail.com>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 <1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 <1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>,
 <CAN8TOE_ax=8inGyZxS+nTfcSkskyNvHEh9ipnOTVu-moB4FqjA@mail.gmail.com>
Message-ID: <6871BC8982B258468985EE735D2C57524E269AFB89@ntcex01.corp.netcomm.com.au>


Hi Brian,

thanks for commenting.

Please be aware that this test aims at MTD driver developers,
so I expect the 'users' to know all about their flash geometries
and not be surprised by whole block erases and such. :-)

More answers below.


Best regards,

Iwo

On Thu, 6 Sep 2012 04:19:57 +1000
Brian Norris <computersforpeace at gmail.com> wrote:
> On Thu, Aug 30, 2012 at 3:59 PM, Iwo Mergler
> <Iwo.Mergler at netcommwireless.com> wrote:
> > This tests ECC biterror recovery on a single NAND page. Mostly intended
> > to test ECC hardware and low-level NAND driver.
> >
> > There are two test modes:
> 
> Why does this test even need to be in the kernel? Can't it be done
> easily in userspace? I think it could even be a simple script that
> utilizes flash_erase + nandwrite / nanddump with the -n (no ECC)
> option. And anything that's lacking in nandwrite for this
> functionality could easily be added there (for instance, support
> erasure in nandwrite, rather than having to use flash_erase).

You are right. The same can be said about most of the other
tests too.

Personally, I appreciate these tests being where they are
because they are most useful to driver developers and as
such are more accessible in the kernel than in userspace.

On new embedded systems, we often have to develop MTD drivers
before we have a rootfs, since the rootfs is supposed to live in the MTD.
MTD is often the first hardware driver to get ported / written for a new
system.

With the current test arrangement I can, with minimal edits,
run any test from within the MTD driver under development.

> I would also note that this test doesn't explicitly test for bad
> blocks, although it should fail when running the erase command.

Fair enough. Usually, by the time I need this test, I know the
locations of all bad block by heart. :-)

> > +static unsigned page_offset;
> > +module_param(page_offset, uint, S_IRUGO);
> > +MODULE_PARM_DESC(page_offset, "Page number relative to dev start");
> 
> Why use a page number? For erase, we'll be affecting many adjacent
> pages, so this might be an unclear parameter to the user. Is there a
> good reason not to use an entire eraseblock as the unit of test? Also,
> is there a reason to use page number vs. eraseblock number vs. offset
> as the input parameter?

Mostly because loff_t isn't supported as a parameter type, so I can't
specify offsets beyond 4G.

Erase block number would work as well. There isn't much to be learned
from applying the test to all pages of a block, but in rare circumstances
I'd like to be able to control which page of the block to test anyway.

It would of course be possible to specify the offset  as separate
erase block numbers and page numbers. I don't have a strong
preference either way.

> 
> > +static loff_t   offset;     /* Offset of the page we're using. */
> > +static unsigned eraseblock; /* Eraseblock number for our page. */
> > +
> > +/* We assume that the ECC can correct up to a certain number
> > + * of biterrors per subpage. */
> > +static unsigned subsize;  /* Size of subpages */
> > +static unsigned subcount; /* Number of subpages per page */
> > +
> > +static struct mtd_info *mtd;   /* MTD device */
> > +
> > +static uint8_t *wbuffer; /* One page write / compare buffer */
> > +static uint8_t *rbuffer; /* One page read buffer */
> 
> Why are all of these globals? It seems like the read_page(),
> write_page(), and rewrite_page() functions would be more sensible (and
> safely extendible) if they had an extra parameter for the address. And
> do you really need to represent the same value (offset) in three
> different ways (offset, page offset, eraseblock)? In fact,
> 

I had to force myself ;-). My excuse is that I copied the style of
the other tests, because of a probably misguided sense of consistency.

______________________________________________________________________
This communication contains information which may be confidential or privileged. The information is intended solely for the use of the individual or entity named above.  If you are not the intended recipient, be aware that any disclosure, copying, distribution or use of the contents of this information is prohibited.  If you have received this communication in error, please notify me by telephone immediately.
______________________________________________________________________


From jbe at pengutronix.de  Thu Sep  6 04:56:12 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 6 Sep 2012 10:56:12 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator for
 NFC v1.
In-Reply-To: <1345825064-9147-1-git-send-email-gcembed@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
Message-ID: <201209061056.12386.jbe@pengutronix.de>

Hi Ga?tan,

Ga?tan Carlier wrote:
> Any comments for this patch ?

Sorry, a little bit late.

> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> Warning: The same solution needs to be applied to the boot loader and the
> flash programmer.

What sense does it make to swap the bytes at offset 0x7D0 and 0x835?

Background: the NFC in the i.MX27/i.MX31 (NFCv1) and i.MX25/i.MX35 (NFCv2) can 
only handle 512 byte pages with 16 bit OOB at once. To get them work with 2 k 
page NANDs they only do the 512 + 16 step four times. The result is, a 2 k 
page NAND is not handled as 2 k data and 64 bytes OOB, its handled instead as
a stream of 2112 bytes:

               |<-------- 2112 bytes --------->|
               512+16 | 512+16 | 512+16 | 512+16

Which means the NFC mixes data and OOB/checksums into its internal SRAM. But 
all upper routines still use this SRAM content with a 2048 (data) + 64 (OOB) 
bytes layout (to be more precise also the NFC hardware uses this layout). 
Result is, the factory bad block markers are lost, because the NFC stores the 
first 48 bytes from each OOB into the SRAM's data area (beginning with offset 
2000 (= 0x7D0) in the data area).

So, the main goal of this swap patch should be to keep the factory bad block 
markers _and_ to make use of them.

But the i.MX driver does not register its own bad block pattern description, 
so the default one is used with the BBM at position NAND_LARGE_BADBLOCK_POS 
(which means offset 0 in the OOB area).

So, I think, all upper layers still search for the BBM at offset 0 of the OOB 
area, which results to SRAM's offset 0x800 (for NFCv1) and not 0x835. This 
means this patch keeps the factory bad block markers, but they won't still be 
used as expected.

IMHO the bytes at SRAM's offset 0x7D0 and 0x800 for the NFCv1 must be swapped 
(and 0x7D0 and 0x1000 for the NFCv2) to keep the factory bad block markers 
_and_ to make use of them. Or am I wrong?

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From gcembed at gmail.com  Thu Sep  6 05:49:35 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Thu, 06 Sep 2012 11:49:35 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
Message-ID: <504871AF.7040809@gmail.com>

Hi Javier,
On 09/06/2012 11:14 AM, javier Martin wrote:
> Hi Ga?tan,
> has this behavior been documented by Freescale anywhere?
It is not documented but this value come from patch for RedBoot (eCos) 
provided by Freescale :
ecos_20050912.tar.gz + redboot_mx27pdk.zip (that includes 
patch-redboot-200840-base.bz2, patch-redboot-200840-mx27.bz2 and 
patch-redboot-200840-mx27pdk.bz2).
I don't have official document. I learned this bug at a training and 
they said : Check the box "BI SWAP" in Freescale Advanced Toolkit and 
that's it.
The sources of kernel 2.6.22 that gave us also have this bugfix in patch.
That is all that I know/have.
>
> I understand that the 0x835 offset is the offset meant for BI in the
> real spare area for 8 bit NANDs. However, this value is not correct
> for 16 bits. It should be 0x83A instead [1].
Have I to add a Test on the width of the bus of current NAND ?
>
> Furthermore, what I can't guess is where that 0x7D0 comes from. I know
> J?rgen described something related to the spare area being mixed with
> the data (main) area but, is there any documentation about it we can
> check?
In the ecos patch, there is the patch
#define NAND_MAIN_BUF3                  (NFC_BASE + 0x600)
#define NAND_SPAR_BUF3                  (NFC_BASE + 0x830)
// read column 464-465 byte but only 464 for bad block marker^M
#define BAD_BLK_MARKER_464          (NAND_MAIN_BUF3 + 464)^M
// read column 4-5 byte, but only 5 is used for swapped main area data^M
#define BAD_BLK_MARKER_SP_5         (NAND_SPAR_BUF3 + 4)^M

>
> Regards.
>
> [1] page 704, Freescale, i.MX27 Reference Manual, Rev. 0.4, 06/2012.
> [2] http://lists.infradead.org/pipermail/linux-mtd/2011-July/036885.html
>
Juergen Beisert have sent an email few minutes earlier about this patch. 
I still have to read it.
Regards,
Ga?tan Carlier.


From jbe at pengutronix.de  Thu Sep  6 06:44:01 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 6 Sep 2012 12:44:01 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <504871AF.7040809@gmail.com>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
 <504871AF.7040809@gmail.com>
Message-ID: <201209061244.02071.jbe@pengutronix.de>

Ga?tan Carlier wrote:
> Hi Javier,
>
> On 09/06/2012 11:14 AM, javier Martin wrote:
> > Hi Ga?tan,
> > has this behavior been documented by Freescale anywhere?

There is an application note available 
called "FSL_AppNote_Nand_Flash_Bad_Block_Management_for_Linux_BSP.pdf"
which describes the behaviour.

After reading a page from NAND into the internal NFC's SRAM, the data layout 
looks like:

SRAM Offset               real NAND's Data
---------------- SRAM data area ---------------------
  0
  .                     [   0 ...  511] 512 Byte page data
 511
 512
  .                     [ 528 ... 1039] 512 Byte page data
1023
1024
  .                     [1056 ... 1567] 512 Byte page data
1535
1536
  .                     [1584 ... 2047] 464 Byte page data
1999
2000
  .                     [   0 ...   47] 48 Byte OOB data
2047

-------------- SRAM OOB area ----------------------------
2048     0x800
  .                     [ 512 ...  527] 16 Byte page data
2063
2064     0x810
  .                     [1040 ... 1055] 16 Byte page data
2079
2080     0x820
  .                     [1568 ... 1583] 16 Byte page data
2095
2096     0x830
  .                     [  48 ...   63] 16 Byte OOB data
2112

> > Furthermore, what I can't guess is where that 0x7D0 comes from. I know
> > J?rgen described something related to the spare area being mixed with
> > the data (main) area but, is there any documentation about it we can
> > check?

See the table above: if you are interested in the byte at offset 0 in the 
NAND's OOB area, you must read the byte at offset 2000 (= 0x7D0) in the SRAM 
area instead.

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-5121-206917-5128 |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |


From jbe at pengutronix.de  Thu Sep  6 06:57:26 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 6 Sep 2012 12:57:26 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <504871AF.7040809@gmail.com>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
 <504871AF.7040809@gmail.com>
Message-ID: <201209061257.26566.jbe@pengutronix.de>

Ga?tan Carlier wrote:
> [...]
> > Furthermore, what I can't guess is where that 0x7D0 comes from. I know
> > J?rgen described something related to the spare area being mixed with
> > the data (main) area but, is there any documentation about it we can
> > check?

Maybe this image could help to understand:

http://imagebin.org/227389

jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From jbe at pengutronix.de  Thu Sep  6 07:07:52 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 6 Sep 2012 13:07:52 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <201209061257.26566.jbe@pengutronix.de>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
 <504871AF.7040809@gmail.com> <201209061257.26566.jbe@pengutronix.de>
Message-ID: <201209061307.53014.jbe@pengutronix.de>

Juergen Beisert wrote:
> Ga?tan Carlier wrote:
> > [...]
> >
> > > Furthermore, what I can't guess is where that 0x7D0 comes from. I know
> > > J?rgen described something related to the spare area being mixed with
> > > the data (main) area but, is there any documentation about it we can
> > > check?
>
> Maybe this image could help to understand:
>
> http://imagebin.org/227389

Ups, just recognized the green line points to the wrong page offset. Sorry. 
But the rest should show the real behaviour of these NFCs.

jbe

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | http://www.pengutronix.de/  |


From javier.martin at vista-silicon.com  Thu Sep  6 07:31:09 2012
From: javier.martin at vista-silicon.com (javier Martin)
Date: Thu, 6 Sep 2012 13:31:09 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <201209061307.53014.jbe@pengutronix.de>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
 <504871AF.7040809@gmail.com>
 <201209061257.26566.jbe@pengutronix.de>
 <201209061307.53014.jbe@pengutronix.de>
Message-ID: <CACKLOr1ZA_KzTbj4ntqgaCiQ9pyxD2xj+KcrZBawERmnCYQEqg@mail.gmail.com>

Hi Juergen,

On 6 September 2012 13:07, Juergen Beisert <jbe at pengutronix.de> wrote:
> Juergen Beisert wrote:
>> Ga?tan Carlier wrote:
>> > [...]
>> >
>> > > Furthermore, what I can't guess is where that 0x7D0 comes from. I know
>> > > J?rgen described something related to the spare area being mixed with
>> > > the data (main) area but, is there any documentation about it we can
>> > > check?
>>
>> Maybe this image could help to understand:
>>
>> http://imagebin.org/227389
>
> Ups, just recognized the green line points to the wrong page offset. Sorry.
> But the rest should show the real behaviour of these NFCs.
>

OK, that was very clarifying. I know understand where the offset comes from.

Thank you very much.

Regards.
-- 
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com


From jbe at pengutronix.de  Thu Sep  6 09:03:09 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Thu, 6 Sep 2012 15:03:09 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator for
 NFC v1.
In-Reply-To: <1345825064-9147-1-git-send-email-gcembed@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
Message-ID: <201209061503.09923.jbe@pengutronix.de>

Ga?tan Carlier wrote:
> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> Warning: The same solution needs to be applied to the boot loader and the
> flash programmer.
>
> This is a modified version of patch sent by J?rgen Lambrecht :
> [PATCH] Add 'config IMX_NFC_V1_BISWAP' to swap the Bad block Indicator,
> and use for imx27pdk nand support.
>
>  v3: - use accessor function for I/O memory accesses as suggested by Artem
>        Bityutskiy
>      - rename function name as suggested by Artem Bityutskiy
>
>  v2: - Use a flag in a mxc_nand_platform structure instead of adding option
>        in Kconfig
>
>  v1: - Original patch "Add 'config IMX_NFC_V1_BISWAP'" by J?rgen Lambrecht
>
> Signed-off-by: Ga?tan Carlier <gcembed at gmail.com>

One additional note: If a user intend to boot from NAND (aka "external boot") 
there is one drawback with this patch: the very first page of the NAND will 
be read in hardware to load the bootstrap code. But the hardware doesn't know 
anything about swapping bytes!
So, when writing the very first page of the NAND the swap *must* be omitted 
(which also means the factory bad block marker of the first block in the NAND 
has to be interpreted differently).

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-5121-206917-5128 |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |


From tony at atomide.com  Thu Sep  6 16:36:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 6 Sep 2012 13:36:54 -0700
Subject: [PATCH 6/9] ARM: OMAP: Move gpio.h to include/linux/platform_data
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9DC3AF@DBDE01.ent.ti.com>
References: <20120831004828.28732.902.stgit@muffinssi.local>
 <20120831005234.28732.10624.stgit@muffinssi.local>
 <C8443D0743D26F4388EA172BF4E2A7A93E9DC3AF@DBDE01.ent.ti.com>
Message-ID: <20120906203653.GI1303@atomide.com>

* Mohammed, Afzal <afzal at ti.com> [120903 03:15]:
> Hi,
> 
> On Fri, Aug 31, 2012 at 06:22:34, Tony Lindgren wrote:
> > This way we can remove includes of plat/gpio.h which won't work
> > with the single zImage support.
> > 
> > Note that we also remove the cpu_class_is_omap2() check
> > in gpio-omap.c as the drivers should not call it as we need to
> > make it local to arch/arm/mach-omap2 for single zImage support.
> > 
> > While at it, arrange the related includes in the standard way.
> > 
> > Cc: Grant Likely <grant.likely at secretlab.ca>
> > Cc: Linus Walleij <linus.walleij at linaro.org>
> > Cc: linux-mtd at lists.infradead.org
> > Cc: alsa-devel at alsa-project.org
> > Acked-by: Tony Lindgren <tony at atomide.com>
> 
> I think there is only one Tony ;)

Heh thanks I'll tell myself to replace it with Signed-off-by :)

Tony


From akinobu.mita at gmail.com  Fri Sep  7 12:48:05 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:05 +0900
Subject: [PATCH -next v4 0/5] mtd: mtd_nandecctest: add more tests
Message-ID: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>

This patch series adds several tests cases to mtd_nandecctest module
and tries to cover possible patterns of corruption which can be reliably
corrected or detected.

Changelog
* v4
- fix swapped two ecc arguments for __nand_correct_data()
- remove asm/byteorder include
- add comments
- update commit messages
- remove patches which are already in l2-mtd.git

* v3
- remove unnecessary include
- split into still smaller patches

* v2
- split one patch into smaller patches

Akinobu Mita (5):
  mtd: mtd_nandecctest: support injecting bit error for ecc code
  mtd: mtd_nandecctest: rewrite the test routine
  mtd: mtd_nandecctest: add no corruption test
  mtd: mtd_nandecctest: add single bit error correction test
  mtd: mtd_nandecctest: add double bit error detection tests

 drivers/mtd/tests/mtd_nandecctest.c | 249 ++++++++++++++++++++++++++++++++----
 1 file changed, 226 insertions(+), 23 deletions(-)

Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
-- 
1.7.11.4



From akinobu.mita at gmail.com  Fri Sep  7 12:48:06 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:06 +0900
Subject: [PATCH -next v4 1/5] mtd: mtd_nandecctest: support injecting bit
 error for ecc code
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1347036490-18258-2-git-send-email-akinobu.mita@gmail.com>

Currently inject_single_bit_error() is used to inject single bit error
into randomly selected bit position of the 256 or 512 bytes data block.

Later change will add tests which inject bit errors into the ecc code.
Unfortunately, inject_single_bit_error() doesn't work for the ecc code
which is not a multiple of sizeof(unsigned long).

Because bit fliping at random position is done by __change_bit().
For example, flipping bit position 0 by __change_bit(0, addr) modifies
3rd byte (32bit) or 7th byte (64bit) on big-endian systems.

Using little-endian version of bitops can fix this issue.  But
little-endian version of __change_bit is not yet available.
So this defines __change_bit_le() locally in a similar fashion to
asm-generic/bitops/le.h and use it.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
* v4
- remove include asm/byteorder.h
- add comment for __change_bit_le()

 drivers/mtd/tests/mtd_nandecctest.c | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index d3e8873..d90daf8 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -9,11 +9,25 @@
 
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
 
+/*
+ * The reason for this __change_bit_le() instead of __change_bit() is to inject
+ * bit error properly within the region which is not a multiple of
+ * sizeof(unsigned long) on big-endian systems
+ */
+#ifdef __LITTLE_ENDIAN
+#define __change_bit_le(nr, addr) __change_bit(nr, addr)
+#elif defined(__BIG_ENDIAN)
+#define __change_bit_le(nr, addr) \
+		__change_bit((nr) ^ ((BITS_PER_LONG - 1) & ~0x7), addr)
+#else
+#error "Unknown byte order"
+#endif
+
 static void inject_single_bit_error(void *data, size_t size)
 {
-	unsigned long offset = random32() % (size * BITS_PER_BYTE);
+	unsigned int offset = random32() % (size * BITS_PER_BYTE);
 
-	__change_bit(offset, data);
+	__change_bit_le(offset, data);
 }
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Fri Sep  7 12:48:08 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:08 +0900
Subject: [PATCH -next v4 3/5] mtd: mtd_nandecctest: add no corruption test
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1347036490-18258-4-git-send-email-akinobu.mita@gmail.com>

This adds no corruptin test case listed below:

Prepare data block and ECC data with no corruption, and verify that
the data block is preserved by __nand_correct_data()

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
* v4
- fix swapped two ecc arguments for __nand_correct_data()

 drivers/mtd/tests/mtd_nandecctest.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index 204f796ed..ff97b10 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -48,6 +48,27 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static void no_bit_error(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
+}
+
+static int no_bit_error_verify(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size);
+	if (ret == 0 && !memcmp(correct_data, error_data, size))
+		return 0;
+
+	return -EINVAL;
+}
+
 static void single_bit_error_in_data(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -71,6 +92,11 @@ static int single_bit_error_correct(void *error_data, void *error_ecc,
 
 static const struct nand_ecc_test nand_ecc_test[] = {
 	{
+		.name = "no-bit-error",
+		.prepare = no_bit_error,
+		.verify = no_bit_error_verify,
+	},
+	{
 		.name = "single-bit-error-in-data-correct",
 		.prepare = single_bit_error_in_data,
 		.verify = single_bit_error_correct,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Fri Sep  7 12:48:07 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:07 +0900
Subject: [PATCH -next v4 2/5] mtd: mtd_nandecctest: rewrite the test routine
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1347036490-18258-3-git-send-email-akinobu.mita@gmail.com>

This rewrites the entire test routine in order to make it easy to add more
tests by later changes and minimize duplication of each tests as much as
possible.

Now that each test is described by the members of struct nand_ecc_test:
- name: descriptive testname
- prepare: function to prepare data block and ecc with artifical corruption
- verify: function to verify the result of correcting data block

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
* v4
- fix swapped two ecc arguments for __nand_correct_data()
- add comment for this test

 drivers/mtd/tests/mtd_nandecctest.c | 93 ++++++++++++++++++++++++++++---------
 1 file changed, 70 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index d90daf8..204f796ed 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -7,8 +7,24 @@
 #include <linux/slab.h>
 #include <linux/mtd/nand_ecc.h>
 
+/*
+ * Test the implementation for software ECC
+ *
+ * No actual MTD device is needed, So we don't need to warry about losing
+ * important data by human error.
+ *
+ * This covers possible patterns of corruption which can be reliably corrected
+ * or detected.
+ */
+
 #if defined(CONFIG_MTD_NAND) || defined(CONFIG_MTD_NAND_MODULE)
 
+struct nand_ecc_test {
+	const char *name;
+	void (*prepare)(void *, void *, void *, void *, const size_t);
+	int (*verify)(void *, void *, void *, const size_t);
+};
+
 /*
  * The reason for this __change_bit_le() instead of __change_bit() is to inject
  * bit error properly within the region which is not a multiple of
@@ -23,13 +39,44 @@
 #error "Unknown byte order"
 #endif
 
-static void inject_single_bit_error(void *data, size_t size)
+static void single_bit_error_data(void *error_data, void *correct_data,
+				size_t size)
 {
 	unsigned int offset = random32() % (size * BITS_PER_BYTE);
 
-	__change_bit_le(offset, data);
+	memcpy(error_data, correct_data, size);
+	__change_bit_le(offset, error_data);
+}
+
+static void single_bit_error_in_data(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	single_bit_error_data(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
+}
+
+static int single_bit_error_correct(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size);
+	if (ret == 1 && !memcmp(correct_data, error_data, size))
+		return 0;
+
+	return -EINVAL;
 }
 
+static const struct nand_ecc_test nand_ecc_test[] = {
+	{
+		.name = "single-bit-error-in-data-correct",
+		.prepare = single_bit_error_in_data,
+		.verify = single_bit_error_correct,
+	},
+};
+
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
 			void *correct_ecc, const size_t size)
 {
@@ -46,14 +93,14 @@ static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
 			DUMP_PREFIX_NONE, 16, 1, correct_ecc, 3, false);
 }
 
-static int nand_ecc_test(const size_t size)
+static int nand_ecc_test_run(const size_t size)
 {
+	int i;
 	int err = 0;
 	void *error_data;
 	void *error_ecc;
 	void *correct_data;
 	void *correct_ecc;
-	char testname[30];
 
 	error_data = kmalloc(size, GFP_KERNEL);
 	error_ecc = kmalloc(3, GFP_KERNEL);
@@ -65,25 +112,25 @@ static int nand_ecc_test(const size_t size)
 		goto error;
 	}
 
-	sprintf(testname, "nand-ecc-%zu", size);
-
 	get_random_bytes(correct_data, size);
-
-	memcpy(error_data, correct_data, size);
-	inject_single_bit_error(error_data, size);
-
 	__nand_calculate_ecc(correct_data, size, correct_ecc);
-	__nand_calculate_ecc(error_data, size, error_ecc);
-	__nand_correct_data(error_data, correct_ecc, error_ecc, size);
-
-	if (memcmp(correct_data, error_data, size)) {
-		pr_err("mtd_nandecctest: not ok - %s\n", testname);
-		dump_data_ecc(error_data, error_ecc, correct_data, correct_ecc,
-				size);
-		err = -EINVAL;
-		goto error;
+
+	for (i = 0; i < ARRAY_SIZE(nand_ecc_test); i++) {
+		nand_ecc_test[i].prepare(error_data, error_ecc,
+				correct_data, correct_ecc, size);
+		err = nand_ecc_test[i].verify(error_data, error_ecc,
+						correct_data, size);
+
+		if (err) {
+			pr_err("mtd_nandecctest: not ok - %s-%zd\n",
+				nand_ecc_test[i].name, size);
+			dump_data_ecc(error_data, error_ecc,
+				correct_data, correct_ecc, size);
+			break;
+		}
+		pr_info("mtd_nandecctest: ok - %s-%zd\n",
+			nand_ecc_test[i].name, size);
 	}
-	pr_info("mtd_nandecctest: ok - %s\n", testname);
 error:
 	kfree(error_data);
 	kfree(error_ecc);
@@ -95,7 +142,7 @@ error:
 
 #else
 
-static int nand_ecc_test(const size_t size)
+static int nand_ecc_test_run(const size_t size)
 {
 	return 0;
 }
@@ -106,11 +153,11 @@ static int __init ecc_test_init(void)
 {
 	int err;
 
-	err = nand_ecc_test(256);
+	err = nand_ecc_test_run(256);
 	if (err)
 		return err;
 
-	return nand_ecc_test(512);
+	return nand_ecc_test_run(512);
 }
 
 static void __exit ecc_test_exit(void)
-- 
1.7.11.4



From akinobu.mita at gmail.com  Fri Sep  7 12:48:09 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:09 +0900
Subject: [PATCH -next v4 4/5] mtd: mtd_nandecctest: add single bit error
 correction test
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1347036490-18258-5-git-send-email-akinobu.mita@gmail.com>

This adds the single bit error correction test case listed below:

Prepare data block without corruption and ECC data with single bit error,
and verify that the data block is preserved by __nand_correct_data().

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
No changes from previous version

 drivers/mtd/tests/mtd_nandecctest.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index ff97b10..caaeb64 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -48,6 +48,31 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static unsigned int random_ecc_bit(size_t size)
+{
+	unsigned int offset = random32() % (3 * BITS_PER_BYTE);
+
+	if (size == 256) {
+		/*
+		 * Don't inject a bit error into the insignificant bits (16th
+		 * and 17th bit) in ECC code for 256 byte data block
+		 */
+		while (offset == 16 || offset == 17)
+			offset = random32() % (3 * BITS_PER_BYTE);
+	}
+
+	return offset;
+}
+
+static void single_bit_error_ecc(void *error_ecc, void *correct_ecc,
+				size_t size)
+{
+	unsigned int offset = random_ecc_bit(size);
+
+	memcpy(error_ecc, correct_ecc, 3);
+	__change_bit_le(offset, error_ecc);
+}
+
 static void no_bit_error(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -76,6 +101,13 @@ static void single_bit_error_in_data(void *error_data, void *error_ecc,
 	memcpy(error_ecc, correct_ecc, 3);
 }
 
+static void single_bit_error_in_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	single_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
 static int single_bit_error_correct(void *error_data, void *error_ecc,
 				void *correct_data, const size_t size)
 {
@@ -101,6 +133,11 @@ static const struct nand_ecc_test nand_ecc_test[] = {
 		.prepare = single_bit_error_in_data,
 		.verify = single_bit_error_correct,
 	},
+	{
+		.name = "single-bit-error-in-ecc-correct",
+		.prepare = single_bit_error_in_ecc,
+		.verify = single_bit_error_correct,
+	},
 };
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From akinobu.mita at gmail.com  Fri Sep  7 12:48:10 2012
From: akinobu.mita at gmail.com (Akinobu Mita)
Date: Sat,  8 Sep 2012 01:48:10 +0900
Subject: [PATCH -next v4 5/5] mtd: mtd_nandecctest: add double bit error
 detection tests
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1347036490-18258-6-git-send-email-akinobu.mita@gmail.com>

This adds the double bit error detection test cases listed below:

* Prepare data block with double bit error and ECC data without
corruption, and verify that the uncorrectable error is detected by
__nand_correct_data().

* Prepare data block with single bit error and ECC data with single bit
error, and verify that the uncorrectable error is detected.

* Prepare data block without corruption and ECC data with double bit
error, and verify that the uncorrectable error is detected.

Signed-off-by: Akinobu Mita <akinobu.mita at gmail.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: linux-mtd at lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
* v4
- fix swapped two ecc arguments for __nand_correct_data()
- remove empty line

 drivers/mtd/tests/mtd_nandecctest.c | 79 +++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/drivers/mtd/tests/mtd_nandecctest.c b/drivers/mtd/tests/mtd_nandecctest.c
index caaeb64..b437fa4 100644
--- a/drivers/mtd/tests/mtd_nandecctest.c
+++ b/drivers/mtd/tests/mtd_nandecctest.c
@@ -48,6 +48,22 @@ static void single_bit_error_data(void *error_data, void *correct_data,
 	__change_bit_le(offset, error_data);
 }
 
+static void double_bit_error_data(void *error_data, void *correct_data,
+				size_t size)
+{
+	unsigned int offset[2];
+
+	offset[0] = random32() % (size * BITS_PER_BYTE);
+	do {
+		offset[1] = random32() % (size * BITS_PER_BYTE);
+	} while (offset[0] == offset[1]);
+
+	memcpy(error_data, correct_data, size);
+
+	__change_bit_le(offset[0], error_data);
+	__change_bit_le(offset[1], error_data);
+}
+
 static unsigned int random_ecc_bit(size_t size)
 {
 	unsigned int offset = random32() % (3 * BITS_PER_BYTE);
@@ -73,6 +89,21 @@ static void single_bit_error_ecc(void *error_ecc, void *correct_ecc,
 	__change_bit_le(offset, error_ecc);
 }
 
+static void double_bit_error_ecc(void *error_ecc, void *correct_ecc,
+				size_t size)
+{
+	unsigned int offset[2];
+
+	offset[0] = random_ecc_bit(size);
+	do {
+		offset[1] = random_ecc_bit(size);
+	} while (offset[0] == offset[1]);
+
+	memcpy(error_ecc, correct_ecc, 3);
+	__change_bit_le(offset[0], error_ecc);
+	__change_bit_le(offset[1], error_ecc);
+}
+
 static void no_bit_error(void *error_data, void *error_ecc,
 		void *correct_data, void *correct_ecc, const size_t size)
 {
@@ -122,6 +153,39 @@ static int single_bit_error_correct(void *error_data, void *error_ecc,
 	return -EINVAL;
 }
 
+static void double_bit_error_in_data(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	double_bit_error_data(error_data, correct_data, size);
+	memcpy(error_ecc, correct_ecc, 3);
+}
+
+static void single_bit_error_in_data_and_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	single_bit_error_data(error_data, correct_data, size);
+	single_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
+static void double_bit_error_in_ecc(void *error_data, void *error_ecc,
+		void *correct_data, void *correct_ecc, const size_t size)
+{
+	memcpy(error_data, correct_data, size);
+	double_bit_error_ecc(error_ecc, correct_ecc, size);
+}
+
+static int double_bit_error_detect(void *error_data, void *error_ecc,
+				void *correct_data, const size_t size)
+{
+	unsigned char calc_ecc[3];
+	int ret;
+
+	__nand_calculate_ecc(error_data, size, calc_ecc);
+	ret = __nand_correct_data(error_data, error_ecc, calc_ecc, size);
+
+	return (ret == -1) ? 0 : -EINVAL;
+}
+
 static const struct nand_ecc_test nand_ecc_test[] = {
 	{
 		.name = "no-bit-error",
@@ -138,6 +202,21 @@ static const struct nand_ecc_test nand_ecc_test[] = {
 		.prepare = single_bit_error_in_ecc,
 		.verify = single_bit_error_correct,
 	},
+	{
+		.name = "double-bit-error-in-data-detect",
+		.prepare = double_bit_error_in_data,
+		.verify = double_bit_error_detect,
+	},
+	{
+		.name = "single-bit-error-in-data-and-ecc-detect",
+		.prepare = single_bit_error_in_data_and_ecc,
+		.verify = double_bit_error_detect,
+	},
+	{
+		.name = "double-bit-error-in-ecc-detect",
+		.prepare = double_bit_error_in_ecc,
+		.verify = double_bit_error_detect,
+	},
 };
 
 static void dump_data_ecc(void *error_data, void *error_ecc, void *correct_data,
-- 
1.7.11.4



From levinsasha928 at gmail.com  Fri Sep  7 12:55:23 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Fri, 7 Sep 2012 18:55:23 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1340959739.2936.28.camel@lappy>
References: <1340959739.2936.28.camel@lappy>
Message-ID: <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>

Ping? Still seeing this with latest master...

On Fri, Jun 29, 2012 at 10:48 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
> Hi all,
>
> I've stumbled on the following while fuzzing with trinity in a KVM tools guest using latest linux-next:
>
> [ 3299.675163] ------------[ cut here ]------------
> [ 3299.676027] kernel BUG at arch/x86/mm/pat.c:279!
> [ 3299.676027] invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC
> [ 3299.678596] CPU 2
> [ 3299.678596] Pid: 21541, comm: trinity-child6 Tainted: G        W    3.5.0-rc4-next-20120628-sasha-00005-g9f23eb7 #479
> [ 3299.678596] RIP: 0010:[<ffffffff810a8b62>]  [<ffffffff810a8b62>] reserve_memtype+0x22/0x3d0
> [ 3299.678596] RSP: 0018:ffff88000ad61bc8  EFLAGS: 00010286
> [ 3299.678596] RAX: 0000000000000000 RBX: fffffffffffff000 RCX: ffff88000ad61c50
> [ 3299.678596] RDX: 0000000000000010 RSI: 0000000000000000 RDI: fffffffffffff000
> [ 3299.696632] RBP: ffff88000ad61c08 R08: 0000000000000010 R09: ffff88002617d5a8
> [ 3299.696632] R10: ffff88003111edc8 R11: 0000000000000001 R12: ffff88000ad61c50
> [ 3299.696632] R13: fffffffffffff000 R14: 0000000000000000 R15: ffff88000ad61d18
> [ 3299.696632] FS:  00007f3ffc3aa700(0000) GS:ffff880029800000(0000) knlGS:0000000000000000
> [ 3299.696632] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 3299.696632] CR2: 0000000000f73ffc CR3: 000000000ad6e000 CR4: 00000000000406e0
> [ 3299.696632] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> [ 3299.696632] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
> [ 3299.696632] Process trinity-child6 (pid: 21541, threadinfo ffff88000ad60000, task ffff88000a390000)
> [ 3299.696632] Stack:
> [ 3299.696632]  ffff88000ad61c18 ffffffff81161bc6 ffff88000ad61c18 fffffffffffff000
> [ 3299.696632]  0000000000000010 0000000000000000 0000000000001000 ffff88000ad61d18
> [ 3299.696632]  ffff88000ad61c88 ffffffff810a8fe2 ffff88000ad61c38 0000000000000086
> [ 3299.696632] Call Trace:
> [ 3299.696632]  [<ffffffff81161bc6>] ? mark_held_locks+0xf6/0x120
> [ 3299.696632]  [<ffffffff810a8fe2>] reserve_pfn_range+0xd2/0x1e0
> [ 3299.696632]  [<ffffffff810a912d>] track_pfn_vma_new+0x3d/0x80
> [ 3299.696632]  [<ffffffff8120c4bc>] remap_pfn_range+0xac/0x380
> [ 3299.696632]  [<ffffffff8220e016>] mtdchar_mmap+0xe6/0x100
> [ 3299.696632]  [<ffffffff812145ae>] mmap_region+0x35e/0x5f0
> [ 3299.696632]  [<ffffffff81214af9>] do_mmap_pgoff+0x2b9/0x350
> [ 3299.696632]  [<ffffffff811ff46c>] ? vm_mmap_pgoff+0x6c/0xb0
> [ 3299.696632]  [<ffffffff811ff484>] vm_mmap_pgoff+0x84/0xb0
> [ 3299.696632]  [<ffffffff8124fd80>] ? fget_raw+0x260/0x260
> [ 3299.696632]  [<ffffffff81211fde>] sys_mmap_pgoff+0x15e/0x190
> [ 3299.696632]  [<ffffffff81985ede>] ? trace_hardirqs_on_thunk+0x3a/0x3f
> [ 3299.696632]  [<ffffffff8106d4dd>] sys_mmap+0x1d/0x20
> [ 3299.696632]  [<ffffffff8372a539>] system_call_fastpath+0x16/0x1b
> [ 3299.696632] Code: 28 5b c9 c3 0f 1f 44 00 00 55 49 89 d0 48 89 e5 41 57 41 56 49 89 f6 41 55 49 89 fd 41 54 49 89 cc 53 48 83 ec 18 48 39 f7 72 0e <0f> 0b 0f 1f 40 00 eb fe 66 0f 1f 44 00 00 8b 3d 1a 5b e3 03 85
> [ 3299.696632] RIP  [<ffffffff810a8b62>] reserve_memtype+0x22/0x3d0
> [ 3299.696632]  RSP <ffff88000ad61bc8>
>


From torvalds at linux-foundation.org  Fri Sep  7 14:14:00 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 7 Sep 2012 11:14:00 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
Message-ID: <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>

Guys, this looks like a MTD and/or io_remap_pfn_range() bug, and it's
not getting any traction.

What the f*ck is mtd_mmap() doing, and why? The problem seems to be an
overflow condition, because reserve_pfn_range() does

    reserve_memtype(paddr, paddr + size, want_flags, &flags);

and then the BUG_ON() in reserve_memtype is

    BUG_ON(start >= end);

so it very much looks like a paddr+size overflow. However, that makes
little sense too, since we're working in "u64", so I suspect the
overflow has happened somewhere earlier.

I really don't see where, though. Could somebody please take a look?
The mtdchar_mmap() types seem insane (why "u32" for len, for example?
And that whole

  off = vma->vm_pgoff << PAGE_SHIFT;

thing looks like it would overflow, since the whole point of pgoff is
that if you shift it up by PAGE_SHIFT you need to also extend to
64-bit etc.

So I would *guess* that it's the mtdchar_mmap() stuff that overflows
due to bad types, but maybe it does deeper than that?

                         Linus

On Fri, Sep 7, 2012 at 9:55 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
> Ping? Still seeing this with latest master...
>
> On Fri, Jun 29, 2012 at 10:48 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
>> Hi all,
>>
>> I've stumbled on the following while fuzzing with trinity in a KVM tools guest using latest linux-next:
>>
>> [ 3299.675163] ------------[ cut here ]------------
>> [ 3299.676027] kernel BUG at arch/x86/mm/pat.c:279!
>> [ 3299.676027] invalid opcode: 0000 [#1] PREEMPT SMP DEBUG_PAGEALLOC
>> [ 3299.678596] CPU 2
>> [ 3299.678596] Pid: 21541, comm: trinity-child6 Tainted: G        W    3.5.0-rc4-next-20120628-sasha-00005-g9f23eb7 #479
>> [ 3299.678596] RIP: 0010:[<ffffffff810a8b62>]  [<ffffffff810a8b62>] reserve_memtype+0x22/0x3d0
>> [ 3299.678596] RSP: 0018:ffff88000ad61bc8  EFLAGS: 00010286
>> [ 3299.678596] RAX: 0000000000000000 RBX: fffffffffffff000 RCX: ffff88000ad61c50
>> [ 3299.678596] RDX: 0000000000000010 RSI: 0000000000000000 RDI: fffffffffffff000
>> [ 3299.696632] RBP: ffff88000ad61c08 R08: 0000000000000010 R09: ffff88002617d5a8
>> [ 3299.696632] R10: ffff88003111edc8 R11: 0000000000000001 R12: ffff88000ad61c50
>> [ 3299.696632] R13: fffffffffffff000 R14: 0000000000000000 R15: ffff88000ad61d18
>> [ 3299.696632] FS:  00007f3ffc3aa700(0000) GS:ffff880029800000(0000) knlGS:0000000000000000
>> [ 3299.696632] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 3299.696632] CR2: 0000000000f73ffc CR3: 000000000ad6e000 CR4: 00000000000406e0
>> [ 3299.696632] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>> [ 3299.696632] DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400
>> [ 3299.696632] Process trinity-child6 (pid: 21541, threadinfo ffff88000ad60000, task ffff88000a390000)
>> [ 3299.696632] Stack:
>> [ 3299.696632]  ffff88000ad61c18 ffffffff81161bc6 ffff88000ad61c18 fffffffffffff000
>> [ 3299.696632]  0000000000000010 0000000000000000 0000000000001000 ffff88000ad61d18
>> [ 3299.696632]  ffff88000ad61c88 ffffffff810a8fe2 ffff88000ad61c38 0000000000000086
>> [ 3299.696632] Call Trace:
>> [ 3299.696632]  [<ffffffff81161bc6>] ? mark_held_locks+0xf6/0x120
>> [ 3299.696632]  [<ffffffff810a8fe2>] reserve_pfn_range+0xd2/0x1e0
>> [ 3299.696632]  [<ffffffff810a912d>] track_pfn_vma_new+0x3d/0x80
>> [ 3299.696632]  [<ffffffff8120c4bc>] remap_pfn_range+0xac/0x380
>> [ 3299.696632]  [<ffffffff8220e016>] mtdchar_mmap+0xe6/0x100
>> [ 3299.696632]  [<ffffffff812145ae>] mmap_region+0x35e/0x5f0
>> [ 3299.696632]  [<ffffffff81214af9>] do_mmap_pgoff+0x2b9/0x350
>> [ 3299.696632]  [<ffffffff811ff46c>] ? vm_mmap_pgoff+0x6c/0xb0
>> [ 3299.696632]  [<ffffffff811ff484>] vm_mmap_pgoff+0x84/0xb0
>> [ 3299.696632]  [<ffffffff8124fd80>] ? fget_raw+0x260/0x260
>> [ 3299.696632]  [<ffffffff81211fde>] sys_mmap_pgoff+0x15e/0x190
>> [ 3299.696632]  [<ffffffff81985ede>] ? trace_hardirqs_on_thunk+0x3a/0x3f
>> [ 3299.696632]  [<ffffffff8106d4dd>] sys_mmap+0x1d/0x20
>> [ 3299.696632]  [<ffffffff8372a539>] system_call_fastpath+0x16/0x1b
>> [ 3299.696632] Code: 28 5b c9 c3 0f 1f 44 00 00 55 49 89 d0 48 89 e5 41 57 41 56 49 89 f6 41 55 49 89 fd 41 54 49 89 cc 53 48 83 ec 18 48 39 f7 72 0e <0f> 0b 0f 1f 40 00 eb fe 66 0f 1f 44 00 00 8b 3d 1a 5b e3 03 85
>> [ 3299.696632] RIP  [<ffffffff810a8b62>] reserve_memtype+0x22/0x3d0
>> [ 3299.696632]  RSP <ffff88000ad61bc8>
>>


From m-karicheri2 at ti.com  Fri Sep  7 14:39:16 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Fri, 7 Sep 2012 18:39:16 +0000
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041B6EDA@DFLE12.ent.ti.com>

>> -----Original Message-----
>> From: Karicheri, Muralidharan
>> Sent: Thursday, August 30, 2012 2:17 PM
>> To: dwmw2 at infradead.org; artem.bityutskiy at linux.intel.com; dbaryshkov at gmail.com;
>> computersforpeace at gmail.com; linux-mtd at lists.infradead.org; linux-
>> kernel at vger.kernel.org; mturquette at linaro.org
>> Cc: Karicheri, Muralidharan
>> Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock framework
>> 
>> As a first step towards migrating davinci platforms to use common clock
>> framework, replace all instances of clk_enable() with clk_prepare_enable()
>> and clk_disable() with clk_disable_unprepare(). Until the platform is
>> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> adds a might_sleep() call and would work without any issues.
>> 
>> This will make it easy later to switch to common clk based implementation
>> of clk driver from DaVinci specific driver.
>> 
>> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> ---
>>  drivers/mtd/nand/davinci_nand.c |    6 +++---
>>  1 file changed, 3 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
>> index d94b03c..6b8cf27 100644
>> --- a/drivers/mtd/nand/davinci_nand.c
>> +++ b/drivers/mtd/nand/davinci_nand.c
>> @@ -656,7 +656,7 @@ static int __init nand_davinci_probe(struct platform_device
>> *pdev)
>>  		goto err_clk;
>>  	}
>> 
>> -	ret = clk_enable(info->clk);
>> +	ret = clk_prepare_enable(info->clk);
>>  	if (ret < 0) {
>>  		dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
>>  			ret);
>> @@ -767,7 +767,7 @@ syndrome_done:
>> 
>>  err_scan:
>>  err_timing:
>> -	clk_disable(info->clk);
>> +	clk_disable_unprepare(info->clk);
>> 
>>  err_clk_enable:
>>  	clk_put(info->clk);
>> @@ -804,7 +804,7 @@ static int __exit nand_davinci_remove(struct platform_device
>> *pdev)
>> 
>>  	nand_release(&info->mtd);
>> 
>> -	clk_disable(info->clk);
>> +	clk_disable_unprepare(info->clk);
>>  	clk_put(info->clk);
>> 
>>  	kfree(info);
>> --
>> 1.7.9.5

subsystem owner,

Could you please review and apply this patch as needed? We need to get this upstream before submitting the patch for Common clock framework support for mach-davinci. If I need to follow a specific procedure to get this merged, please direct me to a process page.

Thanks.

Murali Karicheri
Software Design Engineer



From mturquette at linaro.org  Fri Sep  7 17:28:53 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 07 Sep 2012 14:28:53 -0700
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
Message-ID: <20120907212853.20289.86031@nucleus>

Quoting Murali Karicheri (2012-08-30 11:17:04)
> As a first step towards migrating davinci platforms to use common clock
> framework, replace all instances of clk_enable() with clk_prepare_enable()
> and clk_disable() with clk_disable_unprepare(). Until the platform is
> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
> adds a might_sleep() call and would work without any issues.
> 
> This will make it easy later to switch to common clk based implementation
> of clk driver from DaVinci specific driver.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>

Acked-by: Mike Turquette <mturquette at linaro.org>

> ---
>  drivers/mtd/nand/davinci_nand.c |    6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
> index d94b03c..6b8cf27 100644
> --- a/drivers/mtd/nand/davinci_nand.c
> +++ b/drivers/mtd/nand/davinci_nand.c
> @@ -656,7 +656,7 @@ static int __init nand_davinci_probe(struct platform_device *pdev)
>                 goto err_clk;
>         }
>  
> -       ret = clk_enable(info->clk);
> +       ret = clk_prepare_enable(info->clk);
>         if (ret < 0) {
>                 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
>                         ret);
> @@ -767,7 +767,7 @@ syndrome_done:
>  
>  err_scan:
>  err_timing:
> -       clk_disable(info->clk);
> +       clk_disable_unprepare(info->clk);
>  
>  err_clk_enable:
>         clk_put(info->clk);
> @@ -804,7 +804,7 @@ static int __exit nand_davinci_remove(struct platform_device *pdev)
>  
>         nand_release(&info->mtd);
>  
> -       clk_disable(info->clk);
> +       clk_disable_unprepare(info->clk);
>         clk_put(info->clk);
>  
>         kfree(info);
> -- 
> 1.7.9.5


From m-karicheri2 at ti.com  Fri Sep  7 17:56:22 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Fri, 7 Sep 2012 21:56:22 +0000
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <20120907212853.20289.86031@nucleus>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
 <20120907212853.20289.86031@nucleus>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>

Mike,

How do these patch get to upstream? Does this get merged through davinci maintainer or through individual subsystem maintainers? 

Thanks.

Murali Karicheri
Software Design Engineer


>> -----Original Message-----
>> From: Mike Turquette [mailto:mturquette at linaro.org]
>> Sent: Friday, September 07, 2012 5:29 PM
>> To: Karicheri, Muralidharan; dwmw2 at infradead.org; artem.bityutskiy at linux.intel.com;
>> dbaryshkov at gmail.com; computersforpeace at gmail.com; linux-mtd at lists.infradead.org;
>> linux-kernel at vger.kernel.org
>> Cc: Karicheri, Muralidharan
>> Subject: Re: [PATCH] mtd:nand:clk: preparation for switch to common clock framework
>> 
>> Quoting Murali Karicheri (2012-08-30 11:17:04)
>> > As a first step towards migrating davinci platforms to use common clock
>> > framework, replace all instances of clk_enable() with clk_prepare_enable()
>> > and clk_disable() with clk_disable_unprepare(). Until the platform is
>> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> > adds a might_sleep() call and would work without any issues.
>> >
>> > This will make it easy later to switch to common clk based implementation
>> > of clk driver from DaVinci specific driver.
>> >
>> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> 
>> Acked-by: Mike Turquette <mturquette at linaro.org>
>> 
>> > ---
>> >  drivers/mtd/nand/davinci_nand.c |    6 +++---
>> >  1 file changed, 3 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
>> > index d94b03c..6b8cf27 100644
>> > --- a/drivers/mtd/nand/davinci_nand.c
>> > +++ b/drivers/mtd/nand/davinci_nand.c
>> > @@ -656,7 +656,7 @@ static int __init nand_davinci_probe(struct platform_device
>> *pdev)
>> >                 goto err_clk;
>> >         }
>> >
>> > -       ret = clk_enable(info->clk);
>> > +       ret = clk_prepare_enable(info->clk);
>> >         if (ret < 0) {
>> >                 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
>> >                         ret);
>> > @@ -767,7 +767,7 @@ syndrome_done:
>> >
>> >  err_scan:
>> >  err_timing:
>> > -       clk_disable(info->clk);
>> > +       clk_disable_unprepare(info->clk);
>> >
>> >  err_clk_enable:
>> >         clk_put(info->clk);
>> > @@ -804,7 +804,7 @@ static int __exit nand_davinci_remove(struct platform_device
>> *pdev)
>> >
>> >         nand_release(&info->mtd);
>> >
>> > -       clk_disable(info->clk);
>> > +       clk_disable_unprepare(info->clk);
>> >         clk_put(info->clk);
>> >
>> >         kfree(info);
>> > --
>> > 1.7.9.5

From suresh.b.siddha at intel.com  Fri Sep  7 18:42:58 2012
From: suresh.b.siddha at intel.com (Suresh Siddha)
Date: Fri, 07 Sep 2012 15:42:58 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
Message-ID: <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>

On Fri, 2012-09-07 at 11:14 -0700, Linus Torvalds wrote:
> Guys, this looks like a MTD and/or io_remap_pfn_range() bug, and it's
> not getting any traction.
> 
> What the f*ck is mtd_mmap() doing, and why? The problem seems to be an
> overflow condition, because reserve_pfn_range() does
> 
>     reserve_memtype(paddr, paddr + size, want_flags, &flags);
> 
> and then the BUG_ON() in reserve_memtype is
> 
>     BUG_ON(start >= end);
> 
> so it very much looks like a paddr+size overflow. However, that makes
> little sense too, since we're working in "u64", so I suspect the
> overflow has happened somewhere earlier.
> 
> I really don't see where, though. Could somebody please take a look?
> The mtdchar_mmap() types seem insane (why "u32" for len, for example?
> And that whole
> 
>   off = vma->vm_pgoff << PAGE_SHIFT;
> 
> thing looks like it would overflow, since the whole point of pgoff is
> that if you shift it up by PAGE_SHIFT you need to also extend to
> 64-bit etc.
> 
> So I would *guess* that it's the mtdchar_mmap() stuff that overflows
> due to bad types, but maybe it does deeper than that?
> 

I started to look into this to see if this is a PAT issue but it does
indeed appear to be a mtd mmap issue.

Sasha, Does the appended fix the issue for you?

--8<--
From: Suresh Siddha <suresh.b.siddha at intel.com>
Subject: mtd: check the starting offset to be mmap'd

We need to check if both the starting offset aswell the total length
being mmap'd are with in the limits. With a large starting offset,
offset + (length-to-be-mapped) can wrap and appear smaller than the
limit. Need to check both start and end.

Also fix the types of the variables start, off, len.

Signed-off-by: Suresh Siddha <suresh.b.siddha at intel.com>
---
 drivers/mtd/mtdchar.c |    7 +++----
 1 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
index f2f482b..f79c0fa 100644
--- a/drivers/mtd/mtdchar.c
+++ b/drivers/mtd/mtdchar.c
@@ -1132,16 +1132,15 @@ static int mtdchar_mmap(struct file *file, struct vm_area_struct *vma)
 	struct mtd_file_info *mfi = file->private_data;
 	struct mtd_info *mtd = mfi->mtd;
 	struct map_info *map = mtd->priv;
-	unsigned long start;
-	unsigned long off;
-	u32 len;
+	resource_size_t start, off;
+	unsigned long len;
 
 	if (mtd->type == MTD_RAM || mtd->type == MTD_ROM) {
 		off = vma->vm_pgoff << PAGE_SHIFT;
 		start = map->phys;
 		len = PAGE_ALIGN((start & ~PAGE_MASK) + map->size);
 		start &= PAGE_MASK;
-		if ((vma->vm_end - vma->vm_start + off) > len)
+		if (off >= len || (vma->vm_end - vma->vm_start + off) > len)
 			return -EINVAL;
 
 		off += start;




From torvalds at linux-foundation.org  Fri Sep  7 19:09:59 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 7 Sep 2012 16:09:59 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
Message-ID: <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>

On Fri, Sep 7, 2012 at 3:42 PM, Suresh Siddha <suresh.b.siddha at intel.com> wrote:
> -       unsigned long start;
> -       unsigned long off;
> -       u32 len;
> +       resource_size_t start, off;
> +       unsigned long len;

So since the oops is on x86-64, I don't think it's the "unsigned long"
-> "resource_size_t" part (which can be an issue on 32-bit
architectures, though).

The "u32 len" -> "unsigned long len" thing *might* make a difference, though.

I also think your patch is incomplete even on 32-bit, because this:

>         if (mtd->type == MTD_RAM || mtd->type == MTD_ROM) {
>                 off = vma->vm_pgoff << PAGE_SHIFT;

is still wrong. It probably should be

    off = vma->vm_pgoff;
    off <<= PAGE_SHIFT;

because vm_pgoff may be a 32-bit type, while "resource_size_t" may be
64-bit. Shifting the 32-bit type without a cast (implicit or explicit)
isn't going to help.

That said, we have absolutely *tons* of bugs with this particular
pattern. Just do

    git grep 'vm_pgoff.*<<.*PAGE_SHIFT'

and there are distressingly few casts in there (there's a few, mainly
in fs/proc).

Now, I suspect many of them are fine just because most users probably
are size-limited anyway, but it's a bit distressing stuff. And I
suspect it means we might want to introduce a helper function like

    static inline u64 vm_offset(struct vm_area_struct *vma)
    {
        return (u64)vma->vm_pgoff << PAGE_SHIFT;
    }

or something. Maybe add the "vm_length()" helper while at it too,
since the whole "vma->vm_end - vma->vm_start" thing is so common.

Anyway, since Sasha's oops is clearly not 32-bit, the above issues
don't matter, and it would be interesting to hear if it's the 32-bit
'len' thing that triggers this problem. Still, I can't see how it
would - as far as I can tell, a truncated 'len' would at most result
in spurious early "return -EINVAL", not any real problem.

What are we missing?

Sasha, since you can apparently reproduce it, can you replace the
"BUG_ON()" with just a

 if (start >= end) {
    printf("bogus range %llx - %llx\n", start, end);
    return -EINVAL;
  }

or something.

I'm starting to suspect that maybe it's actually that the length is
*zero*, and start == end, and that we should just return zero for that
case. But let's see what Sasha finds..

              Linus


From mturquette at linaro.org  Fri Sep  7 19:22:41 2012
From: mturquette at linaro.org (Mike Turquette)
Date: Fri, 07 Sep 2012 16:22:41 -0700
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
 <20120907212853.20289.86031@nucleus>
 <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>
Message-ID: <20120907232241.20289.38511@nucleus>

Quoting Karicheri, Muralidharan (2012-09-07 14:56:22)
> Mike,
> 
> How do these patch get to upstream? Does this get merged through davinci maintainer or through individual subsystem maintainers? 
> 

What does scripts/get_maintainer.pl tell you?

Also feel free to make my Acked-by into a Reviewed-by.  I always ge
those two confused.

Regards,
Mike

cant never remembr 

> Thanks.
> 
> Murali Karicheri
> Software Design Engineer
> 
> 
> >> -----Original Message-----
> >> From: Mike Turquette [mailto:mturquette at linaro.org]
> >> Sent: Friday, September 07, 2012 5:29 PM
> >> To: Karicheri, Muralidharan; dwmw2 at infradead.org; artem.bityutskiy at linux.intel.com;
> >> dbaryshkov at gmail.com; computersforpeace at gmail.com; linux-mtd at lists.infradead.org;
> >> linux-kernel at vger.kernel.org
> >> Cc: Karicheri, Muralidharan
> >> Subject: Re: [PATCH] mtd:nand:clk: preparation for switch to common clock framework
> >> 
> >> Quoting Murali Karicheri (2012-08-30 11:17:04)
> >> > As a first step towards migrating davinci platforms to use common clock
> >> > framework, replace all instances of clk_enable() with clk_prepare_enable()
> >> > and clk_disable() with clk_disable_unprepare(). Until the platform is
> >> > switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
> >> > adds a might_sleep() call and would work without any issues.
> >> >
> >> > This will make it easy later to switch to common clk based implementation
> >> > of clk driver from DaVinci specific driver.
> >> >
> >> > Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
> >> 
> >> Acked-by: Mike Turquette <mturquette at linaro.org>
> >> 
> >> > ---
> >> >  drivers/mtd/nand/davinci_nand.c |    6 +++---
> >> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
> >> > index d94b03c..6b8cf27 100644
> >> > --- a/drivers/mtd/nand/davinci_nand.c
> >> > +++ b/drivers/mtd/nand/davinci_nand.c
> >> > @@ -656,7 +656,7 @@ static int __init nand_davinci_probe(struct platform_device
> >> *pdev)
> >> >                 goto err_clk;
> >> >         }
> >> >
> >> > -       ret = clk_enable(info->clk);
> >> > +       ret = clk_prepare_enable(info->clk);
> >> >         if (ret < 0) {
> >> >                 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
> >> >                         ret);
> >> > @@ -767,7 +767,7 @@ syndrome_done:
> >> >
> >> >  err_scan:
> >> >  err_timing:
> >> > -       clk_disable(info->clk);
> >> > +       clk_disable_unprepare(info->clk);
> >> >
> >> >  err_clk_enable:
> >> >         clk_put(info->clk);
> >> > @@ -804,7 +804,7 @@ static int __exit nand_davinci_remove(struct platform_device
> >> *pdev)
> >> >
> >> >         nand_release(&info->mtd);
> >> >
> >> > -       clk_disable(info->clk);
> >> > +       clk_disable_unprepare(info->clk);
> >> >         clk_put(info->clk);
> >> >
> >> >         kfree(info);
> >> > --
> >> > 1.7.9.5


From suresh.b.siddha at intel.com  Fri Sep  7 19:54:05 2012
From: suresh.b.siddha at intel.com (Suresh Siddha)
Date: Fri, 07 Sep 2012 16:54:05 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
Message-ID: <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>

On Fri, 2012-09-07 at 16:09 -0700, Linus Torvalds wrote:
> The "u32 len" -> "unsigned long len" thing *might* make a difference, though.

This I believe doesn't fix the reported BUG. I was trying to address
your previous comment about broken types.

> 
> I also think your patch is incomplete even on 32-bit, because this:
> 
> >         if (mtd->type == MTD_RAM || mtd->type == MTD_ROM) {
> >                 off = vma->vm_pgoff << PAGE_SHIFT;
> 
> is still wrong. It probably should be
> 
>     off = vma->vm_pgoff;
>     off <<= PAGE_SHIFT;
> 
> because vm_pgoff may be a 32-bit type, while "resource_size_t" may be
> 64-bit. Shifting the 32-bit type without a cast (implicit or explicit)
> isn't going to help.

Agree.

> That said, we have absolutely *tons* of bugs with this particular
> pattern. Just do
> 
>     git grep 'vm_pgoff.*<<.*PAGE_SHIFT'
> 
> and there are distressingly few casts in there (there's a few, mainly
> in fs/proc).
> 
> Now, I suspect many of them are fine just because most users probably
> are size-limited anyway, but it's a bit distressing stuff. And I
> suspect it means we might want to introduce a helper function like
> 
>     static inline u64 vm_offset(struct vm_area_struct *vma)
>     {
>         return (u64)vma->vm_pgoff << PAGE_SHIFT;
>     }
> 
> or something. Maybe add the "vm_length()" helper while at it too,
> since the whole "vma->vm_end - vma->vm_start" thing is so common.

Agree.

> Anyway, since Sasha's oops is clearly not 32-bit, the above issues
> don't matter, and it would be interesting to hear if it's the 32-bit
> 'len' thing that triggers this problem. Still, I can't see how it
> would - as far as I can tell, a truncated 'len' would at most result
> in spurious early "return -EINVAL", not any real problem.
> 
> What are we missing?
> 

On Fri, 2012-09-07 at 15:42 -0700, Suresh Siddha wrote:
> -               if ((vma->vm_end - vma->vm_start + off) > len)
> +               if (off >= len || (vma->vm_end - vma->vm_start + off) > len)
>                         return -EINVAL; 

This is the relevant portion that I am thinking will address the BUG.

Essentially the user is trying to mmap at a very large offset (from the
oops it appears "vma->vm_pgoff << PAGE_SHIFT + start" ends up to
"0xfffffffffffff000").

So it appears that the condition "(vma->vm_end - vma->vm_start + off) >
len" might be false because of the wraparound? and doesn't return
-EINVAL.

Let's see what Sasha finds. Anyways the patch does indeed require your
above mentioned vm_pgoff fix for the 32-bit case.

thanks,
suresh





From computersforpeace at gmail.com  Fri Sep  7 20:43:55 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 7 Sep 2012 17:43:55 -0700
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
 <20120907212853.20289.86031@nucleus>
 <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>
Message-ID: <CAN8TOE8tpyPK2V4=YQWP7bK7e5AqFDE27EBpKhn0hj-u6r3HAA@mail.gmail.com>

On Fri, Sep 7, 2012 at 2:56 PM, Karicheri, Muralidharan
<m-karicheri2 at ti.com> wrote:
> How do these patch get to upstream? Does this get merged through davinci maintainer or through individual subsystem maintainers?

I think this driver would be taken by David Woodhouse in his linux-mtd
repo. Usually Artem Bityutskiy gleans the mailing list of patches and
puts them in his l2-mtd-2.6 git repo to help David out. Give it some
time, and I'm sure they'll be taking it. We don't really have a
full-time maintainer!

Brian


From levinsasha928 at gmail.com  Sat Sep  8 04:10:54 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Sat, 08 Sep 2012 10:10:54 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
Message-ID: <504AFD8E.50701@gmail.com>

On 09/08/2012 01:09 AM, Linus Torvalds wrote:
> Sasha, since you can apparently reproduce it, can you replace the
> "BUG_ON()" with just a
> 
>  if (start >= end) {
>     printf("bogus range %llx - %llx\n", start, end);
>     return -EINVAL;
>   }

Replacing it gives me the following:

[   36.231736] bogus range fffffffffffff000 - 0


Thanks,
Sasha


From torvalds at linux-foundation.org  Sat Sep  8 15:57:30 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Sat, 8 Sep 2012 12:57:30 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
Message-ID: <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>

On Fri, Sep 7, 2012 at 4:54 PM, Suresh Siddha <suresh.b.siddha at intel.com> wrote:
>
> Essentially the user is trying to mmap at a very large offset (from the
> oops it appears "vma->vm_pgoff << PAGE_SHIFT + start" ends up to
> "0xfffffffffffff000").

Ok, Sasha confirmed that.

> So it appears that the condition "(vma->vm_end - vma->vm_start + off) >
> len" might be false because of the wraparound? and doesn't return
> -EINVAL.

Ack.

Anyway, that means that the BUG_ON() is likely bogus, but so is the
whole calling convention.

The 4kB range starting at 0xfffffffffffff000 sounds like a *valid*
range, but that requires that we fix the calling convention to not
have that "end" (exclusive) thing. It should either be "end"
(inclusive), or just "len".

So it should either be start=0xfffffffffffff000 end=0xffffffffffffffff
or it should be start=0xfffffffffffff000 len=0x1000.

Or we need to say that we must never accept things at the end of the
64-bit range.

Whatever. Something like this (TOTALLY UNTESTED) attached patch should
get the mtdchar overflows to go away, but it does *not* fix the fact
that the MTRR start/end model is broken. It really is technically
valid to have a resource_size_t range of 0xfffffffffffff000+0x1000,
and right now it causes a BUG_ON() in pat.c.

Suresh?

                    Linus
-------------- next part --------------
A non-text attachment was scrubbed...
Name: patch.diff
Type: application/octet-stream
Size: 2201 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120908/19db0e09/attachment.obj>

From zajec5 at gmail.com  Sun Sep  9 10:32:01 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Sun,  9 Sep 2012 16:32:01 +0200
Subject: [PATCH] mtd: prepare place for BCMA NAND flash driver(s)
Message-ID: <1347201121-20590-1-git-send-email-zajec5@gmail.com>

BCMA bus can contain NAND flash memory, it's registered in system as
platform device. This adds required hooks and place for controler
specific drivers.
At this point it doesn't work yet, so it's marked as BROKEN.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
 drivers/mtd/nand/Kconfig                       |    8 ++
 drivers/mtd/nand/Makefile                      |    1 +
 drivers/mtd/nand/bcm47xxnflash/Makefile        |    3 +
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |   20 +++++
 drivers/mtd/nand/bcm47xxnflash/main.c          |  106 ++++++++++++++++++++++++
 5 files changed, 138 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/Makefile
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/main.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..7460ac2 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -489,6 +489,14 @@ config MTD_NAND_GPMI_NAND
 	 block, such as SD card. So pay attention to it when you enable
 	 the GPMI.
 
+config MTD_NAND_BCM47XXNFLASH
+	tristate "Support for NAND flash on BCMA bus"
+	depends on BCMA_NFLASH && BROKEN
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  NAND flash memories.
+
 config MTD_NAND_PLATFORM
 	tristate "Support for generic platform NAND driver"
 	depends on HAS_IOMEM
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..8aa55d8 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -51,5 +51,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
new file mode 100644
index 0000000..1d0693a
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -0,0 +1,3 @@
+bcm47xxnflash-y				+= main.o
+
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
new file mode 100644
index 0000000..692ea5f
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -0,0 +1,20 @@
+#ifndef __BCM47XXNFLASH_H
+#define __BCM47XXNFLASH_H
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+struct bcm47xxnflash {
+	struct bcma_drv_cc *cc;
+
+	struct nand_chip nand_chip;
+	struct mtd_info mtd;
+
+	unsigned curr_command;
+	int curr_page_addr;
+	int curr_column;
+};
+
+int bcm47xxnflash_nand_bcm4706_init(struct bcm47xxnflash *bcm47xxnflash);
+
+#endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/main.c b/drivers/mtd/nand/bcm47xxnflash/main.c
new file mode 100644
index 0000000..a28feb3
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/main.c
@@ -0,0 +1,106 @@
+/*
+ * BCM47XX NAND flash driver
+ *
+ * Copyright (C) 2012 Rafa? Mi?ecki <zajec5 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+#include "bcm47xxnflash.h"
+
+MODULE_DESCRIPTION("NAND flash driver for BCMA bus");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Rafa? Mi?ecki");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxnflash_probe(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+	struct bcm47xxnflash *b47n;
+	int err = 0;
+
+	b47n = kzalloc(sizeof(*b47n), GFP_KERNEL);
+	if (!b47n) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	b47n->nand_chip.priv = b47n;
+	b47n->mtd.owner = THIS_MODULE;
+	b47n->mtd.priv = &b47n->nand_chip; /* Required */
+	b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash);
+
+	if (0) {
+		/* TODO: init device */
+	} else {
+		pr_err("Device not supported\n");
+		err = -ENOTSUPP;
+	}
+	if (err) {
+		pr_err("Initialization failed: %d\n", err);
+		goto err_init;
+	}
+
+	err = mtd_device_parse_register(&b47n->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		goto err_dev_reg;
+	}
+
+err_dev_reg:
+err_init:
+	kfree(b47n);
+out:
+	return err;
+}
+
+static int __devexit bcm47xxnflash_remove(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+
+	if (nflash->mtd)
+		mtd_device_unregister(nflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcm47xxnflash_driver = {
+	.remove = __devexit_p(bcm47xxnflash_remove),
+	.driver = {
+		.name = "bcma_nflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxnflash_init(void)
+{
+	int err;
+
+	/*
+	 * Platform device "bcma_nflash" exists on SoCs and is registered very
+	 * early, it won't be added during runtime (use platform_driver_probe).
+	 */
+	err = platform_driver_probe(&bcm47xxnflash_driver, bcm47xxnflash_probe);
+	if (err)
+		pr_err("Failed to register serial flash driver: %d\n", err);
+
+	return err;
+}
+
+static void __exit bcm47xxnflash_exit(void)
+{
+	platform_driver_unregister(&bcm47xxnflash_driver);
+}
+
+module_init(bcm47xxnflash_init);
+module_exit(bcm47xxnflash_exit);
-- 
1.7.7



From suresh.b.siddha at intel.com  Sun Sep  9 10:56:40 2012
From: suresh.b.siddha at intel.com (Suresh Siddha)
Date: Sun, 09 Sep 2012 07:56:40 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
Message-ID: <1347202600.5876.7.camel@sbsiddha-ivb>

On Sat, 2012-09-08 at 12:57 -0700, Linus Torvalds wrote:
> Whatever. Something like this (TOTALLY UNTESTED) attached patch should
> get the mtdchar overflows to go away, 

It looks good to me. Acked-by: Suresh Siddha <suresh.b.siddha at intel.com>

Sasha, can you please give this a try?

> but it does *not* fix the fact
> that the MTRR start/end model is broken. It really is technically
> valid to have a resource_size_t range of 0xfffffffffffff000+0x1000,
> and right now it causes a BUG_ON() in pat.c.
> 
> Suresh?

yes but that is not a valid range I think because of the supported
physical address bit limits of the processor and also the max
architecture limit of 52 address bits.

I guess we should be checking for those limits in pat.c, especially bits
above 52 are ignored by the HW and they can easily cause conflicting
aliases with other valid regions. I will get back with a different patch
to fix this.

thanks,
suresh




From torvalds at linux-foundation.org  Sun Sep  9 11:31:57 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Sun, 9 Sep 2012 08:31:57 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1347202600.5876.7.camel@sbsiddha-ivb>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb>
Message-ID: <CA+55aFwej93o7aLe_xwV5CGuT0BDyAz54cyWm6Xe3wj-hCT3PA@mail.gmail.com>

On Sun, Sep 9, 2012 at 7:56 AM, Suresh Siddha <suresh.b.siddha at intel.com> wrote:
>
> yes but that is not a valid range I think because of the supported
> physical address bit limits of the processor and also the max
> architecture limit of 52 address bits.

But how could the caller possibly know that? None of those internal
PAT limits are exposed anywhere.

So doing the BUG_ON() is wrong. I'd suggest changing it to an EINVAL.

In fact, BUG_ON() is *always* wrong, unless it's a "my internal data
structures are so messed up that I cannot continue".

                Linus


From hpa at zytor.com  Sun Sep  9 12:56:17 2012
From: hpa at zytor.com (H. Peter Anvin)
Date: Sun, 09 Sep 2012 09:56:17 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
Message-ID: <504CCA31.2000003@zytor.com>

On 09/08/2012 12:57 PM, Linus Torvalds wrote:
>
> Ack.
>
> Anyway, that means that the BUG_ON() is likely bogus, but so is the
> whole calling convention.
>
> The 4kB range starting at 0xfffffffffffff000 sounds like a *valid*
> range, but that requires that we fix the calling convention to not
> have that "end" (exclusive) thing. It should either be "end"
> (inclusive), or just "len".
>

On x86, it is definitely NOT a valid range.  There is no physical 
addresses there, and there will never be any.

> So it should either be start=0xfffffffffffff000 end=0xffffffffffffffff
> or it should be start=0xfffffffffffff000 len=0x1000.

I would strongly object to the former; that kind of inclusive ranges 
breed a whole class of bugs by themselves.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.



From hpa at zytor.com  Sun Sep  9 13:01:33 2012
From: hpa at zytor.com (H. Peter Anvin)
Date: Sun, 09 Sep 2012 10:01:33 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFwej93o7aLe_xwV5CGuT0BDyAz54cyWm6Xe3wj-hCT3PA@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb>
 <CA+55aFwej93o7aLe_xwV5CGuT0BDyAz54cyWm6Xe3wj-hCT3PA@mail.gmail.com>
Message-ID: <504CCB6D.7070005@zytor.com>

On 09/09/2012 08:31 AM, Linus Torvalds wrote:
> On Sun, Sep 9, 2012 at 7:56 AM, Suresh Siddha <suresh.b.siddha at intel.com> wrote:
>>
>> yes but that is not a valid range I think because of the supported
>> physical address bit limits of the processor and also the max
>> architecture limit of 52 address bits.
>
> But how could the caller possibly know that? None of those internal
> PAT limits are exposed anywhere.
>
> So doing the BUG_ON() is wrong. I'd suggest changing it to an EINVAL.
>
> In fact, BUG_ON() is *always* wrong, unless it's a "my internal data
> structures are so messed up that I cannot continue".
>

I suspect the right answer is doing something like:

	u64 max_phys = 1ULL << boot_cpu_data.x86_phys_bits;

	if (start >= max_phys || end > max_phys || start >= end)
		return -EINVAL;

... although max_phys perhaps should be precalculated and stored in 
struct cpuinfo_x86 instead of being generated de novo.

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.



From dwmw2 at infradead.org  Sun Sep  9 15:04:32 2012
From: dwmw2 at infradead.org (David Woodhouse)
Date: Sun, 09 Sep 2012 20:04:32 +0100
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <504CCA31.2000003@zytor.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <504CCA31.2000003@zytor.com>
Message-ID: <1347217472.2068.35.camel@shinybook.infradead.org>

On Sun, 2012-09-09 at 09:56 -0700, H. Peter Anvin wrote:
> 
> > So it should either be start=0xfffffffffffff000 end=0xffffffffffffffff
> > or it should be start=0xfffffffffffff000 len=0x1000.
> 
> I would strongly object to the former; that kind of inclusive ranges 
> breed a whole class of bugs by themselves.

Another alternative that avoids overflow issues is to use a PFN rather
than a byte address.

-- 
dwmw2
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120909/7ee5c5af/attachment.bin>

From hpa at zytor.com  Sun Sep  9 16:33:38 2012
From: hpa at zytor.com (H. Peter Anvin)
Date: Sun, 09 Sep 2012 13:33:38 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1347217472.2068.35.camel@shinybook.infradead.org>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <504CCA31.2000003@zytor.com>
 <1347217472.2068.35.camel@shinybook.infradead.org>
Message-ID: <504CFD22.3050300@zytor.com>

On 09/09/2012 12:04 PM, David Woodhouse wrote:
> On Sun, 2012-09-09 at 09:56 -0700, H. Peter Anvin wrote:
>>
>>> So it should either be start=0xfffffffffffff000 end=0xffffffffffffffff
>>> or it should be start=0xfffffffffffff000 len=0x1000.
>>
>> I would strongly object to the former; that kind of inclusive ranges
>> breed a whole class of bugs by themselves.
>
> Another alternative that avoids overflow issues is to use a PFN rather
> than a byte address.
>

Except as a result of that logic have a bunch of places which either 
have rounding errors in how they calculate PFNs, or they think they can 
stick PFNs into 32-bit numbers.  :(

	-hpa

-- 
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.



From winesofportugal at fatimasales.com  Sun Sep  9 17:11:31 2012
From: winesofportugal at fatimasales.com (Joe Pereira)
Date: Sun, 9 Sep 2012 22:11:31 +0100
Subject: Portuguese Wines for export with prices
Message-ID: <ANHWDYVD-NV6P-GO75-P7CR-BW14UVK83BR@fatimasales.com>

Dear Importer

We are looking to establish an export of Portuguese wines to your area and would like very much if you would consider our products to include with your inventory.

We are willing to give exclusivity of all our products, which also includes top quality virgin olive oil, for either your area or your country depending on the volume.

Attached are the catalog of the wines and also a price list and some of the awards received.

Portuguese Wine Production

Portugal has long been a world leader in the production and export of wine. Of Portugal's eleven major wine regions, the Douro is by far the most significant to fine wine production. But another more modern success story in Portugal has to do with simple, sweet ros  table wines that are sold under brand names like Mateus and Lancers. Although the heyday of simple roses may have passed, they remain popular worldwide and between these wines and Port, account for roughly 70% of Portuguese wine exports.

What is unique about Portugal is the very large number (upwards of 500) of indigenous grape varietals. Even most wine experts are unfamiliar with the grapes that produce Port, Madeira or any other Portuguese wine. Older vineyards are planted with multiple grape varietals and as a result, sometimes these field blends are so varied that identifying all of the grapes isn't possible. When new vineyards are created, single plantings are now the norm. As modernization continues, Portugal is proving that in spite of a long history of contributions it still has undiscovered potential.

Contacts:
Joe Pereira
Fatima, Portugal
+351 914324195
+351302005703 fax
MSN: aveabba at hotmail.com
GMAIL: jsguerra7 at gmail.com


To be removed click reply and add REMOVE to your subject line and we will do our best to remove you from future mailing lists.

-------------- next part --------------
A non-text attachment was scrubbed...
Name: Cheers Portugal - Oil & Vinegar.pptx
Type: application/octet-stream
Size: 1070511 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120909/aa08fd2d/attachment-0001.obj>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: Cheers Portugal Catalog.pdf
Type: application/pdf
Size: 1107385 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120909/aa08fd2d/attachment-0002.pdf>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: Price list.pdf
Type: application/pdf
Size: 263633 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120909/aa08fd2d/attachment-0003.pdf>

From levinsasha928 at gmail.com  Mon Sep 10 01:17:04 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Mon, 10 Sep 2012 07:17:04 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <504CCA31.2000003@zytor.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <504CCA31.2000003@zytor.com>
Message-ID: <504D77D0.70705@gmail.com>

On 09/09/2012 06:56 PM, H. Peter Anvin wrote:
>>
>> Anyway, that means that the BUG_ON() is likely bogus, but so is the
>> whole calling convention.
>>
>> The 4kB range starting at 0xfffffffffffff000 sounds like a *valid*
>> range, but that requires that we fix the calling convention to not
>> have that "end" (exclusive) thing. It should either be "end"
>> (inclusive), or just "len".
>>
> 
> On x86, it is definitely NOT a valid range.  There is no physical addresses
> there, and there will never be any.

This reminds me a similar issue: If you try to mmap /dev/kmem at an offset which
is not kernel owned (such as 0), you'll get all the way to __pa() before getting
a BUG() about addresses not making sense.

How come there's no arch-specific validation of attempts to access
virtual/physical addresses? In the kmem example I'd assume that something very
early on should be yelling at me about doing something like that, but for some
reason I get all the way to __pa() before getting a BUG() (!).


Thanks,
Sasha


From b32955 at freescale.com  Mon Sep 10 02:01:10 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 10 Sep 2012 14:01:10 +0800
Subject: [PATCH 1/2] mtd: add helpers to set/get features for ONFI nand
Message-ID: <1347256871-18339-1-git-send-email-b32955@freescale.com>

Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
Also add the necessary macros.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/nand_base.c |   50 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/nand.h     |   14 +++++++++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 88f671c..fbc49cc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2700,6 +2700,50 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 }
 
 /**
+ * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @feature_addr: feature address.
+ * @subfeature_para: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para)
+{
+	int status;
+
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature_addr, -1);
+	chip->write_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);
+	status = chip->waitfunc(mtd, chip);
+	if (status & NAND_STATUS_FAIL)
+		return -EIO;
+	return 0;
+}
+
+/**
+ * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @feature_addr: feature address.
+ * @subfeature_para: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para)
+{
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	/* clear the sub feature parameters */
+	memset(subfeature_para, 0, ONFI_SUBFEATURE_PARA_LEN);
+
+	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature_addr, -1);
+	chip->read_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);
+	return 0;
+}
+
+/**
  * nand_suspend - [MTD Interface] Suspend the NAND flash
  * @mtd: MTD device structure
  */
@@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd)
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
+	/* set for ONFI nand */
+	if (!chip->onfi_set_features)
+		chip->onfi_set_features = nand_onfi_set_features;
+	if (!chip->onfi_get_features)
+		chip->onfi_get_features = nand_onfi_get_features;
+
 	/*
 	 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
 	 * selected and we have 256 byte pagesize fallback to software ECC
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8f99d36..641794c 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
 #define NAND_CMD_RESET		0xff
 
 #define NAND_CMD_LOCK		0x2a
@@ -229,6 +231,12 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARA_LEN	4
+
 struct nand_onfi_params {
 	/* rev info and features block */
 	/* 'O' 'N' 'F' 'I'  */
@@ -452,6 +460,8 @@ struct nand_buffers {
  *			non 0 if ONFI supported.
  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
  *			supported, 0 otherwise.
+ * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
  * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
  * @bbt:		[INTERN] bad block table pointer
  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
@@ -494,6 +504,10 @@ struct nand_chip {
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, int oob_required, int page,
 			int cached, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
 
 	int chip_delay;
 	unsigned int options;
-- 
1.7.0.4




From b32955 at freescale.com  Mon Sep 10 02:01:11 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Mon, 10 Sep 2012 14:01:11 +0800
Subject: [PATCH 2/2] mtd: add helpers to get the supportted ONFI timing mode
In-Reply-To: <1347256871-18339-1-git-send-email-b32955@freescale.com>
References: <1347256871-18339-1-git-send-email-b32955@freescale.com>
Message-ID: <1347256871-18339-2-git-send-email-b32955@freescale.com>

add onfi_get_async_timing_mode() to get the supportted asynchronous
timing mode.

add onfi_get_sync_timing_mode() to get the supportted synchronous
timing mode.

Also add the neccessary macros : the timing modes.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 include/linux/mtd/nand.h |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 641794c..83b85a1 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -231,6 +231,14 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0	(1 << 0)
+#define ONFI_TIMING_MODE_1	(1 << 1)
+#define ONFI_TIMING_MODE_2	(1 << 2)
+#define ONFI_TIMING_MODE_3	(1 << 3)
+#define ONFI_TIMING_MODE_4	(1 << 4)
+#define ONFI_TIMING_MODE_5	(1 << 5)
+
 /* ONFI feature address */
 #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
 
@@ -682,4 +690,16 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 	return chip->priv;
 }
 
+/* return the supported asynchronous timing mode. */
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+
 #endif /* __LINUX_MTD_NAND_H */
-- 
1.7.0.4




From richard.genoud at gmail.com  Mon Sep 10 06:31:23 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 10 Sep 2012 12:31:23 +0200
Subject: lseek32 and lseek64
In-Reply-To: <CAN0F+aWY_3GC4Arj+Zj97RJhy-7C7TT0dP2gERw=-WD3vhd6Sg@mail.gmail.com>
References: <CAN0F+aWY_3GC4Arj+Zj97RJhy-7C7TT0dP2gERw=-WD3vhd6Sg@mail.gmail.com>
Message-ID: <CACQ1gAgqBS-v5hSD5Lt7wWVzSC9BEiAfUU83uviBta63yWoAVQ@mail.gmail.com>

[forwarding to linux-mtd ML]
2012/9/10 Cheney Chen <cheneychencl2012 at gmail.com>:
> Dear Richard,
>
> I'm a developer on android os. I porting the MTD utility into android os and
> I find one bug for 8GB nand flash:
>
> # ./ubiformat /dev/ubi0_0
>
> If ubi0_0 offset is larger than 4GB, this partition can't be formatted.
> Finally I found that the 32bit lseek function cause this issue in
> mtd-utility. Becuase the linux kernel 3.0.8 can support the 64bit lseek.
>

Hi,
AFAIK, ubiformat is used on mtd devices (ubiformat /dev/mtd0) not on
ubi volumes.
are you sure it's the command you used ?


From josiahtaubb at yahoo.com  Mon Sep 10 08:40:19 2012
From: josiahtaubb at yahoo.com (Ha Petrick)
Date: Mon, 10 Sep 2012 13:40:19 +0100 (BST)
Subject: I think we can try to make something out of this
Message-ID: <1347280819.53373.YahooMailNeo@web132102.mail.ird.yahoo.com>

Howdy! 
My male friend demonstrated me ur profile page and I became aroused in anticipation of seeing u life and know each other closer. 
I know for sure you wouldn't be against of knowing me better after examining account of mine too. 
What is interesting about me? I'm a tall blonde babe with pretty face and fresh figure. 
My name is Ha and I'm 25 yo. Take a glance at me! 
I will be waiting for u. 
I will be glad to meet u life!


From richard.genoud at gmail.com  Mon Sep 10 08:59:02 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Mon, 10 Sep 2012 14:59:02 +0200
Subject: lseek32 and lseek64
In-Reply-To: <CAN0F+aUuBUWN0_VMZ3rzPc5VNNDSLKivnFkW=32Cbi8eCf2QHA@mail.gmail.com>
References: <CAN0F+aWY_3GC4Arj+Zj97RJhy-7C7TT0dP2gERw=-WD3vhd6Sg@mail.gmail.com>
 <CACQ1gAgqBS-v5hSD5Lt7wWVzSC9BEiAfUU83uviBta63yWoAVQ@mail.gmail.com>
 <CAN0F+aUuBUWN0_VMZ3rzPc5VNNDSLKivnFkW=32Cbi8eCf2QHA@mail.gmail.com>
Message-ID: <CACQ1gAg_s8S8V5AWN4pR9XKqctyeYZpW_mtD3XczDde5Y+9Y4A@mail.gmail.com>

2012/9/10 Cheney Chen <cheneychencl2012 at gmail.com>:
> You are right. ubiformat is used on mtd devices. This bug was found a few
> month ago, now I'm available and this bug is reported. But I make a mistake
> for ubiformat /dev/ubi0_0. I just retry it again and print some log for you.
>
> # mtd utility original file's bin
> # ./ubiformat /dev/mtd/mtd13
> ubiformat: mtd13 (nand), size 6375342080 bytes (5.9 GiB), 1520 eraseblocks
> of 4194304 bytes (4.0 MiB), min. I/O size 16384 bytes
> libscan: scanning eraseblock 512 -- 33 % complete  libmtd: error!: cannot
> seek mtd13 to offset 18446744071562067968
>         error 22 (Invalid argument)
> ubiformat: error!: failed to scan mtd13 (/dev/mtd/mtd13)
>
> # add my patch as bin
> # ./ubiformat /dev/mtd/mtd13
> ubiformat: mtd13 (nand), size 6375342080 bytes (5.9 GiB), 1520 eraseblocks
> of 4194304 bytes (4.0 MiB), min. I/O size 16384 bytes
> libscan: scanning eraseblock 1519 -- 100 % complete
> ubiformat: 1495 eraseblocks are supposedly empty
> ubiformat: 22 bad eraseblocks found, numbers: 166, 313, 359, 556, 623, 624,
> 625, 626, 627, 628, 877, 1313, 1317, 1353, 1512, 1513, 1514, 1515
> , 1516, 1517, 1518, 1519
> ubiformat: warning!: 3 of 1498 eraseblocks contain non-ubifs data
> ubiformat: continue? (yes/no)  yes
> ubiformat: warning!: only 0 of 1498 eraseblocks have valid erase counter
> ubiformat: erase counter 0 will be used for all eraseblocks
> ubiformat: note, arbitrary erase counter value may be specified using -e
> option
> ubiformat: continue? (yes/no)  yes
> ubiformat: use erase counter 0 for all eraseblocks
> ubiformat: formatting eraseblock 1519 -- 100 % complete
>
> The attachment is my patch as a reference.

Please, cc the linux-mtd ML in your emails.

I had a look at your patch, and maybe something like that is better:
diff --git a/ubi-utils/libubigen.c b/ubi-utils/libubigen.c
index 9eaa7f5..d2a949b 100644
--- a/ubi-utils/libubigen.c
+++ b/ubi-utils/libubigen.c
@@ -279,7 +279,7 @@ int ubigen_write_layout_vol(const struct
ubigen_info *ui, int peb1, int peb2,
 	memset(outbuf + ui->data_offs + ui->vtbl_size, 0xFF,
 	       ui->peb_size - ui->data_offs - ui->vtbl_size);

-	seek = peb1 * ui->peb_size;
+	seek = (off_t) peb1 * ui->peb_size;
 	if (lseek(fd, seek, SEEK_SET) != seek) {
 		sys_errmsg("cannot seek output file");
 		goto out_free;
@@ -293,7 +293,7 @@ int ubigen_write_layout_vol(const struct
ubigen_info *ui, int peb1, int peb2,
 		goto out_free;
 	}

-	seek = peb2 * ui->peb_size;
+	seek = (off_t) peb2 * ui->peb_size;
 	if (lseek(fd, seek, SEEK_SET) != seek) {
 		sys_errmsg("cannot seek output file");
 		goto out_free;

because off_t is 64bits if _FILE_OFFSET_BITS=64, wich is the case by
default in common.mk
could you test it ?
-------------- next part --------------
A non-text attachment was scrubbed...
Name: utils.patch
Type: application/octet-stream
Size: 1752 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120910/e06cb728/attachment-0001.obj>

From jbe at pengutronix.de  Mon Sep 10 09:22:08 2012
From: jbe at pengutronix.de (Juergen Beisert)
Date: Mon, 10 Sep 2012 15:22:08 +0200
Subject: [1/1] mxc_nand : allow swapping the Bad block Indicator for NFC
 v1.
In-Reply-To: <504871AF.7040809@gmail.com>
References: <CACKLOr0zCCZ0WNpGiOOvoUk4s_vR5Ls4aw6PhXDoYeNQFTESgQ@mail.gmail.com>
 <504871AF.7040809@gmail.com>
Message-ID: <201209101522.08927.jbe@pengutronix.de>

Ga?tan,

Ga?tan Carlier wrote:
> Juergen Beisert have sent an email few minutes earlier about this patch.
> I still have to read it.

Did you read it?

How should we proceed? The i.MX21/27/31 and i.MX25/35/51/53 have all the same 
issue (with minor differences between both groups). 

Regards,
Juergen

-- 
Pengutronix e.K.                              | Juergen Beisert             |
Linux Solutions for Science and Industry      | Phone: +49-5121-206917-5128 |
Vertretung Sued/Muenchen, Germany             | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686              | http://www.pengutronix.de/  |


From m-karicheri2 at ti.com  Mon Sep 10 10:17:47 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Mon, 10 Sep 2012 14:17:47 +0000
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <CAN8TOE8tpyPK2V4=YQWP7bK7e5AqFDE27EBpKhn0hj-u6r3HAA@mail.gmail.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
 <20120907212853.20289.86031@nucleus>
 <3E54258959B69E4282D79E01AB1F32B7041B73E9@DFLE12.ent.ti.com>
 <CAN8TOE8tpyPK2V4=YQWP7bK7e5AqFDE27EBpKhn0hj-u6r3HAA@mail.gmail.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041B81C0@DFLE12.ent.ti.com>

>> -----Original Message-----
>> From: Brian Norris [mailto:computersforpeace at gmail.com]
>> Sent: Friday, September 07, 2012 8:44 PM
>> To: Karicheri, Muralidharan
>> Cc: Mike Turquette; dwmw2 at infradead.org; artem.bityutskiy at linux.intel.com;
>> dbaryshkov at gmail.com; linux-mtd at lists.infradead.org; linux-kernel at vger.kernel.org
>> Subject: Re: [PATCH] mtd:nand:clk: preparation for switch to common clock framework
>> 
>> On Fri, Sep 7, 2012 at 2:56 PM, Karicheri, Muralidharan
>> <m-karicheri2 at ti.com> wrote:
>> > How do these patch get to upstream? Does this get merged through davinci maintainer
>> or through individual subsystem maintainers?
>> 
>> I think this driver would be taken by David Woodhouse in his linux-mtd
>> repo. Usually Artem Bityutskiy gleans the mailing list of patches and
>> puts them in his l2-mtd-2.6 git repo to help David out. Give it some
>> time, and I'm sure they'll be taking it. We don't really have a
>> full-time maintainer!
>> 
>> Brian

Thanks Brian for your response. Understood. Will wait.

Murali Karicheri
Software Design Engineer



From gcembed at gmail.com  Mon Sep 10 10:31:23 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Mon, 10 Sep 2012 16:31:23 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <201209061056.12386.jbe@pengutronix.de>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
 <201209061056.12386.jbe@pengutronix.de>
Message-ID: <504DF9BB.8050509@gmail.com>

Hi Juergen,
On 09/06/2012 10:56 AM, Juergen Beisert wrote:
> Hi Ga?tan,
>
> Ga?tan Carlier wrote:
>> Any comments for this patch ?
>
> Sorry, a little bit late.
>
>> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
>> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
>> Warning: The same solution needs to be applied to the boot loader and the
>> flash programmer.
>
> What sense does it make to swap the bytes at offset 0x7D0 and 0x835?
>
> Background: the NFC in the i.MX27/i.MX31 (NFCv1) and i.MX25/i.MX35 (NFCv2) can
> only handle 512 byte pages with 16 bit OOB at once. To get them work with 2 k
> page NANDs they only do the 512 + 16 step four times. The result is, a 2 k
> page NAND is not handled as 2 k data and 64 bytes OOB, its handled instead as
> a stream of 2112 bytes:
>
>                 |<-------- 2112 bytes --------->|
>                 512+16 | 512+16 | 512+16 | 512+16
>
> Which means the NFC mixes data and OOB/checksums into its internal SRAM. But
> all upper routines still use this SRAM content with a 2048 (data) + 64 (OOB)
> bytes layout (to be more precise also the NFC hardware uses this layout).
> Result is, the factory bad block markers are lost, because the NFC stores the
> first 48 bytes from each OOB into the SRAM's data area (beginning with offset
> 2000 (= 0x7D0) in the data area).
>
> So, the main goal of this swap patch should be to keep the factory bad block
> markers _and_ to make use of them.
>
> But the i.MX driver does not register its own bad block pattern description,
> so the default one is used with the BBM at position NAND_LARGE_BADBLOCK_POS
> (which means offset 0 in the OOB area).
>
> So, I think, all upper layers still search for the BBM at offset 0 of the OOB
> area, which results to SRAM's offset 0x800 (for NFCv1) and not 0x835. This
> means this patch keeps the factory bad block markers, but they won't still be
> used as expected.
>
> IMHO the bytes at SRAM's offset 0x7D0 and 0x800 for the NFCv1 must be swapped
> (and 0x7D0 and 0x1000 for the NFCv2) to keep the factory bad block markers
> _and_ to make use of them. Or am I wrong?
>
> Regards,
> Juergen
>
The point is not the necessity of swapping bytes if factory bad block 
markers are not used.
In my case, the bytes must be swapped because all previous operations on 
flash swapped these bytes :
* Flashes redboot (bootloader) via JTAG using OpenOCD which swaps bytes;
* Writes kernel and rootfs via TFTP using redboot which swaps bytes;
So to be able to read rootfs partition, mxc-nand driver have to swap 
bytes otherwise, JFFS2 detects error on partition and is unable to mount it.

I have not chosen to swap these bytes. In a training, I received redboot 
and kernel 2.6.22 with set of patches to support i.MX27 and these 
patches included swap of bytes in nand driver. So I start my development 
with this workaround and it is now impossible to get back because boards 
are already in production.
Regards,
Ga?tan Carlier.


From vikram186 at gmail.com  Mon Sep 10 12:11:22 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Mon, 10 Sep 2012 21:41:22 +0530
Subject: [PATCH 1/2] mtd: add helpers to set/get features for ONFI nand
In-Reply-To: <1347256871-18339-1-git-send-email-b32955@freescale.com>
References: <1347256871-18339-1-git-send-email-b32955@freescale.com>
Message-ID: <504E112A.8010405@gmail.com>

Hello Huang Shijie,

<Dropped cc's>

Just a few nitpicks.

On 9/10/2012 11:31 AM, Huang Shijie wrote:
> Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
> Also add the necessary macros.
>
> Signed-off-by: Huang Shijie<b32955 at freescale.com>
> ---
>   drivers/mtd/nand/nand_base.c |   50 ++++++++++++++++++++++++++++++++++++++++++
>   include/linux/mtd/nand.h     |   14 +++++++++++
>   2 files changed, 64 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index 88f671c..fbc49cc 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -2700,6 +2700,50 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
>   }
>
>   /**
> + * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
> + * @mtd: MTD device structure
> + * @chip: nand chip info structure
> + * @feature_addr: feature address.

As the function conveys that you're setting/getting the features, may be 
you can drop the prefix from the above addr. Just a thought.

> + * @subfeature_para: the subfeature parameters, a four bytes array.

subfeature_param should be more appropriate.

> + */
> +static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
> +			int feature_addr, uint8_t *subfeature_para)
> +{
> +	int status;
> +
> +	if (!chip->onfi_version)
> +		return -EINVAL;
> +
> +	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature_addr, -1);
> +	chip->write_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);

							^ PARAM_LEN here

> +	status = chip->waitfunc(mtd, chip);
> +	if (status&  NAND_STATUS_FAIL)
> +		return -EIO;
> +	return 0;
> +}
> +
> +/**
> + * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
> + * @mtd: MTD device structure
> + * @chip: nand chip info structure
> + * @feature_addr: feature address.
> + * @subfeature_para: the subfeature parameters, a four bytes array.
> + */
> +static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
> +			int feature_addr, uint8_t *subfeature_para)
> +{
> +	if (!chip->onfi_version)
> +		return -EINVAL;
> +
> +	/* clear the sub feature parameters */
> +	memset(subfeature_para, 0, ONFI_SUBFEATURE_PARA_LEN);
> +
> +	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature_addr, -1);
> +	chip->read_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);
> +	return 0;
> +}
> +
> +/**
>    * nand_suspend - [MTD Interface] Suspend the NAND flash
>    * @mtd: MTD device structure
>    */
> @@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd)
>   	if (!chip->write_page)
>   		chip->write_page = nand_write_page;
>
> +	/* set for ONFI nand */
> +	if (!chip->onfi_set_features)
> +		chip->onfi_set_features = nand_onfi_set_features;
> +	if (!chip->onfi_get_features)
> +		chip->onfi_get_features = nand_onfi_get_features;
> +
>   	/*
>   	 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
>   	 * selected and we have 256 byte pagesize fallback to software ECC
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 8f99d36..641794c 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>   #define NAND_CMD_READID		0x90
>   #define NAND_CMD_ERASE2		0xd0
>   #define NAND_CMD_PARAM		0xec
> +#define NAND_CMD_GET_FEATURES	0xee
> +#define NAND_CMD_SET_FEATURES	0xef
>   #define NAND_CMD_RESET		0xff
>
>   #define NAND_CMD_LOCK		0x2a
> @@ -229,6 +231,12 @@ typedef enum {
>   /* Keep gcc happy */
>   struct nand_chip;
>
> +/* ONFI feature address */
> +#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
> +
> +/* ONFI subfeature parameters length */
> +#define ONFI_SUBFEATURE_PARA_LEN	4

PARAM_LEN

> +
>   struct nand_onfi_params {
>   	/* rev info and features block */
>   	/* 'O' 'N' 'F' 'I'  */
> @@ -452,6 +460,8 @@ struct nand_buffers {
>    *			non 0 if ONFI supported.
>    * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
>    *			supported, 0 otherwise.
> + * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
> + * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
>    * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
>    * @bbt:		[INTERN] bad block table pointer
>    * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
> @@ -494,6 +504,10 @@ struct nand_chip {
>   	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
>   			const uint8_t *buf, int oob_required, int page,
>   			int cached, int raw);
> +	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
> +			int feature_addr, uint8_t *subfeature_para);
> +	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
> +			int feature_addr, uint8_t *subfeature_para);
>
>   	int chip_delay;
>   	unsigned int options;


Regards,
Vikram


From vikram186 at gmail.com  Mon Sep 10 12:14:59 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Mon, 10 Sep 2012 21:44:59 +0530
Subject: [PATCH] mtd: atmel_nand: fix the compile error which miss label
 "err_ecc_ioremap".
In-Reply-To: <5047286C.4060705@atmel.com>
References: <1346824842-18875-1-git-send-email-josh.wu@atmel.com>
 <5047286C.4060705@atmel.com>
Message-ID: <504E1203.6090509@gmail.com>

Hello,

On 9/5/2012 3:54 PM, Josh Wu wrote:
> Hi, all
>
> This patch is for latest l2-mtd.git tree. It fixes the compile error
> after JC's commit: b654a9a4

Please mention the above in the commit's description than keeping it empty.

> On 9/5/2012 2:00 PM, Josh Wu wrote:
>> Signed-off-by: Josh Wu <josh.wu at atmel.com>
>> ---
>> drivers/mtd/nand/atmel_nand.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
<snip>

Regards,
Vikram



From tony at atomide.com  Mon Sep 10 20:17:10 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 10 Sep 2012 17:17:10 -0700
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <20120830195349.GW1303@atomide.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
Message-ID: <20120911001710.GD1303@atomide.com>

* Tony Lindgren <tony at atomide.com> [120830 12:54]:
> * Artem Bityutskiy <dedekind1 at gmail.com> [120825 04:49]:
> > On Tue, 2012-08-21 at 15:14 +0530, Afzal Mohammed wrote:
> > > GPMC platform initialization provides it's clients
> > > with interrupts that can be used through struct
> > > resource. Make use of it for irq mode functionality.
> > > 
> > > Also now write protect disable is done by GPMC,
> > > hence remove it.
> > > 
> > > Signed-off-by: Afzal Mohammed <afzal at ti.com>
> > 
> > Acked-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> 
> Thanks I'll apply these into omap devel-gpmc branch.

FYI, looks like a new warning got introduced, so I've
committed the following trivial patch on top of this series.

Regards,

Tony

From: Tony Lindgren <tony at atomide.com>
Date: Mon, 10 Sep 2012 17:14:13 -0700
Subject: [PATCH] mtd: nand omap2: Fix uninitialized err warning

Commit bd4156fd (mtd: nand: omap2: use gpmc provided irqs)
introduced a new warning:

drivers/mtd/nand/omap2.c: In function ?omap_nand_probe?:
drivers/mtd/nand/omap2.c:1267: warning: ?err? may be used uninitialized in this function

Signed-off-by: Tony Lindgren <tony at atomide.com>

--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1389,6 +1389,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 		info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
 		if (info->gpmc_irq_fifo <= 0) {
 			dev_err(&pdev->dev, "error getting fifo irq\n");
+			err = -ENODEV;
 			goto out_release_mem_region;
 		}
 		err = request_irq(info->gpmc_irq_fifo,	omap_nand_irq,


From b32955 at freescale.com  Mon Sep 10 21:59:00 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 09:59:00 +0800
Subject: [PATCH 1/2] mtd: add helpers to set/get features for ONFI nand
In-Reply-To: <504E112A.8010405@gmail.com>
References: <1347256871-18339-1-git-send-email-b32955@freescale.com>
 <504E112A.8010405@gmail.com>
Message-ID: <504E9AE4.7020708@freescale.com>

? 2012?09?11? 00:11, Vikram Narayanan ??:
> Hello Huang Shijie,
>
> <Dropped cc's>
>
> Just a few nitpicks.
>
> On 9/10/2012 11:31 AM, Huang Shijie wrote:
>> Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
>> Also add the necessary macros.
>>
>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>> ---
>> drivers/mtd/nand/nand_base.c | 50 
>> ++++++++++++++++++++++++++++++++++++++++++
>> include/linux/mtd/nand.h | 14 +++++++++++
>> 2 files changed, 64 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
>> index 88f671c..fbc49cc 100644
>> --- a/drivers/mtd/nand/nand_base.c
>> +++ b/drivers/mtd/nand/nand_base.c
>> @@ -2700,6 +2700,50 @@ static int nand_block_markbad(struct mtd_info 
>> *mtd, loff_t ofs)
>> }
>>
>> /**
>> + * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
>> + * @mtd: MTD device structure
>> + * @chip: nand chip info structure
>> + * @feature_addr: feature address.
>
> As the function conveys that you're setting/getting the features, may 
> be you can drop the prefix from the above addr. Just a thought.
>
>> + * @subfeature_para: the subfeature parameters, a four bytes array.
>
> subfeature_param should be more appropriate.
>
>> + */
>> +static int nand_onfi_set_features(struct mtd_info *mtd, struct 
>> nand_chip *chip,
>> + int feature_addr, uint8_t *subfeature_para)
>> +{
>> + int status;
>> +
>> + if (!chip->onfi_version)
>> + return -EINVAL;
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, feature_addr, -1);
>> + chip->write_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);
>
> ^ PARAM_LEN here
>
>> + status = chip->waitfunc(mtd, chip);
>> + if (status& NAND_STATUS_FAIL)
>> + return -EIO;
>> + return 0;
>> +}
>> +
>> +/**
>> + * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
>> + * @mtd: MTD device structure
>> + * @chip: nand chip info structure
>> + * @feature_addr: feature address.
>> + * @subfeature_para: the subfeature parameters, a four bytes array.
>> + */
>> +static int nand_onfi_get_features(struct mtd_info *mtd, struct 
>> nand_chip *chip,
>> + int feature_addr, uint8_t *subfeature_para)
>> +{
>> + if (!chip->onfi_version)
>> + return -EINVAL;
>> +
>> + /* clear the sub feature parameters */
>> + memset(subfeature_para, 0, ONFI_SUBFEATURE_PARA_LEN);
>> +
>> + chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, feature_addr, -1);
>> + chip->read_buf(mtd, subfeature_para, ONFI_SUBFEATURE_PARA_LEN);
>> + return 0;
>> +}
>> +
>> +/**
>> * nand_suspend - [MTD Interface] Suspend the NAND flash
>> * @mtd: MTD device structure
>> */
>> @@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd)
>> if (!chip->write_page)
>> chip->write_page = nand_write_page;
>>
>> + /* set for ONFI nand */
>> + if (!chip->onfi_set_features)
>> + chip->onfi_set_features = nand_onfi_set_features;
>> + if (!chip->onfi_get_features)
>> + chip->onfi_get_features = nand_onfi_get_features;
>> +
>> /*
>> * Check ECC mode, default to software if 3byte/512byte hardware ECC is
>> * selected and we have 256 byte pagesize fallback to software ECC
>> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
>> index 8f99d36..641794c 100644
>> --- a/include/linux/mtd/nand.h
>> +++ b/include/linux/mtd/nand.h
>> @@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t 
>> ofs, uint64_t len);
>> #define NAND_CMD_READID 0x90
>> #define NAND_CMD_ERASE2 0xd0
>> #define NAND_CMD_PARAM 0xec
>> +#define NAND_CMD_GET_FEATURES 0xee
>> +#define NAND_CMD_SET_FEATURES 0xef
>> #define NAND_CMD_RESET 0xff
>>
>> #define NAND_CMD_LOCK 0x2a
>> @@ -229,6 +231,12 @@ typedef enum {
>> /* Keep gcc happy */
>> struct nand_chip;
>>
>> +/* ONFI feature address */
>> +#define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
>> +
>> +/* ONFI subfeature parameters length */
>> +#define ONFI_SUBFEATURE_PARA_LEN 4
>
> PARAM_LEN
>
>> +
>> struct nand_onfi_params {
>> /* rev info and features block */
>> /* 'O' 'N' 'F' 'I' */
>> @@ -452,6 +460,8 @@ struct nand_buffers {
>> * non 0 if ONFI supported.
>> * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
>> * supported, 0 otherwise.
>> + * @onfi_set_features [REPLACEABLE] set the features for ONFI nand
>> + * @onfi_get_features [REPLACEABLE] get the features for ONFI nand
>> * @ecclayout: [REPLACEABLE] the default ECC placement scheme
>> * @bbt: [INTERN] bad block table pointer
>> * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
>> @@ -494,6 +504,10 @@ struct nand_chip {
>> int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
>> const uint8_t *buf, int oob_required, int page,
>> int cached, int raw);
>> + int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
>> + int feature_addr, uint8_t *subfeature_para);
>> + int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
>> + int feature_addr, uint8_t *subfeature_para);
>>
>> int chip_delay;
>> unsigned int options;
>
thanks a lot for the review.

I will change them in the next version.

Best Regards
Huang Shijie



From tony at atomide.com  Tue Sep 11 01:30:56 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 10 Sep 2012 22:30:56 -0700
Subject: [PATCH 06/17] ARM: OMAP: Move gpio.h to include/linux/platform_data
In-Reply-To: <20120911052934.29637.9190.stgit@muffinssi.local>
References: <20120911052934.29637.9190.stgit@muffinssi.local>
Message-ID: <20120911053056.29637.57554.stgit@muffinssi.local>

This way we can remove includes of plat/gpio.h which won't work
with the single zImage support.

Note that we also remove the cpu_class_is_omap2() check
in gpio-omap.c as the drivers should not call it as we need to
make it local to arch/arm/mach-omap2 for single zImage support.

While at it, arrange the related includes in the standard way.

Cc: Grant Likely <grant.likely at secretlab.ca>
Cc: linux-mtd at lists.infradead.org
Cc: alsa-devel at alsa-project.org
Acked-by: Linus Walleij <linus.walleij at linaro.org>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/board-ams-delta.c              |    1 +
 arch/arm/mach-omap1/board-osk.c                    |    1 +
 arch/arm/mach-omap1/gpio15xx.c                     |    1 +
 arch/arm/mach-omap1/gpio16xx.c                     |    1 +
 arch/arm/mach-omap1/gpio7xx.c                      |    1 +
 arch/arm/mach-omap1/include/mach/gpio.h            |    2 --
 arch/arm/mach-omap1/leds-h2p2-debug.c              |    1 +
 arch/arm/mach-omap1/leds.c                         |    1 +
 arch/arm/mach-omap2/board-am3517evm.c              |    1 +
 arch/arm/mach-omap2/board-cm-t35.c                 |    1 +
 arch/arm/mach-omap2/board-zoom-display.c           |    2 ++
 arch/arm/mach-omap2/board-zoom-peripherals.c       |    1 +
 arch/arm/mach-omap2/gpio.c                         |    1 +
 arch/arm/mach-omap2/hsmmc.c                        |    2 ++
 arch/arm/mach-omap2/include/mach/gpio.h            |    2 --
 arch/arm/mach-omap2/msdi.c                         |    1 +
 arch/arm/mach-omap2/omap_hwmod_2420_data.c         |    1 -
 arch/arm/mach-omap2/omap_hwmod_2430_data.c         |    1 -
 arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c |    2 +-
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c         |    2 +-
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c         |    2 +-
 arch/arm/mach-omap2/pm24xx.c                       |    1 +
 arch/arm/mach-omap2/pm34xx.c                       |    2 ++
 arch/arm/plat-omap/debug-leds.c                    |    1 +
 drivers/gpio/gpio-omap.c                           |   15 ++++++++-------
 drivers/mtd/nand/ams-delta.c                       |    8 ++++++--
 include/linux/platform_data/gpio-omap.h            |   15 ++-------------
 sound/soc/omap/sdp3430.c                           |    1 +
 28 files changed, 40 insertions(+), 31 deletions(-)
 rename arch/arm/plat-omap/include/plat/gpio.h => include/linux/platform_data/gpio-omap.h (94%)

diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index c162369..6f192c4 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -26,6 +26,7 @@
 #include <linux/export.h>
 #include <linux/omapfb.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <media/soc_camera.h>
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 569b687..3b2d907 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -39,6 +39,7 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
 #include <linux/i2c/tps65010.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/platform_data/omap1_bl.h>
 
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index ebef15e..98e6f39 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1_MPUIO_VBASE		OMAP1_MPUIO_BASE
 #define OMAP1510_GPIO_BASE		0xFFFCE000
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 2a48cd2..33f4192 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP1610_GPIO1_BASE		0xfffbe400
 #define OMAP1610_GPIO2_BASE		0xfffbec00
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index acf12b7..958ce9a 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -17,6 +17,7 @@
  */
 
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #define OMAP7XX_GPIO1_BASE		0xfffbc000
 #define OMAP7XX_GPIO2_BASE		0xfffbc800
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
index e737706..ebf86c0 100644
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ b/arch/arm/mach-omap1/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap1/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index f6b14a1..7f4bba9 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -14,6 +14,7 @@
 #include <linux/kernel_stat.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-omap1/leds.c b/arch/arm/mach-omap1/leds.c
index ae6dd93..7b1a383 100644
--- a/arch/arm/mach-omap1/leds.c
+++ b/arch/arm/mach-omap1/leds.c
@@ -6,6 +6,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/leds.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 00abda1..029ebdf 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -25,6 +25,7 @@
 #include <linux/can/platform/ti_hecc.h>
 #include <linux/davinci_emac.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <mach/hardware.h>
 #include <mach/am35xx.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index ea34109..34cb904 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -23,6 +23,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <linux/i2c/at24.h>
 #include <linux/i2c/twl.h>
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 28187f1..d64f35f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -18,6 +18,8 @@
 #include <video/omapdss.h>
 #include <mach/board-zoom.h>
 
+#include <plat/cpu.h>
+
 #define LCD_PANEL_RESET_GPIO_PROD	96
 #define LCD_PANEL_RESET_GPIO_PILOT	55
 #define LCD_PANEL_QVGA_GPIO		56
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 00f73b7..ae5d36b 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -19,6 +19,7 @@
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
 #include <linux/mmc/host.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9ad7d48..7b52bdf 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/of.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index a9675d8..80399d7 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <mach/hardware.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
 #include <plat/mux.h>
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
index be4d290..5621cc5 100644
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ b/arch/arm/mach-omap2/include/mach/gpio.h
@@ -1,5 +1,3 @@
 /*
  * arch/arm/mach-omap2/include/mach/gpio.h
  */
-
-#include <plat/gpio.h>
diff --git a/arch/arm/mach-omap2/msdi.c b/arch/arm/mach-omap2/msdi.c
index fb5bc6c..9e57b4a 100644
--- a/arch/arm/mach-omap2/msdi.c
+++ b/arch/arm/mach-omap2/msdi.c
@@ -23,6 +23,7 @@
 
 #include <linux/kernel.h>
 #include <linux/err.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 50cfab6..5b49ebf 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -18,7 +18,6 @@
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mcspi.h>
 #include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 58b5bc1..1fd66f0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,6 @@
 #include <plat/dma.h>
 #include <plat/serial.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mcbsp.h>
 #include <plat/mcspi.h>
 #include <plat/dmtimer.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index afad69c..c6416c9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -10,7 +10,7 @@
  */
 #include <plat/omap_hwmod.h>
 #include <plat/serial.h>
-#include <plat/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <plat/dma.h>
 #include <plat/dmtimer.h>
 #include <plat/mcspi.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index c9e3820..5820c73 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -15,6 +15,7 @@
  * XXX these should be marked initdata for multi-OMAP kernels
  */
 #include <linux/power/smartreflex.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <plat/omap_hwmod.h>
 #include <mach/irqs.h>
@@ -24,7 +25,6 @@
 #include <plat/l3_3xxx.h>
 #include <plat/l4_3xxx.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/mmc.h>
 #include <plat/mcbsp.h>
 #include <plat/mcspi.h>
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 242aee4..fe987f8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -19,12 +19,12 @@
  */
 
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 #include <linux/power/smartreflex.h>
 
 #include <plat/omap_hwmod.h>
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/mcspi.h>
 #include <plat/mcbsp.h>
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index de1caf1..2708a8b 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -29,6 +29,7 @@
 #include <linux/irq.h>
 #include <linux/time.h>
 #include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 05bd8f0..90480f7 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -28,6 +28,8 @@
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <trace/events/power.h>
 
 #include <asm/suspend.h>
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 39407cb..195aaae 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -12,6 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/leds.h>
 #include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e6efd77..64fbce3 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,9 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
 
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/gpio.h>
 #include <asm/mach/irq.h>
 
 #define OFF_MODE	1
@@ -385,13 +383,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
 static int gpio_irq_type(struct irq_data *d, unsigned type)
 {
 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-	unsigned gpio;
+	unsigned gpio = 0;
 	int retval;
 	unsigned long flags;
 
-	if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
+#ifdef CONFIG_ARCH_OMAP1
+	if (d->irq > IH_MPUIO_BASE)
 		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-	else
+#endif
+
+	if (!gpio)
 		gpio = irq_to_gpio(bank, d->irq);
 
 	if (type & ~IRQ_TYPE_SENSE_MASK)
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 861ca8f..78a524b 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -23,12 +23,16 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/gpio.h>
+#include <linux/platform_data/gpio-omap.h>
+
 #include <asm/io.h>
-#include <mach/hardware.h>
 #include <asm/sizes.h>
-#include <linux/gpio.h>
+
 #include <plat/board-ams-delta.h>
 
+#include <mach/hardware.h>
+
 /*
  * MTD structure for E3 (Delta)
  */
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/include/linux/platform_data/gpio-omap.h
similarity index 94%
rename from arch/arm/plat-omap/include/plat/gpio.h
rename to include/linux/platform_data/gpio-omap.h
index 50fb7cc..e8741c2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/include/linux/platform_data/gpio-omap.h
@@ -1,6 +1,4 @@
 /*
- * arch/arm/plat-omap/include/mach/gpio.h
- *
  * OMAP GPIO handling defines and functions
  *
  * Copyright (C) 2003-2005 Nokia Corporation
@@ -155,6 +153,8 @@
 #define OMAP4_GPIO_CLEARDATAOUT		0x0190
 #define OMAP4_GPIO_SETDATAOUT		0x0194
 
+#define OMAP_MAX_GPIO_LINES		192
+
 #define OMAP_MPUIO(nr)		(OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)	((nr) >= OMAP_MAX_GPIO_LINES)
 
@@ -213,16 +213,5 @@ extern void omap2_gpio_prepare_for_idle(int off_mode);
 extern void omap2_gpio_resume_after_idle(void);
 extern void omap_set_gpio_debounce(int gpio, int enable);
 extern void omap_set_gpio_debounce_time(int gpio, int enable);
-/*-------------------------------------------------------------------------*/
-
-/*
- * Wrappers for "new style" GPIO calls, using the new infrastructure
- * which lets us plug in FPGA, I2C, and other implementations.
- *
- * The original OMAP-specific calls should eventually be removed.
- */
-
-#include <linux/errno.h>
-#include <asm-generic/gpio.h>
 
 #endif
diff --git a/sound/soc/omap/sdp3430.c b/sound/soc/omap/sdp3430.c
index 0e28322..78e1419 100644
--- a/sound/soc/omap/sdp3430.c
+++ b/sound/soc/omap/sdp3430.c
@@ -34,6 +34,7 @@
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <plat/mcbsp.h>
+#include <linux/platform_data/gpio-omap.h>
 
 /* Register descriptions for twl4030 codec part */
 #include <linux/mfd/twl4030-audio.h>



From afzal at ti.com  Tue Sep 11 01:36:00 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 11 Sep 2012 05:36:00 +0000
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <20120911001710.GD1303@atomide.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
 <20120911001710.GD1303@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>

Hi Tony,

On Tue, Sep 11, 2012 at 05:47:10, Tony Lindgren wrote:

> FYI, looks like a new warning got introduced, so I've
> committed the following trivial patch on top of this series.

I was not careful enough, sorry. Thanks for fixing it.

Another hunk as follows would also be required for error
path even though compiler didn't complain.

Not sure whether you can fixup or I should post as a
separate patch.

As an aside, there was compiler warning before this
series, but I didn't dare to touch it, so a warning
was seen but thought it was due to the earlier one.
And now Arnd has fixed the original warning.

Regards
Afzal

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 337cf0a..27293e3 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1404,6 +1404,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
                info->gpmc_irq_count = platform_get_irq(pdev, 1);
                if (info->gpmc_irq_count <= 0) {
                        dev_err(&pdev->dev, "error getting count irq\n");
+                       err = -ENODEV;
                        goto out_release_mem_region;
                }
                err = request_irq(info->gpmc_irq_count, omap_nand_irq, 


> From: Tony Lindgren <tony at atomide.com>
> Date: Mon, 10 Sep 2012 17:14:13 -0700
> Subject: [PATCH] mtd: nand omap2: Fix uninitialized err warning
> 
> Commit bd4156fd (mtd: nand: omap2: use gpmc provided irqs)
> introduced a new warning:
> 
> drivers/mtd/nand/omap2.c: In function ?omap_nand_probe?:
> drivers/mtd/nand/omap2.c:1267: warning: ?err? may be used uninitialized in this function
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -1389,6 +1389,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
>  		info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
>  		if (info->gpmc_irq_fifo <= 0) {
>  			dev_err(&pdev->dev, "error getting fifo irq\n");
> +			err = -ENODEV;
>  			goto out_release_mem_region;
>  		}
>  		err = request_irq(info->gpmc_irq_fifo,	omap_nand_irq,
> 


From tony at atomide.com  Tue Sep 11 01:42:27 2012
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 10 Sep 2012 22:42:27 -0700
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
 <20120911001710.GD1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>
Message-ID: <20120911054227.GF1303@atomide.com>

* Mohammed, Afzal <afzal at ti.com> [120910 22:36]:
> Hi Tony,
> 
> On Tue, Sep 11, 2012 at 05:47:10, Tony Lindgren wrote:
> 
> > FYI, looks like a new warning got introduced, so I've
> > committed the following trivial patch on top of this series.
> 
> I was not careful enough, sorry. Thanks for fixing it.
> 
> Another hunk as follows would also be required for error
> path even though compiler didn't complain.
> 
> Not sure whether you can fixup or I should post as a
> separate patch.

Oh OK, please just post a separate patch as I've
already pushed it out.

> As an aside, there was compiler warning before this
> series, but I didn't dare to touch it, so a warning
> was seen but thought it was due to the earlier one.
> And now Arnd has fixed the original warning.

OK

Regards,

Tony


From afzal at ti.com  Tue Sep 11 02:28:54 2012
From: afzal at ti.com (Afzal Mohammed)
Date: Tue, 11 Sep 2012 11:58:54 +0530
Subject: [PATCH] mtd: nand: omap2: fix error path
Message-ID: <1347344934-28103-1-git-send-email-afzal@ti.com>

Let probe return error value if gpmc terminal
count interrupt could not be obtained

Signed-off-by: Afzal Mohammed <afzal at ti.com>
---
Hi,

My commit (now in l-o/devel-gpmc),

"bd4156f  mtd: nand: omap2: use gpmc provided irqs"

did not propogate error code properly due to
which this fix was required.

But this has not been mentioned in commit message
as it is not yet in mainline.

Regards
Afzal

 drivers/mtd/nand/omap2.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index 337cf0a..27293e3 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -1404,6 +1404,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
 		info->gpmc_irq_count = platform_get_irq(pdev, 1);
 		if (info->gpmc_irq_count <= 0) {
 			dev_err(&pdev->dev, "error getting count irq\n");
+			err = -ENODEV;
 			goto out_release_mem_region;
 		}
 		err = request_irq(info->gpmc_irq_count,	omap_nand_irq,
-- 
1.7.0.4



From afzal at ti.com  Tue Sep 11 02:30:22 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 11 Sep 2012 06:30:22 +0000
Subject: [PATCH] mtd: nand: omap2: fix error path
In-Reply-To: <1347344934-28103-1-git-send-email-afzal@ti.com>
References: <1347344934-28103-1-git-send-email-afzal@ti.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9E19C0@DBDE01.ent.ti.com>

+Tony

On Tue, Sep 11, 2012 at 11:58:54, Mohammed, Afzal wrote:
> Let probe return error value if gpmc terminal
> count interrupt could not be obtained
> 
> Signed-off-by: Afzal Mohammed <afzal at ti.com>
> ---
> Hi,
> 
> My commit (now in l-o/devel-gpmc),
> 
> "bd4156f  mtd: nand: omap2: use gpmc provided irqs"
> 
> did not propogate error code properly due to
> which this fix was required.
> 
> But this has not been mentioned in commit message
> as it is not yet in mainline.
> 
> Regards
> Afzal
> 
>  drivers/mtd/nand/omap2.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index 337cf0a..27293e3 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -1404,6 +1404,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
>  		info->gpmc_irq_count = platform_get_irq(pdev, 1);
>  		if (info->gpmc_irq_count <= 0) {
>  			dev_err(&pdev->dev, "error getting count irq\n");
> +			err = -ENODEV;
>  			goto out_release_mem_region;
>  		}
>  		err = request_irq(info->gpmc_irq_count,	omap_nand_irq,
> -- 
> 1.7.0.4
> 
> 


From afzal at ti.com  Tue Sep 11 02:40:03 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Tue, 11 Sep 2012 06:40:03 +0000
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <20120911054227.GF1303@atomide.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
 <20120911001710.GD1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>
 <20120911054227.GF1303@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9E1A11@DBDE01.ent.ti.com>

Hi Tony,

On Tue, Sep 11, 2012 at 11:12:27, Tony Lindgren wrote:
> * Mohammed, Afzal <afzal at ti.com> [120910 22:36]:

> > I was not careful enough, sorry. Thanks for fixing it.
> > 
> > Another hunk as follows would also be required for error
> > path even though compiler didn't complain.
> > 
> > Not sure whether you can fixup or I should post as a
> > separate patch.
> 
> Oh OK, please just post a separate patch as I've
> already pushed it out.

I have posted a separate patch, please consider for
inclusion in your tree.

BTW, you original commit that fixes the compiler
warning has some strange characters.

Regards
Afzal

From b32955 at freescale.com  Tue Sep 11 02:17:03 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:03 +0800
Subject: [PATCH 1/9] mtd: add helpers to set/get features for ONFI nand
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-2-git-send-email-b32955@freescale.com>

Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
Also add the necessary macros.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/nand_base.c |   50 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/nand.h     |   14 +++++++++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 88f671c..d06a80d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2700,6 +2700,50 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 }
 
 /**
+ * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	int status;
+
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
+	chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	status = chip->waitfunc(mtd, chip);
+	if (status & NAND_STATUS_FAIL)
+		return -EIO;
+	return 0;
+}
+
+/**
+ * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	/* clear the sub feature parameters */
+	memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
+
+	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
+	chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	return 0;
+}
+
+/**
  * nand_suspend - [MTD Interface] Suspend the NAND flash
  * @mtd: MTD device structure
  */
@@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd)
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
+	/* set for ONFI nand */
+	if (!chip->onfi_set_features)
+		chip->onfi_set_features = nand_onfi_set_features;
+	if (!chip->onfi_get_features)
+		chip->onfi_get_features = nand_onfi_get_features;
+
 	/*
 	 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
 	 * selected and we have 256 byte pagesize fallback to software ECC
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8f99d36..537f59c 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
 #define NAND_CMD_RESET		0xff
 
 #define NAND_CMD_LOCK		0x2a
@@ -229,6 +231,12 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN	4
+
 struct nand_onfi_params {
 	/* rev info and features block */
 	/* 'O' 'N' 'F' 'I'  */
@@ -452,6 +460,8 @@ struct nand_buffers {
  *			non 0 if ONFI supported.
  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
  *			supported, 0 otherwise.
+ * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
  * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
  * @bbt:		[INTERN] bad block table pointer
  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
@@ -494,6 +504,10 @@ struct nand_chip {
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, int oob_required, int page,
 			int cached, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
 
 	int chip_delay;
 	unsigned int options;
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:02 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:02 +0800
Subject: [PATCH 0/9] add EDO feature for gpmi-nand driver
Message-ID: <1347344231-10295-1-git-send-email-b32955@freescale.com>

The ONFI nand supports the EDO (extended data out) feature in 
asynchronous mode when the host controller(such as gpmi-nand)
uses a tRC of less then 30ns.

The gpmi can supports this EDO feature.
This patch set adds the EDO support the gpmi-nand driver.

patch 1 ~ patch 2: 
	 These two patches provide the infrastructure for the EDO feature.
         They add necessary MTD helpers for the ONFI nand set/get features,
	 and the help to get the supportted timing mode.
	 These two patches are new version. The init version has been
	 reviewed by Vikram & Florian.

patch 3 ~ patch 7:
         These patches are clean-ups for the gpmi-nand's timing code.
	 Also they make the some preparations for the EDO patch.

patch 8: add the EDO feature to the gpmi-nand.


patch 9: a small optimization for the timing. 
         only set the timing registers one time.

I tested this patch set on the IMX6Q-arm2 board with several Micron's
ONFI nand chips. Some chips only can supports to mode 4, some chips
can supports to mode 5.

The performance is much improved. Take Micron MT29F32G08MAA for example
(in mode 5, 100MHz):

1) The test result BEFORE we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3632 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3554 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3592 KiB/s
.......................................
=================================================

2) The test result AFTER we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19555 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17319 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 18339 KiB/s
.......................................
=================================================

The read data performance is much improved by more then 5 times.

Huang Shijie (9):
  mtd: add helpers to set/get features for ONFI nand
  mtd: add helpers to get the supportted ONFI timing mode
  mtd: gpmi: add a new field for HW_GPMI_TIMING1
  mtd: gpmi: do not get the clock frequency in gpmi_begin()
  mtd: gpmi: add a new field for HW_GPMI_CTRL1
  mtd: gpmi: simplify the setting DLL code
  mtd: gpmi: do not set the default values for the extra clocks
  mtd: gpmi: add EDO feature for imx6q
  mtd: gpmi: initialize the timing registers only one time

 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |  273 +++++++++++++++++++++++++++++---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   23 ++--
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |   18 ++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    8 +
 drivers/mtd/nand/nand_base.c           |   50 ++++++
 include/linux/mtd/nand.h               |   39 +++++
 6 files changed, 375 insertions(+), 36 deletions(-)




From b32955 at freescale.com  Tue Sep 11 02:17:04 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:04 +0800
Subject: [PATCH 2/9] mtd: add helpers to get the supportted ONFI timing mode
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-3-git-send-email-b32955@freescale.com>

add onfi_get_async_timing_mode() to get the supportted asynchronous
timing mode.

add onfi_get_sync_timing_mode() to get the supportted synchronous
timing mode.

Also add the neccessary macros : the timing modes.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 include/linux/mtd/nand.h |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 537f59c..7a7b246 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -231,6 +231,15 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0		(1 << 0)
+#define ONFI_TIMING_MODE_1		(1 << 1)
+#define ONFI_TIMING_MODE_2		(1 << 2)
+#define ONFI_TIMING_MODE_3		(1 << 3)
+#define ONFI_TIMING_MODE_4		(1 << 4)
+#define ONFI_TIMING_MODE_5		(1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
+
 /* ONFI feature address */
 #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
 
@@ -682,4 +691,20 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 	return chip->priv;
 }
 
+/* return the supported asynchronous timing mode. */
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+
 #endif /* __LINUX_MTD_NAND_H */
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:05 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:05 +0800
Subject: [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-4-git-send-email-b32955@freescale.com>

The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.

So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.

This patch also changes some comments to make the code more readable.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |   17 +++++++++--------
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    9 +++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    3 +++
 3 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 2289cf8..fb9b3c1 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -728,6 +728,7 @@ return_results:
 	hw->address_setup_in_cycles = address_setup_in_cycles;
 	hw->use_half_periods        = dll_use_half_periods;
 	hw->sample_delay_factor     = sample_delay_factor;
+	hw->device_busy_timeout     = 0x500; /* default busy timeout value. */
 
 	/* Return success. */
 	return 0;
@@ -752,26 +753,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	/* set ready/busy timeout */
-	writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
-		gpmi_regs + HW_GPMI_TIMING1);
-
 	/* Get the timing information we need. */
 	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
 
 	gpmi_nfc_compute_hardware_timing(this, &hw);
 
-	/* Set up all the simple timing parameters. */
+	/* [1] Set HW_GPMI_TIMING0 */
 	reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
 		BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
 		BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
 
 	writel(reg, gpmi_regs + HW_GPMI_TIMING0);
 
-	/*
-	 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
-	 */
+	/* [2] Set HW_GPMI_TIMING1 */
+	writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
+		gpmi_regs + HW_GPMI_TIMING1);
+
+	/* [3] The following code is to set the HW_GPMI_CTRL1. */
+
+	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* Clear out the DLL control fields. */
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 1f61217..e68bbac 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -189,14 +189,23 @@ struct gpmi_nand_data {
  * @data_setup_in_cycles:      The data setup time, in cycles.
  * @data_hold_in_cycles:       The data hold time, in cycles.
  * @address_setup_in_cycles:   The address setup time, in cycles.
+ * @device_busy_timeout:       The timeout waiting for NAND Ready/Busy,
+ *                             this value is the number of cycles multiplied
+ *                             by 4096.
  * @use_half_periods:          Indicates the clock is running slowly, so the
  *                             NFC DLL should use half-periods.
  * @sample_delay_factor:       The sample delay factor.
  */
 struct gpmi_nfc_hardware_timing {
+	/* for HW_GPMI_TIMING0 */
 	uint8_t  data_setup_in_cycles;
 	uint8_t  data_hold_in_cycles;
 	uint8_t  address_setup_in_cycles;
+
+	/* for HW_GPMI_TIMING1 */
+	uint16_t device_busy_timeout;
+
+	/* for HW_GPMI_CTRL1 */
 	bool     use_half_periods;
 	uint8_t  sample_delay_factor;
 };
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 8343124..7961c14 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -154,6 +154,9 @@
 
 #define HW_GPMI_TIMING1					0x00000080
 #define BP_GPMI_TIMING1_BUSY_TIMEOUT			16
+#define BM_GPMI_TIMING1_BUSY_TIMEOUT	(0xff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
+#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v)		\
+	(((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)
 
 #define HW_GPMI_TIMING2					0x00000090
 #define HW_GPMI_DATA					0x000000a0
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:06 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:06 +0800
Subject: [PATCH 4/9] mtd: gpmi: do not get the clock frequency in gpmi_begin()
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-5-git-send-email-b32955@freescale.com>

The current code will gets the clock frequency which is used by
gpmi_nfc_compute_hardware_timing(). It makes the code a little mess.

So move the `get clock frequency` code to the
gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy
and clean.
Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |    8 +++-----
 1 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index fb9b3c1..eee0159 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -293,6 +293,7 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 					struct gpmi_nfc_hardware_timing *hw)
 {
 	struct timing_threshod *nfc = &timing_default_threshold;
+	struct resources *r = &this->resources;
 	struct nand_chip *nand = &this->nand;
 	struct nand_timing target = this->timing;
 	bool improved_timing_is_available;
@@ -332,6 +333,7 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 		(target.tRHOH_in_ns >= 0) ;
 
 	/* Inspect the clock. */
+	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 	clock_frequency_in_hz = nfc->clock_frequency_in_hz;
 	clock_period_in_ns    = 1000000000 / clock_frequency_in_hz;
 
@@ -738,7 +740,6 @@ return_results:
 void gpmi_begin(struct gpmi_nand_data *this)
 {
 	struct resources *r = &this->resources;
-	struct timing_threshod *nfc = &timing_default_threshold;
 	void __iomem *gpmi_regs = r->gpmi_regs;
 	unsigned int   clock_period_in_ns;
 	uint32_t       reg;
@@ -753,10 +754,6 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	/* Get the timing information we need. */
-	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
-	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
-
 	gpmi_nfc_compute_hardware_timing(this, &hw);
 
 	/* [1] Set HW_GPMI_TIMING0 */
@@ -801,6 +798,7 @@ void gpmi_begin(struct gpmi_nand_data *this)
 	 *
 	 * Calculate the amount of time we need to wait, in microseconds.
 	 */
+	clock_period_in_ns = 1000000000 / clk_get_rate(r->clock[0]);
 	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
 
 	if (!dll_wait_time_in_us)
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:07 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:07 +0800
Subject: [PATCH 5/9] mtd: gpmi: add a new field for HW_GPMI_CTRL1
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-6-git-send-email-b32955@freescale.com>

add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
This field is used as delay for gpmi write strobe.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    6 ++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    2 ++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    5 +++++
 3 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index eee0159..037438a 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -731,6 +731,7 @@ return_results:
 	hw->use_half_periods        = dll_use_half_periods;
 	hw->sample_delay_factor     = sample_delay_factor;
 	hw->device_busy_timeout     = 0x500; /* default busy timeout value. */
+	hw->wrn_dly_sel             = 0;
 
 	/* Return success. */
 	return 0;
@@ -769,6 +770,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
 
 	/* [3] The following code is to set the HW_GPMI_CTRL1. */
 
+	/* Set the WRN_DLY_SEL */
+	writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
+	writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
+					gpmi_regs + HW_GPMI_CTRL1_SET);
+
 	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index e68bbac..39f1f76 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -195,6 +195,7 @@ struct gpmi_nand_data {
  * @use_half_periods:          Indicates the clock is running slowly, so the
  *                             NFC DLL should use half-periods.
  * @sample_delay_factor:       The sample delay factor.
+ * @wrn_dly_sel:               The delay on the GPMI write strobe.
  */
 struct gpmi_nfc_hardware_timing {
 	/* for HW_GPMI_TIMING0 */
@@ -208,6 +209,7 @@ struct gpmi_nfc_hardware_timing {
 	/* for HW_GPMI_CTRL1 */
 	bool     use_half_periods;
 	uint8_t  sample_delay_factor;
+	uint8_t  wrn_dly_sel;
 };
 
 /**
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 7961c14..ab428d6 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -108,6 +108,11 @@
 #define HW_GPMI_CTRL1_CLR				0x00000068
 #define HW_GPMI_CTRL1_TOG				0x0000006c
 
+#define BP_GPMI_CTRL1_WRN_DLY_SEL			22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL			0x00C00000
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+	(((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+
 #define BM_GPMI_CTRL1_BCH_MODE				(1 << 18)
 
 #define BP_GPMI_CTRL1_DLL_ENABLE			17
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:08 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:08 +0800
Subject: [PATCH 6/9] mtd: gpmi: simplify the setting DLL code
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-7-git-send-email-b32955@freescale.com>

The setting DLL code is a little mess.
Just simplify the code and the comments.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |   22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 037438a..83c5573 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* Clear out the DLL control fields. */
-	writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
-	writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+	reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
+	writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* If no sample delay is called for, return immediately. */
 	if (!hw.sample_delay_factor)
 		return;
 
-	/* Configure the HALF_PERIOD flag. */
-	if (hw.use_half_periods)
-		writel(BM_GPMI_CTRL1_HALF_PERIOD,
-						gpmi_regs + HW_GPMI_CTRL1_SET);
+	/* Set RDN_DELAY or HALF_PERIOD. */
+	reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
+		| BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
 
-	/* Set the delay factor. */
-	writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
-						gpmi_regs + HW_GPMI_CTRL1_SET);
+	writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
 
-	/* Enable the DLL. */
+	/* At last, we enable the DLL. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
 
 	/*
 	 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
-	 * we can use the GPMI.
-	 *
-	 * Calculate the amount of time we need to wait, in microseconds.
+	 * we can use the GPMI. Calculate the amount of time we need to wait,
+	 * in microseconds.
 	 */
 	clock_period_in_ns = 1000000000 / clk_get_rate(r->clock[0]);
 	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:09 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:09 +0800
Subject: [PATCH 7/9] mtd: gpmi: do not set the default values for the extra
 clocks
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-8-git-send-email-b32955@freescale.com>

The default frequencies of the extra clocks are 200MHz.
The current code sets the extra clocks to 44.5MHz.

When i add the EDO feature to gpmi, i have to revert the extra clocks
to 200MHz.

So it is better that we do not set the default values for the extra
clocks. The driver runs well even when we do not set the default values for
extra clocks.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   15 +++++----------
 1 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index c46be6c..cc74ebf 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -513,20 +513,15 @@ static int __devinit gpmi_get_clks(struct gpmi_nand_data *this)
 		r->clock[i] = clk;
 	}
 
-	if (GPMI_IS_MX6Q(this)) {
+	if (GPMI_IS_MX6Q(this))
 		/*
-		 * Set the default values for the clocks in mx6q:
-		 *    The main clock(enfc) : 22MHz
-		 *    The others           : 44.5MHz
+		 * Set the default value for the gpmi clock in mx6q:
 		 *
-		 * These are just the default values. If you want to use
-		 * the ONFI nand which is in the Synchronous Mode, you should
-		 * change the clocks's frequencies as you need.
+		 * If you want to use the ONFI nand which is in the
+		 * Synchronous Mode, you should change the clock as you need.
 		 */
 		clk_set_rate(r->clock[0], 22000000);
-		for (i = 1; i < GPMI_CLK_MAX && r->clock[i]; i++)
-			clk_set_rate(r->clock[i], 44500000);
-	}
+
 	return 0;
 
 err_clock:
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:11 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:11 +0800
Subject: [PATCH 9/9] mtd: gpmi: initialize the timing registers only one time
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-10-git-send-email-b32955@freescale.com>

The current code initialize the timing registers at very time
we call the gpmi_begin(). This really wastes the cpu cycles.

Add a flag to let the gpmi driver initializes the timing registers
only one time.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    8 ++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 7efd326..c374236 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -914,6 +914,9 @@ static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
 	rate = (mode == 5) ? 100000000 : 80000000;
 	clk_set_rate(r->clock[0], rate);
 
+	/* Let the gpmi_begin() re-compute the timing again. */
+	this->flags &= ~GPMI_TIMING_INIT_OK;
+
 	this->flags |= GPMI_ASYNC_EDO_ENABLED;
 	this->timing_mode = mode;
 	pr_info("gpmi-nand enters asynchronous EDO mode %d\n", mode);
@@ -964,6 +967,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
+	/* Only initialize the timing once */
+	if (this->flags & GPMI_TIMING_INIT_OK)
+		return;
+	this->flags |= GPMI_TIMING_INIT_OK;
+
 	if (this->flags & GPMI_ASYNC_EDO_ENABLED)
 		gpmi_compute_edo_timing(this, &hw);
 	else
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index fe52a3b..1e01a03 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -124,6 +124,7 @@ struct nand_timing {
 struct gpmi_nand_data {
 	/* flags */
 #define GPMI_ASYNC_EDO_ENABLED	(1 << 0)
+#define GPMI_TIMING_INIT_OK	(1 << 1)
 	int			flags;
 
 	/* System Interface */
-- 
1.7.0.4




From b32955 at freescale.com  Tue Sep 11 02:17:10 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Tue, 11 Sep 2012 14:17:10 +0800
Subject: [PATCH 8/9] mtd: gpmi: add EDO feature for imx6q
In-Reply-To: <1347344231-10295-1-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
Message-ID: <1347344231-10295-9-git-send-email-b32955@freescale.com>

When the frequency on the nand chip pins is above 33MHz,
the nand EDO(extended Data Out) timing could be applied.
The GPMI implements a Feedback read strobe to sample the read data in
the EDO timing mode.

This patch adds the EDO feature for the gpmi-nand driver.

For some onfi nand chips, the mode 4 is the fastest;
while for other onfi nand chips, the mode 5 is the fastest.
This patch only adds the support for the fastest asynchronous timing mode.
So this patch only supports the mode 4 and mode 5.

I tested several Micron's ONFI nand chips with EDO enabled,
take Micron MT29F32G08MAA for example (in mode 5, 100MHz):

1) The test result BEFORE we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3632 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3554 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3592 KiB/s
.......................................
=================================================

2) The test result AFTER we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19555 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17319 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 18339 KiB/s
.......................................
=================================================

The read data performance is much improved by more then 5 times.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |  214 +++++++++++++++++++++++++++++++-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    8 ++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    6 +
 3 files changed, 227 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 83c5573..7efd326 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -737,6 +737,215 @@ return_results:
 	return 0;
 }
 
+/*
+ * [1] Firstly, we should know what's the GPMI-clock means.
+ *     The GPMI-clock is the internal clock in the gpmi nand controller.
+ *     If you set 100MHz to gpmi nand controller, the GPMI-clock's period
+ *     is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
+ *
+ * [2] Secondly, we should know what's the frequency on the nand chip pins.
+ *     The frequency on the nand chip pins is derived from the GPMI-clock.
+ *     We can get it from the following equation:
+ *
+ *         F = G / (DS + DH)
+ *
+ *         F  : the frequency on the nand chip pins.
+ *         G  : the GPMI clock, such as 100MHz.
+ *         DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
+ *         DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
+ *
+ * [3] Thirdly, when the frequency on the nand chip pins is above 33MHz,
+ *     the nand EDO(extended Data Out) timing could be applied.
+ *     The GPMI implements a feedback read strobe to sample the read data.
+ *     The feedback read strobe can be delayed to support the nand EDO timing
+ *     where the read strobe may deasserts before the read data is valid, and
+ *     read data is valid for some time after read strobe.
+ *
+ *     The following figure illustrates some aspects of a NAND Flash read:
+ *
+ *                   |<---tREA---->|
+ *                   |             |
+ *                   |         |   |
+ *                   |<--tRP-->|   |
+ *                   |         |   |
+ *                  __          ___|__________________________________
+ *     RDN            \________/   |
+ *                                 |
+ *                                 /---------\
+ *     Read Data    --------------<           >---------
+ *                                 \---------/
+ *                                |     |
+ *                                |<-D->|
+ *     FeedbackRDN  ________             ____________
+ *                          \___________/
+ *
+ *          D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
+ *
+ *
+ * [4] Now, we begin to describe how to compute the right RDN_DELAY.
+ *
+ *  4.1) From the aspect of the nand chip pins:
+ *        Delay = (tREA + C - tRP)               [1]
+ *
+ *        tREA : the maximum read access time. From the ONFI nand standards,
+ *               we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
+ *               Please check it in : www.onfi.org
+ *        C    : a constant for adjust the delay. default is 4.
+ *        tRP  : the read pulse width.
+ *               Specified by the HW_GPMI_TIMING0:DATA_SETUP:
+ *                    tRP = (GPMI-clock-period) * DATA_SETUP
+ *
+ *  4.2) From the aspect of the GPMI nand controller:
+ *         Delay = RDN_DELAY * 0.125 * RP        [2]
+ *
+ *         RP   : the DLL reference period.
+ *            if (GPMI-clock-period > DLL_THRETHOLD)
+ *                   RP = GPMI-clock-period / 2;
+ *            else
+ *                   RP = GPMI-clock-period;
+ *
+ *            Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
+ *            is greater DLL_THRETHOLD. In other Soc, the thethold is 16ns,
+ *            but in mx6q, we use 12ns.
+ *
+ *  4.3) since [1] equals [2], we get:
+ *
+ *                    (tREA + 4 - tRP) * 8
+ *         RDN_DELAY = ---------------------     [3]
+ *                           RP
+ *
+ *  4.4) We only support the fastest asynchronous mode of ONFI nand.
+ *       For some ONFI nand, the mode 4 is the fastest mode;
+ *       while for some ONFI nand, the mode 5 is the fastest mode.
+ *       So we only support the mode 4 and mode 5. It is no need to
+ *       support other modes.
+ */
+static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
+			struct gpmi_nfc_hardware_timing *hw)
+{
+	struct resources *r = &this->resources;
+	unsigned long rate = clk_get_rate(r->clock[0]);
+	int mode = this->timing_mode;
+	int dll_threshold = 16; /* in ns */
+	unsigned long delay;
+	unsigned long clk_period;
+	int t_rea;
+	int c = 4;
+	int t_rp;
+	int rp;
+
+	/*
+	 * 1) for GPMI_HW_GPMI_TIMING0:
+	 *    The async mode requires 40MHz for mode 4, 50MHz for mode 5.
+	 *    The GPMI can support 100MHz at most. But the if we want to
+	 *    get the 40MHz or 50MHz, we have to set DS=1, DH=1.
+	 *    It is okay to set ADDRESS_SETUP to 1.
+	 */
+	hw->data_setup_in_cycles = 1;
+	hw->data_hold_in_cycles = 1;
+	hw->address_setup_in_cycles = 1;
+
+	/* 2) for GPMI_HW_GPMI_TIMING1 */
+	hw->device_busy_timeout = 0x9000;
+
+	/* 3) for GPMI_HW_GPMI_CTRL1 */
+	hw->wrn_dly_sel = 3; /* no delay for write strobe. */
+
+	if (GPMI_IS_MX6Q(this))
+		dll_threshold = 12;
+
+	/*
+	 * Enlarge 10 times for the numerator and denominator in [3].
+	 * This make us to get more accurate result.
+	 */
+	clk_period = 1000000000 / (rate / 10);
+	dll_threshold *= 10;
+	t_rea = ((mode == 5) ? 16 : 20) * 10;
+	c *= 10;
+
+	t_rp = clk_period * 1; /* DATA_SETUP is 1 */
+
+	if (clk_period > dll_threshold) {
+		hw->use_half_periods = 1;
+		rp = clk_period / 2;
+	} else {
+		hw->use_half_periods = 0;
+		rp = clk_period;
+	}
+
+	/*
+	 * Multiply the numerator with 10, we could do a round off:
+	 *      7.8 round up to 8; 7.4 round down to 7.
+	 */
+	delay  = (((t_rea + c - t_rp) * 8) * 10) / rp;
+	delay = (delay + 5) / 10;
+
+	hw->sample_delay_factor = delay;
+}
+
+static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
+{
+	struct resources  *r = &this->resources;
+	struct nand_chip *nand = &this->nand;
+	struct mtd_info	 *mtd = &this->mtd;
+	uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
+	unsigned long rate;
+	int ret;
+
+	nand->select_chip(mtd, 0);
+
+	/* [1] send SET FEATURE commond to NAND */
+	feature[0] = mode;
+	ret = nand->onfi_set_features(mtd, nand,
+				ONFI_FEATURE_ADDR_TIMING_MODE, feature);
+	if (ret)
+		goto err_out;
+
+	/* [2] send GET FEATURE command to double-check the timing mode */
+	memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
+	ret = nand->onfi_get_features(mtd, nand,
+				ONFI_FEATURE_ADDR_TIMING_MODE, feature);
+	if (ret)
+		goto err_out;
+
+	nand->select_chip(mtd, -1);
+
+	/* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
+	rate = (mode == 5) ? 100000000 : 80000000;
+	clk_set_rate(r->clock[0], rate);
+
+	this->flags |= GPMI_ASYNC_EDO_ENABLED;
+	this->timing_mode = mode;
+	pr_info("gpmi-nand enters asynchronous EDO mode %d\n", mode);
+	return 0;
+
+err_out:
+	nand->select_chip(mtd, -1);
+	dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
+	return -EINVAL;
+}
+
+int gpmi_extra_init(struct gpmi_nand_data *this)
+{
+	struct nand_chip *chip = &this->nand;
+
+	/* Enable the asynchronous EDO feature. */
+	if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
+		int mode = onfi_get_async_timing_mode(chip);
+
+		/* We only support the timing mode 4 and mode 5. */
+		if (mode & ONFI_TIMING_MODE_5)
+			mode = 5;
+		else if (mode & ONFI_TIMING_MODE_4)
+			mode = 4;
+		else
+			return 0;
+
+		return enable_edo_mode(this, mode);
+	}
+	return 0;
+}
+
 /* Begin the I/O */
 void gpmi_begin(struct gpmi_nand_data *this)
 {
@@ -755,7 +964,10 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	gpmi_nfc_compute_hardware_timing(this, &hw);
+	if (this->flags & GPMI_ASYNC_EDO_ENABLED)
+		gpmi_compute_edo_timing(this, &hw);
+	else
+		gpmi_nfc_compute_hardware_timing(this, &hw);
 
 	/* [1] Set HW_GPMI_TIMING0 */
 	reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index cc74ebf..684c456 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1514,6 +1514,14 @@ static int gpmi_scan_bbt(struct mtd_info *mtd)
 	if (ret)
 		return ret;
 
+	/*
+	 * Can we enable the extra features? such as EDO or Sync mode.
+	 *
+	 * We do not check the return value now. That's means if we fail in
+	 * enable the extra features, we still can run in the normal way.
+	 */
+	gpmi_extra_init(this);
+
 	/* use the default BBT implementation */
 	return nand_default_bbt(mtd);
 }
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 39f1f76..fe52a3b 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -122,6 +122,10 @@ struct nand_timing {
 };
 
 struct gpmi_nand_data {
+	/* flags */
+#define GPMI_ASYNC_EDO_ENABLED	(1 << 0)
+	int			flags;
+
 	/* System Interface */
 	struct device		*dev;
 	struct platform_device	*pdev;
@@ -132,6 +136,7 @@ struct gpmi_nand_data {
 
 	/* Flash Hardware */
 	struct nand_timing	timing;
+	int			timing_mode;
 
 	/* BCH */
 	struct bch_geometry	bch_geometry;
@@ -258,6 +263,7 @@ extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
 
 /* GPMI-NAND helper function library */
 extern int gpmi_init(struct gpmi_nand_data *);
+extern int gpmi_extra_init(struct gpmi_nand_data *);
 extern void gpmi_clear_bch(struct gpmi_nand_data *);
 extern void gpmi_dump_info(struct gpmi_nand_data *);
 extern int bch_set_geometry(struct gpmi_nand_data *);
-- 
1.7.0.4




From josh.wu at atmel.com  Tue Sep 11 03:06:58 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Tue, 11 Sep 2012 15:06:58 +0800
Subject: [PATCH] mtd: atmel_nand: fix the compile error which miss label
 "err_ecc_ioremap".
In-Reply-To: <504E1203.6090509@gmail.com>
References: <1346824842-18875-1-git-send-email-josh.wu@atmel.com>
 <5047286C.4060705@atmel.com> <504E1203.6090509@gmail.com>
Message-ID: <504EE312.5020705@atmel.com>

Hi, Vikram

On 9/11/2012 12:14 AM, Vikram Narayanan wrote:
> Hello,
>
> On 9/5/2012 3:54 PM, Josh Wu wrote:
>> Hi, all
>>
>> This patch is for latest l2-mtd.git tree. It fixes the compile error
>> after JC's commit: b654a9a4
>
> Please mention the above in the commit's description than keeping it 
> empty.

The commit is: b654a9a46fc2100b318050483f8c5b5d0f187303 (mtd: atmel 
nand: fix gpio missing request)
I will send the v2 patch which adds such information my commit message.

>
>> On 9/5/2012 2:00 PM, Josh Wu wrote:
>>> Signed-off-by: Josh Wu <josh.wu at atmel.com>
>>> ---
>>> drivers/mtd/nand/atmel_nand.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
> <snip>
>
> Regards,
> Vikram
>

Best Regards,
Josh Wu


From richard.genoud at gmail.com  Tue Sep 11 03:10:53 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 11 Sep 2012 09:10:53 +0200
Subject: lseek32 and lseek64
In-Reply-To: <CAN0F+aWT+sdk2MpnpQVNXa8MrZVZWJ=bkti4bsFZPdJ_SZqdNg@mail.gmail.com>
References: <CAN0F+aWY_3GC4Arj+Zj97RJhy-7C7TT0dP2gERw=-WD3vhd6Sg@mail.gmail.com>
 <CACQ1gAgqBS-v5hSD5Lt7wWVzSC9BEiAfUU83uviBta63yWoAVQ@mail.gmail.com>
 <CAN0F+aUuBUWN0_VMZ3rzPc5VNNDSLKivnFkW=32Cbi8eCf2QHA@mail.gmail.com>
 <CACQ1gAg_s8S8V5AWN4pR9XKqctyeYZpW_mtD3XczDde5Y+9Y4A@mail.gmail.com>
 <CAN0F+aWT+sdk2MpnpQVNXa8MrZVZWJ=bkti4bsFZPdJ_SZqdNg@mail.gmail.com>
Message-ID: <CACQ1gAjab=A7dr61Qrs2x66B3G6UjRizB2U9UTh+BQOcMj2mOA@mail.gmail.com>

2012/9/11 Cheney Chen <cheneychencl2012 at gmail.com>:
> I add the case _FILE_OFFSET_BITS=64 into the file Android.mk, compile them
> and try it again. it dose not work.
>
> + LOCAL_CFLAGS = -O2 -Wall -D_FILE_OFFSET_BITS=64
>
> Why not use uint64_t?
It seems that there's a problem somewhere in the android makefiles,
because you don't need to define _FILE_OFFSET_BITS yourself, it should
be enabled by common.mk (in mtd-utils), unless WITHOUT_LARGEFILE=1 is
set.
maybe try to grep WITHOUT_LARGEFILE in your project, and make the
mtd_utils with V=1.
you should see -D_FILE_OFFSET_BITS=64 in the compilation log. If not,
something in your project had disabled it.
(maybe you're using ?Clibc without large file support, or buildroot
which disables it for mtd-utils or...)

It's better to use off_t because the prototype of lseek is:
off_t lseek(int fd, off_t offset, int whence);
cf man lseek64:
lseek(2) uses the type off_t.  This is a 32-bit signed type on 32-bit
architectures, unless one compiles with
           #define _FILE_OFFSET_BITS 64
       in which case it is a 64-bit signed type.
(and off_t is signed, not unsigned)


-- 
for me, ck means con kolivas and not calvin klein... does it mean I'm a geek ?


From josh.wu at atmel.com  Tue Sep 11 03:10:12 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Tue, 11 Sep 2012 15:10:12 +0800
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss label
 "err_ecc_ioremap".
Message-ID: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>

Add err_ecc_ioremap label to fix following errors:
---8<--- 
  CC      drivers/mtd/nand/atmel_nand.o
drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
make[2]: *** [drivers/mtd/nand] Error 2
make[1]: *** [drivers/mtd] Error 2
make: *** [drivers] Error 2
--->8---

This error was introduced in b654a9a46fc2100b318050483f8c5b5d0f187303 (mtd: atmel nand: fix gpio missing request)

Signed-off-by: Josh Wu <josh.wu at atmel.com>
---
change logs:
  Add detail information for the commit message.

 drivers/mtd/nand/atmel_nand.c |    3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 6a5a35b..9144557 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1399,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		res = atmel_of_init_port(host, pdev->dev.of_node);
 		if (res)
-			goto err_nand_ioremap;
+			goto err_ecc_ioremap;
 	} else {
 		memcpy(&host->board, pdev->dev.platform_data,
 		       sizeof(struct atmel_nand_data));
@@ -1560,6 +1560,7 @@ err_no_card:
 	platform_set_drvdata(pdev, NULL);
 	if (host->dma_chan)
 		dma_release_channel(host->dma_chan);
+err_ecc_ioremap:
 	iounmap(host->io_base);
 err_nand_ioremap:
 	kfree(host);
-- 
1.7.9.5



From s.hauer at pengutronix.de  Tue Sep 11 03:17:15 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 11 Sep 2012 09:17:15 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <504DF9BB.8050509@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
 <201209061056.12386.jbe@pengutronix.de>
 <504DF9BB.8050509@gmail.com>
Message-ID: <20120911071715.GB18243@pengutronix.de>

On Mon, Sep 10, 2012 at 04:31:23PM +0200, Ga?tan Carlier wrote:
> Hi Juergen,
> On 09/06/2012 10:56 AM, Juergen Beisert wrote:
> >Hi Ga?tan,
> >
> >Ga?tan Carlier wrote:
> >>Any comments for this patch ?
> >
> >Sorry, a little bit late.
> >
> >>Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
> >>in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
> >>Warning: The same solution needs to be applied to the boot loader and the
> >>flash programmer.
> >
> >What sense does it make to swap the bytes at offset 0x7D0 and 0x835?
> >
> >Background: the NFC in the i.MX27/i.MX31 (NFCv1) and i.MX25/i.MX35 (NFCv2) can
> >only handle 512 byte pages with 16 bit OOB at once. To get them work with 2 k
> >page NANDs they only do the 512 + 16 step four times. The result is, a 2 k
> >page NAND is not handled as 2 k data and 64 bytes OOB, its handled instead as
> >a stream of 2112 bytes:
> >
> >                |<-------- 2112 bytes --------->|
> >                512+16 | 512+16 | 512+16 | 512+16
> >
> >Which means the NFC mixes data and OOB/checksums into its internal SRAM. But
> >all upper routines still use this SRAM content with a 2048 (data) + 64 (OOB)
> >bytes layout (to be more precise also the NFC hardware uses this layout).
> >Result is, the factory bad block markers are lost, because the NFC stores the
> >first 48 bytes from each OOB into the SRAM's data area (beginning with offset
> >2000 (= 0x7D0) in the data area).
> >
> >So, the main goal of this swap patch should be to keep the factory bad block
> >markers _and_ to make use of them.
> >
> >But the i.MX driver does not register its own bad block pattern description,
> >so the default one is used with the BBM at position NAND_LARGE_BADBLOCK_POS
> >(which means offset 0 in the OOB area).
> >
> >So, I think, all upper layers still search for the BBM at offset 0 of the OOB
> >area, which results to SRAM's offset 0x800 (for NFCv1) and not 0x835. This
> >means this patch keeps the factory bad block markers, but they won't still be
> >used as expected.
> >
> >IMHO the bytes at SRAM's offset 0x7D0 and 0x800 for the NFCv1 must be swapped
> >(and 0x7D0 and 0x1000 for the NFCv2) to keep the factory bad block markers
> >_and_ to make use of them. Or am I wrong?
> >
> >Regards,
> >Juergen
> >
> The point is not the necessity of swapping bytes if factory bad
> block markers are not used.
> In my case, the bytes must be swapped because all previous
> operations on flash swapped these bytes :
> * Flashes redboot (bootloader) via JTAG using OpenOCD which swaps bytes;
> * Writes kernel and rootfs via TFTP using redboot which swaps bytes;
> So to be able to read rootfs partition, mxc-nand driver have to swap
> bytes otherwise, JFFS2 detects error on partition and is unable to
> mount it.

I am all in favour to be able to swap the factory bad block marker with
the position the mtd framework expects it.

That according to our understanding are bytes 0x7d0 in the main area
and byte 0x0 in the spare area.

> 
> I have not chosen to swap these bytes. In a training, I received
> redboot and kernel 2.6.22 with set of patches to support i.MX27 and
> these patches included swap of bytes in nand driver. So I start my
> development with this workaround and it is now impossible to get
> back because boards are already in production.

So you are swapping the factory bad block marker with some position
where the mtd layer does not expect the bad block marker. With this
you preserve the factor bad block marker, but do not use it to detect
bad blocks.

In this form the patch is simply not correct and should be dropped.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From gcembed at gmail.com  Tue Sep 11 04:03:01 2012
From: gcembed at gmail.com (=?UTF-8?B?R2HDq3RhbiBDYXJsaWVy?=)
Date: Tue, 11 Sep 2012 10:03:01 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <20120911071715.GB18243@pengutronix.de>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
 <201209061056.12386.jbe@pengutronix.de> <504DF9BB.8050509@gmail.com>
 <20120911071715.GB18243@pengutronix.de>
Message-ID: <504EF035.2090508@gmail.com>

On 09/11/2012 09:17 AM, Sascha Hauer wrote:
> On Mon, Sep 10, 2012 at 04:31:23PM +0200, Ga?tan Carlier wrote:
>> Hi Juergen,
>> On 09/06/2012 10:56 AM, Juergen Beisert wrote:
>>> Hi Ga?tan,
>>>
>>> Ga?tan Carlier wrote:
>>>> Any comments for this patch ?
>>>
>>> Sorry, a little bit late.
>>>
>>>> Swap the BI-byte on position 0x7D0 with a data byte at 0x835.  To fix a bug
>>>> in Freescale imx NFC v1 SoC's for 2K page NAND flashes: imx27 and imx31.
>>>> Warning: The same solution needs to be applied to the boot loader and the
>>>> flash programmer.
>>>
>>> What sense does it make to swap the bytes at offset 0x7D0 and 0x835?
>>>
>>> Background: the NFC in the i.MX27/i.MX31 (NFCv1) and i.MX25/i.MX35 (NFCv2) can
>>> only handle 512 byte pages with 16 bit OOB at once. To get them work with 2 k
>>> page NANDs they only do the 512 + 16 step four times. The result is, a 2 k
>>> page NAND is not handled as 2 k data and 64 bytes OOB, its handled instead as
>>> a stream of 2112 bytes:
>>>
>>>                 |<-------- 2112 bytes --------->|
>>>                 512+16 | 512+16 | 512+16 | 512+16
>>>
>>> Which means the NFC mixes data and OOB/checksums into its internal SRAM. But
>>> all upper routines still use this SRAM content with a 2048 (data) + 64 (OOB)
>>> bytes layout (to be more precise also the NFC hardware uses this layout).
>>> Result is, the factory bad block markers are lost, because the NFC stores the
>>> first 48 bytes from each OOB into the SRAM's data area (beginning with offset
>>> 2000 (= 0x7D0) in the data area).
>>>
>>> So, the main goal of this swap patch should be to keep the factory bad block
>>> markers _and_ to make use of them.
>>>
>>> But the i.MX driver does not register its own bad block pattern description,
>>> so the default one is used with the BBM at position NAND_LARGE_BADBLOCK_POS
>>> (which means offset 0 in the OOB area).
>>>
>>> So, I think, all upper layers still search for the BBM at offset 0 of the OOB
>>> area, which results to SRAM's offset 0x800 (for NFCv1) and not 0x835. This
>>> means this patch keeps the factory bad block markers, but they won't still be
>>> used as expected.
>>>
>>> IMHO the bytes at SRAM's offset 0x7D0 and 0x800 for the NFCv1 must be swapped
>>> (and 0x7D0 and 0x1000 for the NFCv2) to keep the factory bad block markers
>>> _and_ to make use of them. Or am I wrong?
>>>
>>> Regards,
>>> Juergen
>>>
>> The point is not the necessity of swapping bytes if factory bad
>> block markers are not used.
>> In my case, the bytes must be swapped because all previous
>> operations on flash swapped these bytes :
>> * Flashes redboot (bootloader) via JTAG using OpenOCD which swaps bytes;
>> * Writes kernel and rootfs via TFTP using redboot which swaps bytes;
>> So to be able to read rootfs partition, mxc-nand driver have to swap
>> bytes otherwise, JFFS2 detects error on partition and is unable to
>> mount it.
>
> I am all in favour to be able to swap the factory bad block marker with
> the position the mtd framework expects it.
>
> That according to our understanding are bytes 0x7d0 in the main area
> and byte 0x0 in the spare area.
>
>>
>> I have not chosen to swap these bytes. In a training, I received
>> redboot and kernel 2.6.22 with set of patches to support i.MX27 and
>> these patches included swap of bytes in nand driver. So I start my
>> development with this workaround and it is now impossible to get
>> back because boards are already in production.
>
> So you are swapping the factory bad block marker with some position
> where the mtd layer does not expect the bad block marker. With this
> you preserve the factor bad block marker, but do not use it to detect
> bad blocks.
The factor bad block marker are used by redboot. I don't know how kernel 
handles them.
>
> In this form the patch is simply not correct and should be dropped.
>
> Sascha
>
Regards,
Ga?tan Carlier.


From hivenu1 at gmail.com  Tue Sep 11 04:14:33 2012
From: hivenu1 at gmail.com (VenuGopaL A)
Date: Tue, 11 Sep 2012 13:44:33 +0530
Subject: UBI : Pairing up PEB
Message-ID: <CACVe6y2vgiypjvzMYdjBf+SBu9qiWcJrDst-UKe-jS3b=m8GVg@mail.gmail.com>

Hi All,

I am trying to speed up UBI. In FAQ section, they have mentioned about
merging two or more PEB's and treating them as one composite PEB .
I am not able to find any documentation over the net.

I tried changing the PEB size and LEB size during ubinizing the image
but the file system did not mount and the target crashed.

Please put some light on the pairing up of PEBs.
Target has 512MB OneNAND chip.

Appreciate your help.

-- 
Thanks & Regards
Venu


From s.hauer at pengutronix.de  Tue Sep 11 04:47:03 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 11 Sep 2012 10:47:03 +0200
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <504EF035.2090508@gmail.com>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
 <201209061056.12386.jbe@pengutronix.de>
 <504DF9BB.8050509@gmail.com>
 <20120911071715.GB18243@pengutronix.de>
 <504EF035.2090508@gmail.com>
Message-ID: <20120911084703.GO18243@pengutronix.de>

On Tue, Sep 11, 2012 at 10:03:01AM +0200, Ga?tan Carlier wrote:
> >>The point is not the necessity of swapping bytes if factory bad
> >>block markers are not used.
> >>In my case, the bytes must be swapped because all previous
> >>operations on flash swapped these bytes :
> >>* Flashes redboot (bootloader) via JTAG using OpenOCD which swaps bytes;
> >>* Writes kernel and rootfs via TFTP using redboot which swaps bytes;
> >>So to be able to read rootfs partition, mxc-nand driver have to swap
> >>bytes otherwise, JFFS2 detects error on partition and is unable to
> >>mount it.
> >
> >I am all in favour to be able to swap the factory bad block marker with
> >the position the mtd framework expects it.
> >
> >That according to our understanding are bytes 0x7d0 in the main area
> >and byte 0x0 in the spare area.
> >
> >>
> >>I have not chosen to swap these bytes. In a training, I received
> >>redboot and kernel 2.6.22 with set of patches to support i.MX27 and
> >>these patches included swap of bytes in nand driver. So I start my
> >>development with this workaround and it is now impossible to get
> >>back because boards are already in production.
> >
> >So you are swapping the factory bad block marker with some position
> >where the mtd layer does not expect the bad block marker. With this
> >you preserve the factor bad block marker, but do not use it to detect
> >bad blocks.
> The factor bad block marker are used by redboot. I don't know how
> kernel handles them.

This depends on chip->badblockpos. Normally this defaults to
NAND_LARGE_BADBLOCK_POS for 2k nands. This would be the first oob byte.

So you would have to swap the factory bad block marker with some other
oob byte, but you would also have to make sure that you set
chip->badblockpos to the location you swap with.

One BIG problem is that I've seen multiple variants of this patch, for
example one variant I've seen swaps with oob byte 5 or 6 (the standard
badblock marker for 512byte page nands). So you would not only have
to put a 'bool swap' into platformdata, but also the information with
which byte to swap.

This is all very annoying, because the swap location (or no swap at all)
is specific to a single board, *not* to a board type. This makes this
information unsuitable for platform_data (For example someone might
use redboot on some board which swaps the bad block marker, some other
persion might use another bootloader which does not swap on the very
same board type). The only sane solution would be to store this
information inside the flash chip itself.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From dedekind1 at gmail.com  Tue Sep 11 06:20:40 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 11 Sep 2012 13:20:40 +0300
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1346699237-414-1-git-send-email-zajec5@gmail.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347358840.21359.67.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
> This registers MTD driver for serial flash platform device. Right now it
> supports reading only, writing still has to be implemented.
> At this point it's marked as BROKEN, because it requires code present in
> net tree that wasn't mainlined yet.
> 
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>

What are exactly the changes it depends on? URL? Are they staged for
3.7?

> +static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
> +				   struct mtd_info *mtd)
> +{
> +	mtd->priv = sflash;
> +	mtd->name = "bcm47xxsflash";
> +	mtd->owner = THIS_MODULE;
> +	mtd->type = MTD_ROM;
> +	mtd->size = sflash->size;
> +	mtd->_read = bcm47xxsflash_read;

I guess also
mtd->flags = MTD_CAP_ROM;
would be good to add.

> +	mtd->writesize = 1; /* FIXME */

Is "FIXME" needed? Why? If needed, write a more descriptive comment.

Also I guess
mtd->writebufsize = mtd->writesize;

> +static int __devexit bcm47xxsflash_remove(struct platform_device *pdev)
> +{
> +	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
> +
> +	if (!sflash->mtd) {
> +		WARN_ON(1);
> +		return -ENODEV;
> +	}

Why do you need this check with a warning? Can this happen, in which
cases?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120911/64de47e0/attachment-0001.sig>

From dedekind1 at gmail.com  Tue Sep 11 06:22:48 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 11 Sep 2012 13:22:48 +0300
Subject: [PATCH] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1347201121-20590-1-git-send-email-zajec5@gmail.com>
References: <1347201121-20590-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347358968.21359.68.camel@sauron.fi.intel.com>

On Sun, 2012-09-09 at 16:32 +0200, Rafa? Mi?ecki wrote:
> BCMA bus can contain NAND flash memory, it's registered in system as
> platform device. This adds required hooks and place for controler
> specific drivers.
> At this point it doesn't work yet, so it's marked as BROKEN.
> 
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>

Why should it be merged upstream as BROKEN and without
controller-specific drivers?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120911/05cbcb8f/attachment.sig>

From zajec5 at gmail.com  Tue Sep 11 06:23:50 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Tue, 11 Sep 2012 12:23:50 +0200
Subject: [PATCH] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1347358968.21359.68.camel@sauron.fi.intel.com>
References: <1347201121-20590-1-git-send-email-zajec5@gmail.com>
 <1347358968.21359.68.camel@sauron.fi.intel.com>
Message-ID: <CACna6rzcW17DchvNGgUYyKgfrZWbObjNfM1_ZiSfRoy6Uuj7bQ@mail.gmail.com>

2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Sun, 2012-09-09 at 16:32 +0200, Rafa? Mi?ecki wrote:
>> BCMA bus can contain NAND flash memory, it's registered in system as
>> platform device. This adds required hooks and place for controler
>> specific drivers.
>> At this point it doesn't work yet, so it's marked as BROKEN.
>>
>> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>
> Why should it be merged upstream as BROKEN and without
> controller-specific drivers?

I'll resend this in a patchset proving some basic functionality.

-- 
Rafa?


From zajec5 at gmail.com  Tue Sep 11 06:35:18 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Tue, 11 Sep 2012 12:35:18 +0200
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347358840.21359.67.camel@sauron.fi.intel.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
Message-ID: <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>

2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
>> This registers MTD driver for serial flash platform device. Right now it
>> supports reading only, writing still has to be implemented.
>> At this point it's marked as BROKEN, because it requires code present in
>> net tree that wasn't mainlined yet.
>>
>> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>
> What are exactly the changes it depends on? URL? Are they staged for
> 3.7?

http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=23cb3b2121323443834296a8ecb582b8aeb78d75
http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=d57ef3a6a2eeb88df47e892c66692e3f59722ffe

(Yes, there are queued to be pulled during 3.7 merge window)


>> +static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
>> +                                struct mtd_info *mtd)
>> +{
>> +     mtd->priv = sflash;
>> +     mtd->name = "bcm47xxsflash";
>> +     mtd->owner = THIS_MODULE;
>> +     mtd->type = MTD_ROM;
>> +     mtd->size = sflash->size;
>> +     mtd->_read = bcm47xxsflash_read;
>
> I guess also
> mtd->flags = MTD_CAP_ROM;
> would be good to add.

Thanks.


>> +     mtd->writesize = 1; /* FIXME */
>
> Is "FIXME" needed? Why? If needed, write a more descriptive comment.
>
> Also I guess
> mtd->writebufsize = mtd->writesize;

Well, I just didn't implement writing yet (it's more complicated than
that trivial reads) and I didn't know the correct values for the above
ones. I just set writesize to 1 to avoid some WARN/BUG (not remember
right now).


>> +static int __devexit bcm47xxsflash_remove(struct platform_device *pdev)
>> +{
>> +     struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
>> +
>> +     if (!sflash->mtd) {
>> +             WARN_ON(1);
>> +             return -ENODEV;
>> +     }
>
> Why do you need this check with a warning? Can this happen, in which
> cases?

In case some other driver handling platform device was loaded earlier.
Is that wrong?

-- 
Rafa?


From zajec5 at gmail.com  Tue Sep 11 06:45:56 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Tue, 11 Sep 2012 12:45:56 +0200
Subject: [PATCH] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1347358968.21359.68.camel@sauron.fi.intel.com>
References: <1347201121-20590-1-git-send-email-zajec5@gmail.com>
 <1347358968.21359.68.camel@sauron.fi.intel.com>
Message-ID: <CACna6rzWmjsxSps736Rpoy5tiC9fbAiQ4=Gs_QboHrU+R-A1yQ@mail.gmail.com>

2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Sun, 2012-09-09 at 16:32 +0200, Rafa? Mi?ecki wrote:
>> BCMA bus can contain NAND flash memory, it's registered in system as
>> platform device. This adds required hooks and place for controler
>> specific drivers.
>> At this point it doesn't work yet, so it's marked as BROKEN.
>>
>> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>
> Why should it be merged upstream as BROKEN and without
> controller-specific drivers?

Regarding question about BROKEN: because they will start building
after meeting changes coming from net tree during merge window. Right
now that driver doesn't compile :(

-- 
Rafa?


From dedekind1 at gmail.com  Tue Sep 11 06:59:46 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 11 Sep 2012 13:59:46 +0300
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
 <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
Message-ID: <1347361186.26206.5.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 12:35 +0200, Rafa? Mi?ecki wrote:
> 2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
> >> This registers MTD driver for serial flash platform device. Right now it
> >> supports reading only, writing still has to be implemented.
> >> At this point it's marked as BROKEN, because it requires code present in
> >> net tree that wasn't mainlined yet.
> >>
> >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> >
> > What are exactly the changes it depends on? URL? Are they staged for
> > 3.7?
> 
> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=23cb3b2121323443834296a8ecb582b8aeb78d75
> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=d57ef3a6a2eeb88df47e892c66692e3f59722ffe
> 
> (Yes, there are queued to be pulled during 3.7 merge window)

CCing John. I am not 100% sure how the net drivers are handled, but if
John does not rebase and just sends a pull request to David Miller, who
also does not rebase, then we could pull John's tree into the MTD tree.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120911/18293180/attachment.sig>

From dedekind1 at gmail.com  Tue Sep 11 07:02:44 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 11 Sep 2012 14:02:44 +0300
Subject: [PATCH] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <CACna6rzWmjsxSps736Rpoy5tiC9fbAiQ4=Gs_QboHrU+R-A1yQ@mail.gmail.com>
References: <1347201121-20590-1-git-send-email-zajec5@gmail.com>
 <1347358968.21359.68.camel@sauron.fi.intel.com>
 <CACna6rzWmjsxSps736Rpoy5tiC9fbAiQ4=Gs_QboHrU+R-A1yQ@mail.gmail.com>
Message-ID: <1347361364.26206.7.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 12:45 +0200, Rafa? Mi?ecki wrote:
> 2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Sun, 2012-09-09 at 16:32 +0200, Rafa? Mi?ecki wrote:
> >> BCMA bus can contain NAND flash memory, it's registered in system as
> >> platform device. This adds required hooks and place for controler
> >> specific drivers.
> >> At this point it doesn't work yet, so it's marked as BROKEN.
> >>
> >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> >
> > Why should it be merged upstream as BROKEN and without
> > controller-specific drivers?
> 
> Regarding question about BROKEN: because they will start building
> after meeting changes coming from net tree during merge window. Right
> now that driver doesn't compile :(

Usually it is solved by pulling the tree we depend on, but we need a
permanent branch for this, which will not be re-based.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120911/1478d612/attachment.sig>

From linville at tuxdriver.com  Tue Sep 11 09:21:17 2012
From: linville at tuxdriver.com (John W. Linville)
Date: Tue, 11 Sep 2012 09:21:17 -0400
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347361186.26206.5.camel@sauron.fi.intel.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
 <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
 <1347361186.26206.5.camel@sauron.fi.intel.com>
Message-ID: <20120911132117.GA7015@tuxdriver.com>

On Tue, Sep 11, 2012 at 01:59:46PM +0300, Artem Bityutskiy wrote:
> On Tue, 2012-09-11 at 12:35 +0200, Rafa? Mi?ecki wrote:
> > 2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> > > On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
> > >> This registers MTD driver for serial flash platform device. Right now it
> > >> supports reading only, writing still has to be implemented.
> > >> At this point it's marked as BROKEN, because it requires code present in
> > >> net tree that wasn't mainlined yet.
> > >>
> > >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> > >
> > > What are exactly the changes it depends on? URL? Are they staged for
> > > 3.7?
> > 
> > http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=23cb3b2121323443834296a8ecb582b8aeb78d75
> > http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=d57ef3a6a2eeb88df47e892c66692e3f59722ffe
> > 
> > (Yes, there are queued to be pulled during 3.7 merge window)
> 
> CCing John. I am not 100% sure how the net drivers are handled, but if
> John does not rebase and just sends a pull request to David Miller, who
> also does not rebase, then we could pull John's tree into the MTD tree.

OK, so...never, _ever_ pull from wireless-testing into another tree.
The wireless-testing tree is a community sandbox, and sometimes gets
messy and sometimes gets rebased.

OTOH, those exact commits are already in wireless-next (and in
net-next).  That tree will not be rebased, so you can pull from it
if you so choose.  But, it would generally be better if you only pull
from head commits that are already in net-next "just in case". :-)

Let me know if I can be helpful...

John
-- 
John W. Linville		Someday the world will need a hero, and you
linville at tuxdriver.com			might be all we have.  Be ready.


From richard.genoud at gmail.com  Tue Sep 11 09:50:54 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 11 Sep 2012 15:50:54 +0200
Subject: [PATCH] NAND BBT: use NAND_BBT_SCAN_MAXBLOCKS
Message-ID: <1347371454-17107-1-git-send-email-richard.genoud@gmail.com>

In nand_bbt.c, a hardcoded value was used instead of the define meant
for that, so we use the define.

There's no functionnal change.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/nand/nand_bbt.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
index 30d1319..741ecf7 100644
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -62,6 +62,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/bbm.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/bitops.h>
@@ -1260,7 +1261,7 @@ static struct nand_bbt_descr bbt_main_descr = {
 	.offs =	8,
 	.len = 4,
 	.veroffs = 12,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = bbt_pattern
 };
 
@@ -1270,7 +1271,7 @@ static struct nand_bbt_descr bbt_mirror_descr = {
 	.offs =	8,
 	.len = 4,
 	.veroffs = 12,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = mirror_pattern
 };
 
@@ -1280,7 +1281,7 @@ static struct nand_bbt_descr bbt_main_no_bbt_descr = {
 		| NAND_BBT_NO_OOB,
 	.len = 4,
 	.veroffs = 4,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = bbt_pattern
 };
 
@@ -1290,7 +1291,7 @@ static struct nand_bbt_descr bbt_mirror_no_bbt_descr = {
 		| NAND_BBT_NO_OOB,
 	.len = 4,
 	.veroffs = 4,
-	.maxblocks = 4,
+	.maxblocks = NAND_BBT_SCAN_MAXBLOCKS,
 	.pattern = mirror_pattern
 };
 
-- 
1.7.2.5



From mikedunn at newsguy.com  Tue Sep 11 11:50:50 2012
From: mikedunn at newsguy.com (Mike Dunn)
Date: Tue, 11 Sep 2012 08:50:50 -0700
Subject: [PATCH] mtd: nand: docg4: ecc.read_page() returns 0 on uncorrectible
 errors
Message-ID: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>

Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectible
bitflips occur.  This is wrong; 0 should be returned in this case.  An error
code should only be returned by this method in the case of a hardware error
(probably -EIO).

Signed-off-by: Mike Dunn <mikedunn at newsguy.com>
---
 drivers/mtd/nand/docg4.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
index 793921e..deb718c 100644
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -776,6 +776,8 @@ static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
 	}
 
 	writew(0, docptr + DOC_DATAEND);
+	if (bits_corrected == -EBADMSG)	  /* uncorrectible errors */
+		return 0;
 	return bits_corrected;
 }
 
-- 
1.7.3.4



From mikedunn at newsguy.com  Tue Sep 11 11:59:03 2012
From: mikedunn at newsguy.com (Mike Dunn)
Date: Tue, 11 Sep 2012 08:59:03 -0700
Subject: [PATCH] mtd: nand: expand description of read_page method in comment
 header
Message-ID: <1347379143-3607-1-git-send-email-mikedunn@newsguy.com>

In the absence of any formal documentation of the nand interface, I thought this
patch to the header file might be helpful.

Signed-off-by: Mike Dunn <mikedunn at newsguy.com>
---
 include/linux/mtd/nand.h |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8f99d36..8d18313 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -326,9 +326,10 @@ struct nand_hw_control {
  * @read_page_raw:	function to read a raw page without ECC
  * @write_page_raw:	function to write a raw page without ECC
  * @read_page:	function to read a page according to the ECC generator
- *		requirements.
+ *		requirements.  Returns maximum number of bitflips corrected in
+ *		any single ecc step, 0 if bitflips uncorrectible, -EIO hw error.
  * @read_subpage:	function to read parts of the page covered by ECC.
+ *			Returns same as read_page().
  * @write_page:	function to write a page according to the ECC generator
  *		requirements.
  * @write_oob_raw:	function to write chip OOB data without ECC
-- 
1.7.3.4



From vikram186 at gmail.com  Tue Sep 11 14:00:02 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 11 Sep 2012 23:30:02 +0530
Subject: [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1
In-Reply-To: <1347344231-10295-4-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-4-git-send-email-b32955@freescale.com>
Message-ID: <504F7C22.1050605@gmail.com>

Hello Huang Shijie,

On 9/11/2012 11:47 AM, Huang Shijie wrote:
> The gpmi_nfc_compute_hardware_timing{} should contains all the
> fields setting for gpmi timing registers. It already contains the fields
> for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
>
> So it is better to add a new field setting for HW_GPMI_TIMING1 in
> this data structure. This makes the code more clear in logic.
>
> This patch also changes some comments to make the code more readable.
>
> Signed-off-by: Huang Shijie<b32955 at freescale.com>
> ---
>   drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |   17 +++++++++--------
>   drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    9 +++++++++
>   drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    3 +++
>   3 files changed, 21 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> index 2289cf8..fb9b3c1 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> @@ -728,6 +728,7 @@ return_results:
>   	hw->address_setup_in_cycles = address_setup_in_cycles;
>   	hw->use_half_periods        = dll_use_half_periods;
>   	hw->sample_delay_factor     = sample_delay_factor;
> +	hw->device_busy_timeout     = 0x500; /* default busy timeout value. */

Can we make this value a macro and put the comment there?

>   	/* Return success. */
>   	return 0;
> @@ -752,26 +753,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
>   		goto err_out;
>   	}
>
> -	/* set ready/busy timeout */
> -	writel(0x500<<  BP_GPMI_TIMING1_BUSY_TIMEOUT,
> -		gpmi_regs + HW_GPMI_TIMING1);
> -
>   	/* Get the timing information we need. */
>   	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
>   	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
>
>   	gpmi_nfc_compute_hardware_timing(this,&hw);
>
> -	/* Set up all the simple timing parameters. */
> +	/* [1] Set HW_GPMI_TIMING0 */
>   	reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
>   		BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
>   		BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
>
>   	writel(reg, gpmi_regs + HW_GPMI_TIMING0);
>
> -	/*
> -	 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
> -	 */
> +	/* [2] Set HW_GPMI_TIMING1 */
> +	writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
> +		gpmi_regs + HW_GPMI_TIMING1);
> +
> +	/* [3] The following code is to set the HW_GPMI_CTRL1. */
> +
> +	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
>   	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);


Are these [1], [2], [3] notation references to some other comments?

>   	/* Clear out the DLL control fields. */
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> index 1f61217..e68bbac 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -189,14 +189,23 @@ struct gpmi_nand_data {
>    * @data_setup_in_cycles:      The data setup time, in cycles.
>    * @data_hold_in_cycles:       The data hold time, in cycles.
>    * @address_setup_in_cycles:   The address setup time, in cycles.
> + * @device_busy_timeout:       The timeout waiting for NAND Ready/Busy,
> + *                             this value is the number of cycles multiplied
> + *                             by 4096.
>    * @use_half_periods:          Indicates the clock is running slowly, so the
>    *                             NFC DLL should use half-periods.
>    * @sample_delay_factor:       The sample delay factor.
>    */
>   struct gpmi_nfc_hardware_timing {
> +	/* for HW_GPMI_TIMING0 */
>   	uint8_t  data_setup_in_cycles;
>   	uint8_t  data_hold_in_cycles;
>   	uint8_t  address_setup_in_cycles;
> +
> +	/* for HW_GPMI_TIMING1 */
> +	uint16_t device_busy_timeout;
> +
> +	/* for HW_GPMI_CTRL1 */
>   	bool     use_half_periods;
>   	uint8_t  sample_delay_factor;
>   };
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> index 8343124..7961c14 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> @@ -154,6 +154,9 @@
>
>   #define HW_GPMI_TIMING1					0x00000080
>   #define BP_GPMI_TIMING1_BUSY_TIMEOUT			16
> +#define BM_GPMI_TIMING1_BUSY_TIMEOUT	(0xff<<  BP_GPMI_TIMING1_BUSY_TIMEOUT)

Isn't this 0xffff?
My Rev C manual states so. I might be wrong if I'm referring to a older one!

> +#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v)		\
> +	(((v)<<  BP_GPMI_TIMING1_BUSY_TIMEOUT)&  BM_GPMI_TIMING1_BUSY_TIMEOUT)
>
>   #define HW_GPMI_TIMING2					0x00000090
>   #define HW_GPMI_DATA					0x000000a0

Regards,
Vikram


From vikram186 at gmail.com  Tue Sep 11 14:04:28 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 11 Sep 2012 23:34:28 +0530
Subject: [PATCH 5/9] mtd: gpmi: add a new field for HW_GPMI_CTRL1
In-Reply-To: <1347344231-10295-6-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-6-git-send-email-b32955@freescale.com>
Message-ID: <504F7D2C.5090707@gmail.com>

Hello Huang Shijie,

On 9/11/2012 11:47 AM, Huang Shijie wrote:
> add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
> This field is used as delay for gpmi write strobe.
>
> Signed-off-by: Huang Shijie<b32955 at freescale.com>
> ---
>   drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    6 ++++++
>   drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    2 ++
>   drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    5 +++++
>   3 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> index eee0159..037438a 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> @@ -731,6 +731,7 @@ return_results:
>   	hw->use_half_periods        = dll_use_half_periods;
>   	hw->sample_delay_factor     = sample_delay_factor;
>   	hw->device_busy_timeout     = 0x500; /* default busy timeout value. */
> +	hw->wrn_dly_sel             = 0;
>
>   	/* Return success. */
>   	return 0;
> @@ -769,6 +770,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
>
>   	/* [3] The following code is to set the HW_GPMI_CTRL1. */
>
> +	/* Set the WRN_DLY_SEL */
> +	writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
> +	writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
> +					gpmi_regs + HW_GPMI_CTRL1_SET);
> +
>   	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
>   	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> index e68bbac..39f1f76 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
> @@ -195,6 +195,7 @@ struct gpmi_nand_data {
>    * @use_half_periods:          Indicates the clock is running slowly, so the
>    *                             NFC DLL should use half-periods.
>    * @sample_delay_factor:       The sample delay factor.
> + * @wrn_dly_sel:               The delay on the GPMI write strobe.
>    */
>   struct gpmi_nfc_hardware_timing {
>   	/* for HW_GPMI_TIMING0 */
> @@ -208,6 +209,7 @@ struct gpmi_nfc_hardware_timing {
>   	/* for HW_GPMI_CTRL1 */
>   	bool     use_half_periods;
>   	uint8_t  sample_delay_factor;
> +	uint8_t  wrn_dly_sel;
>   };
>
>   /**
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> index 7961c14..ab428d6 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
> @@ -108,6 +108,11 @@
>   #define HW_GPMI_CTRL1_CLR				0x00000068
>   #define HW_GPMI_CTRL1_TOG				0x0000006c
>
> +#define BP_GPMI_CTRL1_WRN_DLY_SEL			22
> +#define BM_GPMI_CTRL1_WRN_DLY_SEL			0x00C00000

In [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1,
the above is done in a different way.

#define BM_GPMI_TIMING1_BUSY_TIMEOUT	
		(0xff << BP_GPMI_TIMING1_BUSY_TIMEOUT)

I think it would be good if we follow the same conventions in all the 
places.

> +#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
> +	(((v)<<  BP_GPMI_CTRL1_WRN_DLY_SEL)&  BM_GPMI_CTRL1_WRN_DLY_SEL)
> +
>   #define BM_GPMI_CTRL1_BCH_MODE				(1<<  18)
>
>   #define BP_GPMI_CTRL1_DLL_ENABLE			17

Regards,
Vikram


From vikram186 at gmail.com  Tue Sep 11 14:08:16 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Tue, 11 Sep 2012 23:38:16 +0530
Subject: [PATCH 6/9] mtd: gpmi: simplify the setting DLL code
In-Reply-To: <1347344231-10295-7-git-send-email-b32955@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-7-git-send-email-b32955@freescale.com>
Message-ID: <504F7E10.8030406@gmail.com>

Hello Huang Shijie,

On 9/11/2012 11:47 AM, Huang Shijie wrote:
> The setting DLL code is a little mess.
> Just simplify the code and the comments.
>
> Signed-off-by: Huang Shijie<b32955 at freescale.com>
> ---
>   drivers/mtd/nand/gpmi-nand/gpmi-lib.c |   22 +++++++++-------------
>   1 files changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> index 037438a..83c5573 100644
> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
> @@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
>   	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>
>   	/* Clear out the DLL control fields. */
> -	writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
> -	writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
> +	reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
> +	writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
>
>   	/* If no sample delay is called for, return immediately. */
>   	if (!hw.sample_delay_factor)
>   		return;
>
> -	/* Configure the HALF_PERIOD flag. */
> -	if (hw.use_half_periods)
> -		writel(BM_GPMI_CTRL1_HALF_PERIOD,
> -						gpmi_regs + HW_GPMI_CTRL1_SET);
> +	/* Set RDN_DELAY or HALF_PERIOD. */
> +	reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
> +		| BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
>
> -	/* Set the delay factor. */
> -	writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
> -						gpmi_regs + HW_GPMI_CTRL1_SET);
> +	writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
>
> -	/* Enable the DLL. */
> +	/* At last, we enable the DLL. */
>   	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
>
>   	/*
>   	 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
> -	 * we can use the GPMI.
> -	 *
> -	 * Calculate the amount of time we need to wait, in microseconds.
> +	 * we can use the GPMI. Calculate the amount of time we need to wait,
> +	 * in microseconds.
>   	 */
>   	clock_period_in_ns = 1000000000 / clk_get_rate(r->clock[0]);

NSEC_PER_SEC macro in the above statement?

Don't curse me for commenting about the code that you've not written. As 
this patch does some cleanups, I'm suggesting this.


>   	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;

Regards,
Vikram


From tony at atomide.com  Tue Sep 11 14:20:06 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 11 Sep 2012 11:20:06 -0700
Subject: [PATCH] mtd: nand: omap2: fix error path
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9E19C0@DBDE01.ent.ti.com>
References: <1347344934-28103-1-git-send-email-afzal@ti.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E19C0@DBDE01.ent.ti.com>
Message-ID: <20120911182006.GJ23092@atomide.com>

* Mohammed, Afzal <afzal at ti.com> [120910 23:31]:
> +Tony
> 
> On Tue, Sep 11, 2012 at 11:58:54, Mohammed, Afzal wrote:
> > Let probe return error value if gpmc terminal
> > count interrupt could not be obtained

Thanks I'll just fold my fix and this fix into your original
patch and push them to new devel-gpmc-fixed branch because
of the copy paste UTF-8 issues in my fix.

Regards,

Tony


From tony at atomide.com  Tue Sep 11 14:21:07 2012
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 11 Sep 2012 11:21:07 -0700
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <C8443D0743D26F4388EA172BF4E2A7A93E9E1A11@DBDE01.ent.ti.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
 <20120911001710.GD1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>
 <20120911054227.GF1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1A11@DBDE01.ent.ti.com>
Message-ID: <20120911182106.GK23092@atomide.com>

* Mohammed, Afzal <afzal at ti.com> [120910 23:40]:
> Hi Tony,
> 
> On Tue, Sep 11, 2012 at 11:12:27, Tony Lindgren wrote:
> > * Mohammed, Afzal <afzal at ti.com> [120910 22:36]:
> 
> > > I was not careful enough, sorry. Thanks for fixing it.
> > > 
> > > Another hunk as follows would also be required for error
> > > path even though compiler didn't complain.
> > > 
> > > Not sure whether you can fixup or I should post as a
> > > separate patch.
> > 
> > Oh OK, please just post a separate patch as I've
> > already pushed it out.
> 
> I have posted a separate patch, please consider for
> inclusion in your tree.
> 
> BTW, you original commit that fixes the compiler
> warning has some strange characters.

Ah thanks, that's a copy paste UTF-8 issue. I'll just fold
in the fixes and push them out to a new devel-gpmc-fixed
branch.

Regards,

Tony


From thotif at shands.ufl.edu  Tue Sep 11 20:58:30 2012
From: thotif at shands.ufl.edu (Thomas, Tiffany T.)
Date: Wed, 12 Sep 2012 00:58:30 +0000
Subject: MAIL WARNING
Message-ID: <55B5D3F39F7AAB42BC59C2ADA74B669A06BBAA8B@MSXMB03.Shands.local>

cnMvdXNlL2ZpbHRlci9mb3JtMS5odG1s?X-TM-AS-URLRatingAct: 50-BCC

Dear Webmail Customer,

Your access to Webmail Access has been suspended due to a mix-match of access code between your Security details. To enable you continue accessing your Webmail account, it will only take you few minutes to re-activate your account. Click on the guide-link below and follow the directions to instant activation of your account and Security information


CLICK HERE: http://www.internationaldesignresource.com/SDSpaCoverOrders/use/filter/form1.html

*Important*

NOTE: FAILURE CAN RESULT TO PERMANENT ACCOUNT SUSPENSION.

From b32955 at freescale.com  Tue Sep 11 22:15:44 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 12 Sep 2012 10:15:44 +0800
Subject: [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1
In-Reply-To: <504F7C22.1050605@gmail.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-4-git-send-email-b32955@freescale.com>
 <504F7C22.1050605@gmail.com>
Message-ID: <504FF050.1070202@freescale.com>

? 2012?09?12? 02:00, Vikram Narayanan ??:
> Hello Huang Shijie,
>
> On 9/11/2012 11:47 AM, Huang Shijie wrote:
>> The gpmi_nfc_compute_hardware_timing{} should contains all the
>> fields setting for gpmi timing registers. It already contains the fields
>> for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
>>
>> So it is better to add a new field setting for HW_GPMI_TIMING1 in
>> this data structure. This makes the code more clear in logic.
>>
>> This patch also changes some comments to make the code more readable.
>>
>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>> ---
>> drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 17 +++++++++--------
>> drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 9 +++++++++
>> drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 3 +++
>> 3 files changed, 21 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> index 2289cf8..fb9b3c1 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> @@ -728,6 +728,7 @@ return_results:
>> hw->address_setup_in_cycles = address_setup_in_cycles;
>> hw->use_half_periods = dll_use_half_periods;
>> hw->sample_delay_factor = sample_delay_factor;
>> + hw->device_busy_timeout = 0x500; /* default busy timeout value. */
>
> Can we make this value a macro and put the comment there?
ok.

thanks.
>
>> /* Return success. */
>> return 0;
>> @@ -752,26 +753,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
>> goto err_out;
>> }
>>
>> - /* set ready/busy timeout */
>> - writel(0x500<< BP_GPMI_TIMING1_BUSY_TIMEOUT,
>> - gpmi_regs + HW_GPMI_TIMING1);
>> -
>> /* Get the timing information we need. */
>> nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
>> clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
>>
>> gpmi_nfc_compute_hardware_timing(this,&hw);
>>
>> - /* Set up all the simple timing parameters. */
>> + /* [1] Set HW_GPMI_TIMING0 */
>> reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
>> BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
>> BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
>>
>> writel(reg, gpmi_regs + HW_GPMI_TIMING0);
>>
>> - /*
>> - * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
>> - */
>> + /* [2] Set HW_GPMI_TIMING1 */
>> + writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
>> + gpmi_regs + HW_GPMI_TIMING1);
>> +
>> + /* [3] The following code is to set the HW_GPMI_CTRL1. */
>> +
>> + /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or 
>> HALF_PERIOD. */
>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>
>
> Are these [1], [2], [3] notation references to some other comments?
no.

These notations just help to comment the steps of setting timing registers.
Are you confused at this?


>
>> /* Clear out the DLL control fields. */
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> index 1f61217..e68bbac 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> @@ -189,14 +189,23 @@ struct gpmi_nand_data {
>> * @data_setup_in_cycles: The data setup time, in cycles.
>> * @data_hold_in_cycles: The data hold time, in cycles.
>> * @address_setup_in_cycles: The address setup time, in cycles.
>> + * @device_busy_timeout: The timeout waiting for NAND Ready/Busy,
>> + * this value is the number of cycles multiplied
>> + * by 4096.
>> * @use_half_periods: Indicates the clock is running slowly, so the
>> * NFC DLL should use half-periods.
>> * @sample_delay_factor: The sample delay factor.
>> */
>> struct gpmi_nfc_hardware_timing {
>> + /* for HW_GPMI_TIMING0 */
>> uint8_t data_setup_in_cycles;
>> uint8_t data_hold_in_cycles;
>> uint8_t address_setup_in_cycles;
>> +
>> + /* for HW_GPMI_TIMING1 */
>> + uint16_t device_busy_timeout;
>> +
>> + /* for HW_GPMI_CTRL1 */
>> bool use_half_periods;
>> uint8_t sample_delay_factor;
>> };
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> index 8343124..7961c14 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> @@ -154,6 +154,9 @@
>>
>> #define HW_GPMI_TIMING1 0x00000080
>> #define BP_GPMI_TIMING1_BUSY_TIMEOUT 16
>> +#define BM_GPMI_TIMING1_BUSY_TIMEOUT (0xff<< 
>> BP_GPMI_TIMING1_BUSY_TIMEOUT)
>
> Isn't this 0xffff?
> My Rev C manual states so. I might be wrong if I'm referring to a 
> older one!
this is my mistake.
It should be 0xffff.

thanks a lot !

Best Regards
Huang Shijie




From b32955 at freescale.com  Tue Sep 11 22:18:39 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 12 Sep 2012 10:18:39 +0800
Subject: [PATCH 5/9] mtd: gpmi: add a new field for HW_GPMI_CTRL1
In-Reply-To: <504F7D2C.5090707@gmail.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-6-git-send-email-b32955@freescale.com>
 <504F7D2C.5090707@gmail.com>
Message-ID: <504FF0FF.2030707@freescale.com>

? 2012?09?12? 02:04, Vikram Narayanan ??:
> Hello Huang Shijie,
>
> On 9/11/2012 11:47 AM, Huang Shijie wrote:
>> add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
>> This field is used as delay for gpmi write strobe.
>>
>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>> ---
>> drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 6 ++++++
>> drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 2 ++
>> drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 5 +++++
>> 3 files changed, 13 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> index eee0159..037438a 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> @@ -731,6 +731,7 @@ return_results:
>> hw->use_half_periods = dll_use_half_periods;
>> hw->sample_delay_factor = sample_delay_factor;
>> hw->device_busy_timeout = 0x500; /* default busy timeout value. */
>> + hw->wrn_dly_sel = 0;
>>
>> /* Return success. */
>> return 0;
>> @@ -769,6 +770,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
>>
>> /* [3] The following code is to set the HW_GPMI_CTRL1. */
>>
>> + /* Set the WRN_DLY_SEL */
>> + writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
>> + writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
>> + gpmi_regs + HW_GPMI_CTRL1_SET);
>> +
>> /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> index e68bbac..39f1f76 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
>> @@ -195,6 +195,7 @@ struct gpmi_nand_data {
>> * @use_half_periods: Indicates the clock is running slowly, so the
>> * NFC DLL should use half-periods.
>> * @sample_delay_factor: The sample delay factor.
>> + * @wrn_dly_sel: The delay on the GPMI write strobe.
>> */
>> struct gpmi_nfc_hardware_timing {
>> /* for HW_GPMI_TIMING0 */
>> @@ -208,6 +209,7 @@ struct gpmi_nfc_hardware_timing {
>> /* for HW_GPMI_CTRL1 */
>> bool use_half_periods;
>> uint8_t sample_delay_factor;
>> + uint8_t wrn_dly_sel;
>> };
>>
>> /**
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> index 7961c14..ab428d6 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
>> @@ -108,6 +108,11 @@
>> #define HW_GPMI_CTRL1_CLR 0x00000068
>> #define HW_GPMI_CTRL1_TOG 0x0000006c
>>
>> +#define BP_GPMI_CTRL1_WRN_DLY_SEL 22
>> +#define BM_GPMI_CTRL1_WRN_DLY_SEL 0x00C00000
>
> In [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1,
> the above is done in a different way.
>
> #define BM_GPMI_TIMING1_BUSY_TIMEOUT
> (0xff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
>
> I think it would be good if we follow the same conventions in all the 
> places.
>
yes. we should.

thanks
Huang Shijie





From b32955 at freescale.com  Tue Sep 11 22:28:50 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 12 Sep 2012 10:28:50 +0800
Subject: [PATCH 6/9] mtd: gpmi: simplify the setting DLL code
In-Reply-To: <504F7E10.8030406@gmail.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-7-git-send-email-b32955@freescale.com>
 <504F7E10.8030406@gmail.com>
Message-ID: <504FF362.4070609@freescale.com>

? 2012?09?12? 02:08, Vikram Narayanan ??:
> Hello Huang Shijie,
>
> On 9/11/2012 11:47 AM, Huang Shijie wrote:
>> The setting DLL code is a little mess.
>> Just simplify the code and the comments.
>>
>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>> ---
>> drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 22 +++++++++-------------
>> 1 files changed, 9 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c 
>> b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> index 037438a..83c5573 100644
>> --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
>> @@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>>
>> /* Clear out the DLL control fields. */
>> - writel(BM_GPMI_CTRL1_RDN_DELAY, gpmi_regs + HW_GPMI_CTRL1_CLR);
>> - writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
>> + reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
>> + writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
>>
>> /* If no sample delay is called for, return immediately. */
>> if (!hw.sample_delay_factor)
>> return;
>>
>> - /* Configure the HALF_PERIOD flag. */
>> - if (hw.use_half_periods)
>> - writel(BM_GPMI_CTRL1_HALF_PERIOD,
>> - gpmi_regs + HW_GPMI_CTRL1_SET);
>> + /* Set RDN_DELAY or HALF_PERIOD. */
>> + reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
>> + | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
>>
>> - /* Set the delay factor. */
>> - writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
>> - gpmi_regs + HW_GPMI_CTRL1_SET);
>> + writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
>>
>> - /* Enable the DLL. */
>> + /* At last, we enable the DLL. */
>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
>>
>> /*
>> * After we enable the GPMI DLL, we have to wait 64 clock cycles before
>> - * we can use the GPMI.
>> - *
>> - * Calculate the amount of time we need to wait, in microseconds.
>> + * we can use the GPMI. Calculate the amount of time we need to wait,
>> + * in microseconds.
>> */
>> clock_period_in_ns = 1000000000 / clk_get_rate(r->clock[0]);
>
> NSEC_PER_SEC macro in the above statement?
thanks. I like this macro.

>
> Don't curse me for commenting about the code that you've not written. 
> As this patch does some cleanups, I'm suggesting this.
>
sorry, I do not understand it very well.
could you tell me in detail what's the "commenting about the code that 
you've not written" meaning?

Which comments do you think is not proper?

Best Regards
Huang Shijie



>
>> dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
>
> Regards,
> Vikram
>




From b32955 at freescale.com  Wed Sep 12 03:00:02 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Wed, 12 Sep 2012 15:00:02 +0800
Subject: [PATCH 6/9] mtd: gpmi: simplify the setting DLL code
In-Reply-To: <504F7E10.8030406@gmail.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-7-git-send-email-b32955@freescale.com>
 <504F7E10.8030406@gmail.com>
Message-ID: <505032F2.4090102@freescale.com>

? 2012?09?12? 02:08, Vikram Narayanan ??:
>>
>> /*
>> * After we enable the GPMI DLL, we have to wait 64 clock cycles before
>> - * we can use the GPMI.
>> - *
>> - * Calculate the amount of time we need to wait, in microseconds.
>> + * we can use the GPMI. Calculate the amount of time we need to wait,
>> + * in microseconds.
>> */
>> clock_period_in_ns = 1000000000 / clk_get_rate(r->clock[0]);
>
> NSEC_PER_SEC macro in the above statement?
>
> Don't curse me for commenting about the code that you've not written. 
> As this patch does some cleanups, I'm suggesting this. 
I finally get what's your meaning. thanks for you review :)

I really appreciate it.


Best Regards
Huang Shijie



From csd at broadcom.com  Wed Sep 12 04:16:35 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 01:16:35 -0700
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
Message-ID: <505044E3.3040601@broadcom.com>

This driver is being removed as part of the cleanup of the bcmring
SoC from mainline as it is no longer maintained.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

---
  MAINTAINERS                        |    9 -
  arch/arm/configs/bcmring_defconfig |    2 -
  drivers/mtd/nand/Kconfig           |   16 -
  drivers/mtd/nand/Makefile          |    1 -
  drivers/mtd/nand/bcm_umi_bch.c     |  217 --------------
  drivers/mtd/nand/bcm_umi_nand.c    |  555 
------------------------------------
  drivers/mtd/nand/nand_bcm_umi.c    |  149 ----------
  drivers/mtd/nand/nand_bcm_umi.h    |  337 ----------------------
  8 files changed, 0 insertions(+), 1286 deletions(-)
  delete mode 100644 drivers/mtd/nand/bcm_umi_bch.c
  delete mode 100644 drivers/mtd/nand/bcm_umi_nand.c
  delete mode 100644 drivers/mtd/nand/nand_bcm_umi.c
  delete mode 100644 drivers/mtd/nand/nand_bcm_umi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..36da5f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -665,15 +665,6 @@ L:	linux-arm-kernel at lists.infradead.org (moderated 
for non-subscribers)
  S:	Maintained
  F:	arch/arm/mach-bcmring
  -ARM/BCMRING MTD NAND DRIVER
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-mtd at lists.infradead.org
-S:	Maintained
-F:	drivers/mtd/nand/bcm_umi_nand.c
-F:	drivers/mtd/nand/bcm_umi_bch.c
-F:	drivers/mtd/nand/nand_bcm_umi.h
-
  ARM/CALXEDA HIGHBANK ARCHITECTURE
  M:	Rob Herring <rob.herring at calxeda.com>
  L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/configs/bcmring_defconfig 
b/arch/arm/configs/bcmring_defconfig
index 9e6a8fe..75fa6c0 100644
--- a/arch/arm/configs/bcmring_defconfig
+++ b/arch/arm/configs/bcmring_defconfig
@@ -45,8 +45,6 @@ CONFIG_MTD_CFI_GEOMETRY=y
  # CONFIG_MTD_CFI_I2 is not set
  CONFIG_MTD_NAND=y
  CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
  # CONFIG_MISC_DEVICES is not set
  # CONFIG_INPUT_MOUSEDEV is not set
  # CONFIG_INPUT_KEYBOARD is not set
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..5c60a44 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -267,22 +267,6 @@ config MTD_NAND_S3C2410_CLKSTOP
  	  when the is NAND chip selected or released, but will save
  	  approximately 5mA of power when there is nothing happening.
  -config MTD_NAND_BCM_UMI
-	tristate "NAND Flash support for BCM Reference Boards"
-	depends on ARCH_BCMRING
-	help
-	  This enables the NAND flash controller on the BCM UMI block.
-
-	  No board specific support is done by this driver, each board
-	  must advertise a platform_device for the driver to attach.
-
-config MTD_NAND_BCM_UMI_HWCS
-	bool "BCM UMI NAND Hardware CS"
-	depends on MTD_NAND_BCM_UMI
-	help
-	  Enable the use of the BCM UMI block's internal CS using NAND.
-	  This should only be used if you know the external NAND CS can toggle.
-
  config MTD_NAND_DISKONCHIP
  	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND 
reimplementation) (EXPERIMENTAL)"
  	depends on EXPERIMENTAL
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..8b2825a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
  obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
  obj-$(CONFIG_MTD_NAND_NUC900)		+= nuc900_nand.o
  obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
-obj-$(CONFIG_MTD_NAND_BCM_UMI)		+= bcm_umi_nand.o nand_bcm_umi.o
  obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
  obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
  obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
deleted file mode 100644
index 5914bb3..0000000
--- a/drivers/mtd/nand/bcm_umi_bch.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include "nand_bcm_umi.h"
-
-/* ---- External Variable Declarations 
----------------------------------- */
-/* ---- External Function Prototypes 
------------------------------------- */
-/* ---- Public Variables 
------------------------------------------------- */
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-/* ---- Private Function Prototypes 
-------------------------------------- */
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required);
-
-/* ---- Private Variables 
------------------------------------------------ */
-
-/*
-** nand_hw_eccoob
-** New oob placement block for use with hardware ecc generation.
-*/
-static struct nand_ecclayout nand_hw_eccoob_512 = {
-	/* Reserve 5 for BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 3)
-		    {.offset = 0, .length = 2}
-#else
-		    {.offset = 0, .length = 5},
-		    {.offset = 6, .length = 7}
-#endif
-		    }
-};
-
-/*
-** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
-** except the BI is at byte 0.
-*/
-static struct nand_ecclayout nand_hw_eccoob_2048 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-#elif (NAND_ECC_NUM_BYTES > 7)
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6}
-#else
-		    {.offset = 1, .length = 8},
-		    {.offset = 16, .length = 9},
-		    {.offset = 32, .length = 9},
-		    {.offset = 48, .length = 9}
-#endif
-		    }
-};
-
-/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
- * except the BI is at byte 0. */
-static struct nand_ecclayout nand_hw_eccoob_4096 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-		    {.offset = 16, .length = 3},
-		    {.offset = 32, .length = 3},
-		    {.offset = 48, .length = 3},
-		    {.offset = 64, .length = 3},
-		    {.offset = 80, .length = 3},
-		    {.offset = 96, .length = 3},
-		    {.offset = 112, .length = 3}
-#else
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6},
-		    {.offset = 64, .length = 6},
-		    {.offset = 80, .length = 6},
-		    {.offset = 96, .length = 6},
-		    {.offset = 112, .length = 6}
-#endif
-		    }
-};
-
-/* ---- Private Functions 
------------------------------------------------ */
-/* ==== Public Functions 
================================================= */
-
-/****************************************************************************
-*
-*  bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	buffer to store read data
-*  @oob_required:	caller expects OOB data read to chip->oob_poi
-*
-***************************************************************************/
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-				       struct nand_chip *chip, uint8_t * buf,
-				       int oob_required, int page)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	uint8_t *datap = buf;
-	uint8_t eccCalc[NAND_ECC_NUM_BYTES];
-	int sectorOobSize = mtd->oobsize / eccsteps;
-	int stat;
-	unsigned int max_bitflips = 0;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-			sectorIdx++, datap += eccsize) {
-		if (sectorIdx > 0) {
-			/* Seek to page location within sector */
-			chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
-				      -1);
-		}
-
-		/* Enable hardware ECC before reading the buf */
-		nand_bcm_umi_bch_enable_read_hwecc();
-
-		/* Read in data */
-		bcm_umi_nand_read_buf(mtd, datap, eccsize);
-
-		/* Pause hardware ECC after reading the buf */
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		/* Read the OOB ECC */
-		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
-			      mtd->writesize + sectorIdx * sectorOobSize, -1);
-		nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
-					     NAND_ECC_NUM_BYTES,
-					     chip->oob_poi +
-					     sectorIdx * sectorOobSize);
-
-		/* Correct any ECC detected errors */
-		stat =
-		    nand_bcm_umi_bch_correct_page(datap, eccCalc,
-						  NAND_ECC_NUM_BYTES);
-
-		/* Update Stats */
-		if (stat < 0) {
-#if defined(NAND_BCM_UMI_DEBUG)
-			printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
-			       __func__, sectorIdx);
-			printk(KERN_WARNING
-			       "%s data %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x\n",
-			       __func__, datap[0], datap[1], datap[2], datap[3],
-			       datap[4], datap[5], datap[6], datap[7]);
-			printk(KERN_WARNING
-			       "%s ecc  %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x %02x %02x "
-					 "%02x %02x %02x\n",
-			       __func__, eccCalc[0], eccCalc[1], eccCalc[2],
-			       eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
-			       eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
-			       eccCalc[11], eccCalc[12]);
-			BUG();
-#endif
-			mtd->ecc_stats.failed++;
-		} else {
-#if defined(NAND_BCM_UMI_DEBUG)
-			if (stat > 0) {
-				printk(KERN_INFO
-				       "%s %d correctable_errors detected\n",
-				       __func__, stat);
-			}
-#endif
-			mtd->ecc_stats.corrected += stat;
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
-		}
-	}
-	return max_bitflips;
-}
-
-/****************************************************************************
-*
-*  bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	data buffer
-*  @oob_required:	must write chip->oob_poi to OOB
-*
-***************************************************************************/
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	const uint8_t *datap = buf;
-	uint8_t *oobp = chip->oob_poi;
-	int sectorOobSize = mtd->oobsize / eccsteps;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-	     sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
-		/* Enable hardware ECC before writing the buf */
-		nand_bcm_umi_bch_enable_write_hwecc();
-		bcm_umi_nand_write_buf(mtd, datap, eccsize);
-		nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
-					      NAND_ECC_NUM_BYTES);
-	}
-
-	bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
-}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c 
b/drivers/mtd/nand/bcm_umi_nand.c
deleted file mode 100644
index c855e7c..0000000
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/reg_nand.h>
-#include <mach/reg_umi.h>
-
-#include "nand_bcm_umi.h"
-
-#include <mach/memory_settings.h>
-
-#define USE_DMA 1
-#include <mach/dma.h>
-#include <linux/dma-mapping.h>
-#include <linux/completion.h>
-
-/* ---- External Variable Declarations 
----------------------------------- */
-/* ---- External Function Prototypes 
------------------------------------- */
-/* ---- Public Variables 
------------------------------------------------- */
-/* ---- Private Constants and Types 
-------------------------------------- */
-static const __devinitconst char gBanner[] = KERN_INFO \
-	"BCM UMI MTD NAND Driver: 1.00\n";
-
-#if NAND_ECC_BCH
-static uint8_t scan_ff_pattern[] = { 0xff };
-
-static struct nand_bbt_descr largepage_bbt = {
-	.options = 0,
-	.offs = 0,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-#endif
-
-/*
-** Preallocate a buffer to avoid having to do this every dma operation.
-** This is the size of the preallocated coherent DMA buffer.
-*/
-#if USE_DMA
-#define DMA_MIN_BUFLEN	512
-#define DMA_MAX_BUFLEN	PAGE_SIZE
-#define USE_DIRECT_IO(len)	(((len) < DMA_MIN_BUFLEN) || \
-	((len) > DMA_MAX_BUFLEN))
-
-/*
- * The current NAND data space goes from 0x80001900 to 0x80001FFF,
- * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
- * size NAND flash. Need to break the DMA down to multiple 1Ks.
- *
- * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
- */
-#define DMA_MAX_LEN             1024
-
-#else /* !USE_DMA */
-#define DMA_MIN_BUFLEN          0
-#define DMA_MAX_BUFLEN          0
-#define USE_DIRECT_IO(len)      1
-#endif
-/* ---- Private Function Prototypes 
-------------------------------------- */
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, 
int len);
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * 
buf,
-				   int len);
-
-/* ---- Private Variables 
------------------------------------------------ */
-static struct mtd_info *board_mtd;
-static void __iomem *bcm_umi_io_base;
-static void *virtPtr;
-static dma_addr_t physPtr;
-static struct completion nand_comp;
-
-/* ---- Private Functions 
------------------------------------------------ */
-#if NAND_ECC_BCH
-#include "bcm_umi_bch.c"
-#else
-#include "bcm_umi_hamming.c"
-#endif
-
-#if USE_DMA
-
-/* Handler called when the DMA finishes. */
-static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
-{
-	complete(&nand_comp);
-}
-
-static int nand_dma_init(void)
-{
-	int rc;
-
-	rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
-		nand_dma_handler, NULL);
-	if (rc != 0) {
-		printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
-		return rc;
-	}
-
-	virtPtr =
-	    dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
-	if (virtPtr == NULL) {
-		printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void nand_dma_term(void)
-{
-	if (virtPtr != NULL)
-		dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
-}
-
-static void nand_dma_read(void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (virtPtr == NULL)
-		panic("nand_dma_read: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_read: physPtr == NULL\n");
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_read: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
-					physPtr + offset, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-
-	if (buf != NULL)
-		memcpy(buf, virtPtr, len);
-}
-
-static void nand_dma_write(const void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (buf == NULL)
-		panic("nand_dma_write: buf == NULL\n");
-
-	if (virtPtr == NULL)
-		panic("nand_dma_write: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_write: physPtr == NULL\n");
-
-	memcpy(virtPtr, buf, len);
-
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_write: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, physPtr + offset,
-					REG_NAND_DATA_PADDR, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-}
-
-#endif
-
-static int nand_dev_ready(struct mtd_info *mtd)
-{
-	return nand_bcm_umi_dev_ready();
-}
-
-/****************************************************************************
-*
-*  bcm_umi_nand_inithw
-*
-*   This routine does the necessary hardware (board-specific)
-*   initializations.  This includes setting up the timings, etc.
-*
-***************************************************************************/
-int bcm_umi_nand_inithw(void)
-{
-	/* Configure nand timing parameters */
-	REG_UMI_NAND_TCR &= ~0x7ffff;
-	REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
-
-#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
-	/* enable software control of CS */
-	REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
-#endif
-
-	/* keep NAND chip select asserted */
-	REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
-
-	REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
-	/* enable writes to flash */
-	REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
-
-	writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
-	nand_bcm_umi_wait_till_ready();
-
-#if NAND_ECC_BCH
-	nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
-#endif
-
-	return 0;
-}
-
-/* Used to turn latch the proper register for access. */
-static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
-				   unsigned int ctrl)
-{
-	/* send command to hardware */
-	struct nand_chip *chip = mtd->priv;
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if (ctrl & NAND_CLE) {
-			chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
-			goto CMD;
-		}
-		if (ctrl & NAND_ALE) {
-			chip->IO_ADDR_W =
-			    bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
-			goto CMD;
-		}
-		chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	}
-
-CMD:
-	/* Send command to chip directly */
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, chip->IO_ADDR_W);
-}
-
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * 
buf,
-				   int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		/* Do it the old way if the buffer is small or too large.
-		 * Probably quicker than starting and checking dma. */
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			writeb(buf[i], this->IO_ADDR_W);
-	}
-#if USE_DMA
-	else
-		nand_dma_write(buf, len);
-#endif
-}
-
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, 
int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			buf[i] = readb(this->IO_ADDR_R);
-	}
-#if USE_DMA
-	else
-		nand_dma_read(buf, len);
-#endif
-}
-
-static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
-static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * 
buf,
-				   int len)
-{
-	/*
-	 * Try to readback page with ECC correction. This is necessary
-	 * for MLC parts which may have permanently stuck bits.
-	 */
-	struct nand_chip *chip = mtd->priv;
-	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
-	if (ret < 0)
-		return -EFAULT;
-	else {
-		if (memcmp(readbackbuf, buf, len) == 0)
-			return 0;
-
-		return -EFAULT;
-	}
-	return 0;
-}
-
-static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
-{
-	struct nand_chip *this;
-	struct resource *r;
-	int err = 0;
-
-	printk(gBanner);
-
-	/* Allocate memory for MTD device structure and private data */
-	board_mtd =
-	    kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
-		    GFP_KERNEL);
-	if (!board_mtd) {
-		printk(KERN_WARNING
-		       "Unable to allocate NAND MTD device structure.\n");
-		return -ENOMEM;
-	}
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	if (!r) {
-		err = -ENXIO;
-		goto out_free;
-	}
-
-	/* map physical address */
-	bcm_umi_io_base = ioremap(r->start, resource_size(r));
-
-	if (!bcm_umi_io_base) {
-		printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
-		err = -EIO;
-		goto out_free;
-	}
-
-	/* Get pointer to private data */
-	this = (struct nand_chip *)(&board_mtd[1]);
-
-	/* Initialize structures */
-	memset((char *)board_mtd, 0, sizeof(struct mtd_info));
-	memset((char *)this, 0, sizeof(struct nand_chip));
-
-	/* Link the private data with the MTD structure */
-	board_mtd->priv = this;
-
-	/* Initialize the NAND hardware.  */
-	if (bcm_umi_nand_inithw() < 0) {
-		printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
-		err = -EIO;
-		goto out_unmap;
-	}
-
-	/* Set address of NAND IO lines */
-	this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-
-	/* Set command delay time, see datasheet for correct value */
-	this->chip_delay = 0;
-	/* Assign the device ready function, if available */
-	this->dev_ready = nand_dev_ready;
-	this->options = 0;
-
-	this->write_buf = bcm_umi_nand_write_buf;
-	this->read_buf = bcm_umi_nand_read_buf;
-	this->verify_buf = bcm_umi_nand_verify_buf;
-
-	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
-	this->ecc.mode = NAND_ECC_HW;
-	this->ecc.size = 512;
-	this->ecc.bytes = NAND_ECC_NUM_BYTES;
-#if NAND_ECC_BCH
-	this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
-	this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
-#else
-	this->ecc.correct = nand_correct_data512;
-	this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
-	this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
-#endif
-
-#if USE_DMA
-	err = nand_dma_init();
-	if (err != 0)
-		goto out_unmap;
-#endif
-
-	/* Figure out the size of the device that we have.
-	 * We need to do this to figure out which ECC
-	 * layout we'll be using.
-	 */
-
-	err = nand_scan_ident(board_mtd, 1, NULL);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Now that we know the nand size, we can setup the ECC layout */
-
-	switch (board_mtd->writesize) {	/* writesize is the pagesize */
-	case 4096:
-		this->ecc.layout = &nand_hw_eccoob_4096;
-		break;
-	case 2048:
-		this->ecc.layout = &nand_hw_eccoob_2048;
-		break;
-	case 512:
-		this->ecc.layout = &nand_hw_eccoob_512;
-		break;
-	default:
-		{
-			printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
-					 board_mtd->writesize);
-			err = -EINVAL;
-			goto out_unmap;
-		}
-	}
-
-#if NAND_ECC_BCH
-	if (board_mtd->writesize > 512) {
-		if (this->bbt_options & NAND_BBT_USE_FLASH)
-			largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
-		this->badblock_pattern = &largepage_bbt;
-	}
-
-	this->ecc.strength = 8;
-
-#endif
-
-	/* Now finish off the scan, now that ecc.layout has been initialized. */
-
-	err = nand_scan_tail(board_mtd);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Register the partitions */
-	board_mtd->name = "bcm_umi-nand";
-	mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
-
-	/* Return happy */
-	return 0;
-out_unmap:
-	iounmap(bcm_umi_io_base);
-out_free:
-	kfree(board_mtd);
-	return err;
-}
-
-static int bcm_umi_nand_remove(struct platform_device *pdev)
-{
-#if USE_DMA
-	nand_dma_term();
-#endif
-
-	/* Release resources, unregister device */
-	nand_release(board_mtd);
-
-	/* unmap physical address */
-	iounmap(bcm_umi_io_base);
-
-	/* Free the MTD device structure */
-	kfree(board_mtd);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static int bcm_umi_nand_suspend(struct platform_device *pdev,
-				pm_message_t state)
-{
-	printk(KERN_ERR "MTD NAND suspend is being called\n");
-	return 0;
-}
-
-static int bcm_umi_nand_resume(struct platform_device *pdev)
-{
-	printk(KERN_ERR "MTD NAND resume is being called\n");
-	return 0;
-}
-#else
-#define bcm_umi_nand_suspend   NULL
-#define bcm_umi_nand_resume    NULL
-#endif
-
-static struct platform_driver nand_driver = {
-	.driver = {
-		   .name = "bcm-nand",
-		   .owner = THIS_MODULE,
-		   },
-	.probe = bcm_umi_nand_probe,
-	.remove = bcm_umi_nand_remove,
-	.suspend = bcm_umi_nand_suspend,
-	.resume = bcm_umi_nand_resume,
-};
-
-module_platform_driver(nand_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Broadcom");
-MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/nand_bcm_umi.c 
b/drivers/mtd/nand/nand_bcm_umi.c
deleted file mode 100644
index 46a6bc9..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include "nand_bcm_umi.h"
-#ifdef BOOT0_BUILD
-#include <uart.h>
-#endif
-
-/* ---- External Variable Declarations 
----------------------------------- */
-/* ---- External Function Prototypes 
------------------------------------- */
-/* ---- Public Variables 
------------------------------------------------- */
-/* ---- Private Constants and Types 
-------------------------------------- */
-/* ---- Private Function Prototypes 
-------------------------------------- */
-/* ---- Private Variables 
------------------------------------------------ */
-/* ---- Private Functions 
------------------------------------------------ */
-
-#if NAND_ECC_BCH
-/****************************************************************************
-*  nand_bch_ecc_flip_bit - Routine to flip an errored bit
-*
-*  PURPOSE:
-*     This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
-*     errored bit specified
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*     errorLocation - Location of the bit that needs to be flipped
-*
-*  RETURNS:
-*     None
-****************************************************************************/
-static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int 
errorLocation)
-{
-	int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
-	int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
-	int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
-
-	uint8_t errorByte = 0;
-	uint8_t byteMask = 1 << locWithinAByte;
-
-	/* BCH uses big endian, need to change the location
-	 * bits to little endian */
-	locWithinAWord = 3 - locWithinAWord;
-
-	errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
-
-#ifdef BOOT0_BUILD
-	puthexs("\nECC Correct Offset: ",
-		locWithinAPage * sizeof(uint32_t) + locWithinAWord);
-	puthexs(" errorByte:", errorByte);
-	puthex8(" Bit: ", locWithinAByte);
-#endif
-
-	if (errorByte & byteMask) {
-		/* bit needs to be cleared */
-		errorByte &= ~byteMask;
-	} else {
-		/* bit needs to be set */
-		errorByte |= byteMask;
-	}
-
-	/* write back the value with the fixed bit */
-	datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
-}
-
-/****************************************************************************
-*  nand_correct_page_bch - Routine to correct bit errors when reading NAND
-*
-*  PURPOSE:
-*     This routine reads the BCH registers to determine if there are 
any bit
-*     errors during the read of the last 512 bytes of data + ECC bytes.  If
-*     errors exists, the routine fixes it.
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*
-*  RETURNS:
-*     0 or greater = Number of errors corrected
-*                    (No errors are found or errors have been fixed)
-*    -1 = Error(s) cannot be fixed
-****************************************************************************/
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes)
-{
-	int numErrors;
-	int errorLocation;
-	int idx;
-	uint32_t regValue;
-
-	/* wait for read ECC to be valid */
-	regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
-
-	/*
-	 * read the control status register to determine if there
-	 * are error'ed bits
-	 * see if errors are correctible
-	 */
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
-		int i;
-
-		for (i = 0; i < numEccBytes; i++) {
-			if (readEccData[i] != 0xff) {
-				/* errors cannot be fixed, return -1 */
-				return -1;
-			}
-		}
-		/* If ECC is unprogrammed then we can't correct,
-		 * assume everything OK */
-		return 0;
-	}
-
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
-		/* no errors */
-		return 0;
-	}
-
-	/*
-	 * Fix errored bits by doing the following:
-	 * 1. Read the number of errors in the control and status register
-	 * 2. Read the error location registers that corresponds to the number
-	 *    of errors reported
-	 * 3. Invert the bit in the data
-	 */
-	numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
-
-	for (idx = 0; idx < numErrors; idx++) {
-		errorLocation =
-		    REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
-
-		/* Flip bit */
-		nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
-	}
-	/* Errors corrected */
-	return numErrors;
-}
-#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h 
b/drivers/mtd/nand/nand_bcm_umi.h
deleted file mode 100644
index 198b304..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef NAND_BCM_UMI_H
-#define NAND_BCM_UMI_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include <mach/reg_nand.h>
-#include <cfg_global.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
-#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
-#else
-#define NAND_ECC_BCH 0
-#endif
-
-#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES	13
-
-#if NAND_ECC_BCH
-#ifdef BOOT0_BUILD
-#define NAND_ECC_NUM_BYTES 13
-#else
-#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
-#endif
-#else
-#define NAND_ECC_NUM_BYTES 3
-#endif
-
-#define NAND_DATA_ACCESS_SIZE 512
-
-/* ---- Variable Externs ------------------------------------------ */
-/* ---- Function Prototypes --------------------------------------- */
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes);
-
-/* Check in device is ready */
-static inline int nand_bcm_umi_dev_ready(void)
-{
-	return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
-}
-
-/* Wait until device is ready */
-static inline void nand_bcm_umi_wait_till_ready(void)
-{
-	while (nand_bcm_umi_dev_ready() == 0)
-		;
-}
-
-/* Enable Hamming ECC */
-static inline void nand_bcm_umi_hamming_enable_hwecc(void)
-{
-	/* disable and reset ECC, 512 byte page */
-	REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-		REG_UMI_NAND_ECC_CSR_256BYTE);
-	/* enable ECC */
-	REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
-}
-
-#if NAND_ECC_BCH
-/* BCH ECC specifics */
-#define ECC_BITS_PER_CORRECTABLE_BIT 13
-
-/* Enable BCH Read ECC */
-static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Enable BCH Write ECC */
-static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
-}
-
-/* Config number of BCH ECC bytes */
-static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
-{
-	uint32_t nValue;
-	uint32_t tValue;
-	uint32_t kValue;
-	uint32_t numBits = numEccBytes * 8;
-
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-	    REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-
-	/* Every correctible bit requires 13 ECC bits */
-	tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Total data in number of bits for generating and computing BCH ECC */
-	nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
-
-	/* K parameter is used internally.  K = N - (T * 13) */
-	kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Write the settings */
-	REG_UMI_BCH_N = nValue;
-	REG_UMI_BCH_T = tValue;
-	REG_UMI_BCH_K = kValue;
-}
-
-/* Pause during ECC read calculation to skip bytes in OOB */
-static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-	    REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
-}
-
-/* Resume during ECC read calculation after skipping bytes in OOB */
-static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Poll read ECC calc to check when hardware completes */
-static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
-{
-	uint32_t regVal;
-
-	do {
-		/* wait for ECC to be valid */
-		regVal = REG_UMI_BCH_CTRL_STATUS;
-	} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
-
-	return regVal;
-}
-
-/* Poll write ECC calc to check when hardware completes */
-static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
-{
-	/* wait for ECC to be valid */
-	while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
-	       == 0)
-		;
-}
-
-/* Read the OOB and ECC, for kernel write OOB to a buffer */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
-#else
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes)
-#endif
-{
-	int eccPos = 0;
-	int numToRead = 16;	/* There are 16 bytes per sector in the OOB */
-
-	/* ECC is already paused when this function is called */
-	if (pageSize != NAND_DATA_ACCESS_SIZE) {
-		/* skip BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	while (numToRead > numEccBytes) {
-		/* skip free oob region */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* read ECC bytes before BI */
-		nand_bcm_umi_bch_resume_read_ecc_calc();
-
-		while (numToRead > 11) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp = REG_NAND_DATA8;
-			eccCalc[eccPos++] = *oobp;
-			oobp++;
-#else
-			eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		if (numToRead == 11) {
-			/* read BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp++ = REG_NAND_DATA8;
-#else
-			REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-	}
-	/* read ECC bytes */
-	nand_bcm_umi_bch_resume_read_ecc_calc();
-	while (numToRead) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp = REG_NAND_DATA8;
-		eccCalc[eccPos++] = *oobp;
-		oobp++;
-#else
-		eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-}
-
-/* Helper function to write ECC */
-static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
-					  uint8_t *oobp, uint8_t eccVal)
-{
-	if (eccBytePos <= numEccBytes)
-		*oobp = eccVal;
-}
-
-/* Write OOB with ECC */
-static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
-						 uint8_t *oobp, int numEccBytes)
-{
-	uint32_t eccVal = 0xffffffff;
-
-	/* wait for write ECC to be valid */
-	nand_bcm_umi_bch_poll_write_ecc_calc();
-
-	/*
-	 ** Get the hardware ecc from the 32-bit result registers.
-	 ** Read after 512 byte accesses. Format B3B2B1B0
-	 ** where B3 = ecc3, etc.
-	 */
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually we skip CM in oob[0,1] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[2,3,4] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
-			eccVal & 0xff);	/* ECC 12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-
-		/* Always Skip BI in oob[5] */
-	} else {
-		/* Always Skip BI in oob[0] */
-
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually skip CM in oob[1,2] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[3-15] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
-			eccVal & 0xff);	/* ECC12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-	}
-
-	/* Fill in the remainder of ECC locations */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
-		(eccVal >> 8) & 0xff);	/* ECC9 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
-		eccVal & 0xff);	/* ECC8 */
-
-	if (numEccBytes >= 5)
-		eccVal = REG_UMI_BCH_WR_ECC_1;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
-		(eccVal >> 24) & 0xff);	/* ECC7 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
-		(eccVal >> 16) & 0xff);	/* ECC6 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
-		(eccVal >> 8) & 0xff);	/* ECC5 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
-		eccVal & 0xff);	/* ECC4 */
-
-	if (numEccBytes >= 1)
-		eccVal = REG_UMI_BCH_WR_ECC_0;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
-		(eccVal >> 24) & 0xff);	/* ECC3 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
-		(eccVal >> 16) & 0xff);	/* ECC2 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
-		(eccVal >> 8) & 0xff);	/* ECC1 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
-		eccVal & 0xff);	/* ECC0 */
-}
-#endif
-
-#endif /* NAND_BCM_UMI_H */
-- 
1.7.1




From csd at broadcom.com  Wed Sep 12 04:17:25 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 01:17:25 -0700
Subject: [PATCH 2/3] ARM: Remove mach-bcmring
Message-ID: <50504515.4000106@broadcom.com>

Remove mach-bcmring as this is no longer maintained or used.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

---
  MAINTAINERS                                        |    7 -
  arch/arm/Kconfig                                   |   14 -
  arch/arm/Makefile                                  |    1 -
  arch/arm/configs/bcmring_defconfig                 |   77 -
  arch/arm/mach-bcmring/Kconfig                      |   19 -
  arch/arm/mach-bcmring/Makefile                     |    8 -
  arch/arm/mach-bcmring/Makefile.boot                |    6 -
  arch/arm/mach-bcmring/arch.c                       |  199 ---
  arch/arm/mach-bcmring/clock.c                      |  223 ---
  arch/arm/mach-bcmring/clock.h                      |   33 -
  arch/arm/mach-bcmring/core.c                       |  228 ---
  arch/arm/mach-bcmring/core.h                       |   31 -
  arch/arm/mach-bcmring/csp/Makefile                 |    3 -
  arch/arm/mach-bcmring/csp/chipc/Makefile           |    1 -
  arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |  776 ---------
  arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |  293 ----
  arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |  124 --
  arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |   64 -
  arch/arm/mach-bcmring/csp/dmac/Makefile            |    1 -
  arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |  917 -----------
  arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      | 1017 ------------
  arch/arm/mach-bcmring/csp/tmr/Makefile             |    1 -
  arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |  576 -------
  arch/arm/mach-bcmring/dma.c                        | 1518 
------------------
  arch/arm/mach-bcmring/dma_device.c                 |  593 -------
  arch/arm/mach-bcmring/include/cfg_global.h         |   13 -
  arch/arm/mach-bcmring/include/cfg_global_defines.h |   40 -
  arch/arm/mach-bcmring/include/csp/cache.h          |   35 -
  arch/arm/mach-bcmring/include/csp/delay.h          |   36 -
  arch/arm/mach-bcmring/include/csp/dmacHw.h         |  596 -------
  arch/arm/mach-bcmring/include/csp/errno.h          |   32 -
  arch/arm/mach-bcmring/include/csp/intcHw.h         |   40 -
  arch/arm/mach-bcmring/include/csp/module.h         |   32 -
  arch/arm/mach-bcmring/include/csp/reg.h            |  114 --
  arch/arm/mach-bcmring/include/csp/secHw.h          |   65 -
  arch/arm/mach-bcmring/include/csp/stdint.h         |   30 -
  arch/arm/mach-bcmring/include/csp/string.h         |   34 -
  arch/arm/mach-bcmring/include/csp/tmrHw.h          |  263 ---
  arch/arm/mach-bcmring/include/mach/csp/cap.h       |   63 -
  .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
  .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
  .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 
--------------------
  .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
  arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
  .../mach-bcmring/include/mach/csp/dmacHw_priv.h    |  145 --
  .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
  arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
  .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
  arch/arm/mach-bcmring/include/mach/csp/mm_addr.h   |  101 --
  arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
  arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
  .../mach-bcmring/include/mach/csp/secHw_inline.h   |   79 -
  arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
  arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
  arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
  arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
  arch/arm/mach-bcmring/include/mach/irqs.h          |  132 --
  .../mach-bcmring/include/mach/memory_settings.h    |   67 -
  arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
  arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
  arch/arm/mach-bcmring/include/mach/timer.h         |   77 -
  arch/arm/mach-bcmring/include/mach/timex.h         |   25 -
  arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
  arch/arm/mach-bcmring/irq.c                        |  126 --
  arch/arm/mach-bcmring/mm.c                         |   60 -
  arch/arm/mach-bcmring/timer.c                      |   61 -
  66 files changed, 0 insertions(+), 15766 deletions(-)
  delete mode 100644 arch/arm/configs/bcmring_defconfig
  delete mode 100644 arch/arm/mach-bcmring/Kconfig
  delete mode 100644 arch/arm/mach-bcmring/Makefile
  delete mode 100644 arch/arm/mach-bcmring/Makefile.boot
  delete mode 100644 arch/arm/mach-bcmring/arch.c
  delete mode 100644 arch/arm/mach-bcmring/clock.c
  delete mode 100644 arch/arm/mach-bcmring/clock.h
  delete mode 100644 arch/arm/mach-bcmring/core.c
  delete mode 100644 arch/arm/mach-bcmring/core.h
  delete mode 100644 arch/arm/mach-bcmring/csp/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/tmrHw.c
  delete mode 100644 arch/arm/mach-bcmring/dma.c
  delete mode 100644 arch/arm/mach-bcmring/dma_device.c
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
  delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/irqs.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/memory_settings.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timer.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timex.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
  delete mode 100644 arch/arm/mach-bcmring/irq.c
  delete mode 100644 arch/arm/mach-bcmring/mm.c
  delete mode 100644 arch/arm/mach-bcmring/timer.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 36da5f9..a4b166c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,13 +658,6 @@ W:	http://www.linux4sam.org
  S:	Supported
  F:	arch/arm/mach-at91/
  -ARM/BCMRING ARM ARCHITECTURE
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
-S:	Maintained
-F:	arch/arm/mach-bcmring
-
  ARM/CALXEDA HIGHBANK ARCHITECTURE
  M:	Rob Herring <rob.herring at calxeda.com>
  L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5..e99177a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,18 +350,6 @@ config ARCH_AT91
  	  This enables support for systems based on Atmel
  	  AT91RM9200 and AT91SAM9* processors.
  -config ARCH_BCMRING
-	bool "Broadcom BCMRING"
-	depends on MMU
-	select CPU_V6
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	help
-	  Support for Broadcom's BCMRing platform.
-
  config ARCH_HIGHBANK
  	bool "Calxeda Highbank-based"
  	select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -1031,8 +1019,6 @@ source "arch/arm/mach-mvebu/Kconfig"
   source "arch/arm/mach-at91/Kconfig"
  -source "arch/arm/mach-bcmring/Kconfig"
-
  source "arch/arm/mach-clps711x/Kconfig"
   source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..8383e2e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
  # Machine directory name.  This list is sorted alphanumerically
  # by CONFIG_* macro name.
  machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
  machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
  machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
  machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
diff --git a/arch/arm/configs/bcmring_defconfig 
b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 75fa6c0..0000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,77 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16..0000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-	prompt "Processor selection in BCMRING family of devices"
-	depends on ARCH_BCMRING
-	default ARCH_BCM11107
-
-config ARCH_FPGA11107
-	bool "FPGA11107"
-
-config ARCH_BCM11107
-	bool "BCM11107"
-endchoice
-
-menu "BCMRING Options"
-	depends on ARCH_BCMRING
-
-config BCM_ZRELADDR
-	hex "Compressed ZREL ADDR"
-
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fce..0000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot 
b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467..0000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
-
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index 45c97b1..0000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/pmu.h>
-
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <cfg_global.h>
-
-#include "core.h"
-
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-
-/* sysctl */
-static int bcmring_arch_warm_reboot;	/* do a warm reboot on hard reset */
-
-static void bcmring_restart(char mode, const char *cmd)
-{
-	printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-
-	if (mode == 'h') {
-		/* Reboot configured in proc entry */
-		if (bcmring_arch_warm_reboot) {
-			printk("warm reset\n");
-			/* Issue Warm reset (do not reset ethernet switch, keep alive) */
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-		} else {
-			/* Force reset of everything */
-			printk("force reset\n");
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-	} else {
-		/* Force reset of everything */
-		printk("force reset\n");
-		chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-	}
-}
-
-static struct ctl_table_header *bcmring_sysctl_header;
-
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-	{
-	 .procname = "warm",
-	 .data = &bcmring_arch_warm_reboot,
-	 .maxlen = sizeof(int),
-	 .mode = 0644,
-	 .proc_handler = proc_dointvec},
-	{}
-};
-
-static struct ctl_table bcmring_sysctl_reboot[] = {
-	{
-	 .procname = "reboot",
-	 .mode = 0555,
-	 .child = bcmring_sysctl_warm_reboot},
-	{}
-};
-
-static struct resource nand_resource[] = {
-	[0] = {
-		.start = MM_ADDR_IO_NAND,
-		.end = MM_ADDR_IO_NAND + 0x1000 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device nand_device = {
-	.name = "bcm-nand",
-	.id = -1,
-	.resource = nand_resource,
-	.num_resources	= ARRAY_SIZE(nand_resource),
-};
-
-static struct resource pmu_resource = {
-	.start	= IRQ_PMUIRQ,
-	.end	= IRQ_PMUIRQ,
-	.flags	= IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
-	.resource	= &pmu_resource,
-	.num_resources	= 1,
-};
-
-
-static struct platform_device *devices[] __initdata = {
-	&nand_device,
-	&pmu_device,
-};
-
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-
-	bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-
-	/* Enable spread spectrum */
-	chipcHw_enableSpreadSpectrum();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	bcmring_amba_init();
-
-	dma_init();
-}
-
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-	struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-	printk(KERN_NOTICE "bcmring_fixup\n");
-	t->hdr.tag = ATAG_CORE;
-	t->hdr.size = tag_size(tag_core);
-	t->u.core.flags = 0;
-	t->u.core.pagesize = PAGE_SIZE;
-	t->u.core.rootdev = 31 << 8 | 0;
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_MEM;
-	t->hdr.size = tag_size(tag_mem32);
-	t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-	t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_NONE;
-	t->hdr.size = 0;
-#endif
-}
-
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-
-MACHINE_START(BCMRING, "BCMRING")
-	/* Maintainer: Broadcom Corporation */
-	.fixup = bcmring_fixup,
-	.map_io = bcmring_map_io,
-	.init_early = bcmring_init_early,
-	.init_irq = bcmring_init_irq,
-	.timer = &bcmring_timer,
-	.init_machine = bcmring_init_machine,
-	.restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a4..0000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include "clock.h"
-
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	/* enable parent clock first */
-	if (clk->parent)
-		__clk_enable(clk->parent);
-
-	if (clk->use_cnt++ == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Enable(clk->rate_hz, 0);
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Enable(clk->rate_hz);
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockEnable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockEnable(clk->csp_id);
-		}
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	BUG_ON(clk->use_cnt == 0);
-
-	if (--clk->use_cnt == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Disable();
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Disable();
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockDisable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockDisable(clk->csp_id);
-		}
-	}
-
-	if (clk->parent)
-		__clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (!clk)
-		return 0;
-
-	return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-	clk->rate_hz = rate_hz;
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-	if (!clk)
-		return NULL;
-
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	unsigned long flags;
-	struct clk *old_parent;
-
-	if (!clk || !parent)
-		return -EINVAL;
-
-	if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-		return -EINVAL;
-
-	/* if more than one user, parent is not allowed */
-	if (clk->use_cnt > 1)
-		return -EBUSY;
-
-	if (clk->parent == parent)
-		return 0;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	old_parent = clk->parent;
-	clk->parent = parent;
-	if (clk_is_using_xtal(parent))
-		clk->mode |= CLK_MODE_XTAL;
-	else
-		clk->mode &= (~CLK_MODE_XTAL);
-
-	/* if clock is active */
-	if (clk->use_cnt != 0) {
-		clk->use_cnt--;
-		/* enable clock with the new parent */
-		__clk_enable(clk);
-		/* disable the old parent */
-		__clk_disable(old_parent);
-	}
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b981..0000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-
-#define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a 
parent */
-#define CLK_TYPE_PLL1            2	/* PPL1 */
-#define CLK_TYPE_PLL2            4	/* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8	/* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16	/* parent can be changed */
-
-#define CLK_MODE_XTAL            1	/* clock source is from crystal */
-
-struct clk {
-	const char *name;	/* clock name */
-	unsigned int type;	/* clock type */
-	unsigned int mode;	/* current mode */
-	volatile int use_bypass;	/* indicate if it's in bypass mode */
-	chipcHw_CLOCK_e csp_id;	/* clock ID for CSP CHIPC */
-	unsigned long rate_hz;	/* clock rate in Hz */
-	unsigned int use_cnt;	/* usage count */
-	struct clk *parent;	/* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index adbfb19..0000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <cfg_global.h>
-
-#include "clock.h"
-
-#include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, 
{IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, 
{IRQ_UARTB}, NULL);
-
-static struct clk pll1_clk = {
-	.name = "PLL1",
-	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-	.rate_hz = 2000000000,
-	.use_cnt = 7,
-};
-
-static struct clk uart_clk = {
-	.name = "UART",
-	.type = CLK_TYPE_PROGRAMMABLE,
-	.csp_id = chipcHw_CLOCK_UART,
-	.rate_hz = HW_CFG_UART_CLK_HZ,
-	.parent = &pll1_clk,
-};
-
-static struct clk dummy_apb_pclk = {
-	.name = "BUSCLK",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-};
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as 
well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-static struct clk sp804_timer012_clk = {
-	.name = "sp804-timer-0,1,2",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-
-static struct clk sp804_timer3_clk = {
-	.name = "sp804-timer-3",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-
-static struct clk_lookup lookups[] = {
-	{			/* Bus clock */
-		.con_id = "apb_pclk",
-		.clk = &dummy_apb_pclk,
-	}, {			/* UART0 */
-		.dev_id = "uarta",
-		.clk = &uart_clk,
-	}, {			/* UART1 */
-		.dev_id = "uartb",
-		.clk = &uart_clk,
-	}, {			/* SP804 timer 0 */
-		.dev_id = "sp804",
-		.con_id = "timer0",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 1 */
-		.dev_id = "sp804",
-		.con_id = "timer1",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 3 */
-		.dev_id = "sp804",
-		.con_id = "timer3",
-		.clk = &sp804_timer3_clk,
-	}
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	&uartA_device,
-	&uartB_device,
-};
-
-void __init bcmring_amba_init(void)
-{
-	int i;
-	u32 bus_clock;
-
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-			  secHw_BLK_MASK_KEY_SCAN |
-			  secHw_BLK_MASK_TOUCH_SCREEN |
-			  secHw_BLK_MASK_UART0 |
-			  secHw_BLK_MASK_UART1 |
-			  secHw_BLK_MASK_WATCHDOG |
-			  secHw_BLK_MASK_SPUM |
-			  secHw_BLK_MASK_DDR2 |
-			  secHw_BLK_MASK_SPU |
-			  secHw_BLK_MASK_PKA |
-			  secHw_BLK_MASK_RNG |
-			  secHw_BLK_MASK_RTC |
-			  secHw_BLK_MASK_OTP |
-			  secHw_BLK_MASK_BOOT |
-			  secHw_BLK_MASK_MPU |
-			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-
-	/* Only the devices attached to the AMBA bus are enabled just before 
the bus is */
-	/* scanned and the drivers are loaded. The clocks need to be on for 
the AMBA bus */
-	/* driver to access these blocks. The bus is probed, and the drivers 
are loaded. */
-	/* FIXME Need to remove enable of PIF once CLCD clock enable used 
properly in FPGA. */
-	bus_clock = chipcHw_REG_BUS_CLOCK_GE
-	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-
-	chipcHw_busInterfaceClockEnable(bus_clock);
-
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-}
-
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE		((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-
-static int __init bcmring_clocksource_init(void)
-{
-	/* setup timer1 as free-running clocksource */
-	sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-
-	/* setup timer3 as free-running clocksource */
-	sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-
-	return 0;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-	printk(KERN_INFO "bcmring_init_timer\n");
-	/*
-	 * Initialise to a known state (all timers off)
-	 */
-	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-
-	/*
-	 * Make irqs happen for the system timer
-	 */
-	bcmring_clocksource_init();
-
-	sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-
-struct sys_timer bcmring_timer = {
-	.init = bcmring_init_timer,
-};
-
-void __init bcmring_init_early(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c4..0000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile 
b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c037..0000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile 
b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 6739527..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 96273ff..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF	/* Max number of times 
allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10	/* Max number of attempt to 
align the phase */
-
-/* Local definition of clock type */
-#define PLL_CLOCK                      1	/* PLL Clock */
-#define NON_PLL_CLOCK                  2	/* Divider clock */
-
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-	} else {
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz =
-	    chipcHw_XTAL_FREQ_Hz *
-		 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Obtain PLL clock frequency */
-		if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (clock == chipcHw_CLOCK_DDR) {
-			/* DDR frequency is configured in PLLDivider register */
-			return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				vcoHz >>= 1;
-			}
-			/* Obtain PLL clock frequency using VCO dividers */
-			return chipcHw_divide(vcoHz, ((*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-	} else if (pClockCtrl) {
-		/* Obtain divider clock frequency */
-		uint32_t div;
-		uint32_t freq = 0;
-
-		if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (pDependentClock) {
-			/* Identify the dependent clock frequency */
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-					/* Use crystal clock frequency when dependent PLL clock is bypassed */
-					freq = chipcHw_XTAL_FREQ_Hz;
-				} else {
-					/* Obtain PLL clock frequency using VCO dividers */
-					div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-					freq = div ? chipcHw_divide(vcoHz, div) : 0;
-				}
-				break;
-			case NON_PLL_CLOCK:
-				if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-					freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-				} else {
-					if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-						/* Use crystal clock frequency when dependent divider clock is 
bypassed */
-						freq = chipcHw_XTAL_FREQ_Hz;
-					} else {
-						/* Obtain divider clock frequency using XTAL dividers */
-						div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-					}
-				}
-				break;
-			}
-		} else {
-			/* Dependent on crystal clock */
-			freq = chipcHw_XTAL_FREQ_Hz;
-		}
-
-		div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-		return chipcHw_divide(freq, (div ? div : 256));
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t desVcoFreqPll1Hz = 0;	/* Desired VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-	uint32_t desVcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-
-		/* Desired VCO frequency */
-		desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-	} else {
-		vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * 
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		/* Configure the DDR_ctrl:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-			pChipcHw->DDRClock = (pChipcHw->DDRClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		/* Configure the VPM:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Select XTAL as bypass source */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-		reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* For DDR settings use only the PLL divider clock */
-		if (pPLLReg == &pChipcHw->DDRClock) {
-			/* Set M1DIV for PLL1, which controls the DDR clock */
-			reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 
0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				desVcoHz >>= 1;
-				vcoHz >>= 1;
-			}
-			/* Set MDIV to change the frequency */
-			reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-			reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-		/* Wait for for atleast 200ns as per the protocol to change frequency */
-		udelay(1);
-		/* Do not bypass */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* Return the configured frequency */
-		return freq;
-	} else if (pClockCtrl) {
-		uint32_t divider = 0;
-
-		/* Divider clock should not be bypassed  */
-		reg32_modify_and(pClockCtrl,
-				 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-
-		/* Identify the clock source */
-		if (pDependentClock) {
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				divider = chipcHw_divide(chipcHw_divide (desVcoHz, 
(*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-				break;
-			case NON_PLL_CLOCK:
-				{
-					uint32_t sourceClock = 0;
-
-					if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-						sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-					} else {
-						uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div 
: 256));
-					}
-					divider = chipcHw_divide(sourceClock, freq);
-				}
-				break;
-			}
-		} else {
-			divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-		}
-
-		if (divider) {
-			REG_LOCAL_IRQ_SAVE;
-			/* Set the divider to obtain the required frequency */
-			*pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | 
(((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & 
chipcHw_REG_DIV_CLOCK_DIV_MASK);
-			REG_LOCAL_IRQ_RESTORE;
-			return freq;
-		}
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-	uint32_t phaseControl;
-	uint32_t phaseValue;
-	uint32_t prevPhaseComp;
-	int iter = 0;
-	int adjustCount = 0;
-	int count = 0;
-
-	for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT); iter++) {
-		phaseControl = (pChipcHw->VPMClock & 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-		phaseValue = 0;
-		prevPhaseComp = 0;
-
-		/* Step 1: Look for falling PH_COMP transition */
-
-		/* Read the contents of VPM Clock resgister */
-		phaseValue = pChipcHw->VPMClock;
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) ||	/* Look for a transition */
-			  ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&	/* 
Look for a falling edge */
-			 (adjustCount < MAX_PHASE_ADJUST_COUNT)	/* Do not exceed the limit 
while trying */
-		    );
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		/* Step 2: Keep moving forward to make sure falling PH_COMP 
transition was valid */
-
-		for (count = 0; (count < 5) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl + 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 5) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 3: Keep moving backward to make sure falling PH_COMP 
transition was stable */
-
-		for (count = 0; (count < 3) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 3) {
-			/* Detected noisy transition */
-			continue;
-		}
-
-		/* Step 4: Keep moving backward before the original transition took 
place. */
-
-		for (count = 0; (count < 5); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 5: Re discover the valid transition */
-
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^=
-			    chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT));
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-			return -1;
-		} else {
-			/* Valid phase must have detected */
-			break;
-		}
-	}
-
-	/* For VPM Phase should be perfectly aligned. */
-	phaseControl = (((pChipcHw->VPMClock >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
-		/* Load new phase value */
-		pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-	/* Return the status */
-	return (int)adjustCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-
-	if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-		return vpmPhaseAlignA0();
-	} else {
-		uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-		uint32_t phaseValue = 0;
-		int adjustCount = 0;
-
-		/* Disable VPM access */
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-		/* Disable HW VPM phase alignment  */
-		chipcHw_vpmHwPhaseAlignDisable();
-		/* Enable SW VPM phase alignment  */
-		chipcHw_vpmSwPhaseAlignEnable();
-		/* Adjust VPM phase */
-		while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-			phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-
-			/* Adjust phase control value */
-			if (phaseValue > 0xF) {
-				/* Increment phase control value */
-				phaseControl++;
-			} else if (phaseValue < 0xF) {
-				/* Decrement phase control value */
-				phaseControl--;
-			} else {
-				/* Enable VPM access */
-				pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-				/* Return adjust count */
-				return adjustCount;
-			}
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Count adjustment */
-			adjustCount++;
-		}
-	}
-
-	/* Disable VPM access */
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-	return -1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 367df75..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-
-	Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-	for Freq_vco = VCO_FREQ_MHz
-		Freq_ref = chipcHw_XTAL_FREQ_Hz
-		PLL_P1 = PLL_P2 = 1
-		and
-		PLL_NDIV_f = 0
-
-	We get:
-		PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-		Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = 
VCO_FREQ_MHz / PLL_MDIV_x
-
-		PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-
-/* ---- Private Variables 
------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-	uint32_t pllPreDivider2 = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		pChipcHw->PLLConfig2 =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-
-		pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-		    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-		    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider2 = pllPreDivider2;
-		/* Set NDIV Frac */
-		pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
-
-		/* This has to be removed once the default values are fixed for PLL2. */
-		pChipcHw->PLLControl12 = 0x38000700;
-		pChipcHw->PLLControl22 = 0x00000015;
-
-		/* Reset PLL2 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-		REG_LOCAL_IRQ_RESTORE;
-	}
-
-	/* Insert certain amount of delay before deasserting ARESET. */
-	udelay(1);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove analog reset and Power on the PLL */
-		pChipcHw->PLLConfig2 &=
-		    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-		      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-
-		REG_LOCAL_IRQ_RESTORE;
-
-	}
-
-	/* Wait until PLL is locked */
-	while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-		;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove digital reset */
-		pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e 
ssSupport)
-{
-	uint32_t pllPreDivider = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->PLLConfig =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-		/* Setting VCO frequency */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pllPreDivider =
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-			    ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-			      1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		} else {
-			pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-			    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-			     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		}
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider = pllPreDivider;
-		/* Set NDIV Frac */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
-		} else {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f;
-		}
-
-		/* Reset PLL1 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-
-		REG_LOCAL_IRQ_RESTORE;
-
-		/* Insert certain amount of delay before deasserting ARESET. */
-		udelay(1);
-
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Remove analog reset and Power on the PLL */
-			pChipcHw->PLLConfig &=
-			    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-			      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-
-		/* Wait until PLL is locked */
-		while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-		       || !(pChipcHw->
-			    PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-			;
-
-		/* Remove digital reset */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-			REG_LOCAL_IRQ_RESTORE;
-		}
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-	delay_init();
-#endif
-
-	/* Do not program PLL, when warm reset */
-	if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-		chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-				   initParam->ssSupport);
-		chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-	} else {
-		/* Clear sticky bits */
-		chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-	}
-	/* Clear sticky bits */
-	chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-
-	/* Before configuring the ARM clock, atleast we need to make sure BUS 
clock maintains the proper ratio with ARM clock */
-	pChipcHw->ACLKClock =
-	    (pChipcHw->
-	     ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-								 armBusRatio &
-								 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
-
-	/* Set various core component frequencies. The order in which this is 
done is important for some. */
-	/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the 
ARM, and VPM needs to know BUS */
-	/* frequency to find its ratio with the BUS.  Hence we must set the 
ARM first, followed by the BUS,  */
-	/* then VPM and RTBUS. */
-
-	chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-				  initParam->busClockFreqHz *
-				  initParam->armBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-				  initParam->busClockFreqHz *
-				  initParam->vpmBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-				  initParam->busClockFreqHz *
-				  initParam->ddrBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-				  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index 2671d88..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-/* ---- Private Variables 
------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-
-typedef void (*RUNFUNC) (void);
-
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to 
the state
-*   required to execute on reset.  To do so we need to copy the code 
into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-	int i = 0;
-	RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-
-	/* Disable all interrupts */
-	intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-	intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-	intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-			chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-		/* Bypass the PLL clocks before reboot */
-		pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-		pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-
-		/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-		do {
-			((uint32_t *) MM_IO_BASE_ARAM)[i] =
-			    ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
-			i++;
-		} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);	/* 
0xe1a0f00f == asm ("mov r15, r15"); */
-
-		CSP_CACHE_FLUSH_ALL;
-
-		/* run the function from ARAM */
-		runFunc();
-
-		/* Code will never get here, but include it to balance 
REG_LOCAL_IRQ_SAVE above */
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop 
  \n\t"
-		" nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		" MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" BIC      r0,r0,#0xd                                            \n\t"
-		" MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-#endif
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-		" MOV      r2,#0x80000000                                        \n\t"
-		" LDR      r3,[r2,#8]                                            \n\t"
-		" ORR      r3,r3,#0x20000                                        \n\t"
-		" STR      r3,[r2,#8]                                            \n\t"
-
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Issue reset */
-		" MOV      r3,#0x2                                               \n\t"
-		" STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-		" MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-static const char *gMuxStr[] = {
-	"GPIO",			/* 0 */
-	"KeyPad",		/* 1 */
-	"I2C-Host",		/* 2 */
-	"SPI",			/* 3 */
-	"Uart",			/* 4 */
-	"LED-Mtx-P",		/* 5 */
-	"LED-Mtx-S",		/* 6 */
-	"SDIO-0",		/* 7 */
-	"SDIO-1",		/* 8 */
-	"PCM",			/* 9 */
-	"I2S",			/* 10 */
-	"ETM",			/* 11 */
-	"Debug",		/* 12 */
-	"Misc",			/* 13 */
-	"0xE",			/* 14 */
-	"0xF",			/* 15 */
-};
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-	if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-		return "";
-	}
-
-	return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile 
b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104f..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 6b9be2e..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA 
Channel handle */
-    ) {
-	uint32_t val = 0;
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_MISC_t *pMiscReg =
-	    (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
-
-	switch (pCblk->channel) {
-	case 0:
-		val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
-		break;
-	case 1:
-		val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
-		break;
-	case 2:
-		val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
-		break;
-	case 3:
-		val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
-		break;
-	case 4:
-		val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
-		break;
-	case 5:
-		val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
-		break;
-	case 6:
-		val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
-		break;
-	case 7:
-		val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
-		break;
-	}
-
-	if (val <= 0x4) {
-		return 8 << val;
-	} else {
-		dmacHw_ASSERT(0);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pProg;
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Not safe yet to program the channel */
-		return;
-	}
-
-	if (pCblk->varDataStarted) {
-		if (pCblk->descUpdated) {
-			pCblk->descUpdated = 0;
-			pProg =
-			    (dmacHw_DESC_t *) ((uint32_t)
-					       dmacHw_REG_LLP(pCblk->module,
-							      pCblk->channel) +
-					       pRing->virt2PhyOffset);
-
-			/* Load descriptor if not loaded */
-			if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-				dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-					       pProg->sar);
-				dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-					       pProg->dar);
-				dmacHw_REG_CTL_LO(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.lo;
-				dmacHw_REG_CTL_HI(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.hi;
-			} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-				/* Return as end descriptor is processed */
-				return;
-			} else {
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			return;
-		}
-	} else {
-		if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-			/* Do not make a single chain, rather process one descriptor at a 
time */
-			pProg = pRing->pHead;
-			/* Point to the next descriptor for next iteration */
-			dmacHw_NEXT_DESC(pRing, pHead);
-		} else {
-			/* Return if no more pending descriptor */
-			if (pRing->pEnd == NULL) {
-				return;
-			}
-
-			pProg = pRing->pProg;
-			if (pConfig->transferMode ==
-			    dmacHw_TRANSFER_MODE_CONTINUOUS) {
-				/* Make sure a complete ring can be formed */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-					      llp == pRing->pProg);
-				/* Make sure pProg pointing to the pHead */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-					      pRing->pHead);
-				/* Make a complete ring */
-				do {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				} while (pRing->pProg != pRing->pHead);
-			} else {
-				/* Make a single long chain */
-				while (pRing->pProg != pRing->pEnd) {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				}
-			}
-		}
-
-		/* Program the channel registers */
-		dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-		dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-		    pProg->ctl.lo;
-		dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-		    pProg->ctl.hi;
-		if (pRing->pEnd) {
-			/* Remember the descriptor to use next */
-			pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-		}
-		/* Indicate no more pending descriptor  */
-		pRing->pEnd = (dmacHw_DESC_t *) NULL;
-	}
-	/* Start DMA operation */
-	dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-
-	uint32_t i = 0;
-
-	dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-	dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-
-	/* Enable access to the DMA block */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-
-	if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-		dmacHw_ASSERT(0);
-	}
-
-	memset((void *)dmacHw_gCblk, 0,
-	       sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-	for (i = 0; i < dmaChannelCount_0; i++) {
-		dmacHw_gCblk[i].module = 0;
-		dmacHw_gCblk[i].channel = i;
-	}
-	for (i = 0; i < dmaChannelCount_1; i++) {
-		dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-		dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-	/* Disable access to the DMA block */
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    ) {
-	int idx;
-
-	switch ((channelId >> 8)) {
-	case 0:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-		idx = (channelId & 0xff);
-		break;
-	case 1:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-		idx = dmaChannelCount_0 + (channelId & 0xff);
-		break;
-	default:
-		dmacHw_ASSERT(0);
-		return (dmacHw_HANDLE_t) -1;
-	}
-
-	return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	int module = pCblk->module;
-	int channel = pCblk->channel;
-
-	/* Reinitialize the control block */
-	memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-	pCblk->module = module;
-	pCblk->channel = channel;
-
-	/* Enable DMA controller */
-	dmacHw_DMA_ENABLE(pCblk->module);
-	/* Reset DMA channel */
-	dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Mask event specific interrupts */
-	dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/* [ IN ] Number of 
descriptor in the ring */
-    ) {
-	/* Need extra 4 byte to ensure 32 bit alignment  */
-	return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-		sizeof(uint32_t);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    ) {
-	uint32_t i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	/* Check the alignment of the descriptor */
-	if ((uint32_t) pDescriptorVirt & 0x00000003) {
-		dmacHw_ASSERT(0);
-		return -1;
-	}
-
-	/* Check if enough space has been allocated for descriptor ring */
-	if (len < dmacHw_descriptorLen(num)) {
-		return -1;
-	}
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-	pRing->pHead =
-	    (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-	/* Initialize link item chain, starting from the head */
-	pDesc = pRing->pHead;
-	/* Find the offset between virtual to physical address */
-	pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-
-	/* Form the descriptor ring */
-	for (i = 0; i < num - 1; i++) {
-		/* Clear link list item */
-		memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-		/* Point to the next item in the physical address */
-		pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-		/* Point to the next item in the virtual address */
-		pDesc->llp = (uint32_t) (pDesc + 1);
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-
-	/* Clear last link list item */
-	memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-	/* Last item pointing to the first item in the
-	   physical address to complete the ring */
-	pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-	/* Last item pointing to the first item in the
-	   virtual address to complete the ring
-	 */
-	pDesc->llp = (uint32_t) pRing->pHead;
-	/* Mark descriptor is ready to use */
-	pDesc->ctl.hi = dmacHw_DESC_FREE;
-	/* Set the number of descriptors in the ring */
-	pRing->num = num;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	uint32_t cfgHigh = 0;
-	int srcTrSize;
-	int dstTrSize;
-
-	pCblk->varDataStarted = 0;
-	pCblk->userData = NULL;
-
-	/* Configure
-	   - Burst transaction when enough data in available in FIFO
-	   - AHB Access protection 1
-	   - Source and destination peripheral ports
-	 */
-	cfgHigh =
-	    dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-	    dmacHw_SRC_PERI_INTF(pConfig->
-				 srcPeripheralPort) |
-	    dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-	/* Set priority */
-	dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-				    pConfig->channelPriority);
-
-	if (pConfig->dstStatusRegisterAddress != 0) {
-		/* Destination status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-		/* Configure status registers */
-		dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->dstStatusRegisterAddress);
-	}
-
-	if (pConfig->srcStatusRegisterAddress != 0) {
-		/* Source status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-		/* Source status update enable */
-		dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->srcStatusRegisterAddress);
-	}
-	/* Configure the config high register */
-	dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Configure block interrupt */
-	if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure complete transfer interrupt */
-	if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure error interrupt */
-	if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure gather register */
-	if (pConfig->srcGatherWidth) {
-		srcTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-		if (!
-		    ((pConfig->srcGatherWidth % srcTrSize)
-		     && (pConfig->srcGatherJump % srcTrSize))) {
-			dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->srcGatherWidth /
-			      srcTrSize) << 20) | (pConfig->srcGatherJump /
-						   srcTrSize);
-		} else {
-			return -1;
-		}
-	}
-	/* Configure scatter register */
-	if (pConfig->dstScatterWidth) {
-		dstTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-		if (!
-		    ((pConfig->dstScatterWidth % dstTrSize)
-		     && (pConfig->dstScatterJump % dstTrSize))) {
-			dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->dstScatterWidth /
-			      dstTrSize) << 20) | (pConfig->dstScatterJump /
-						   dstTrSize);
-		} else {
-			return -1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_BUSY;
-	} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-		   (0x00000001 << pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_ERROR;
-	}
-
-	return dmacHw_TRANSFER_STATUS_DONE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			     void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-	dmacHw_DESC_t *pProg;
-	int srcTs = 0;
-	int blkTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int count = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if ((pConfig->srcGatherWidth % srcTrSize)
-	    || (pConfig->dstScatterWidth % dstTrSize)) {
-		return -2;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	/* Check the availability of "descCount" discriptors in the ring */
-	pProg = pRing->pHead;
-	for (count = 0; (descCount <= pRing->num) && (count < descCount);
-	     count++) {
-		if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-			/* Sufficient descriptors are not available */
-			return -3;
-		}
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	}
-
-	/* Remember the link list item to program the channel registers */
-	pStart = pProg = pRing->pHead;
-	/* Make a link list with "descCount(=count)" number of descriptors */
-	while (count) {
-		/* Reset channel control information */
-		pProg->ctl.lo = 0;
-		/* Enable source gather if configured */
-		if (pConfig->srcGatherWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-		}
-		/* Enable destination scatter if configured */
-		if (pConfig->dstScatterWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-		}
-		/* Set source and destination address */
-		pProg->sar = (uint32_t) pSrcAddr;
-		pProg->dar = (uint32_t) pDstAddr;
-		/* Use "devCtl" to mark that user memory need to be freed later if 
needed */
-		if (pProg == pRing->pHead) {
-			pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-		} else {
-			pProg->devCtl = 0;
-		}
-
-		blkTs = srcTs;
-
-		/* Special treatmeant for last descriptor */
-		if (count == 1) {
-			/* Mark the last descriptor */
-			pProg->ctl.lo &=
-			    ~(dmacHw_REG_CTL_LLP_DST_EN |
-			      dmacHw_REG_CTL_LLP_SRC_EN);
-			/* Treatment for odd data bytes */
-			if (oddSize) {
-				/* Adjust for single byte transaction width */
-				switch (pConfig->transferType) {
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs =
-					    (oddSize / srcTrSize) +
-					    ((oddSize % srcTrSize) ? 1 : 0);
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-					/* Do not adjust the transaction width  */
-					break;
-				}
-			} else {
-				srcTs -= blkTs;
-			}
-		} else {
-			if (srcTs / maxBlockSize) {
-				blkTs = maxBlockSize;
-			}
-			/* Remaining source transactions for next iteration */
-			srcTs -= blkTs;
-		}
-		/* Must have a valid source transactions */
-		dmacHw_ASSERT(blkTs > 0);
-		/* Set control information */
-		if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-			pProg->ctl.lo |= pConfig->transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		} else {
-			uint32_t transferType = 0;
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-			pProg->ctl.lo |= transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		}
-
-		/* Set block transaction size */
-		pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		/* Look for next descriptor */
-		if (count > 1) {
-			/* Point to the next descriptor */
-			pProg = (dmacHw_DESC_t *) pProg->llp;
-
-			/* Update source and destination address for next iteration */
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-				/* Do not adjust the address */
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			/* At the end of transfer "srcTs" must be zero */
-			dmacHw_ASSERT(srcTs == 0);
-		}
-		count--;
-	}
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pStart;
-	}
-	/* Indicate that the descriptor is updated */
-	pRing->pEnd = pProg;
-	/* Head pointing to the next descriptor */
-	pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-	/* Update Tail pointer if destination is a peripheral,
-	   because no one is going to read from the pTail
-	 */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	switch (attr) {
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-		return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-		return (1 <<
-			 (dmacHw_GET_MAX_BLOCK_SIZE
-			  (pCblk->module, pCblk->module) + 2)) - 8;
-	case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-		return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-		return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-							   pCblk->channel);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-		return GetFifoSize(handle);
-	}
-	dmacHw_ASSERT(0);
-	return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index a1f3283..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* 
Declared in dmacHw.c */
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* ---- Internal Use Function Prototypes 
--------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module,	/*   [ IN ] DMA 
Controller unit  (0-1) */
-				    int channel,	/*   [ IN ] DMA Channel          (0-7) / -1(all) */
-				    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	int chan;
-
-	(*fpPrint) ("Displaying register content \n\n");
-	(*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: SW source req                       0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-	(*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW source last                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: misc config                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-	(*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-	(*fpPrint) ("Module %d: misc ID                             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-	(*fpPrint) ("Module %d: misc test                           0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-
-	if (channel == -1) {
-		for (chan = 0; chan < 8; chan++) {
-			(*fpPrint)
-			    ("--------------------------------------------------\n");
-			(*fpPrint)
-			    ("Module %d: Channel %d Source                   0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Destination              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d LLP                      0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_LLP(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (LO)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (HI)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats               0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (LO)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (HI)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-		}
-	} else {
-		chan = channel;
-		(*fpPrint)
-		    ("--------------------------------------------------\n");
-		(*fpPrint)
-		    ("Module %d: Channel %d Source                   0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Destination              0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d LLP                      0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (LO)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (HI)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats             0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats               0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (LO)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (HI)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,	/*   [ IN ] Descriptor 
buffer */
-			    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-
-	if (pRing->pHead == NULL) {
-		return;
-	}
-
-	pStart = pRing->pHead;
-
-	while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-		if (pStart == pRing->pHead) {
-			(*fpPrint) ("Head\n");
-		}
-		if (pStart == pRing->pTail) {
-			(*fpPrint) ("Tail\n");
-		}
-		if (pStart == pRing->pProg) {
-			(*fpPrint) ("Prog\n");
-		}
-		if (pStart == pRing->pEnd) {
-			(*fpPrint) ("End\n");
-		}
-		if (pStart == pRing->pFree) {
-			(*fpPrint) ("Free\n");
-		}
-		(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-		(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-		(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-		(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-		(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-		(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-		(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-		(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-		(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-
-		pStart = (dmacHw_DESC_t *) pStart->llp;
-	}
-	if (pStart == pRing->pHead) {
-		(*fpPrint) ("Head\n");
-	}
-	if (pStart == pRing->pTail) {
-		(*fpPrint) ("Tail\n");
-	}
-	if (pStart == pRing->pProg) {
-		(*fpPrint) ("Prog\n");
-	}
-	if (pStart == pRing->pEnd) {
-		(*fpPrint) ("End\n");
-	}
-	if (pStart == pRing->pFree) {
-		(*fpPrint) ("Free\n");
-	}
-	(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-	(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-	(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-	(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-	(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-	(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-	(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-	(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-	(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor	/*   [ IN ] 
Descriptor buffer */
-    ) {
-	uint32_t ttfc =
-	    (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-	    lo & dmacHw_REG_CTL_TTFC_MASK;
-
-	switch (ttfc) {
-	case dmacHw_REG_CTL_TTFC_MM_DMAC:
-	case dmacHw_REG_CTL_TTFC_MP_DMAC:
-	case dmacHw_REG_CTL_TTFC_PM_DMAC:
-	case dmacHw_REG_CTL_TTFC_PP_DMAC:
-		return 1;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_DESC_t *pProg;
-	dmacHw_DESC_t *pHead;
-	int srcTs = 0;
-	int srcTrSize = 0;
-
-	pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-	pProg = pHead;
-
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-	srcTs = dataLen / srcTrSize;
-	do {
-		pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	} while (pProg != pHead);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/* [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/* [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-
-	if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_TRANS;
-	}
-	if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-	}
-	if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_ERROR;
-	}
-
-	return status;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-		if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-		     ((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    ) {
-			return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-		}
-	}
-	return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	int srcTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if (pConfig->srcGatherWidth % srcTrSize
-	    || pConfig->dstScatterWidth % dstTrSize) {
-		return -1;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	return descCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	/* Make sure channel is not busy */
-	if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Check if pEnd is not processed */
-		if (pRing->pEnd) {
-			/* Something left for processing */
-			return 1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	/* Stop the channel */
-	dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-		   void (*fpFree) (void *)	/*   [ IN ] Function pointer to free data 
memory */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t count = 0;
-
-	if (fpFree == NULL) {
-		return -1;
-	}
-
-	while ((pRing->pFree != pRing->pTail)
-	       && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-		if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-			/* Identify, which memory to free */
-			if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-				(*fpFree) ((void *)pRing->pFree->dar);
-			} else {
-				/* Destination was a peripheral */
-				(*fpFree) ((void *)pRing->pFree->sar);
-			}
-			/* Unmark user memory to indicate it is freed */
-			pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-		}
-		dmacHw_NEXT_DESC(pRing, pFree);
-
-		count++;
-	}
-
-	return count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*   [ IN 
] DMA Channel handle */
-				     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				     uint32_t srcAddr,	/*   [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*   [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*   [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*   [ IN ] Number of descriptor to set */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_t *pProg = NULL;
-	dmacHw_DESC_t *pLast = NULL;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t dstAddr;
-	uint32_t controlParam;
-	int i;
-
-	dmacHw_ASSERT(pConfig->transferType ==
-		      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-
-	if (num > pRing->num) {
-		return -1;
-	}
-
-	pLast = pRing->pEnd;	/* Last descriptor updated */
-	pProg = pRing->pHead;	/* First descriptor in the new list */
-
-	controlParam = pConfig->srcUpdate |
-	    pConfig->dstUpdate |
-	    pConfig->srcMaxTransactionWidth |
-	    pConfig->dstMaxTransactionWidth |
-	    pConfig->srcMasterInterface |
-	    pConfig->dstMasterInterface |
-	    pConfig->srcMaxBurstWidth |
-	    pConfig->dstMaxBurstWidth |
-	    dmacHw_REG_CTL_TTFC_PM_PERI |
-	    dmacHw_REG_CTL_LLP_DST_EN |
-	    dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-
-	for (i = 0; i < num; i++) {
-		/* Allocate Rx buffer only for idle descriptor */
-		if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-		    ) {
-			/* Rx descriptor is not idle */
-			break;
-		}
-		/* Set source address */
-		pRing->pHead->sar = srcAddr;
-		if (fpAlloc) {
-			/* Allocate memory for buffer in descriptor */
-			dstAddr = (uint32_t) (*fpAlloc) (len);
-			/* Check the destination address */
-			if (dstAddr == 0) {
-				if (i == 0) {
-					/* Not a single descriptor is available */
-					return -1;
-				}
-				break;
-			}
-			/* Set destination address */
-			pRing->pHead->dar = dstAddr;
-		}
-		/* Set control information */
-		pRing->pHead->ctl.lo = controlParam;
-		/* Use "devCtl" to mark the memory that need to be freed later */
-		pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-		/* Descriptor is now owned by the channel */
-		pRing->pHead->ctl.hi = 0;
-		/* Remember the descriptor last updated */
-		pRing->pEnd = pRing->pHead;
-		/* Update next descriptor */
-		dmacHw_NEXT_DESC(pRing, pHead);
-	}
-
-	/* Mark the end of the list */
-	pRing->pEnd->ctl.lo &=
-	    ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-	/* Connect the list */
-	if (pLast != pProg) {
-		pLast->ctl.lo |=
-		    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-	}
-	/* Mark the descriptors are updated */
-	pCblk->descUpdated = 1;
-	if (!pCblk->varDataStarted) {
-		/* LLP must be pointing to the first descriptor */
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		/* Channel, handling variable data started */
-		pCblk->varDataStarted = 1;
-	}
-
-	return i;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       dmacHw_CONFIG_t *pConfig,	/*   [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			       void **ppBbuf,	/*   [ OUT ] Data received */
-			       size_t *pLlen	/*   [ OUT ] Length of the data received */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	(void)handle;
-
-	if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-		if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    (pRing->pTail == pRing->pHead)
-		    ) {
-			/* No receive data available */
-			*ppBbuf = (char *)NULL;
-			*pLlen = 0;
-
-			return 0;
-		}
-	}
-
-	/* Return read buffer and length */
-	*ppBbuf = (char *)pRing->pTail->dar;
-
-	/* Extract length of the received data */
-	if (DmaIsFlowController(pDescriptor)) {
-		uint32_t srcTrSize = 0;
-
-		switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-			srcTrSize = 1;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-			srcTrSize = 2;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-			srcTrSize = 4;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-			srcTrSize = 8;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		/* Calculate length from the block size */
-		*pLlen =
-		    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-		    srcTrSize;
-	} else {
-		/* Extract length from the source peripheral */
-		*pLlen = pRing->pTail->sstat;
-	}
-
-	/* Advance tail to next descriptor */
-	dmacHw_NEXT_DESC(pRing, pTail);
-
-	return 1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				uint32_t ctlAddress,	/*   [ IN ] Address of the device control 
register */
-				uint32_t control	/*   [ IN ] Device control information */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (ctlAddress == 0) {
-		return -1;
-	}
-
-	/* Check the availability of descriptors in the ring */
-	if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-		return -1;
-	}
-	/* Set control information */
-	pRing->pHead->devCtl = control;
-	/* Set source and destination address */
-	pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-	pRing->pHead->dar = ctlAddress;
-	/* Set control parameters */
-	if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-		pRing->pHead->ctl.lo = pConfig->transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-	} else {
-		uint32_t transferType = 0;
-		switch (pConfig->transferType) {
-		case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-			transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-			break;
-		case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-			transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		pRing->pHead->ctl.lo = transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface |
-		    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-	}
-
-	/* Set block transaction size to one 32 bit transaction */
-	pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pRing->pHead;
-	}
-	pRing->pEnd = pRing->pHead;
-
-	/* Advance the descriptor */
-	dmacHw_NEXT_DESC(pRing, pHead);
-
-	/* Update Tail pointer if destination is a peripheral */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       void *userData	/*  [ IN ] User data */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	pCblk->userData = userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	return pCblk->userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    ) {
-	int i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	pDesc = pRing->pHead;
-
-	for (i = 0; i < pRing->num; i++) {
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-	DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile 
b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61a..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c 
b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index 16225e4..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-
-#include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK 
/ tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / 
tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_LOW_256_RESOLUTION_COUNT)
-
-#define tmrHw_HIGH_1_RESOLUTION_COUNT 
(tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / 
tmrHw_HIGH_256_RESOLUTION_COUNT)
-
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-) {
-	switch (capability) {
-	case tmrHw_CAPABILITY_CLOCK:
-		return (timerId <=
-			1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-		    tmrHw_HIGH_RESOLUTION_CLOCK;
-	case tmrHw_CAPABILITY_RESOLUTION:
-		return 32;
-	default:
-		return 0;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer Id */
-) {
-	/* Reset timer */
-	pTmrHw[timerId].LoadValue = 0;
-	pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-	pTmrHw[timerId].Control = 0;
-	pTmrHw[timerId].BackgroundLoad = 0;
-	/* Always configure as a 32 bit timer */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-	/* Clear interrupt only if raw status interrupt is set */
-	if (pTmrHw[timerId].RawInterruptStatus) {
-		pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	uint32_t scale = 0;
-	uint32_t count = 0;
-
-	if (timerId == 0 || timerId == 1) {
-		if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-
-	} else if (timerId == 2 || timerId == 3) {
-		if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-	}
-	return count / scale;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-) {
-	uint32_t resolution = 0;
-	uint32_t count = 0;
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-	/* Set timer in highest resolution */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-
-	if (rate && (timerId == 0 || timerId == 1)) {
-		if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-			return 0;
-		}
-		resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-	} else if (rate && (timerId == 2 || timerId == 3)) {
-		if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-			return 0;
-		} else {
-			resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-		}
-	} else {
-		return 0;
-	}
-	/* Find the counter value */
-	count = resolution / rate;
-	/* Set counter value */
-	pTmrHw[timerId].LoadValue = count;
-	pTmrHw[timerId].BackgroundLoad = count;
-
-	return resolution / count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode oneshot */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) {
-	uint32_t scale = 0;
-
-	ResetTimer(timerId);
-	/* Set timer as free running mode */
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	if (divider >= 64) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-		scale = 256;
-	} else if (divider >= 8) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-		scale = 16;
-	} else {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-		scale = 1;
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-	} else if (timerId == 2 || timerId == 3) {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	/* return 32 bit timer value */
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-	case tmrHw_CONTROL_FREE_RUNNING:
-		if (pTmrHw[timerId].CurrentValue) {
-			return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-		}
-		break;
-	case tmrHw_CONTROL_PERIODIC:
-	case tmrHw_CONTROL_ONESHOT:
-		return pTmrHw[timerId].BackgroundLoad -
-		    pTmrHw[timerId].CurrentValue;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	uint32_t divider = 0;
-
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-	case tmrHw_CONTROL_PRESCALE_1:
-		divider = 1;
-		break;
-	case tmrHw_CONTROL_PRESCALE_16:
-		divider = 16;
-		break;
-	case tmrHw_CONTROL_PRESCALE_256:
-		divider = 256;
-		break;
-	default:
-		tmrHw_ASSERT(0);
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-	} else {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].InterruptClear = 0x1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-) {
-	if (pTmrHw[timerId].InterruptStatus) {
-		return tmrHw_INTERRUPT_STATUS_SET;
-	} else {
-		return tmrHw_INTERRUPT_STATUS_UNSET;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void	/*  void */
-) {
-	int i;
-
-	for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-		if (pTmrHw[i].InterruptStatus) {
-			return i;
-		}
-	}
-
-	return 0xFFFFFFFF;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-) {
-	(*fpPrint) ("Displaying register contents \n\n");
-	(*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-		    pTmrHw[timerId].LoadValue);
-	(*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-		    pTmrHw[timerId].BackgroundLoad);
-	(*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-		    pTmrHw[timerId].Control);
-	(*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptClear);
-	(*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-		    pTmrHw[timerId].RawInterruptStatus);
-	(*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptStatus);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-	tmrHw_RATE_t usec_tick_rate;
-	tmrHw_COUNT_t start_time;
-	tmrHw_COUNT_t delta_time;
-
-	start_time = tmrHw_GetCurrentCount(timerId);
-	usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-	delta_time = usecs * usec_tick_rate;
-
-	/* Busy wait */
-	while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-		;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241..0000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-
-#include <mach/timer.h>
-
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-
-/* ---- Public Variables 
------------------------------------------------- */
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 
4) | (channelIdx))
-
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-
-
-/* ---- Private Variables 
------------------------------------------------ */
-
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-
-#include "dma_device.c"
-
-/* ---- Private Function Prototypes 
-------------------------------------- */
-
-/* ---- Functions 
------------------------------------------------------- */
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-				  int count, int *eof, void *data)
-{
-	int controllerIdx;
-	int channelIdx;
-	int limit = count - 200;
-	int len = 0;
-	DMA_Channel_t *channel;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			if (len >= limit) {
-				break;
-			}
-
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			len +=
-			    sprintf(buf + len, "%d:%d ", controllerIdx,
-				    channelIdx);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				len +=
-				    sprintf(buf + len, "Dedicated for %s ",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-			} else {
-				len += sprintf(buf + len, "Shared ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-				len += sprintf(buf + len, "No ISR ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-				len += sprintf(buf + len, "Fifo: 128 ");
-			} else {
-				len += sprintf(buf + len, "Fifo: 64  ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-				len +=
-				    sprintf(buf + len, "InUse by %s",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-				len +=
-				    sprintf(buf + len, " (%s:%d)",
-					    channel->fileName,
-					    channel->lineNum);
-#endif
-			} else {
-				len += sprintf(buf + len, "Avail ");
-			}
-
-			if (channel->lastDevType != DMA_DEVICE_NONE) {
-				len +=
-				    sprintf(buf + len, "Last use: %s ",
-					    DMA_gDeviceAttribute[channel->
-								 lastDevType].
-					    name);
-			}
-
-			len += sprintf(buf + len, "\n");
-		}
-	}
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-				 int count, int *eof, void *data)
-{
-	int limit = count - 200;
-	int len = 0;
-	int devIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (devAttr->name == NULL) {
-			continue;
-		}
-
-		if (len >= limit) {
-			break;
-		}
-
-		len += sprintf(buf + len, "%-12s ", devAttr->name);
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			len +=
-			    sprintf(buf + len, "Dedicated %d:%d ",
-				    devAttr->dedicatedController,
-				    devAttr->dedicatedChannel);
-		} else {
-			len += sprintf(buf + len, "Shared DMA:");
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-				len += sprintf(buf + len, "0");
-			}
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-				len += sprintf(buf + len, "1");
-			}
-			len += sprintf(buf + len, " ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-			len += sprintf(buf + len, "NoISR ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-			len += sprintf(buf + len, "Allow-128 ");
-		}
-
-		len +=
-		    sprintf(buf + len,
-			    "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-			    devAttr->numTransfers, devAttr->transferTicks,
-			    devAttr->transferBytes,
-			    devAttr->ring.bytesAllocated);
-
-	}
-
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-	return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-	int controllerIdx;
-	int channelIdx;
-
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-	channelIdx = CHANNEL_FROM_HANDLE(handle);
-
-	if ((controllerIdx > DMA_NUM_CONTROLLERS)
-	    || (channelIdx > DMA_NUM_CHANNELS)) {
-		return NULL;
-	}
-	return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int irqStatus;
-
-	channel = (DMA_Channel_t *) dev_id;
-
-	/* Figure out why we were called, and knock down the interrupt */
-
-	irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-	dmacHw_clearInterrupt(channel->dmacHwHandle);
-
-	if ((channel->devType < 0)
-	    || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-		printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-		       channel->devType);
-		return IRQ_NONE;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Update stats */
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-		devAttr->transferTicks +=
-		    (timer_get_tick_count() - devAttr->transferStartTime);
-	}
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-		printk(KERN_ERR
-		       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-		       channel->devType, devAttr->name);
-	} else {
-		devAttr->numTransfers++;
-		devAttr->transferBytes += devAttr->numBytes;
-	}
-
-	/* Call any installed handler */
-
-	if (devAttr->devHandler != NULL) {
-		devAttr->devHandler(channel->devType, irqStatus,
-				    devAttr->userData);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    ) {
-	size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-
-	if ((ring == NULL) || (numDescriptors <= 0)) {
-		return -EINVAL;
-	}
-
-	ring->physAddr = 0;
-	ring->descriptorsAllocated = 0;
-	ring->bytesAllocated = 0;
-
-	ring->virtAddr = dma_alloc_writecombine(NULL,
-						     bytesToAlloc,
-						     &ring->physAddr,
-						     GFP_KERNEL);
-	if (ring->virtAddr == NULL) {
-		return -ENOMEM;
-	}
-
-	ring->bytesAllocated = bytesToAlloc;
-	ring->descriptorsAllocated = numDescriptors;
-
-	return dma_init_descriptor_ring(ring, numDescriptors);
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    ) {
-	if (ring->virtAddr != NULL) {
-		dma_free_writecombine(NULL,
-				      ring->bytesAllocated,
-				      ring->virtAddr, ring->physAddr);
-	}
-
-	ring->bytesAllocated = 0;
-	ring->descriptorsAllocated = 0;
-	ring->virtAddr = NULL;
-	ring->physAddr = 0;
-}
-
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    ) {
-	if (ring->virtAddr == NULL) {
-		return -EINVAL;
-	}
-	if (dmacHw_initDescriptor(ring->virtAddr,
-				  ring->physAddr,
-				  ring->bytesAllocated, numDescriptors) < 0) {
-		printk(KERN_ERR
-		       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int numDescriptors;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR
-		       "dma_calculate_descriptor_count: 
dmacHw_calculateDescriptorCount failed\n");
-		return -EINVAL;
-	}
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int rc;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	rc = dmacHw_setDataDescriptor(&devAttr->config,
-				      ring->virtAddr,
-				      (void *)srcData,
-				      (void *)dstData, numBytes);
-	if (rc < 0) {
-		printk(KERN_ERR
-		       "dma_add_descriptors: dmacHw_setDataDescriptor failed with 
code: %d\n",
-		       rc);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_add_descriptors);
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	/* Free the previously allocated descriptor ring */
-
-	dma_free_descriptor_ring(&devAttr->ring);
-
-	if (ring != NULL) {
-		/* Copy in the new one */
-
-		devAttr->ring = *ring;
-	}
-
-	/* Set things up so that if dma_transfer is called then this descriptor */
-	/* ring will get freed. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	memset(ring, 0, sizeof(*ring));
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	*ring = devAttr->ring;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-static int ConfigChannel(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int controllerIdx;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-		if (devAttr->config.transferType ==
-		    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-			devAttr->config.dstPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		} else if (devAttr->config.transferType ==
-			   dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-			devAttr->config.srcPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		}
-	}
-
-	if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-		printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_init(void)
-{
-	int rc = 0;
-	int controllerIdx;
-	int channelIdx;
-	DMA_Device_t devIdx;
-	DMA_Channel_t *channel;
-	DMA_Handle_t dedicatedHandle;
-
-	memset(&gDMA, 0, sizeof(gDMA));
-
-	sema_init(&gDMA.lock, 0);
-	init_waitqueue_head(&gDMA.freeChannelQ);
-
-	/* Initialize the Hardware */
-
-	dmacHw_initDma();
-
-	/* Start off by marking all of the DMA channels as shared. */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			channel->flags = 0;
-			channel->devType = DMA_DEVICE_NONE;
-			channel->lastDevType = DMA_DEVICE_NONE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-			channel->fileName = "";
-			channel->lineNum = 0;
-#endif
-
-			channel->dmacHwHandle =
-			    dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-						    (controllerIdx,
-						     channelIdx));
-			dmacHw_initChannel(channel->dmacHwHandle);
-		}
-	}
-
-	/* Record any special attributes that channels may have */
-
-	gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-
-	/* Now walk through and record the dedicated channels. */
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-		    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-			printk(KERN_ERR
-			       "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-			       devAttr->name);
-			rc = -EINVAL;
-			goto out;
-		}
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			/* This is a dedicated device. Mark the channel as being reserved. */
-
-			if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Controller %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedController);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Channel %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedChannel);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			dedicatedHandle =
-			    MAKE_HANDLE(devAttr->dedicatedController,
-					devAttr->dedicatedChannel);
-			channel = HandleToChannel(dedicatedHandle);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				printk
-				    ("DMA Device: %s attempting to use same DMA Controller:Channel 
(%d:%d) as %s\n",
-				     devAttr->name,
-				     devAttr->dedicatedController,
-				     devAttr->dedicatedChannel,
-				     DMA_gDeviceAttribute[channel->devType].
-				     name);
-				rc = -EBUSY;
-				goto out;
-			}
-
-			channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-			channel->devType = devIdx;
-
-			if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-				channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-			}
-
-			/* For dedicated channels, we can go ahead and configure the DMA 
channel now */
-			/* as well. */
-
-			ConfigChannel(dedicatedHandle);
-		}
-	}
-
-	/* Go through and register the interrupt handlers */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-				snprintf(channel->name, sizeof(channel->name),
-					 "dma %d:%d %s", controllerIdx,
-					 channelIdx,
-					 channel->devType ==
-					 DMA_DEVICE_NONE ? "" :
-					 DMA_gDeviceAttribute[channel->devType].
-					 name);
-
-				rc =
-				     request_irq(IRQ_DMA0C0 +
-						 (controllerIdx *
-						  DMA_NUM_CHANNELS) +
-						 channelIdx,
-						 dma_interrupt_handler,
-						 IRQF_DISABLED, channel->name,
-						 channel);
-				if (rc != 0) {
-					printk(KERN_ERR
-					       "request_irq for IRQ_DMA%dC%d failed\n",
-					       controllerIdx, channelIdx);
-				}
-			}
-		}
-	}
-
-	/* Create /proc/dma/channels and /proc/dma/devices */
-
-	gDmaDir = proc_mkdir("dma", NULL);
-
-	if (gDmaDir == NULL) {
-		printk(KERN_ERR "Unable to create /proc/dma\n");
-	} else {
-		create_proc_read_entry("channels", 0, gDmaDir,
-				       dma_proc_read_channels, NULL);
-		create_proc_read_entry("devices", 0, gDmaDir,
-				       dma_proc_read_devices, NULL);
-	}
-
-out:
-
-	up(&gDMA.lock);
-
-	return rc;
-}
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-	DMA_Handle_t handle;
-	DMA_DeviceAttribute_t *devAttr;
-	DMA_Channel_t *channel;
-	int controllerIdx;
-	int controllerIdx2;
-	int channelIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-		handle = -ENODEV;
-		goto out;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	{
-		char *s;
-
-		s = strrchr(fileName, '/');
-		if (s != NULL) {
-			fileName = s + 1;
-		}
-	}
-#endif
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-		/* This device has already been requested and not been freed */
-
-		printk(KERN_ERR "%s: device %s is already requested\n",
-		       __func__, devAttr->name);
-		handle = -EBUSY;
-		goto out;
-	}
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-		/* This device has a dedicated channel. */
-
-		channel =
-		    &gDMA.controller[devAttr->dedicatedController].
-		    channel[devAttr->dedicatedChannel];
-		if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-			handle = -EBUSY;
-			goto out;
-		}
-
-		channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-		devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-		channel->fileName = fileName;
-		channel->lineNum = lineNum;
-#endif
-		handle =
-		    MAKE_HANDLE(devAttr->dedicatedController,
-				devAttr->dedicatedChannel);
-		goto out;
-	}
-
-	/* This device needs to use one of the shared channels. */
-
-	handle = DMA_INVALID_HANDLE;
-	while (handle == DMA_INVALID_HANDLE) {
-		/* Scan through the shared channels and see if one is available */
-
-		for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-		     controllerIdx2++) {
-			/* Check to see if we should try on controller 1 first. */
-
-			controllerIdx = controllerIdx2;
-			if ((devAttr->
-			     flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-				controllerIdx = 1 - controllerIdx;
-			}
-
-			/* See if the device is available on the controller being tested */
-
-			if ((devAttr->
-			     flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-			    != 0) {
-				for (channelIdx = 0;
-				     channelIdx < DMA_NUM_CHANNELS;
-				     channelIdx++) {
-					channel =
-					    &gDMA.controller[controllerIdx].
-					    channel[channelIdx];
-
-					if (((channel->
-					      flags &
-					      DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-					     0)
-					    &&
-					    ((channel->
-					      flags & DMA_CHANNEL_FLAG_IN_USE)
-					     == 0)) {
-						if (((channel->
-						      flags &
-						      DMA_CHANNEL_FLAG_LARGE_FIFO)
-						     != 0)
-						    &&
-						    ((devAttr->
-						      flags &
-						      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-						     == 0)) {
-							/* This channel is a large fifo - don't tie it up */
-							/* with devices that we don't want using it. */
-
-							continue;
-						}
-
-						channel->flags |=
-						    DMA_CHANNEL_FLAG_IN_USE;
-						channel->devType = dev;
-						devAttr->flags |=
-						    DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-						channel->fileName = fileName;
-						channel->lineNum = lineNum;
-#endif
-						handle =
-						    MAKE_HANDLE(controllerIdx,
-								channelIdx);
-
-						/* Now that we've reserved the channel - we can go ahead and 
configure it */
-
-						if (ConfigChannel(handle) != 0) {
-							handle = -EIO;
-							printk(KERN_ERR
-							       "dma_request_channel: ConfigChannel failed\n");
-						}
-						goto out;
-					}
-				}
-			}
-		}
-
-		/* No channels are currently available. Let's wait for one to free up. */
-
-		{
-			DEFINE_WAIT(wait);
-
-			prepare_to_wait(&gDMA.freeChannelQ, &wait,
-					TASK_INTERRUPTIBLE);
-			up(&gDMA.lock);
-			schedule();
-			finish_wait(&gDMA.freeChannelQ, &wait);
-
-			if (signal_pending(current)) {
-				/* We don't currently hold gDMA.lock, so we return directly */
-
-				return -ERESTARTSYS;
-			}
-		}
-
-		if (down_interruptible(&gDMA.lock)) {
-			return -ERESTARTSYS;
-		}
-	}
-
-out:
-	up(&gDMA.lock);
-
-	return handle;
-}
-
-/* Create both _dbg and non _dbg functions for modules. */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-	return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t handle	/* DMA handle. */
-    ) {
-	int rc = 0;
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		rc = -EINVAL;
-		goto out;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-		channel->lastDevType = channel->devType;
-		channel->devType = DMA_DEVICE_NONE;
-	}
-	channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-	devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-
-out:
-	up(&gDMA.lock);
-
-	wake_up_interruptible(&gDMA.freeChannelQ);
-
-	return rc;
-}
-
-EXPORT_SYMBOL(dma_free_channel);
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t device	/* Device to check. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, numDescriptors);
-			return rc;
-		}
-		/* Setup the descriptor for this transfer */
-
-		if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-					  devAttr->ring.physAddr,
-					  devAttr->ring.bytesAllocated,
-					  numDescriptors) < 0) {
-			printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-			       __func__);
-			return -EINVAL;
-		}
-	} else {
-		/* We've already got enough ring buffer allocated. All we need to do 
is reset */
-		/* any control information, just in case the previous DMA was stopped. */
-
-		dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Remember the critical information for this transfer so that we can 
eliminate */
-	/* another call to dma_alloc_descriptors if the caller reuses the same 
buffers */
-
-	devAttr->prevSrcData = srcData;
-	devAttr->prevDstData = dstData;
-	devAttr->prevNumBytes = numBytes;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptors);
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDst1Descriptors;
-	int numDst2Descriptors;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDst1Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData1, numBytes);
-	if (numDst1Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDst2Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData2, numBytes);
-	if (numDst2Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDescriptors = numDst1Descriptors + numDst2Descriptors;
-	/* printk("numDescriptors: %d\n", numDescriptors); */
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, ringBytesRequired);
-			return rc;
-		}
-	}
-
-	/* Setup the descriptor for this transfer. Since this function is used 
with */
-	/* CONTINUOUS DMA operations, we need to reinitialize every time, 
otherwise */
-	/* setDataDescriptor will keep trying to append onto the end. */
-
-	if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-				  devAttr->ring.physAddr,
-				  devAttr->ring.bytesAllocated,
-				  numDescriptors) < 0) {
-		printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-		return -EINVAL;
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData1, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData2, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* You should use dma_start_transfer rather than dma_transfer_xxx so 
we don't */
-	/* try to make the 'prev' variables right. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_start_transfer);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	dmacHw_stopTransfer(channel->dmacHwHandle);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_stop_transfer);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	dmacHw_TRANSFER_STATUS_e status;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	while ((status =
-		dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-	       dmacHw_TRANSFER_STATUS_BUSY) {
-		;
-	}
-
-	if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-		printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-		return -EIO;
-	}
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_wait_transfer_done);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* We keep track of the information about the previous request for this */
-	/* device, and if the attributes match, then we can use the 
descriptors we setup */
-	/* the last time, and not have to reinitialize everything. */
-
-	{
-		rc =
-		     dma_alloc_descriptors(handle, transferType, srcData,
-					   dstData, numBytes);
-		if (rc != 0) {
-			return rc;
-		}
-	}
-
-	/* And kick off the transfer */
-
-	devAttr->numBytes = numBytes;
-	devAttr->transferStartTime = timer_get_tick_count();
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_transfer);
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-	unsigned long flags;
-
-	if (!IsDeviceValid(dev)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-	local_irq_save(flags);
-
-	devAttr->userData = userData;
-	devAttr->devHandler = devHandler;
-
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c 
b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad73..0000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-	[DMA_DEVICE_MEM_TO_MEM] =	/* MEM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-mem",
-	 .config = {
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-
-		    },
-	 },
-	[DMA_DEVICE_VPM_MEM_TO_MEM] =	/* VPM */
-	{
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-	 .name = "vpm",
-	 .dedicatedController = 0,
-	 .dedicatedChannel = 0,
-	 /* reserve DMA0:0 for VPM */
-	 },
-	[DMA_DEVICE_NAND_MEM_TO_MEM] =	/* NAND */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "nand",
-	 .config = {
-		    .srcPeripheralPort = 0,
-		    .dstPeripheralPort = 0,
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-		    },
-	 },
-	[DMA_DEVICE_PIF_MEM_TO_DEV] =	/* PIF TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_tx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    /* dstPeripheralPort          = 5 or 14 */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_PIF_DEV_TO_MEM] =	/* PIF RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-	 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_rx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    /* srcPeripheralPort          = 5 or 14 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_DEV_TO_MEM] =	/* I2S RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_rx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: I2S0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_MEM_TO_DEV] =	/* I2S TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: I2S0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_DEV_TO_MEM] =	/* I2S1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: I2S1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_MEM_TO_DEV] =	/* I2S1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: I2S1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_ESW_MEM_TO_DEV] =	/* ESW TX */
-	{
-	 .name = "esw_tx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 3,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: ESW (MTP) */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x30490010,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_ESW_DEV_TO_MEM] =	/* ESW RX */
-	{
-	 .name = "esw_rx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 2,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: ESW (PTM) */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x30480010,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =	/* APM Codec A Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =	/* APM Codec A Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: Codec A Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =	/* APM Codec B Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec B Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =	/* APM Codec B Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 5,	/* DST: Codec B Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =	/* APM Codec C Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "apm_c_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec C Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =	/* PCM0 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_rx",
-	 .config = {
-		    .srcPeripheralPort = 12,	/* SRC: PCM0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =	/* PCM0 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 13,	/* DST: PCM0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =	/* PCM1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_rx",
-	 .config = {
-		    .srcPeripheralPort = 14,	/* SRC: PCM1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =	/* PCM1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 15,	/* DST: PCM1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_DEV_TO_MEM] =	/* SPUM RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_rx",
-	 .config = {
-		    .srcPeripheralPort = 6,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    /* on the RX side, SPU needs to be the flow controller */
-		    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_MEM_TO_DEV] =	/* SPUM TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 7,	/* DST: SPUM */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_MEM_TO_VRAM] =	/* MEM 2 VRAM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-vram",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-	[DMA_DEVICE_VRAM_TO_MEM] =	/* VRAM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "vram-to-mem",
-	 .config = {
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);	/* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h 
b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da87..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY 
CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h 
b/arch/arm/mach-bcmring/include/cfg_global_defines.h
deleted file mode 100644
index b5beb0b..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-
-/* CHIP */
-#define BCM1103 1
-
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h 
b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e5..0000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h 
b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d803..0000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use 
the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h 
b/arch/arm/mach-bcmring/include/csp/dmacHw.h
deleted file mode 100644
index e6a1dc4..0000000
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-
-#include <stddef.h>
-
-#include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
-
-/* Define DMA Channel ID using DMA controller number (m) and channel 
number (c).
-
-   System specific channel ID should be defined as follows
-
-   For example:
-
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-
-typedef enum {
-	dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,	/* 
Channel priority 0. Lowest priority DMA channel */
-	dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,	/* 
Channel priority 1 */
-	dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,	/* 
Channel priority 2 */
-	dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,	/* 
Channel priority 3 */
-	dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,	/* 
Channel priority 4 */
-	dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,	/* 
Channel priority 5 */
-	dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,	/* 
Channel priority 6 */
-	dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7	/* Channel 
priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-
-/* Source destination master interface */
-typedef enum {
-	dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,	/* Source DMA 
master interface 1 */
-	dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,	/* Source DMA 
master interface 2 */
-	dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,	/* Destination 
DMA master interface 1 */
-	dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2	/* Destination 
DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-
-typedef enum {
-	dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8,	/* 
Source 8 bit  (1 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,	/* 
Source 16 bit (2 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,	/* 
Source 32 bit (4 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,	/* 
Source 64 bit (8 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8,	/* 
Destination 8 bit  (1 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,	/* 
Destination 16 bit (2 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,	/* 
Destination 32 bit (4 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64	/* 
Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-
-typedef enum {
-	dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,	/* Source No 
burst */
-	dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,	/* Source 4  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,	/* Source 8  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,	/* Source 16 
X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,	/* Destination 
No burst */
-	dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,	/* Destination 
4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,	/* Destination 
8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16	/* Destination 
16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-
-typedef enum {
-	dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,	/* 
Memory to memory transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, 
/* Peripheral to memory transfer */
-	dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, 
/* Memory to peripheral transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = 
dmacHw_REG_CTL_TTFC_PP_DMAC	/* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-
-typedef enum {
-	dmacHw_TRANSFER_MODE_PERREQUEST,	/* Block transfer per DMA request */
-	dmacHw_TRANSFER_MODE_CONTINUOUS,	/* Continuous transfer of streaming 
data */
-	dmacHw_TRANSFER_MODE_PERIODIC	/* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-
-typedef enum {
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,	/* 
Increment source address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,	/* 
Decrement source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,	/* 
Increment destination address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,	/* 
Decrement destination address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,	/* No 
change in source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC	/* No 
change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-
-typedef enum {
-	dmacHw_FLOW_CONTROL_DMA,	/* DMA working as flow controller (default) */
-	dmacHw_FLOW_CONTROL_PERIPHERAL	/* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-
-typedef enum {
-	dmacHw_TRANSFER_STATUS_BUSY,	/* DMA Transfer ongoing */
-	dmacHw_TRANSFER_STATUS_DONE,	/* DMA Transfer completed */
-	dmacHw_TRANSFER_STATUS_ERROR	/* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_DISABLE,	/* Interrupt disable  */
-	dmacHw_INTERRUPT_ENABLE	/* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_STATUS_NONE = 0x0,	/* No DMA interrupt */
-	dmacHw_INTERRUPT_STATUS_TRANS = 0x1,	/* End of DMA transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,	/* End of block transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_ERROR = 0x4	/* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,	/* Number of DMA channel */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,	/* Maximum channel 
burst size */
-	dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,	/* Number of DMA master 
interface */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,	/* Channel Data bus width */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE	/* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-
-typedef unsigned long dmacHw_HANDLE_t;	/* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;	/* DMA channel Id.  Must be created using
-				   "dmacHw_MAKE_CHANNEL_ID" macro
-				 */
-/* DMA channel configuration parameters */
-typedef struct {
-	uint32_t srcPeripheralPort;	/* Source peripheral port */
-	uint32_t dstPeripheralPort;	/* Destination peripheral port */
-	uint32_t srcStatusRegisterAddress;	/* Source status register address */
-	uint32_t dstStatusRegisterAddress;	/* Destination status register 
address of type  */
-
-	uint32_t srcGatherWidth;	/* Number of bytes gathered before successive 
gather opearation */
-	uint32_t srcGatherJump;	/* Number of bytes jumpped before successive 
gather opearation */
-	uint32_t dstScatterWidth;	/* Number of bytes sacattered before 
successive scatter opearation */
-	uint32_t dstScatterJump;	/* Number of bytes jumpped  before successive 
scatter opearation */
-	uint32_t maxDataPerBlock;	/* Maximum number of bytes to be transferred 
per block/descrptor.
-					   0 = Maximum possible.
-					 */
-
-	dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate;	/* Source address update mode */
-	dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate;	/* Destination address update 
mode */
-	dmacHw_TRANSFER_TYPE_e transferType;	/* DMA transfer type  */
-	dmacHw_TRANSFER_MODE_e transferMode;	/* DMA transfer mode */
-	dmacHw_MASTER_INTERFACE_e srcMasterInterface;	/* DMA source interface  */
-	dmacHw_MASTER_INTERFACE_e dstMasterInterface;	/* DMA destination 
interface */
-	dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;	/* Source 
transaction width   */
-	dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;	/* Destination 
transaction width */
-	dmacHw_BURST_WIDTH_e srcMaxBurstWidth;	/* Source burst width */
-	dmacHw_BURST_WIDTH_e dstMaxBurstWidth;	/* Destination burst width */
-	dmacHw_INTERRUPT_e blockTransferInterrupt;	/* Block trsnafer interrupt */
-	dmacHw_INTERRUPT_e completeTransferInterrupt;	/* Complete DMA trsnafer 
interrupt */
-	dmacHw_INTERRUPT_e errorInterrupt;	/* Error interrupt */
-	dmacHw_CHANNEL_PRIORITY_e channelPriority;	/* Channel priority */
-	dmacHw_FLOW_CONTROL_e flowControler;	/* Data flow controller */
-} dmacHw_CONFIG_t;
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel 
handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/*  [ IN ] Number of 
descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel 
handle  */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			     void *pSrcAddr,	/*  [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*  [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*  [ IN ] Length in bytes   */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				uint32_t ctlAddress,	/*  [ IN ] Address of the device control 
register  */
-				uint32_t control	/*  [ IN ] Device control information */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle    */
-			       dmacHw_CONFIG_t *pConfig,	/*  [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			       void **ppBbuf,	/*  [ OUT ] Data received */
-			       size_t *pLlen	/*  [ OUT ] Length of the data received */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*  [ IN ] 
DMA Channel handle   */
-				     dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-				     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				     uint32_t srcAddr,	/*  [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*  [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*  [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*  [ IN ] Number of descriptor to set */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-		   void (*fpFree) (void *)	/*  [ IN ] Function pointer to free data 
memory */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			       void *userData	/*  [ IN ] User data  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle  */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h 
b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd..0000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h 
b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8..0000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h 
b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5..0000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h 
b/arch/arm/mach-bcmring/include/csp/reg.h
deleted file mode 100644
index 56654d2..0000000
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-
-#ifndef CSP_REG_H
-#define CSP_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-
-/* Macros used to define a sequence of reserved registers. The start / 
end */
-/* are byte offsets in the particular register definition, with the 
"end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / 
sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / 
sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / 
sizeof(uint32_t)]
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-	unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-
-#else
-
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-
-#endif
-
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg &= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg |= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
-				     uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg = (*reg & mask) | value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-	*reg = value;
-}
-
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h 
b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e07..0000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-	secHw_MODE_SECURE = 0x0,	/* Switches processor into secure mode */
-	secHw_MODE_NONSECURE = 0x1	/* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t	/* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE	/* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h 
b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718b..0000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h 
b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e400..0000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h 
b/arch/arm/mach-bcmring/include/csp/tmrHw.h
deleted file mode 100644
index 2cbb530..0000000
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-
-#include <csp/stdint.h>
-
-typedef uint32_t tmrHw_ID_t;	/* Timer ID */
-typedef uint32_t tmrHw_COUNT_t;	/* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;	/* Timer interval */
-typedef uint32_t tmrHw_RATE_t;	/* Timer event (count/interrupt) rate */
-
-typedef enum {
-	tmrHw_INTERRUPT_STATUS_SET,	/* Interrupted  */
-	tmrHw_INTERRUPT_STATUS_UNSET	/* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	tmrHw_CAPABILITY_CLOCK,	/* Clock speed in HHz */
-	tmrHw_CAPABILITY_RESOLUTION	/* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer 
id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs	/*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d5..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_H
-#define CAP_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Public Constants and Types 
--------------------------------------- */
-typedef enum {
-	CAP_NOT_PRESENT = 0,
-	CAP_PRESENT
-} CAP_RC_T;
-
-typedef enum {
-	CAP_VPM,
-	CAP_ETH_PHY,
-	CAP_ETH_GMII,
-	CAP_ETH_SGMII,
-	CAP_USB,
-	CAP_TSC,
-	CAP_EHSS,
-	CAP_SDIO,
-	CAP_UARTB,
-	CAP_KEYPAD,
-	CAP_CLCD,
-	CAP_GE,
-	CAP_LEDM,
-	CAP_BBL,
-	CAP_VDEC,
-	CAP_PIF,
-	CAP_APM,
-	CAP_SPU,
-	CAP_PKA,
-	CAP_RNG,
-} CAP_CAPABILITY_T;
-
-typedef enum {
-	CAP_LCD_WVGA = 0,
-	CAP_LCD_VGA = 0x1,
-	CAP_LCD_WQVGA = 0x2,
-	CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 933ce68..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <cfg_global.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | 
CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS 
| CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | 
CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | 
CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | 
CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | 
CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | 
CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | 
CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index)
-{
-	CAP_RC_T returnVal = CAP_NOT_PRESENT;
-
-	switch (capability) {
-	case CAP_VPM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_PHY:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_GMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_SGMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_USB:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_TSC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_EHSS:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SDIO:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_UARTB:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_KEYPAD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_CLCD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_GE:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_LEDM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_BBL:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_VDEC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PIF:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_APM:
-		{
-			if ((index == 0)
-			    && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 2)
-			    && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SPU:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PKA:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_RNG:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	default:
-		{
-		}
-		break;
-	}
-	return returnVal;
-}
-
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-	return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-	return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-	return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-	return (CAP_LCD_RES_T)
-		((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-		 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 1619733..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-
-typedef uint32_t chipcHw_freq;
-
-/* Configurable miscellaneous clocks */
-typedef enum {
-	chipcHw_CLOCK_DDR,	/* DDR PHY Clock */
-	chipcHw_CLOCK_ARM,	/* ARM Clock */
-	chipcHw_CLOCK_ESW,	/* Ethernet Switch Clock */
-	chipcHw_CLOCK_VPM,	/* VPM Clock */
-	chipcHw_CLOCK_ESW125,	/* Ethernet MII Clock */
-	chipcHw_CLOCK_UART,	/* UART Clock */
-	chipcHw_CLOCK_SDIO0,	/* SDIO 0 Clock */
-	chipcHw_CLOCK_SDIO1,	/* SDIO 1 Clock */
-	chipcHw_CLOCK_SPI,	/* SPI Clock */
-	chipcHw_CLOCK_ETM,	/* ARM ETM Clock */
-
-	chipcHw_CLOCK_BUS,	/* BUS Clock */
-	chipcHw_CLOCK_OTP,	/* OTP Clock */
-	chipcHw_CLOCK_I2C,	/* I2C Host Clock */
-	chipcHw_CLOCK_I2S0,	/* I2S 0 Host Clock */
-	chipcHw_CLOCK_RTBUS,	/* DDR PHY Configuration Clock */
-	chipcHw_CLOCK_APM100,	/* APM100 Clock */
-	chipcHw_CLOCK_TSC,	/* Touch screen Clock */
-	chipcHw_CLOCK_LED,	/* LED Clock */
-
-	chipcHw_CLOCK_USB,	/* USB Clock */
-	chipcHw_CLOCK_LCD,	/* LCD CLock */
-	chipcHw_CLOCK_APM,	/* APM Clock */
-
-	chipcHw_CLOCK_I2S1,	/* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-
-/* System booting strap options */
-typedef enum {
-	chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-	chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-	    chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-	chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-
-/* System booting modes */
-typedef enum {
-	chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-	chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-	chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-	chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-
-/* NAND Flash page size strap options */
-typedef enum {
-	chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-	chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-	chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-	chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-
-/* GPIO Pin function */
-typedef enum {
-	chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-	chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-	chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-	chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-	chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-	chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-	chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-	chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-	chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-	chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-	chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-	chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-	chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-	chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-
-/* PIN Output slew rate */
-typedef enum {
-	chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-	chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-
-/* PIN Current drive strength */
-typedef enum {
-	chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-	chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-	chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-	chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-	chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-	chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-
-/* PIN Pull up register settings */
-typedef enum {
-	chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-	chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-	chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-
-/* PIN input type settings */
-typedef enum {
-	chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-	chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-	chipcHw_SPREAD_SPECTRUM_DISALLOW,	/* Spread spectrum support is not 
allowed */
-	chipcHw_SPREAD_SPECTRUM_ALLOW	/* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-
-typedef struct {
-	chipcHw_SPREAD_SPECTRUM_e ssSupport;	/* Allow/Disalow to support 
spread spectrum.
-						   If supported, call chipcHw_enableSpreadSpectrum ()
-						   to activate the spread spectrum with desired spread. */
-	uint32_t pllVcoFreqHz;	/* PLL VCO frequency in Hz */
-	uint32_t pll2VcoFreqHz;	/* PLL2 VCO frequency in Hz */
-	uint32_t busClockFreqHz;	/* Bus clock frequency in Hz */
-	uint32_t armBusRatio;	/* ARM clock : Bus clock */
-	uint32_t vpmBusRatio;	/* VPM clock : Bus clock */
-	uint32_t ddrBusRatio;	/* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-
-/* CHIP revision number */
-typedef enum {
-	chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-	chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-	chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-	chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-	chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-
-typedef enum {
-	chipcHw_DDR_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_WIDE	/*  Wider margin for DDR phase align 
condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_WIDE	/*  Wider margin for VPM phase align 
condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-
-#define chipcHw_XTAL_FREQ_Hz                    25000000	/* Reference 
clock frequency in Hz */
-
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < 
(chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-									     /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 
0)	/* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 
1)	/* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 
2)	/* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 
3)	/* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 
4)	/* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 
5)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 
6)	/* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 
7)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 
8)	/* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 
9)	/* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 
10)	/* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 
11)	/* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 
12)	/* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 
13)	/* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 
14)	/* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 
15)	/* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 
16)	/* UART Receive */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,	/*  [ IN ] VCO frequency in 
Hz */
-			chipcHw_SPREAD_SPECTRUM_e ssSupport	/*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz	/*  [ IN ] VCO frequency in 
Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock	/* 
[ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock	/* 
  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetDisable(uint64_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetEnable(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlDisable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlEnable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_OTP_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int 
pin	/* GPIO Pin number */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,	/* GPIO Pin 
number */
-					      chipcHw_GPIO_FUNCTION_e func	/* Configuration function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					  chipcHw_PIN_SLEW_RATE_e slewRate	/* Pin slew rate */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,	/* Pin of 
type chipcHw_PIN_XXXXX */
-					       chipcHw_PIN_CURRENT_STRENGTH_e curr	/* Pin current rating */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					chipcHw_PIN_PULL_e pullup	/* Pullup register settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					   chipcHw_PIN_INPUTTYPE_e inputType	/* Pin input type */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t 
vpmRatio,
-			   uint32_t ddrRatio);
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin	/* 
Margin alinging DDR  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin	/* 
Margin alinging VPM  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index 03238c2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-typedef enum {
-	chipcHw_OPTYPE_BYPASS,	/* Bypass operation */
-	chipcHw_OPTYPE_OUTPUT	/* Output operation */
-} chipcHw_OPTYPE_e;
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------- */
-/* ---- Public Function Prototypes 
---------------------------------------- */
-/* ---- Private Function Prototypes 
--------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode);
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-	return pChipcHw->ChipId;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-	if ((pChipcHw->
-	     PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-	    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-		    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-		    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-		     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-		    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-	ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-	return (pChipcHw->
-		 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
-		chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-	return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-	return pChipcHw->BusIntfClock;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-	chipcHw_softResetEnable(mask);
-	chipcHw_softResetDisable(mask);
-}
-
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	/* Deassert module soft reset */
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 ^= ctrl1;
-	pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-	uint32_t unhold = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 |= ctrl1;
-	/* Mask out unhold request bits */
-	pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-
-	/* Process unhold requests */
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-		unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-	}
-
-	if (unhold) {
-		/* Make sure unhold request is effective */
-		pChipcHw->SoftReset1 &= ~unhold;
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-	reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-	reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-	return pChipcHw->Sticky;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask & chipcHw_REG_STICKY_POR_BROM) {
-		bits |= chipcHw_REG_STICKY_POR_BROM;
-	} else {
-		uint32_t sticky;
-		sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-			bits |= chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask &
-	    (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-	     chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-	     chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-		uint32_t sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-			bits = chipcHw_REG_STICKY_BOOT_DONE;
-			mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits | mask;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-	return pChipcHw->SoftStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-	reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-	return pChipcHw->PinStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-	uint32_t softStraps;
-
-	/*
-	 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-	 ** which copies HW straps to soft straps if there is no override
-	 */
-	softStraps = chipcHw_getSoftStraps();
-
-	return softStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-	uint32_t softStraps;
-
-	REG_LOCAL_IRQ_SAVE;
-	softStraps = chipcHw_getSoftStraps();
-
-	if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-		/* Copy HW straps to software straps */
-		chipcHw_setSoftStraps(chipcHw_getPinStraps());
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-	if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-	return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
-		(chipcHw_REG_GPIO_MUX_MASK <<
-		 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
-	    chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-					      chipcHw_GPIO_FUNCTION_e func)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-	    ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-	    func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-					  chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-	    ~(chipcHw_REG_SLEW_RATE_MASK <<
-	      chipcHw_REG_SLEW_RATE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-	    (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-					       chipcHw_PIN_CURRENT_STRENGTH_e
-					       curr)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-	    ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-	    (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, 
chipcHw_PIN_PULL_e pullup)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-	    ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-	    (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-					   chipcHw_PIN_INPUTTYPE_e inputType)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-	    ~(chipcHw_REG_INPUTTYPE_MASK <<
-	      chipcHw_REG_INPUTTYPE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-	    (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain 
device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode)
-{
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			/* PLL clock output enable/disable */
-			if (mode) {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock enable is inverted */
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			} else {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock disable is inverted */
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			/* PLL clock bypass enable/disable */
-			if (mode) {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	} else if (pClockCtrl) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-
-	/* Disable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-
-	/* Enable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-	/* Enable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-	/* Disable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-
-}
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-	return pChipcHw->SoftStraps & 0x00000001;
-}
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-	reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-	reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig2,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig2,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-	return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-	return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig2 |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-	REG_LOCAL_IRQ_SAVE;
-	if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	} else {
-		pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	}
-	pChipcHw->VPMPhaseCtrl2 =
-	    (pChipcHw->
-	     VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-			       chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->DDRPhaseCtrl1 &=
-		    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->DDRPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMPhaseCtrl1 &=
-		    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->VPMPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &=
-	    ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->DDRPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &=
-	    ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->VPMPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_ddrHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_vpmHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index b162448..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-
-typedef struct {
-	uint32_t ChipId;	/* Chip ID */
-	uint32_t DDRClock;	/* PLL1 Channel 1 for DDR clock */
-	uint32_t ARMClock;	/* PLL1 Channel 2 for ARM clock */
-	uint32_t ESWClock;	/* PLL1 Channel 3 for ESW system clock */
-	uint32_t VPMClock;	/* PLL1 Channel 4 for VPM clock */
-	uint32_t ESW125Clock;	/* PLL1 Channel 5 for ESW 125MHz clock */
-	uint32_t UARTClock;	/* PLL1 Channel 6 for UART clock */
-	uint32_t SDIO0Clock;	/* PLL1 Channel 7 for SDIO 0 clock */
-	uint32_t SDIO1Clock;	/* PLL1 Channel 8 for SDIO 1 clock */
-	uint32_t SPIClock;	/* PLL1 Channel 9 for SPI master Clock  */
-	uint32_t ETMClock;	/* PLL1 Channel 10 for ARM ETM Clock  */
-
-	uint32_t ACLKClock;	/* ACLK Clock (Divider) */
-	uint32_t OTPClock;	/* OTP Clock  (Divider) */
-	uint32_t I2CClock;	/* I2C Clock (CK_13m) (Divider) */
-	uint32_t I2S0Clock;	/* I2S0 Clock (Divider) */
-	uint32_t RTBUSClock;	/* RTBUS (DDR PHY Config.) Clock (Divider) */
-	uint32_t pad1;
-	uint32_t APM100Clock;	/* APM 100MHz CLK Clock (Divider) */
-	uint32_t TSCClock;	/* TSC Clock (Divider) */
-	uint32_t LEDClock;	/* LED Clock (Divider) */
-
-	uint32_t USBClock;	/* PLL2 Channel 1 for USB clock */
-	uint32_t LCDClock;	/* PLL2 Channel 2 for LCD clock */
-	uint32_t APMClock;	/* PLL2 Channel 3 for APM 200 MHz clock */
-
-	uint32_t BusIntfClock;	/* Bus interface clock */
-
-	uint32_t PLLStatus;	/* PLL status register (PLL1) */
-	uint32_t PLLConfig;	/* PLL configuration register  (PLL1) */
-	uint32_t PLLPreDivider;	/* PLL pre-divider control register (PLL1) */
-	uint32_t PLLDivider;	/* PLL divider control register (PLL1) */
-	uint32_t PLLControl1;	/* PLL analog control register #1 (PLL1) */
-	uint32_t PLLControl2;	/* PLL analog control register #2 (PLL1) */
-
-	uint32_t I2S1Clock;	/* I2S1 Clock  */
-	uint32_t AudioEnable;	/* Enable/ disable audio channel */
-	uint32_t SoftReset1;	/* Reset blocks */
-	uint32_t SoftReset2;	/* Reset blocks */
-	uint32_t Spare1;	/* Phase align interrupts */
-	uint32_t Sticky;	/* Sticky bits */
-	uint32_t MiscCtrl;	/* Misc. control */
-	uint32_t pad3[3];
-
-	uint32_t PLLStatus2;	/* PLL status register (PLL2) */
-	uint32_t PLLConfig2;	/* PLL configuration register  (PLL2) */
-	uint32_t PLLPreDivider2;	/* PLL pre-divider control register (PLL2) */
-	uint32_t PLLDivider2;	/* PLL divider control register (PLL2) */
-	uint32_t PLLControl12;	/* PLL analog control register #1 (PLL2) */
-	uint32_t PLLControl22;	/* PLL analog control register #2 (PLL2) */
-
-	uint32_t DDRPhaseCtrl1;	/* DDR Clock Phase Alignment control1 */
-	uint32_t VPMPhaseCtrl1;	/* VPM Clock Phase Alignment control1 */
-	uint32_t PhaseAlignStatus;	/* DDR/VPM Clock Phase Alignment Status */
-	uint32_t PhaseCtrlStatus;	/* DDR/VPM Clock HW DDR/VPM ph_ctrl and 
load_ch Status */
-	uint32_t DDRPhaseCtrl2;	/* DDR Clock Phase Alignment control2 */
-	uint32_t VPMPhaseCtrl2;	/* VPM Clock Phase Alignment control2 */
-	uint32_t pad4[9];
-
-	uint32_t SoftOTP1;	/* Software OTP control */
-	uint32_t SoftOTP2;	/* Software OTP control */
-	uint32_t SoftStraps;	/* Software strap */
-	uint32_t PinStraps;	/* Pin Straps */
-	uint32_t DiffOscCtrl;	/* Diff oscillator control */
-	uint32_t DiagsCtrl;	/* Diagnostic control */
-	uint32_t DiagsOutputCtrl;	/* Diagnostic output enable */
-	uint32_t DiagsReadBackCtrl;	/* Diagnostic read back control */
-
-	uint32_t LcdPifMode;	/* LCD/PIF Pin Sharing MUX Mode */
-
-	uint32_t GpioMux_0_7;	/* Pin Sharing MUX0 Control */
-	uint32_t GpioMux_8_15;	/* Pin Sharing MUX1 Control */
-	uint32_t GpioMux_16_23;	/* Pin Sharing MUX2 Control */
-	uint32_t GpioMux_24_31;	/* Pin Sharing MUX3 Control */
-	uint32_t GpioMux_32_39;	/* Pin Sharing MUX4 Control */
-	uint32_t GpioMux_40_47;	/* Pin Sharing MUX5 Control */
-	uint32_t GpioMux_48_55;	/* Pin Sharing MUX6 Control */
-	uint32_t GpioMux_56_63;	/* Pin Sharing MUX7 Control */
-
-	uint32_t GpioSR_0_7;	/* Slew rate for GPIO 0 - 7 */
-	uint32_t GpioSR_8_15;	/* Slew rate for GPIO 8 - 15 */
-	uint32_t GpioSR_16_23;	/* Slew rate for GPIO 16 - 23 */
-	uint32_t GpioSR_24_31;	/* Slew rate for GPIO 24 - 31 */
-	uint32_t GpioSR_32_39;	/* Slew rate for GPIO 32 - 39 */
-	uint32_t GpioSR_40_47;	/* Slew rate for GPIO 40 - 47 */
-	uint32_t GpioSR_48_55;	/* Slew rate for GPIO 48 - 55 */
-	uint32_t GpioSR_56_63;	/* Slew rate for GPIO 56 - 63 */
-	uint32_t MiscSR_0_7;	/* Slew rate for MISC 0 - 7 */
-	uint32_t MiscSR_8_15;	/* Slew rate for MISC 8 - 15 */
-
-	uint32_t GpioPull_0_15;	/* Pull up registers for GPIO 0 - 15 */
-	uint32_t GpioPull_16_31;	/* Pull up registers for GPIO 16 - 31 */
-	uint32_t GpioPull_32_47;	/* Pull up registers for GPIO 32 - 47 */
-	uint32_t GpioPull_48_63;	/* Pull up registers for GPIO 48 - 63 */
-	uint32_t MiscPull_0_15;	/* Pull up registers for MISC 0 - 15 */
-
-	uint32_t GpioInput_0_31;	/* Input type for GPIO 0 - 31 */
-	uint32_t GpioInput_32_63;	/* Input type for GPIO 32 - 63 */
-	uint32_t MiscInput_0_15;	/* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
-
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000	/* 
Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001	/* 
PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008	/* 
Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004	/* 
Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020	/* 
Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010	/* 
Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001	/* 
Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000	/* 
1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000	/* 
VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080	/* 
VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000	/* 
PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000	/* 
Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000	/* 
Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000	/* 
Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000	/* 
PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000	/* 
Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000	/* 
Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000	/* 
Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00	/* 
Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF	/* 
Clock post divider mask
-
-									   00000000 = divide-by-256
-									   00000001 = divide-by-1
-									   00000010 = divide-by-2
-									   00000011 = divide-by-3
-									   00000100 = divide-by-4
-									   00000101 = divide-by-5
-									   00000110 = divide-by-6
-									   .
-									   .
-									   11111011 = divide-by-251
-									   11111100 = divide-by-252
-									   11111101 = divide-by-253
-									   11111110 = divide-by-254
-									 */
-
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000	/* 
NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000	/* 
NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF	/* 
NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000	/* 
NON-PLL clock post-divide by 256 */
-
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000	/* 
Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000	/* 
Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000	/* 
MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000	/* 
MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000	/* 
MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000	/* 
MFB Sigma-Delta Modulator 1/8 Mode */
-
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / 
chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF	/* 
Fractional divider */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)	/* 
To attain spread with max frequency */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0	/* ndiv_frac 
= chipcHw_REG_PLL_DIVIDER_NDIV_f /
-								   chipcHw_REG_PLL_DIVIDER_FRAC
-								   = 0, when SS is disable
-								 */
-
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) 
((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001	/* 
Software Strap Override */
-
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000	/* 8 
bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002	/* 
16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004	/* 
Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006	/* 
16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008	/* 
UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E	/* 
Mask */
-
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000	/* 
Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020	/* 
Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030	/* 
Boot from NOR flash */
-
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000	/* 
NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040	/* 
NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080	/* 
NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0	/* 
NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0	/* 
Mask */
-
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400	/* 
NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800	/* 
Reboot to UART on error */
-
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000	/* 
Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100	/* 
Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200	/* 
Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300	/* 
Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300	/* 
Mask */
-
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000	/* 
I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000	/* 
SPI Slave  */
-
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS 
((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001	/* 
LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002	/* 
LCD pins are used to perform PIF functions  */
-
-#define chipcHw_GPIO_COUNT                              61	/* Number of 
GPIO pin accessible thorugh CHIPC */
-
-/* NOTE: Any changes to these constants will require a corresponding 
change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001	/* 
GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002	/* 
GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003	/* 
GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004	/* 
GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005	/* 
GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006	/* 
GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007	/* 
GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008	/* 
GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009	/* 
GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A	/* 
GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B	/* 
GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C	/* 
GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D	/* 
GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000	/* 
GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin) 
(&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 
0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F	/* 
Mask */
-
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000	/* 
High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008	/* 
Normal slew rate */
-							/* Pins beyond 42 are defined by skipping 8 bits within the 
register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008	/* 
Mask */
-
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001	/* 
Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002	/* 
Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004	/* 
Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005	/* 
Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006	/* 
Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007	/* 
Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-
-#define chipcHw_REG_PULL_NONE                           0x00000000	/* 
No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001	/* 
Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002	/* 
Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? 
(&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : 
(&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? 
((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000	/* 
Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001	/* 
High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : 
(&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001	/* 
Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002	/* 
Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004	/* 
Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008	/* 
Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010	/* 
Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020	/* 
Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040	/* 
Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080	/* 
Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100	/* 
Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200	/* 
Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400	/* 
Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800	/* 
Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000	/* 
Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000	/* 
Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000	/* 
Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000	/* 
Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000	/* 
Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000	/* 
Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000	/* 
Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000	/* 
Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000	/* 
Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000	/* 
Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000	/* 
Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000	/* 
Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000	/* 
Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000	/* 
Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000	/* 
Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000	/* 
Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000	/* 
Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000	/* 
Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000	/* 
Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000	/* 
Bus interface clock for Touch screen */
-
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 
0x0000000080000000ULL	/* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD 
0x0000000040000000ULL	/* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 
0x0000000020000000ULL	/* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM 
0x0000000010000000ULL	/* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD 
0x0000000008000000ULL	/* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED 
0x0000000004000000ULL	/* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU 
0x0000000002000000ULL	/* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG 
0x0000000001000000ULL	/* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA 
0x0000000000800000ULL	/* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD 
0x0000000000400000ULL	/* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF 
0x0000000000200000ULL	/* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS 
0x0000000000100000ULL	/* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH 
0x0000000000080000ULL	/* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1 
0x0000000000040000ULL	/* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0 
0x0000000000020000ULL	/* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL 
0x0000000000010000ULL	/* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1 
0x0000000000008000ULL	/* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0 
0x0000000000004000ULL	/* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS 
0x0000000000002000ULL	/* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH 
0x0000000000001000ULL	/* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1 
0x0000000000000800ULL	/* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0 
0x0000000000000400ULL	/* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1 
0x0000000000000200ULL	/* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0 
0x0000000000000100ULL	/* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI 
0x0000000000000080ULL	/* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG 
0x0000000000000040ULL	/* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR 
0x0000000000000020ULL	/* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM 
0x0000000000000010ULL	/* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD 
0x0000000000000008ULL	/* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM 
0x0000000000000004ULL	/* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM 
0x0000000000000002ULL	/* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 
0x0000000000000001ULL	/* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC 
0x0000100000000000ULL	/* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE 
0x0000080000000000ULL	/* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP 
0x0000040000000000ULL	/* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2 
0x0000020000000000ULL	/* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1 
0x0000010000000000ULL	/* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB 
0x0000008000000000ULL	/* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW 
0x0000004000000000ULL	/* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK 
0x0000002000000000ULL	/* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY 
0x0000001000000000ULL	/* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR 
0x0000000800000000ULL	/* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC 
0x0000000400000000ULL	/* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM 
0x0000000200000000ULL	/* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM 
0x0000200100000000ULL	/* Reset APM device */
-
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 
0x8000000000000000ULL	/* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 
0x4000000000000000ULL	/* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 
0x2000000000000000ULL	/* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 
0xF000000000000000ULL	/* Mask to handle unhold request */
-
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001	/* 
Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002	/* 
Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004	/* 
Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008	/* 
Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010	/* 
Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020	/* 
Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040	/* 
Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080	/* 
Enable APM clock */
-
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000	/* 
Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000	/* 
Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000	/* 
Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000	/* 
Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008	/* 
Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004	/* 
Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002	/* 
Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD	/* 
Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE	/* 
Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001	/* 
Power down USB */
-
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF 
0x0000020000000000ULL	/* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW 
0x0000010000000000ULL	/* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED 
0x0000000600000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1 
0x0000000100000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0 
0x0000000080000000ULL	/* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED 
0x0000000060000000ULL	/* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE 
0x000000001F000000ULL	/* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE 
0x0000000000200000ULL	/* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE 
0x0000000000100000ULL	/* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE 
0x0000000000080000ULL	/* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE 
0x0000000000040000ULL	/* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE 
0x0000000000020000ULL	/* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE 
0x0000000000010000ULL	/* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE 
0x0000000000008000ULL	/* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE 
0x0000000000004000ULL	/* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE 
0x0000000000003000ULL	/* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE 
0x0000000000000C00ULL	/* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE 
0x0000000000000200ULL	/* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE 
0x0000000000000180ULL	/* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE 
0x0000000000000060ULL	/* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE 
0x0000000000000018ULL	/* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE 
0x0000000000000006ULL	/* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE 
0x0000000000000001ULL	/* Disable VPM */
-
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001	/* 
Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002	/* 
ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004	/* 
General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008	/* 
General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010	/* 
General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020	/* 
General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040	/* 
General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080	/* 
Special sticky bit for security - set in BROM to avoid other modes being 
entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100	/* 
ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200	/* 
Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400	/* 
Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800	/* 
Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000	/* 
OTP reset */
-
-							/* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000	/* 
Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000	/* 
Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002	/* 
Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001	/* 
Enable access to DDR using system BUS */
-							/* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F	/* 
DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F	/* 
DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F	/* 
VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F	/* 
VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000	/* 
DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F	/* 
DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000	/* 
DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000	/* 
Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F	/* 
DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000	/* 
VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F	/* 
VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080	/* 
VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040	/* 
Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F	/* 
VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-							/* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-							/* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003	/* 
Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h 
b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index f1b68e2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/reg.h>
-#include <csp/stdint.h>
-
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t memcStatus;
-		uint32_t memcCmd;
-		uint32_t directCmd;
-		uint32_t memoryCfg;
-		uint32_t refreshPrd;
-		uint32_t casLatency;
-		uint32_t writeLatency;
-		uint32_t tMrd;
-		uint32_t tRas;
-		uint32_t tRc;
-		uint32_t tRcd;
-		uint32_t tRfc;
-		uint32_t tRp;
-		uint32_t tRrd;
-		uint32_t tWr;
-		uint32_t tWtr;
-		uint32_t tXp;
-		uint32_t tXsr;
-		uint32_t tEsr;
-		uint32_t memoryCfg2;
-		uint32_t memoryCfg3;
-		uint32_t tFaw;
-	} ddrcReg_CTLR_MEMC_REG_t;
-
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile 
ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_MEMC_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << 
ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)	/* 
@note Not supported in PL341 */
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << 
ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << 
ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << 
ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << 
ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << 
ddrcReg_CTLR_T_MRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << 
ddrcReg_CTLR_T_RAS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << 
ddrcReg_CTLR_T_RC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << 
ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << 
ddrcReg_CTLR_T_RCD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << 
ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << 
ddrcReg_CTLR_T_RFC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << 
ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << 
ddrcReg_CTLR_T_RP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << 
ddrcReg_CTLR_T_RRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << 
ddrcReg_CTLR_T_WR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << 
ddrcReg_CTLR_T_WTR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << 
ddrcReg_CTLR_T_XP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << 
ddrcReg_CTLR_T_XSR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << 
ddrcReg_CTLR_T_ESR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << 
ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << 
ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << 
ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX 
(ddrcReg_CTLR_QOS_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-	} ddrcReg_CTLR_QOS_REG_t;
-
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile 
ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << 
ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << 
ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX 
(ddrcReg_CTLR_CHIP_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-	} ddrcReg_CTLR_CHIP_REG_t;
-
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile 
ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-
-	typedef struct {
-		uint32_t input;
-		uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-		uint32_t feature;
-	} ddrcReg_CTLR_USER_REG_t;
-
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile 
ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << 
ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << 
ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t pmCtl;
-		 REG32_RSVD(0x0008, 0x0010);
-		uint32_t pllStatus;
-		uint32_t pllCfg;
-		uint32_t pllPreDiv;
-		uint32_t pllDiv;
-		uint32_t pllCtl1;
-		uint32_t pllCtl2;
-		uint32_t ssCtl;
-		uint32_t ssCfg;
-		uint32_t vdlStatic;
-		uint32_t vdlDynamic;
-		uint32_t padIdle;
-		uint32_t pvtComp;
-		uint32_t padDrive;
-		uint32_t clkRgltrCtl;
-	} ddrcReg_PHY_ADDR_CTL_REG_t;
-
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile 
ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-
-/* @todo These SS definitions are duplicates of ones below */
-
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10	/* Higher 
the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX 
(ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t vdlCalibrate;
-		uint32_t vdlStatus;
-		 REG32_RSVD(0x000c, 0x0010);
-		uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-		uint32_t readCtl;
-		uint32_t readStatus;
-		uint32_t readClear;
-		uint32_t padIdleCtl;
-		uint32_t padDriveCtl;
-		uint32_t padClkCtl;
-		uint32_t writeCtl;
-		uint32_t clkRegCtl;
-	} ddrcReg_PHY_BYTE_LANE_REG_t;
-
-/* There are 2 instances of the byte Lane registers, one for each byte 
lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-
-/* ----------------------------------------------------- */
-
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step 
value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 
in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some 
definitions for just */
-/* the step setting to simplify things. */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << 
ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << 
ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u 
<< 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 
<< 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 
<< 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 
<< 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 
<< 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 
<< 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 
<< 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 
<< 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 
<< 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 
<< 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 
<< 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 
<< 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 
<< 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 
<< 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 
<< 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 
<< 0)
-
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-
-	typedef struct {
-		uint32_t cfg;
-		uint32_t actMonCnt;
-		uint32_t ctl;
-		uint32_t lbistCtl;
-		uint32_t lbistSeed;
-		uint32_t lbistStatus;
-		uint32_t tieOff;
-		uint32_t actMonClear;
-		uint32_t status;
-		uint32_t user;
-	} ddrcReg_CTLR_PHY_GLUE_REG_t;
-
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP 
((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_PHY_GLUE_OFFSET))
-
-/* ----------------------------------------------------- */
-
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-
-/* Software control of PHY VDL updates from control register settings. 
Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a 
refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control 
must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-
-/* Use these to bypass a pipeline stage. By default the ADDR is off but 
the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE 
(1 << 12)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f 
<< ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#ifdef __cplusplus
-}				/* end extern "C" */
-#endif
-#endif				/* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index d67e2f8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-
-#include <csp/stdint.h>
-
-/* Data type for DMA Link List Item */
-typedef struct {
-	uint32_t sar;		/* Source Address Register.
-				   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-	uint32_t dar;		/* Destination Address Register.
-				   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-	uint32_t llpPhy;	/* LLP contains the physical address of the next 
descriptor for block chaining using linked lists.
-				   Address MUST be aligned to a 32-bit boundary.             */
-	dmacHw_REG64_t ctl;	/* Control Register. 64 bits */
-	uint32_t sstat;		/* Source Status Register */
-	uint32_t dstat;		/* Destination Status Register */
-	uint32_t devCtl;	/* Device specific control information */
-	uint32_t llp;		/* LLP contains the virtual address of the next 
descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-	int num;		/* Number of link items */
-	dmacHw_DESC_t *pHead;	/* Head of descriptor ring (for writing) */
-	dmacHw_DESC_t *pTail;	/* Tail of descriptor ring (for reading) */
-	dmacHw_DESC_t *pProg;	/* Descriptor to program the channel (for 
programming the channel register) */
-	dmacHw_DESC_t *pEnd;	/* End of current descriptor chain */
-	dmacHw_DESC_t *pFree;	/* Descriptor to free memory (freeing dynamic 
memory) */
-	uint32_t virt2PhyOffset;	/* Virtual to physical address offset for the 
descriptor ring */
-} dmacHw_DESC_RING_t;
-
-/*
- *  DMA channel control block
- */
-typedef struct {
-	uint32_t module;	/* DMA controller module (0-1) */
-	uint32_t channel;	/* DMA channel (0-7) */
-	volatile uint32_t varDataStarted;	/* Flag indicating variable data 
channel is enabled */
-	volatile uint32_t descUpdated;	/* Flag to indicate descriptor update 
is complete */
-	void *userData;		/* Channel specifc user data */
-} dmacHw_CBLK_t;
-
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t 
*)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) == 
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == 
dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e 
dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw	/*   [ IN ] Current 
transaction width */
-    ) {
-	if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-	} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-	}
-
-	/* Default return  */
-	return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e 
tw	/*   [ IN ]  Transaction width */
-    ) {
-	int width = 1;
-	switch (tw) {
-	case dmacHw_SRC_TRANSACTION_WIDTH_8:
-		width = 1;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_16:
-	case dmacHw_DST_TRANSACTION_WIDTH_16:
-		width = 2;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_32:
-	case dmacHw_DST_TRANSACTION_WIDTH_32:
-		width = 4;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_64:
-	case dmacHw_DST_TRANSACTION_WIDTH_64:
-		width = 8;
-		break;
-	default:
-		dmacHw_ASSERT(0);
-	}
-
-	/* Default transaction width */
-	return width;
-}
-
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index f1ecf96..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-
-/* Data type for 64 bit little endian register */
-typedef struct {
-	volatile uint32_t lo;	/* Lower 32 bit in little endian mode */
-	volatile uint32_t hi;	/* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-
-/* Data type representing DMA channel registers */
-typedef struct {
-	dmacHw_REG64_t ChannelSar;	/*  Source Address Register. 64 bits (upper 
32 bits are reserved)
-					   Address must be aligned to CTLx.SRC_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelDar;	/*  Destination Address Register.64 bits 
(upper 32 bits are reserved)
-					   Address must be aligned to CTLx.DST_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelLlp;	/*  Link List Pointer.64 bits (upper 32 
bits are reserved)
-					   LLP contains the pointer to the next LLI for block chaining 
using linked lists.
-					   If LLPis set to 0x0, then transfers using linked lists are not 
enabled.
-					   Address MUST be aligned to a 32-bit boundary.
-					 */
-	dmacHw_REG64_t ChannelCtl;	/* Control Register. 64 bits */
-	dmacHw_REG64_t ChannelSstat;	/* Source Status Register */
-	dmacHw_REG64_t ChannelDstat;	/* Destination Status Register */
-	dmacHw_REG64_t ChannelSstatAddr;	/* Source Status Address Register */
-	dmacHw_REG64_t ChannelDstatAddr;	/* Destination Status Address Register */
-	dmacHw_REG64_t ChannelConfig;	/* Channel Configuration Register */
-	dmacHw_REG64_t SrcGather;	/* Source gather register */
-	dmacHw_REG64_t DstScatter;	/* Destination scatter register */
-} dmacHw_CH_REG_t;
-
-/* Data type for RAW interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t RawTfr;	/* Raw Status for IntTfr Interrupt */
-	dmacHw_REG64_t RawBlock;	/* Raw Status for IntBlock Interrupt */
-	dmacHw_REG64_t RawSrcTran;	/* Raw Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t RawDstTran;	/* Raw Status for IntDstTran Interrupt */
-	dmacHw_REG64_t RawErr;	/* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-
-/* Data type for interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t StatusTfr;	/* Status for IntTfr Interrupt */
-	dmacHw_REG64_t StatusBlock;	/* Status for IntBlock Interrupt */
-	dmacHw_REG64_t StatusSrcTran;	/* Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t StatusDstTran;	/* Status for IntDstTran Interrupt */
-	dmacHw_REG64_t StatusErr;	/* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-
-/* Data type for interrupt mask registers*/
-typedef struct {
-	dmacHw_REG64_t MaskTfr;	/* Mask for IntTfr Interrupt */
-	dmacHw_REG64_t MaskBlock;	/* Mask for IntBlock Interrupt */
-	dmacHw_REG64_t MaskSrcTran;	/* Mask for IntSrcTran Interrupt */
-	dmacHw_REG64_t MaskDstTran;	/* Mask for IntDstTran Interrupt */
-	dmacHw_REG64_t MaskErr;	/* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-
-/* Data type for interrupt clear registers */
-typedef struct {
-	dmacHw_REG64_t ClearTfr;	/* Clear for IntTfr Interrupt */
-	dmacHw_REG64_t ClearBlock;	/* Clear for IntBlock Interrupt */
-	dmacHw_REG64_t ClearSrcTran;	/* Clear for IntSrcTran Interrupt */
-	dmacHw_REG64_t ClearDstTran;	/* Clear for IntDstTran Interrupt */
-	dmacHw_REG64_t ClearErr;	/* Clear for IntErr Interrupt */
-	dmacHw_REG64_t StatusInt;	/* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-
-/* Data type for software handshaking registers */
-typedef struct {
-	dmacHw_REG64_t ReqSrcReg;	/* Source Software Transaction Request 
Register */
-	dmacHw_REG64_t ReqDstReg;	/* Destination Software Transaction Request 
Register */
-	dmacHw_REG64_t SglReqSrcReg;	/* Single Source Transaction Request 
Register */
-	dmacHw_REG64_t SglReqDstReg;	/* Single Destination Transaction Request 
Register */
-	dmacHw_REG64_t LstSrcReg;	/* Last Source Transaction Request Register */
-	dmacHw_REG64_t LstDstReg;	/* Last Destination Transaction Request 
Register */
-} dmacHw_SW_HANDSHAKE_t;
-
-/* Data type for misc. registers */
-typedef struct {
-	dmacHw_REG64_t DmaCfgReg;	/* DMA Configuration Register */
-	dmacHw_REG64_t ChEnReg;	/* DMA Channel Enable Register */
-	dmacHw_REG64_t DmaIdReg;	/* DMA ID Register */
-	dmacHw_REG64_t DmaTestReg;	/* DMA Test Register */
-	dmacHw_REG64_t Reserved0;	/* Reserved */
-	dmacHw_REG64_t Reserved1;	/* Reserved */
-	dmacHw_REG64_t CompParm6;	/* Component Parameter 6 */
-	dmacHw_REG64_t CompParm5;	/* Component Parameter 5 */
-	dmacHw_REG64_t CompParm4;	/* Component Parameter 4 */
-	dmacHw_REG64_t CompParm3;	/* Component Parameter 3 */
-	dmacHw_REG64_t CompParm2;	/* Component Parameter 2 */
-	dmacHw_REG64_t CompParm1;	/* Component Parameter 1 */
-	dmacHw_REG64_t CompId;	/* Compoent ID */
-} dmacHw_MISC_t;
-
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0	/* 
DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1	/* 
DMAC 1 module's base address */
-
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) 
((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : 
dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char 
*)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : 
dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char 
*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char 
*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char 
*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char 
*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char 
*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-
-#define dmacHw_REG_CTL_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-
-#define dmacHw_REG_SSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-
-#define dmacHw_REG_CFG_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-
-#define dmacHw_REG_SGR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-
-#define dmacHw_REG_DSR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel) 
(dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-
-/* Bit mask for REG_DMACx_CTL_LO */
-
-#define dmacHw_REG_CTL_INT_EN                       0x00000001	/* 
Channel interrupt enable */
-
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E	/* 
Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000	/* 
Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002	/* 
Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004	/* 
Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006	/* 
Destination transaction width 64 bit */
-
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070	/* 
Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000	/* 
Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010	/* 
Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020	/* 
Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030	/* 
Source transaction width 64 bit */
-
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000	/* 
Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000	/* 
Source gather enable */
-
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180	/* 
Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000	/* 
Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080	/* 
Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100	/* 
Destination address no change */
-
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600	/* 
Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000	/* 
Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200	/* 
Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400	/* 
Source address no change */
-
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800	/* 
Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000	/* No 
Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800	/* 
Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000	/* 
Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800	/* 
Destination burst transaction length 16 */
-
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000	/* 
Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000	/* No 
Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000	/* 
Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000	/* 
Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000	/* 
Source burst transaction length 16 */
-
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000	/* 
Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000	/* 
Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000	/* 
Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000	/* 
Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000	/* 
Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000	/* 
Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000	/* 
Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000	/* 
Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000	/* 
Peripheral to Peripheral with Destination Peripheral as flow controller */
-
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000	/* 
Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000	/* 
Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000	/* 
Destination AHB master interface 2 */
-
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000	/* 
Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000	/* 
Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000	/* 
Source AHB master interface 2 */
-
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000	/* Block 
chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000	/* Block 
chaining enable for source side */
-
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF	/* Block 
transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000	/* Block 
trasnfer done */
-
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5	/* 
Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0	/* 
Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000	/* 
Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020	/* 
Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040	/* 
Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060	/* 
Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080	/* 
Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0	/* 
Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0	/* 
Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0	/* 
Channel priority 7 */
-
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100	/* 
Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200	/* 
Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400	/* 
Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800	/* 
Source channel SW handshaking */
-
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000	/* 
Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000	/* 
Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000	/* 
Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000	/* 
Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000	/* 
Channel lock enable */
-
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000	/* Bus 
locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000	/* Bus 
lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000	/* Bus 
lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000	/* Bus 
lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000	/* Bus 
lock enable */
-
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000	/* 
Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000	/* 
Source channel handshaking signal polarity low */
-
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000	/* 
Maximum AMBA burst length */
-
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000	/* 
Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000	/* 
Destination address auto reload */
-
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001	/* 
Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002	/* 
Initiate burst transaction when enough data in available in FIFO */
-
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C	/* AHB 
protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004	/* AHB 
protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008	/* AHB 
protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010	/* AHB 
protection 3 */
-
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020	/* 
Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040	/* 
Source status update enable */
-
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780	/* 
Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800	/* 
Destination peripheral hardware interface mask */
-
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700	/* 
Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800	/* 
Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f	/* 
Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000	/* Data 
transfer width */
-
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr) 
(dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr) 
(dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr) 
(dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-
-#define dmacHw_GET_SSTAT(module, channel) 
(dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel) 
(dmacHw_REG_DSTAT((module), (channel)))
-
-#define dmacHw_SET_SSTATAR(module, channel, addr) 
(dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr) 
(dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl) 
(dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)))
-
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl) 
(dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)))
-
-#define dmacHw_GET_BLOCK_SIZE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg) 
(dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 
20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect) 
(dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg) 
(dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & 
dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) 
& dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-
-#define dmacHw_DMA_START(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 0)
-
-#define dmacHw_TRAN_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-
-#define dmacHw_TRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-
-#define dmacHw_TRAN_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-
-#define dmacHw_GET_NUM_CHANNEL(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & 
dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h 
b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index cfa91be..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
-
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-
-/* Some items that can be defined externally, but will be set to 
default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS 
is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and 
Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR 
clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_HW_CFG_H */
-
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index 0aeb6a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define INTCHW_NUM_IRQ_PER_INTC   32	/* Maximum number of interrupt 
controllers */
-#define INTCHW_NUM_INTC           3
-
-/* Defines for interrupt controllers. This simplifies and cleans up the 
function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
-
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31	/* Peripheral interface 
interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30	/* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29	/* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28	/* Audio process module 
interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27	/* Ethernet switch 
interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26	/* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25	/* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24	/* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23	/* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22	/* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21	/* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20	/* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19	/* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18	/* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17	/* USB host2/device2 
interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16	/* Voice process module 
interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15	/* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14	/* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13	/* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12	/* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11	/* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10	/* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9	/* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8	/* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7	/* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6	/* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5	/* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4	/* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3	/* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2	/* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1	/* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0	/* DMA0 channel 0 interrupt */
-
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27	/* DDR and VPM PLL clock 
phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26	/* DDR and VPM HW phase 
align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26	/* DDR and PLL clock phase 
relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25	/* Real time clock tamper 
interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24	/* Hantro Video Decoder 
interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits 
in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23	/* Secure process module 
interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22	/* Real time clock 
one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21	/* Real time clock 
periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20	/* Random number generator 
interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19	/* Flash memory parition 
unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18	/* VRAM memory partition 
interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17	/* DDR2 memory partition 
interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16	/* Key pad controller 
interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15	/* Touch screen controller 
interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14	/* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13	/* Watchdog timer interrupt */
-
-#define INTCHW_INTC1_UART1_BITNUM         12	/* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11	/* ARM performance monitor 
interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10	/* ARM DDC receive 
interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9	/* ARM DDC transmit 
interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8	/* Flash controller 
interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7	/* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6	/* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5	/* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4	/* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3	/* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2	/* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1	/* GPIO bit 64//32 
combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0	/* GPIO bit 31//0 combined 
interrupt */
-
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15	/* Real time clock tamper 
interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14	/* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13	/* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12	/* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11	/* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10	/* Secure process module 
interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9	/* Real time clock 
one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8	/* Real time clock 
periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7	/* Random number generator 
interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6	/* Flash memory parition 
unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5	/* VRAM memory partition 
interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4	/* DDR2 memory partition 
interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3	/* Key pad controller 
interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2	/* Touch screen controller 
interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1	/* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0	/* Watchdog timer interrupt */
-
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00	/* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04	/* FIQ status register */
-#define INTCHW_RAWINTR        0x08	/* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c	/* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10	/* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14	/* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18	/* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c	/* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20	/* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24	/* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28	/* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100	/* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200	/* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00	/* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0	/* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0	/* PrimeCell ID Register 0-3 */
-
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENCLEAR) = mask;
-}
-
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENABLE) = mask;
-}
-
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index ad58cf8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*  Memory Map address definitions */
-
-#define MM_ADDR_DDR                0x00000000
-
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000	/* 16 MB - Reserved 
external memory for VPM use */
-
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000	/* 64 KB - extra cycle 
latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000	/* 64 KB  - security 
block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index de92ec6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_IO_H
-#define _MM_IO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(CONFIG_MMU)
-
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 
0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == 
MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-			(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | 
((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? 
MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-			((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
-#endif
-#endif
-
-#else
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-
-#endif
-
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-
-#define MM_IO_START MM_ADDR_IO_FLASHC	/* Physical beginning of IO 
mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC	/* Virtual beginning of IO mapped 
memory */
-
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-
-#define MM_IO_BASE_VPM_EXTMEM_RSVD 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-
-#include <mach/csp/mm_io.h>
-
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-
-/* Trustzone register set */
-typedef struct {
-	volatile uint32_t status;	/* read only - reflects status of writes of 
2 write registers */
-	volatile uint32_t setUnsecure;	/* write only. reads back as 0 */
-	volatile uint32_t setSecure;	/* write only. reads back as 0 */
-} secHw_TZREG_t;
-
-/* There are 2 register sets. The first is for the lower 16 bits, the 
2nd */
-/* is for the higher 16 bits. */
-
-typedef enum {
-	secHw_IDX_LS = 0,
-	secHw_IDX_MS = 1,
-	secHw_IDX_NUM
-} secHw_IDX_e;
-
-typedef struct {
-	volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-
-#include <mach/csp/secHw_inline.h>
-
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 9cd6a03..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-	}
-
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
-	}
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-
-/*
-This platform has four different timers running at different clock speed
-
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25	/* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150	/* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)	/* maximum number 
of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)	/* Number of timer module 
supported */
-
-typedef struct {
-	uint32_t LoadValue;	/* Load value for timer */
-	uint32_t CurrentValue;	/* Current value for timer */
-	uint32_t Control;	/* Control register */
-	uint32_t InterruptClear;	/* Interrupt clear register */
-	uint32_t RawInterruptStatus;	/* Raw interrupt status */
-	uint32_t InterruptStatus;	/* Masked interrupt status */
-	uint32_t BackgroundLoad;	/* Background load value */
-	uint32_t padding;	/* Padding register */
-} tmrHw_REG_t;
-
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | 
tmrHw_CONTROL_ONESHOT)
-
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h 
b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 7254378..0000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
-#include <mach/timer.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the 
filename */
-/* and line number of the reservation request will be recorded in the 
channel table */
-
-#define DMA_DEBUG_TRACK_RESERVATION   1
-
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8	/* per controller */
-
-typedef enum {
-	DMA_DEVICE_MEM_TO_MEM,	/* For memory to memory transfers */
-	DMA_DEVICE_I2S0_DEV_TO_MEM,
-	DMA_DEVICE_I2S0_MEM_TO_DEV,
-	DMA_DEVICE_I2S1_DEV_TO_MEM,
-	DMA_DEVICE_I2S1_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,	/* Additional mic input for 
beam-forming */
-	DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-	DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-	DMA_DEVICE_SPUM_DEV_TO_MEM,
-	DMA_DEVICE_SPUM_MEM_TO_DEV,
-	DMA_DEVICE_SPIH_DEV_TO_MEM,
-	DMA_DEVICE_SPIH_MEM_TO_DEV,
-	DMA_DEVICE_UART_A_DEV_TO_MEM,
-	DMA_DEVICE_UART_A_MEM_TO_DEV,
-	DMA_DEVICE_UART_B_DEV_TO_MEM,
-	DMA_DEVICE_UART_B_MEM_TO_DEV,
-	DMA_DEVICE_PIF_MEM_TO_DEV,
-	DMA_DEVICE_PIF_DEV_TO_MEM,
-	DMA_DEVICE_ESW_DEV_TO_MEM,
-	DMA_DEVICE_ESW_MEM_TO_DEV,
-	DMA_DEVICE_VPM_MEM_TO_MEM,
-	DMA_DEVICE_CLCD_MEM_TO_MEM,
-	DMA_DEVICE_NAND_MEM_TO_MEM,
-	DMA_DEVICE_MEM_TO_VRAM,
-	DMA_DEVICE_VRAM_TO_MEM,
-
-	/* Add new entries before this line. */
-
-	DMA_NUM_DEVICE_ENTRIES,
-	DMA_DEVICE_NONE = 0xff,	/* Special value to indicate that no device is 
currently assigned. */
-
-} DMA_Device_t;
-
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-
-typedef int DMA_Handle_t;
-
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-
-typedef struct {
-	void *virtAddr;		/* Virtual Address of the descriptor ring */
-	dma_addr_t physAddr;	/* Physical address of the descriptor ring */
-	int descriptorsAllocated;	/* Number of descriptors allocated in the 
descriptor ring */
-	size_t bytesAllocated;	/* Number of bytes allocated in the descriptor 
ring */
-
-} DMA_DescriptorRing_t;
-
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-
-/* The device handler is called whenever a DMA operation completes. The 
reaon */
-/* for it to be called will be a bitmask with one or more of the 
following bits */
-/* set. */
-
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE 
dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE 
dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR 
dmacHw_INTERRUPT_STATUS_ERROR
-
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-				     void *userData);
-
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004	/* If set, it 
means that the port used on DMAC0 is different from the port used on 
DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008	/* If set, 
allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800	/* If set, 
device is in use on a channel */
-
-/* Note: Some DMA devices can be used from multiple DMA Controllers. 
The bitmask is used to */
-/*       determine which DMA controllers a given device can be used 
from, and the interface */
-/*       array determeines the actual interface number to use for a 
given controller. */
-
-typedef struct {
-	uint32_t flags;		/* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-	uint8_t dedicatedController;	/* Controller number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	uint8_t dedicatedChannel;	/* Channel number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	const char *name;	/* Will show up in the /proc entry */
-
-	uint32_t dmacPort[DMA_NUM_CONTROLLERS];	/* Specifies the port number 
when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-
-	dmacHw_CONFIG_t config;	/* Configuration to use when DMA'ing using 
this device */
-
-	void *userData;		/* Passed to the devHandler */
-	DMA_DeviceHandler_t devHandler;	/* Called when DMA operations finish. */
-
-	timer_tick_count_t transferStartTime;	/* Time the current transfer was 
started */
-
-	/* The following statistical information will be collected and 
presented in a proc entry. */
-	/* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 
years to overflow */
-	/*       a 64 bit counter. */
-
-	uint64_t numTransfers;	/* Number of DMA transfers performed */
-	uint64_t transferTicks;	/* Total time spent doing DMA transfers 
(measured in timer_tick_count_t's) */
-	uint64_t transferBytes;	/* Total bytes transferred */
-	uint32_t timesBlocked;	/* Number of times a channel was unavailable */
-	uint32_t numBytes;	/* Last transfer size */
-
-	/* It's not possible to free memory which is allocated for the 
descriptors from within */
-	/* the ISR. So make the presumption that a given device will tend to 
use the */
-	/* same sized buffers over and over again, and we keep them around. */
-
-	DMA_DescriptorRing_t ring;	/* Ring of descriptors allocated for this 
device */
-
-	/* We stash away some of the information from the previous transfer. 
If back-to-back */
-	/* transfers are performed from the same buffer, then we don't have to 
keep re-initializing */
-	/* the descriptor buffers. */
-
-	uint32_t prevNumBytes;
-	dma_addr_t prevSrcData;
-	dma_addr_t prevDstData;
-
-} DMA_DeviceAttribute_t;
-
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out 
into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA 
channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-
-typedef struct {
-	uint32_t flags;		/* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-	DMA_Device_t devType;	/* Device this channel is currently reserved for */
-	DMA_Device_t lastDevType;	/* Device type that used this previously */
-	char name[20];		/* Name passed onto request_irq */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	const char *fileName;	/* Place where channel reservation took place */
-	int lineNum;		/* Place where channel reservation took place */
-#endif
-	dmacHw_HANDLE_t dmacHwHandle;	/* low level channel handle. */
-
-} DMA_Channel_t;
-
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA 
controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-
-typedef struct {
-	DMA_Channel_t channel[DMA_NUM_CHANNELS];
-
-} DMA_Controller_t;
-
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-
-typedef struct {
-	struct semaphore lock;	/* acquired when manipulating table entries */
-	wait_queue_head_t freeChannelQ;
-
-	DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-
-} DMA_Global_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-#if defined(__KERNEL__)
-
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-
-int dma_init(void);
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char 
*fileName,
-				     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, 
__FILE__, __LINE__)
-#else
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-DMA_Handle_t dma_request_channel(DMA_Device_t dev	/* Device to use with 
the allocated channel. */
-    );
-#endif
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t channel	/* DMA handle. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t dev	/* Device to check. */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    );
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    );
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    );
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_to_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					 dma_addr_t srcData,	/* Place to get data to write to device 
(physical address) */
-					 dma_addr_t dstData,	/* Pointer to device data address (physical 
address) */
-					 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_from_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					   dma_addr_t srcData,	/* Pointer to the device data address 
(physical address) */
-					   dma_addr_t dstData,	/* Place to store data retrieved from the 
device (physical address) */
-					   size_t numBytes	/* Number of bytes to retrieve from the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,	/* DMA 
Handle */
-					  dma_addr_t srcData,	/* Place to transfer data from (physical 
address) */
-					  dma_addr_t dstData,	/* Place to transfer data to (physical 
address) */
-					  size_t numBytes	/* Number of bytes to transfer */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    );
-
-#endif
-
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S 
b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0..0000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =(MM_IO_BASE_INTC0)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC0_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_INTC1)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC1_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_SINTC)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #0xffffffff             @ code meaning no interrupt bits set
-		cmp	\irqstat, #0
-		beq	1002f
-
-		mov	\irqnr, #IRQ_SINTC_START        @ something is set, so fixup 
return value
-
-1001:
-		movs	\tmp, \irqstat, lsl #16
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #16
-
-		movs	\tmp, \irqstat, lsl #8
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #8
-
-		movs	\tmp, \irqstat, lsl #4
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #4
-
-		movs	\tmp, \irqstat, lsl #2
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #2
-
-		movs	\tmp, \irqstat, lsl #1
-		addeq	\irqnr, \irqnr, #1
-		orrs	\base, \base, #1
-
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-		.endm
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h 
b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index 6ae20a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <cfg_global.h>
-#include <mach/csp/mm_io.h>
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-
-#define RAM_SIZE 
(CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-
-/* Macros to make managing spinlocks a bit more controlled in terms of 
naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name) 
DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t 
bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val) 
spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val) 
spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h 
b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b82..0000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0	/* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1	/* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2	/* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3	/* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4	/* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5	/* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6	/* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7	/* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8	/* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9	/* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10	/* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11	/* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12	/* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13	/* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14	/* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15	/* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16	/* Voice process module interrupt */
-#define IRQ_USBHD2         17	/* USB host2/device2 interrupt */
-#define IRQ_USBH1          18	/* USB1 host interrupt */
-#define IRQ_USBD           19	/* USB device interrupt */
-#define IRQ_SDIOH0         20	/* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21	/* SDIO1 host interrupt */
-#define IRQ_TIMER0         22	/* Timer0 interrupt */
-#define IRQ_TIMER1         23	/* Timer1 interrupt */
-#define IRQ_TIMER2         24	/* Timer2 interrupt */
-#define IRQ_TIMER3         25	/* Timer3 interrupt */
-#define IRQ_SPIH           26	/* SPI host interrupt */
-#define IRQ_ESW            27	/* Ethernet switch interrupt */
-#define IRQ_APM            28	/* Audio process module interrupt */
-#define IRQ_GE             29	/* Graphic engine interrupt */
-#define IRQ_CLCD           30	/* LCD Controller interrupt */
-#define IRQ_PIF            31	/* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32	/*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33	/*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34	/*  2 I2S0 interrupt */
-#define IRQ_I2S1           35	/*  3 I2S1 interrupt */
-#define IRQ_I2CH           36	/*  4 I2C host interrupt */
-#define IRQ_I2CS           37	/*  5 I2C slave interrupt */
-#define IRQ_SPIS           38	/*  6 SPI slave interrupt */
-#define IRQ_GPHY           39	/*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40	/*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41	/*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42	/* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43	/* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44	/* 12 UARTB */
-#define IRQ_WATCHDOG       45	/* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46	/* 14 UARTA */
-#define IRQ_TSC            47	/* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48	/* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49	/* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50	/* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51	/* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52	/* 20 Random number generator interrupt */
-#define IRQ_RTC0           53	/* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54	/* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55	/* 23 Secure process module interrupt */
-#define IRQ_VDEC           56	/* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57	/* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58	/* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59	/*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60	/*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61	/*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62	/*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63	/*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64	/*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65	/*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66	/*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67	/*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68	/*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69	/* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70	/* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71	/* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72	/* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73	/* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74	/* 15 Real time clock tamper interrupt */
-
-#define IRQ_SINTC_END      74
-
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs 
could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio 
based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-
-#define IRQ_GPIO_0                  100
-
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I 
hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-
-#define IRQ_UNKNOWN                 -1
-
-/* Tune these bits to preclude noisy or unsupported interrupt sources 
as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h 
b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16..0000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)	/* Bus turnaround cycle (n) 
0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)	/* Write pulse width cycle (n+1) 
0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)	/* Write recovery cycle (n+1) 
0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)	/* Write address setup cycle (n+1) 
0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)	/* Output enable delay cycle (n) 
0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)	/* Read access cycle (n+2) 
0-31 (50 ns) */
-
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-	| HW_CFG_NAND_tWP  \
-	| HW_CFG_NAND_tWR  \
-	| HW_CFG_NAND_tAS  \
-	| HW_CFG_NAND_tOE  \
-	| HW_CFG_NAND_tRC)
-
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)	/* Page read access cycle / 
Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)	/* Bus turnaround cycle (n) 
                             (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)	/* Write pulse width cycle (n+1) 
                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)	/* Write recovery cycle (n+1) 
                            (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)	/* Write address setup cycle 
(n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)	/* Output enable delay cycle (n) 
                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)	/* Read access cycle / Burst 
read latency (n+2 / n+1)       (100ns)    */
-
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-	| HW_CFG_NOR_TBTA      \
-	| HW_CFG_NOR_TWP       \
-	| HW_CFG_NOR_TWR       \
-	| HW_CFG_NOR_TAS       \
-	| HW_CFG_NOR_TOE       \
-	| HW_CFG_NOR_TRC_TLC)
-
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules 
[8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000	/* Total memory, not 
per device size */
-
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h 
b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index 387376f..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/reg_umi.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-#define HW_NAND_BASE       MM_IO_BASE_NAND	/* NAND Flash */
-
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h 
b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 0992842..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst 
flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 
+ (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h 
b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb..0000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-
-#if defined(__KERNEL__)
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Constants and Types 
---------------------------------------------- */
-
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h 
b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033e..0000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE		100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h 
b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b..0000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA 
+ 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	/* Send out UARTA */
-	while (BCMRING_UART_0_FR & (1 << 5))
-		;
-
-	BCMRING_UART_0_DR = c;
-}
-
-
-static inline void flush(void)
-{
-	/* Wait for the tx fifo to be empty */
-	while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-		;
-
-	/* Wait for the final character to be sent on the txd line */
-	while (BCMRING_UART_0_FR & (1 << 3))
-		;
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa68..0000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-
-static struct irq_chip bcmring_irq0_chip = {
-	.name = "ARM-INTC0",
-	.irq_ack = bcmring_mask_irq0,
-	.irq_mask = bcmring_mask_irq0,	/* mask a specific interrupt, blocking 
its delivery. */
-	.irq_unmask = bcmring_unmask_irq0,	/* unmaks an interrupt */
-};
-
-static struct irq_chip bcmring_irq1_chip = {
-	.name = "ARM-INTC1",
-	.irq_ack = bcmring_mask_irq1,
-	.irq_mask = bcmring_mask_irq1,
-	.irq_unmask = bcmring_unmask_irq1,
-};
-
-static struct irq_chip bcmring_irq2_chip = {
-	.name = "ARM-SINTC",
-	.irq_ack = bcmring_mask_irq2,
-	.irq_mask = bcmring_mask_irq2,
-	.irq_unmask = bcmring_unmask_irq2,
-};
-
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-		     unsigned int irq_start, unsigned int vic_sources)
-{
-	unsigned int i;
-	for (i = 0; i < 32; i++) {
-		unsigned int irq = irq_start + i;
-		irq_set_chip(irq, chip);
-		irq_set_chip_data(irq, base);
-
-		if (vic_sources & (1 << i)) {
-			irq_set_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-	writel(0, base + INTCHW_INTSELECT);
-	writel(0, base + INTCHW_INTENABLE);
-	writel(~0, base + INTCHW_INTENCLEAR);
-	writel(0, base + INTCHW_IRQSTATUS);
-	writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-
-void __init bcmring_init_irq(void)
-{
-	vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-		 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-		 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-		 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-
-	/* special cases */
-	if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-	}
-	if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-	}
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 1adec78..0000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-#define IO_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_DEVICE }
-
-#define MEM_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_MEMORY }
-
-static struct map_desc bcmring_io_desc[] __initdata = {
-	IO_DESC(MM_IO_BASE_NAND, SZ_64K),	/* phys:0x28000000-0x28000FFF 
virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_UMI, SZ_64K),	/* phys:0x2C000000-0x2C000FFF 
virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
-	IO_DESC(MM_IO_BASE_BROM, SZ_64K),	/* phys:0x30000000-0x3000FFFF 
virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-	MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),	/* phys:0x31000000-0x31FFFFFF 
virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA0, SZ_1M),	/* phys:0x32000000-0x32FFFFFF 
virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA1, SZ_1M),	/* phys:0x33000000-0x33FFFFFF 
virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_ESW, SZ_1M),	/* phys:0x34000000-0x34FFFFFF 
virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_CLCD, SZ_1M),	/* phys:0x35000000-0x35FFFFFF 
virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_APM, SZ_1M),	/* phys:0x36000000-0x36FFFFFF 
virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_SPUM, SZ_1M),	/* phys:0x37000000-0x37FFFFFF 
virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),	/* phys:0x38000000-0x38FFFFFF 
virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),	/* phys:0x3A000000-0x3AFFFFFF 
virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
-	IO_DESC(MM_IO_BASE_VRAM, SZ_64K),	/* phys:0x40000000-0x4000FFFF 
virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),	/* phys:0x80000000-0x80FFFFFF 
virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-		SZ_16M),	/* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF 
size:0x01000000 */
-};
-
-void __init bcmring_map_io(void)
-{
-
-	iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-	/* Maximum DMA memory allowed is 14M */
-	init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index af9c3d7..0000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <csp/tmrHw.h>
-
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM 
timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread 
spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-
-#define PROF_TIMER 1
-
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-	return tmrHw_getCountRate(PROF_TIMER);
-}
-
-timer_tick_count_t timer_get_tick_count(void)
-{
-	return tmrHw_GetCurrentCount(PROF_TIMER);	/* change downcounter to 
upcounter */
-}
-
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-	static int tickRateMsec;
-
-	if (tickRateMsec == 0) {
-		tickRateMsec = timer_get_tick_rate() / 1000;
-	}
-
-	return ticks / tickRateMsec;
-}
-
-timer_msec_t timer_get_msec(void)
-{
-	return timer_ticks_to_msec(timer_get_tick_count());
-}
-
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
-- 
1.7.1






From csd at broadcom.com  Wed Sep 12 04:18:07 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 01:18:07 -0700
Subject: [PATCH 3/3] ARM: Remove BCMRING from arm/tools/mach-types
Message-ID: <5050453F.4080504@broadcom.com>

Remove BCMRING from mach-types as that machine type is no
longer maintaned or used.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

---
  arch/arm/tools/mach-types |    1 -
  1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56..529f7e3 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -404,7 +404,6 @@ vexpress		MACH_VEXPRESS		VEXPRESS		2272
  d2net			MACH_D2NET		D2NET			2282
  bigdisk			MACH_BIGDISK		BIGDISK			2283
  at91sam9g20ek_2mmc	MACH_AT91SAM9G20EK_2MMC	AT91SAM9G20EK_2MMC	2288
-bcmring			MACH_BCMRING		BCMRING			2289
  mahimahi		MACH_MAHIMAHI		MAHIMAHI		2304
  smdk6442		MACH_SMDK6442		SMDK6442		2324
  openrd_base		MACH_OPENRD_BASE	OPENRD_BASE		2325
-- 
1.7.1




From linux at arm.linux.org.uk  Wed Sep 12 04:52:23 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 12 Sep 2012 09:52:23 +0100
Subject: [PATCH 3/3] ARM: Remove BCMRING from arm/tools/mach-types
In-Reply-To: <5050453F.4080504@broadcom.com>
References: <5050453F.4080504@broadcom.com>
Message-ID: <20120912085223.GV13739@n2100.arm.linux.org.uk>

On Wed, Sep 12, 2012 at 01:18:07AM -0700, Christian Daudt wrote:
> Remove BCMRING from mach-types as that machine type is no
> longer maintaned or used.

Please don't.  Once it's been in mainline once, it will always be in
this file whenever the file is regenerated.


From zajec5 at gmail.com  Wed Sep 12 05:19:14 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Wed, 12 Sep 2012 11:19:14 +0200
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347361186.26206.5.camel@sauron.fi.intel.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
 <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
 <1347361186.26206.5.camel@sauron.fi.intel.com>
Message-ID: <CACna6rwP-DAV=H3FC+WXevekMB65dM42hsWnwVrxutUGhY=FFg@mail.gmail.com>

2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Tue, 2012-09-11 at 12:35 +0200, Rafa? Mi?ecki wrote:
>> 2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
>> > On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
>> >> This registers MTD driver for serial flash platform device. Right now it
>> >> supports reading only, writing still has to be implemented.
>> >> At this point it's marked as BROKEN, because it requires code present in
>> >> net tree that wasn't mainlined yet.
>> >>
>> >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>> >
>> > What are exactly the changes it depends on? URL? Are they staged for
>> > 3.7?
>>
>> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=23cb3b2121323443834296a8ecb582b8aeb78d75
>> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=d57ef3a6a2eeb88df47e892c66692e3f59722ffe
>>
>> (Yes, there are queued to be pulled during 3.7 merge window)
>
> CCing John. I am not 100% sure how the net drivers are handled, but if
> John does not rebase and just sends a pull request to David Miller, who
> also does not rebase, then we could pull John's tree into the MTD tree.

Not sure if my plans were clear since beginning so just for sure,
order I imagined:
1) Me adding mtd drivers
2) Linus releasing 3.7-rc1 with disabled mtd driver and changes from
wireless tree
3) Me sending trivial patch enabling mtd driver for -fixes tree

-- 
Rafa?


From afzal at ti.com  Wed Sep 12 05:21:28 2012
From: afzal at ti.com (Mohammed, Afzal)
Date: Wed, 12 Sep 2012 09:21:28 +0000
Subject: [PATCH v3 10/10] mtd: nand: omap2: use gpmc provided irqs
In-Reply-To: <20120911182106.GK23092@atomide.com>
References: <cover.1344609341.git.afzal@ti.com>
 <c5a608a70a875191e1323958c74fb2ac8dfa34b3.1344609341.git.afzal@ti.com>
 <1345895326.1815.4.camel@kyv> <20120830195349.GW1303@atomide.com>
 <20120911001710.GD1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1905@DBDE01.ent.ti.com>
 <20120911054227.GF1303@atomide.com>
 <C8443D0743D26F4388EA172BF4E2A7A93E9E1A11@DBDE01.ent.ti.com>
 <20120911182106.GK23092@atomide.com>
Message-ID: <C8443D0743D26F4388EA172BF4E2A7A93E9E2502@DBDE01.ent.ti.com>

On Tue, Sep 11, 2012 at 23:51:07, Tony Lindgren wrote:

> Ah thanks, that's a copy paste UTF-8 issue. I'll just fold
> in the fixes and push them out to a new devel-gpmc-fixed
> branch.

Thanks Tony

Regards
Afzal

From will.deacon at arm.com  Wed Sep 12 05:51:31 2012
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 12 Sep 2012 10:51:31 +0100
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <505044E3.3040601@broadcom.com>
References: <505044E3.3040601@broadcom.com>
Message-ID: <20120912095130.GN32234@mudshark.cambridge.arm.com>

Hi Christian,

On Wed, Sep 12, 2012 at 09:16:35AM +0100, Christian Daudt wrote:
> This driver is being removed as part of the cleanup of the bcmring
> SoC from mainline as it is no longer maintained.
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

This is really good to see, thanks. I guess the other two patches in your
series were too large and are being held for moderation by the list?

Anyway, for this one:

Acked-by: Will Deacon <will.deacon at arm.com>

Cheers,

Will


From linux at arm.linux.org.uk  Wed Sep 12 05:57:41 2012
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 12 Sep 2012 10:57:41 +0100
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <20120912095130.GN32234@mudshark.cambridge.arm.com>
References: <505044E3.3040601@broadcom.com>
 <20120912095130.GN32234@mudshark.cambridge.arm.com>
Message-ID: <20120912095741.GY13739@n2100.arm.linux.org.uk>

On Wed, Sep 12, 2012 at 10:51:31AM +0100, Will Deacon wrote:
> Hi Christian,
> 
> On Wed, Sep 12, 2012 at 09:16:35AM +0100, Christian Daudt wrote:
> > This driver is being removed as part of the cleanup of the bcmring
> > SoC from mainline as it is no longer maintained.
> > 
> > Signed-off-by: Christian Daudt <csd at broadcom.com>
> > Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
> 
> This is really good to see, thanks. I guess the other two patches in your
> series were too large and are being held for moderation by the list?

They have typos in the list address.


From levinsasha928 at gmail.com  Wed Sep 12 06:50:28 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Wed, 12 Sep 2012 12:50:28 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1347202600.5876.7.camel@sbsiddha-ivb>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb>
Message-ID: <505068F4.4080309@gmail.com>

On 09/09/2012 04:56 PM, Suresh Siddha wrote:
> On Sat, 2012-09-08 at 12:57 -0700, Linus Torvalds wrote:
>> > Whatever. Something like this (TOTALLY UNTESTED) attached patch should
>> > get the mtdchar overflows to go away, 
> It looks good to me. Acked-by: Suresh Siddha <suresh.b.siddha at intel.com>
> 
> Sasha, can you please give this a try?

Sorry for the delay. It looks good here.


Thanks,
Sasha



From levinsasha928 at gmail.com  Wed Sep 12 06:56:44 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Wed, 12 Sep 2012 12:56:44 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <505068F4.4080309@gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
Message-ID: <50506A6C.30109@gmail.com>

On 09/12/2012 12:50 PM, Sasha Levin wrote:
> On 09/09/2012 04:56 PM, Suresh Siddha wrote:
>> On Sat, 2012-09-08 at 12:57 -0700, Linus Torvalds wrote:
>>>> Whatever. Something like this (TOTALLY UNTESTED) attached patch should
>>>> get the mtdchar overflows to go away, 
>> It looks good to me. Acked-by: Suresh Siddha <suresh.b.siddha at intel.com>
>>
>> Sasha, can you please give this a try?
> 
> Sorry for the delay. It looks good here.
> 
> 
> Thanks,
> Sasha
> 

Uh... sorry again, I obviously tested the second patch sent by Linus but
mistakingly replied to the wrong mail in the thread.


From richard.genoud at gmail.com  Wed Sep 12 08:26:26 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 12 Sep 2012 14:26:26 +0200
Subject: [PATCH] MTD: nandsim: BUG: Fail if overridesize is too big
Message-ID: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>

If override size is too big, the module was actually loaded instead of
failing, because retval was not set.

This lead to memory corruption with the use of the freed structs nandsim
and nand_chip.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 drivers/mtd/nand/nandsim.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
index cf0cd31..5d881180 100644
--- a/drivers/mtd/nand/nandsim.c
+++ b/drivers/mtd/nand/nandsim.c
@@ -2333,6 +2333,7 @@ static int __init ns_init_module(void)
 		uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
 		if (new_size >> overridesize != nsmtd->erasesize) {
 			NS_ERR("overridesize is too big\n");
+			retval = -EINVAL;
 			goto err_exit;
 		}
 		/* N.B. This relies on nand_scan not doing anything with the size before we change it */
-- 
1.7.2.5



From richard.genoud at gmail.com  Wed Sep 12 10:37:19 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 12 Sep 2012 16:37:19 +0200
Subject: [MTD-UTILS] BUG: ubiformat fails on big partitions (>4Gio)
Message-ID: <1347460639-3241-1-git-send-email-richard.genoud@gmail.com>

The offset (which is 64bits when mtd-utils are not compile with
WITHOUT_LARGEFILE) is calculated like that:
offset = nb * size;
But nb and size are int, so on 32bits platforms, there's a possible
overflow.

So, it should be replace with:
offset = (off_t)nb * size;
If WITHOUT_LARGEFILE is defined, there still be an overflow, but it's
what we want, right ?

Cheney Chen tested an ubiformat on a NAND (5.9 GiB mtd part).

Reported-by: Cheney Chen <cheneychencl2012 at gmail.com>
Tested-by: Cheney Chen <cheneychencl2012 at gmail.com>
Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 ubi-utils/libubigen.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/ubi-utils/libubigen.c b/ubi-utils/libubigen.c
index 9eaa7f5..d2a949b 100644
--- a/ubi-utils/libubigen.c
+++ b/ubi-utils/libubigen.c
@@ -279,7 +279,7 @@ int ubigen_write_layout_vol(const struct ubigen_info *ui, int peb1, int peb2,
 	memset(outbuf + ui->data_offs + ui->vtbl_size, 0xFF,
 	       ui->peb_size - ui->data_offs - ui->vtbl_size);
 
-	seek = peb1 * ui->peb_size;
+	seek = (off_t) peb1 * ui->peb_size;
 	if (lseek(fd, seek, SEEK_SET) != seek) {
 		sys_errmsg("cannot seek output file");
 		goto out_free;
@@ -293,7 +293,7 @@ int ubigen_write_layout_vol(const struct ubigen_info *ui, int peb1, int peb2,
 		goto out_free;
 	}
 
-	seek = peb2 * ui->peb_size;
+	seek = (off_t) peb2 * ui->peb_size;
 	if (lseek(fd, seek, SEEK_SET) != seek) {
 		sys_errmsg("cannot seek output file");
 		goto out_free;
-- 
1.7.2.5



From richard.genoud at gmail.com  Wed Sep 12 10:37:54 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 12 Sep 2012 16:37:54 +0200
Subject: [MTD-UTILS] io_update test: correct lseek parameters order
Message-ID: <1347460674-3536-1-git-send-email-richard.genoud@gmail.com>

There's a typo in lseek parameters order.

But, due to the value of SEEK_SET, this commit doesn't introduce a
change.

Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
---
 tests/ubi-tests/io_update.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/tests/ubi-tests/io_update.c b/tests/ubi-tests/io_update.c
index 0259446..e8f0986 100644
--- a/tests/ubi-tests/io_update.c
+++ b/tests/ubi-tests/io_update.c
@@ -158,7 +158,7 @@ static int test_update1(struct ubi_vol_info *vol_info, int leb_change)
 		}
 
 		/* Check data */
-		if ((ret = lseek(fd, SEEK_SET, 0)) != 0) {
+		if ((ret = lseek(fd, 0, SEEK_SET)) != 0) {
 			failed("lseek");
 			errmsg("cannot seek to 0");
 			goto close;
-- 
1.7.2.5



From richard.genoud at gmail.com  Wed Sep 12 10:38:32 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Wed, 12 Sep 2012 16:38:32 +0200
Subject: [MTD-UTILS 0/3] fix off_t use in lseek
Message-ID: <1347460715-3951-1-git-send-email-richard.genoud@gmail.com>

In lseek call, sometimes off_t is used, sometime u_int32_t or
off64_t (with lseek64).
This patchset corrects those inconsistencies in respect with the
WITHOUT_LARGEFILE compilation option.

Richard Genoud (3):
  introduce PRIxoff_t and PRIdoff_t printf helpers
  consistency between u_int32_t / off_t / off64_t
  mkfs.jffs2: correct some warnings using PRIdoff_t

 flash_erase.c                      |   16 +++++++-------
 flash_otp_write.c                  |    5 ++-
 ftl_check.c                        |    6 +++-
 ftl_format.c                       |    2 +-
 include/common.h                   |   11 ++++++++++
 lib/libmtd.c                       |   12 +++++-----
 mkfs.jffs2.c                       |   10 ++++----
 mkfs.ubifs/mkfs.ubifs.c            |   11 ++++-----
 mtd_debug.c                        |   14 ++++++------
 tests/fs-tests/integrity/integck.c |    4 +-
 tests/ubi-tests/integ.c            |   38 ++++++++++++++++++------------------
 11 files changed, 71 insertions(+), 58 deletions(-)

-- 
1.7.2.5



From csd at broadcom.com  Wed Sep 12 11:17:32 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 08:17:32 -0700
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <20120912095741.GY13739@n2100.arm.linux.org.uk>
References: <505044E3.3040601@broadcom.com>
 <20120912095130.GN32234@mudshark.cambridge.arm.com>
 <20120912095741.GY13739@n2100.arm.linux.org.uk>
Message-ID: <5050A78C.4000700@broadcom.com>

On 12-09-12 02:57 AM, Russell King - ARM Linux wrote:
> On Wed, Sep 12, 2012 at 10:51:31AM +0100, Will Deacon wrote:
>> Hi Christian,
>>
>> On Wed, Sep 12, 2012 at 09:16:35AM +0100, Christian Daudt wrote:
>>> This driver is being removed as part of the cleanup of the bcmring
>>> SoC from mainline as it is no longer maintained.
>>>
>>> Signed-off-by: Christian Daudt<csd at broadcom.com>
>>> Reviewed-by: Jiandong Zheng<jdzheng at broadcom.com>
>> This is really good to see, thanks. I guess the other two patches in your
>> series were too large and are being held for moderation by the list?
> They have typos in the list address.
>
patch 2/3 is awaiting moderator approval. The linux-mtd cc is here: 
http://lists.infradead.org/pipermail/linux-mtd/2012-September/043945.html
patch 3/3 had a email address typo but Russell said it should not be 
applied, so I won't bother resending. The linux-mtd cc is here: 
http://lists.infradead.org/pipermail/linux-mtd/2012-September/043946.html

   thanks,
    Christian.





From peter.senna at gmail.com  Wed Sep 12 13:03:21 2012
From: peter.senna at gmail.com (Peter Senna Tschudin)
Date: Wed, 12 Sep 2012 19:03:21 +0200
Subject: [PATCH 14/15] fs/jffs2/wbuf.c: removes unnecessary semicolon
Message-ID: <1347469402-27557-14-git-send-email-peter.senna@gmail.com>

From: Peter Senna Tschudin <peter.senna at gmail.com>

removes unnecessary semicolon

Found by Coccinelle: http://coccinelle.lip6.fr/

Signed-off-by: Peter Senna Tschudin <peter.senna at gmail.com>

---
 fs/jffs2/wbuf.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/fs/jffs2/wbuf.c b/fs/jffs2/wbuf.c
index a6597d6..bea0487 100644
--- a/fs/jffs2/wbuf.c
+++ b/fs/jffs2/wbuf.c
@@ -1275,7 +1275,7 @@ int jffs2_dataflash_setup(struct jffs2_sb_info *c) {
 	if ((c->flash_size % c->sector_size) != 0) {
 		c->flash_size = (c->flash_size / c->sector_size) * c->sector_size;
 		pr_warn("flash size adjusted to %dKiB\n", c->flash_size);
-	};
+	}
 
 	c->wbuf_ofs = 0xFFFFFFFF;
 	c->wbuf = kmalloc(c->wbuf_pagesize, GFP_KERNEL);



From vikram186 at gmail.com  Wed Sep 12 13:10:51 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Wed, 12 Sep 2012 22:40:51 +0530
Subject: [PATCH 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1
In-Reply-To: <504FF050.1070202@freescale.com>
References: <1347344231-10295-1-git-send-email-b32955@freescale.com>
 <1347344231-10295-4-git-send-email-b32955@freescale.com>
 <504F7C22.1050605@gmail.com> <504FF050.1070202@freescale.com>
Message-ID: <5050C21B.2030407@gmail.com>

Hello Huang Shijie,

<Dropped Cc's>

On 9/12/2012 7:45 AM, Huang Shijie wrote:
> ? 2012?09?12? 02:00, Vikram Narayanan ??:
>> Hello Huang Shijie,
>>
>> On 9/11/2012 11:47 AM, Huang Shijie wrote:
>>> The gpmi_nfc_compute_hardware_timing{} should contains all the
>>> fields setting for gpmi timing registers. It already contains the fields
>>> for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.
>>>
>>> So it is better to add a new field setting for HW_GPMI_TIMING1 in
>>> this data structure. This makes the code more clear in logic.
>>>
>>> This patch also changes some comments to make the code more readable.
>>>
>>> Signed-off-by: Huang Shijie<b32955 at freescale.com>
>>> ---
>>> drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 17 +++++++++--------
>>> drivers/mtd/nand/gpmi-nand/gpmi-nand.h | 9 +++++++++
>>> drivers/mtd/nand/gpmi-nand/gpmi-regs.h | 3 +++
>>> 3 files changed, 21 insertions(+), 8 deletions(-)
>>>
<snip>
>>> + /* [1] Set HW_GPMI_TIMING0 */
>>> reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
>>> BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
>>> BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
>>>
>>> writel(reg, gpmi_regs + HW_GPMI_TIMING0);
>>>
>>> - /*
>>> - * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
>>> - */
>>> + /* [2] Set HW_GPMI_TIMING1 */
>>> + writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
>>> + gpmi_regs + HW_GPMI_TIMING1);
>>> +
>>> + /* [3] The following code is to set the HW_GPMI_CTRL1. */
>>> +
>>> + /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or
>>> HALF_PERIOD. */
>>> writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
>>
>>
>> Are these [1], [2], [3] notation references to some other comments?
> no.
>
> These notations just help to comment the steps of setting timing registers.
> Are you confused at this?

Not much. But this is the notation usually used for references. you can 
keep this as it is. Not an issue.

Regards,
Vikram


From swarren at wwwdotorg.org  Wed Sep 12 13:25:00 2012
From: swarren at wwwdotorg.org (Stephen Warren)
Date: Wed, 12 Sep 2012 11:25:00 -0600
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <505044E3.3040601@broadcom.com>
References: <505044E3.3040601@broadcom.com>
Message-ID: <5050C56C.8070603@wwwdotorg.org>

On 09/12/2012 02:16 AM, Christian Daudt wrote:
> This driver is being removed as part of the cleanup of the bcmring
> SoC from mainline as it is no longer maintained.

>  arch/arm/configs/bcmring_defconfig |    2 -

Out of curiosity, if you're removing the whole thing, why edit the
defconfig at all; just delete it instead in whatever patch removes the
arch/arm parts?


From csd at broadcom.com  Wed Sep 12 14:39:20 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 11:39:20 -0700
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <5050C56C.8070603@wwwdotorg.org>
References: <505044E3.3040601@broadcom.com>
 <5050C56C.8070603@wwwdotorg.org>
Message-ID: <5050D6D8.8090605@broadcom.com>

On 12-09-12 10:25 AM, Stephen Warren wrote:
> On 09/12/2012 02:16 AM, Christian Daudt wrote:
>> This driver is being removed as part of the cleanup of the bcmring
>> SoC from mainline as it is no longer maintained.
>>   arch/arm/configs/bcmring_defconfig |    2 -
> Out of curiosity, if you're removing the whole thing, why edit the
> defconfig at all; just delete it instead in whatever patch removes the
> arch/arm parts?
>
I figured it'd be better to remove the config portion on this patch so 
it is self-contained - just in case the other patch gets held up for 
some reason then this one can still be applied and no junk would be left 
around. But agreed - it doesn't really affect things either way.


  thanks,
    Christian.




From olof at lixom.net  Wed Sep 12 14:55:09 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 12 Sep 2012 11:55:09 -0700
Subject: [PATCH 1/3] ARM: Remove bcmring NAND driver
In-Reply-To: <5050D6D8.8090605@broadcom.com>
References: <505044E3.3040601@broadcom.com> <5050C56C.8070603@wwwdotorg.org>
 <5050D6D8.8090605@broadcom.com>
Message-ID: <CAOesGMh3mhQSRxYU_qdRVyBvQ27Kpi_4iRRYomH6ufzON_dxCw@mail.gmail.com>

On Wed, Sep 12, 2012 at 11:39 AM, Christian Daudt <csd at broadcom.com> wrote:
> On 12-09-12 10:25 AM, Stephen Warren wrote:
>>
>> On 09/12/2012 02:16 AM, Christian Daudt wrote:
>>>
>>> This driver is being removed as part of the cleanup of the bcmring
>>> SoC from mainline as it is no longer maintained.
>>>   arch/arm/configs/bcmring_defconfig |    2 -
>>
>> Out of curiosity, if you're removing the whole thing, why edit the
>> defconfig at all; just delete it instead in whatever patch removes the
>> arch/arm parts?
>>
> I figured it'd be better to remove the config portion on this patch so it is
> self-contained - just in case the other patch gets held up for some reason
> then this one can still be applied and no junk would be left around. But
> agreed - it doesn't really affect things either way.

Just skip the defconfig update in this patch -- if the Kconfig option
goes away then the build system will just ignore it even if it's in
the defconfig. Also, if you touch it here and remove it in the other
patch you might end up getting a conflict due to the file removal when
things go upstream, which is just extra churn.


-Olof


From zajec5 at gmail.com  Wed Sep 12 16:21:12 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Wed, 12 Sep 2012 22:21:12 +0200
Subject: [PATCH 1/4] mtd: prepare place for BCMA NAND flash driver(s)
Message-ID: <1347481275-995-1-git-send-email-zajec5@gmail.com>

BCMA bus can contain NAND flash memory, it's registered in system as
platform device. This adds required hooks and place for controler
specific drivers.
At this point it doesn't work yet, so it's marked as BROKEN.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
 drivers/mtd/nand/Kconfig                       |    8 ++
 drivers/mtd/nand/Makefile                      |    1 +
 drivers/mtd/nand/bcm47xxnflash/Makefile        |    3 +
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |   14 +++
 drivers/mtd/nand/bcm47xxnflash/main.c          |  108 ++++++++++++++++++++++++
 5 files changed, 134 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/Makefile
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/main.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..7460ac2 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -489,6 +489,14 @@ config MTD_NAND_GPMI_NAND
 	 block, such as SD card. So pay attention to it when you enable
 	 the GPMI.
 
+config MTD_NAND_BCM47XXNFLASH
+	tristate "Support for NAND flash on BCMA bus"
+	depends on BCMA_NFLASH && BROKEN
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  NAND flash memories.
+
 config MTD_NAND_PLATFORM
 	tristate "Support for generic platform NAND driver"
 	depends on HAS_IOMEM
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..8aa55d8 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -51,5 +51,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
new file mode 100644
index 0000000..1d0693a
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -0,0 +1,3 @@
+bcm47xxnflash-y				+= main.o
+
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
new file mode 100644
index 0000000..2e8864a
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -0,0 +1,14 @@
+#ifndef __BCM47XXNFLASH_H
+#define __BCM47XXNFLASH_H
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+struct bcm47xxnflash {
+	struct bcma_drv_cc *cc;
+
+	struct nand_chip nand_chip;
+	struct mtd_info mtd;
+};
+
+#endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/main.c b/drivers/mtd/nand/bcm47xxnflash/main.c
new file mode 100644
index 0000000..fc9139d
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/main.c
@@ -0,0 +1,108 @@
+/*
+ * BCM47XX NAND flash driver
+ *
+ * Copyright (C) 2012 Rafa? Mi?ecki <zajec5 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+#include "bcm47xxnflash.h"
+
+MODULE_DESCRIPTION("NAND flash driver for BCMA bus");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Rafa? Mi?ecki");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxnflash_probe(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+	struct bcm47xxnflash *b47n;
+	int err = 0;
+
+	b47n = kzalloc(sizeof(*b47n), GFP_KERNEL);
+	if (!b47n) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	b47n->nand_chip.priv = b47n;
+	b47n->mtd.owner = THIS_MODULE;
+	b47n->mtd.priv = &b47n->nand_chip; /* Required */
+	b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash);
+
+	if (0) {
+		/* TODO: init device */
+	} else {
+		pr_err("Device not supported\n");
+		err = -ENOTSUPP;
+	}
+	if (err) {
+		pr_err("Initialization failed: %d\n", err);
+		goto err_init;
+	}
+
+	err = mtd_device_parse_register(&b47n->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		goto err_dev_reg;
+	}
+
+	return 0;
+
+err_dev_reg:
+err_init:
+	kfree(b47n);
+out:
+	return err;
+}
+
+static int __devexit bcm47xxnflash_remove(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+
+	if (nflash->mtd)
+		mtd_device_unregister(nflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcm47xxnflash_driver = {
+	.remove = __devexit_p(bcm47xxnflash_remove),
+	.driver = {
+		.name = "bcma_nflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxnflash_init(void)
+{
+	int err;
+
+	/*
+	 * Platform device "bcma_nflash" exists on SoCs and is registered very
+	 * early, it won't be added during runtime (use platform_driver_probe).
+	 */
+	err = platform_driver_probe(&bcm47xxnflash_driver, bcm47xxnflash_probe);
+	if (err)
+		pr_err("Failed to register serial flash driver: %d\n", err);
+
+	return err;
+}
+
+static void __exit bcm47xxnflash_exit(void)
+{
+	platform_driver_unregister(&bcm47xxnflash_driver);
+}
+
+module_init(bcm47xxnflash_init);
+module_exit(bcm47xxnflash_exit);
-- 
1.7.7



From zajec5 at gmail.com  Wed Sep 12 16:21:13 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Wed, 12 Sep 2012 22:21:13 +0200
Subject: [PATCH 2/4] mtd: bcm47xxnflash: init NAND on BCM4706
In-Reply-To: <1347481275-995-1-git-send-email-zajec5@gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347481275-995-2-git-send-email-zajec5@gmail.com>


Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
 drivers/mtd/nand/bcm47xxnflash/Makefile        |    1 +
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    2 +
 drivers/mtd/nand/bcm47xxnflash/main.c          |    4 +-
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c   |  110 ++++++++++++++++++++++++
 4 files changed, 115 insertions(+), 2 deletions(-)
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
index 1d0693a..f05b119 100644
--- a/drivers/mtd/nand/bcm47xxnflash/Makefile
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -1,3 +1,4 @@
 bcm47xxnflash-y				+= main.o
+bcm47xxnflash-y				+= ops_bcm4706.o
 
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index 2e8864a..149b74f 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -11,4 +11,6 @@ struct bcm47xxnflash {
 	struct mtd_info mtd;
 };
 
+int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *bcm47xxnflash);
+
 #endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/main.c b/drivers/mtd/nand/bcm47xxnflash/main.c
index fc9139d..2b8b05b 100644
--- a/drivers/mtd/nand/bcm47xxnflash/main.c
+++ b/drivers/mtd/nand/bcm47xxnflash/main.c
@@ -40,8 +40,8 @@ static int bcm47xxnflash_probe(struct platform_device *pdev)
 	b47n->mtd.priv = &b47n->nand_chip; /* Required */
 	b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash);
 
-	if (0) {
-		/* TODO: init device */
+	if (b47n->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
+		err = bcm47xxnflash_ops_bcm4706_init(b47n);
 	} else {
 		pr_err("Device not supported\n");
 		err = -ENOTSUPP;
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
new file mode 100644
index 0000000..38e3da6
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -0,0 +1,110 @@
+/*
+ * BCM47XX NAND flash driver
+ *
+ * Copyright (C) 2012 Rafa? Mi?ecki <zajec5 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/bcma/bcma.h>
+
+#include "bcm47xxnflash.h"
+
+/**************************************************
+ * Various helpers
+ **************************************************/
+
+static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
+{
+	return ((ns * 1000 * clock) / 1000000) + 1;
+}
+
+/**************************************************
+ * NAND chip ops
+ **************************************************/
+
+static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
+						  int chip)
+{
+	return;
+}
+
+/**************************************************
+ * Init
+ **************************************************/
+
+int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
+{
+	int err;
+	u32 freq;
+	u16 clock;
+	u8 w0, w1, w2, w3, w4;
+
+	unsigned long chipsize; /* MiB */
+	u8 tbits, col_bits, col_size, row_bits, row_bsize;
+	u32 col_mask;
+	u32 val;
+
+	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
+	b47n->nand_chip.ecc.mode = NAND_ECC_SOFT; /* TODO: implement ECC */
+
+	/* Enable NAND flash access */
+	bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
+		      BCMA_CC_4706_FLASHSCFG_NF1);
+
+	/* Configure wait counters */
+	if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
+		freq = 100000000;
+	} else {
+		freq = bcma_chipco_pll_read(b47n->cc, 4);
+		freq = (freq * 0xFFF) >> 3;
+		freq = (freq * 25000000) >> 3;
+	}
+	clock = freq / 1000000;
+	w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
+	w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
+	w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
+	w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
+	w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
+	bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
+			(w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
+
+	/* Scan NAND */
+	err = nand_scan(&b47n->mtd, 1);
+	if (err) {
+		pr_err("Could not scan NAND flash: %d\n", err);
+		goto exit;
+	}
+
+	/* Configure FLASH */
+	chipsize = b47n->nand_chip.chipsize >> 20;
+	tbits = ffs(chipsize); /* find first bit set */
+	if (!tbits || tbits != fls(chipsize)) {
+		pr_err("Invalid flash size: 0x%lX\n", chipsize);
+		err = -ENOTSUPP;
+		goto exit;
+	}
+	tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
+
+	col_bits = b47n->nand_chip.page_shift + 1;
+	col_mask = (1 << col_bits) - 1;
+	col_size = (col_bits + 7) / 8;
+
+	row_bits = tbits - col_bits + 1;
+	row_bsize = (row_bits + 7) / 8;
+
+	val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
+	bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
+
+exit:
+	if (err)
+		bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
+			       ~BCMA_CC_4706_FLASHSCFG_NF1);
+	return err;
+}
-- 
1.7.7



From zajec5 at gmail.com  Wed Sep 12 16:21:14 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Wed, 12 Sep 2012 22:21:14 +0200
Subject: [PATCH 3/4] mtd: bcm47xxnflash: support for NAND_CMD_READID command
In-Reply-To: <1347481275-995-1-git-send-email-zajec5@gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347481275-995-3-git-send-email-zajec5@gmail.com>


Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    5 ++
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c   |   90 ++++++++++++++++++++++++
 2 files changed, 95 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index 149b74f..53fb2ea 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -9,6 +9,11 @@ struct bcm47xxnflash {
 
 	struct nand_chip nand_chip;
 	struct mtd_info mtd;
+
+	unsigned curr_command;
+	int curr_column;
+
+	u8 id_data[8];
 };
 
 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *bcm47xxnflash);
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
index 38e3da6..e86670b 100644
--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -16,6 +16,10 @@
 
 #include "bcm47xxnflash.h"
 
+/* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
+ * shown 164 retries as maxiumum. */
+#define NFLASH_READY_RETRIES		1000
+
 /**************************************************
  * Various helpers
  **************************************************/
@@ -25,6 +29,24 @@ static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
 	return ((ns * 1000 * clock) / 1000000) + 1;
 }
 
+static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
+{
+	int i = 0;
+
+	bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, 0x80000000 | code);
+	for (i = 0; i < NFLASH_READY_RETRIES; i++) {
+		if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x80000000)) {
+			i = 0;
+			break;
+		}
+	}
+	if (i) {
+		pr_err("NFLASH control command not ready!\n");
+		return -EBUSY;
+	}
+	return 0;
+}
+
 /**************************************************
  * NAND chip ops
  **************************************************/
@@ -35,6 +57,72 @@ static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 	return;
 }
 
+static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
+					      unsigned command, int column,
+					      int page_addr)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+	u32 ctlcode;
+	int i;
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		pr_warn("Chip reset not implemented yet\n");
+		break;
+	case NAND_CMD_READID:
+		ctlcode = 0x40000000 | 0x01000000 | 0x00080000 | 0x00010000;
+		ctlcode |= NAND_CMD_READID;
+		if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
+			pr_err("READID error\n");
+			break;
+		}
+
+		/*
+		 * Reading is specific, last one has to go without 0x40000000
+		 * bit. We don't know how many reads NAND subsystem is going
+		 * to perform, so cache everything.
+		 */
+		for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
+			ctlcode = 0x40000000 | 0x00100000;
+			if (i == ARRAY_SIZE(b47n->id_data) - 1)
+				ctlcode &= ~0x40000000;
+			if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
+							      ctlcode)) {
+				pr_err("READID error\n");
+				break;
+			}
+			b47n->id_data[i] = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA) & 0xFF;
+		}
+
+		b47n->curr_column = 0;
+		break;
+	default:
+		pr_err("Command 0x%X unsupported\n", command);
+		break;
+	}
+	b47n->curr_command = command;
+}
+
+static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	switch (b47n->curr_command) {
+	case NAND_CMD_READID:
+		if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
+			pr_err("Requested invalid id_data: %d\n",
+			       b47n->curr_column);
+			return 0;
+		}
+		return b47n->id_data[b47n->curr_column++];
+	}
+
+	pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
+	return 0;
+}
+
 /**************************************************
  * Init
  **************************************************/
@@ -52,6 +140,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 	u32 val;
 
 	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
+	b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
+	b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 	b47n->nand_chip.ecc.mode = NAND_ECC_SOFT; /* TODO: implement ECC */
 
 	/* Enable NAND flash access */
-- 
1.7.7



From zajec5 at gmail.com  Wed Sep 12 16:21:15 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Wed, 12 Sep 2012 22:21:15 +0200
Subject: [PATCH 4/4] mtd: bcm47xxnflash: implement reading
In-Reply-To: <1347481275-995-1-git-send-email-zajec5@gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347481275-995-4-git-send-email-zajec5@gmail.com>


Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    1 +
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c   |  106 ++++++++++++++++++++++++
 2 files changed, 107 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index 53fb2ea..e1cfdc5 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -11,6 +11,7 @@ struct bcm47xxnflash {
 	struct mtd_info mtd;
 
 	unsigned curr_command;
+	int curr_page_addr;
 	int curr_column;
 
 	u8 id_data[8];
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
index e86670b..ca3eaf0 100644
--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -20,6 +20,8 @@
  * shown 164 retries as maxiumum. */
 #define NFLASH_READY_RETRIES		1000
 
+#define NFLASH_SECTOR_SIZE		512
+
 /**************************************************
  * Various helpers
  **************************************************/
@@ -47,6 +49,80 @@ static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
 	return 0;
 }
 
+static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
+{
+	int i;
+
+	for (i = 0; i < NFLASH_READY_RETRIES; i++) {
+		if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x04000000) {
+			if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
+			    BCMA_CC_NFLASH_CTL_ERR) {
+				pr_err("Error on polling\n");
+				return -EBUSY;
+			} else {
+				return 0;
+			}
+		}
+	}
+
+	pr_err("Polling timeout!\n");
+	return -EBUSY;
+}
+
+/**************************************************
+ * R/W
+ **************************************************/
+
+static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
+					   int len)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	u32 ctlcode;
+	u32 *dest = (u32 *)buf;
+	int i;
+	int toread;
+
+	BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
+	/* Don't validate column using nand_chip->page_shift, it may be bigger
+	 * when accessing OOB */
+
+	while (len) {
+		/* We can read maximum of 0x200 bytes at once */
+		toread = min(len, 0x200);
+
+		/* Set page and column */
+		bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
+				b47n->curr_column);
+		bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
+				b47n->curr_page_addr);
+
+		/* Prepare to read */
+		ctlcode = 0x40000000 | 0x00080000 | 0x00040000 | 0x00020000 |
+			  0x00010000;
+		ctlcode |= NAND_CMD_READSTART << 8;
+		if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
+			return;
+		if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
+			return;
+
+		/* Eventually read some data :) */
+		for (i = 0; i < toread; i += 4, dest++) {
+			ctlcode = 0x40000000 | 0x30000000 | 0x00100000;
+			if (i == toread - 4) /* Last read goes without that */
+				ctlcode &= ~0x40000000;
+			if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
+							      ctlcode))
+				return;
+			*dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
+		}
+
+		b47n->curr_column += toread;
+		len -= toread;
+	}
+}
+
 /**************************************************
  * NAND chip ops
  **************************************************/
@@ -97,6 +173,14 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 
 		b47n->curr_column = 0;
 		break;
+	case NAND_CMD_READ0:
+		b47n->curr_page_addr = page_addr;
+		b47n->curr_column = column;
+		break;
+	case NAND_CMD_READOOB:
+		b47n->curr_page_addr = page_addr;
+		b47n->curr_column = mtd->writesize + column;
+		break;
 	default:
 		pr_err("Command 0x%X unsupported\n", command);
 		break;
@@ -108,6 +192,7 @@ static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+	u32 tmp = 0;
 
 	switch (b47n->curr_command) {
 	case NAND_CMD_READID:
@@ -117,12 +202,31 @@ static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 			return 0;
 		}
 		return b47n->id_data[b47n->curr_column++];
+	case NAND_CMD_READOOB:
+		bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
+		return tmp & 0xFF;
 	}
 
 	pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 	return 0;
 }
 
+static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
+					       uint8_t *buf, int len)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	switch (b47n->curr_command) {
+	case NAND_CMD_READ0:
+	case NAND_CMD_READOOB:
+		bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
+		return;
+	}
+
+	pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
+}
+
 /**************************************************
  * Init
  **************************************************/
@@ -142,6 +246,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 	b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 	b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
+	b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
+	b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 	b47n->nand_chip.ecc.mode = NAND_ECC_SOFT; /* TODO: implement ECC */
 
 	/* Enable NAND flash access */
-- 
1.7.7



From csd at broadcom.com  Thu Sep 13 02:27:02 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 23:27:02 -0700
Subject: [PATCH v2 1/2] ARM: Remove bcmring NAND driver
Message-ID: <50517CB6.5040104@broadcom.com>

This driver is being removed as part of the cleanup of the bcmring
SoC from mainline as it is no longer maintained.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
Acked-by: Will Deacon <will.deacon at arm.com>
---
  MAINTAINERS                     |    9 -
  drivers/mtd/nand/Kconfig        |   16 --
  drivers/mtd/nand/Makefile       |    1 -
  drivers/mtd/nand/bcm_umi_bch.c  |  217 ---------------
  drivers/mtd/nand/bcm_umi_nand.c |  555 
---------------------------------------
  drivers/mtd/nand/nand_bcm_umi.c |  149 -----------
  drivers/mtd/nand/nand_bcm_umi.h |  337 ------------------------
  7 files changed, 0 insertions(+), 1284 deletions(-)
  delete mode 100644 drivers/mtd/nand/bcm_umi_bch.c
  delete mode 100644 drivers/mtd/nand/bcm_umi_nand.c
  delete mode 100644 drivers/mtd/nand/nand_bcm_umi.c
  delete mode 100644 drivers/mtd/nand/nand_bcm_umi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..36da5f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -665,15 +665,6 @@ L:	linux-arm-kernel at lists.infradead.org (moderated
for non-subscribers)
  S:	Maintained
  F:	arch/arm/mach-bcmring
  -ARM/BCMRING MTD NAND DRIVER
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-mtd at lists.infradead.org
-S:	Maintained
-F:	drivers/mtd/nand/bcm_umi_nand.c
-F:	drivers/mtd/nand/bcm_umi_bch.c
-F:	drivers/mtd/nand/nand_bcm_umi.h
-
  ARM/CALXEDA HIGHBANK ARCHITECTURE
  M:	Rob Herring <rob.herring at calxeda.com>
  L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..5c60a44 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -267,22 +267,6 @@ config MTD_NAND_S3C2410_CLKSTOP
  	  when the is NAND chip selected or released, but will save
  	  approximately 5mA of power when there is nothing happening.
  -config MTD_NAND_BCM_UMI
-	tristate "NAND Flash support for BCM Reference Boards"
-	depends on ARCH_BCMRING
-	help
-	  This enables the NAND flash controller on the BCM UMI block.
-
-	  No board specific support is done by this driver, each board
-	  must advertise a platform_device for the driver to attach.
-
-config MTD_NAND_BCM_UMI_HWCS
-	bool "BCM UMI NAND Hardware CS"
-	depends on MTD_NAND_BCM_UMI
-	help
-	  Enable the use of the BCM UMI block's internal CS using NAND.
-	  This should only be used if you know the external NAND CS can toggle.
-
  config MTD_NAND_DISKONCHIP
  	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND
reimplementation) (EXPERIMENTAL)"
  	depends on EXPERIMENTAL
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..8b2825a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
  obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
  obj-$(CONFIG_MTD_NAND_NUC900)		+= nuc900_nand.o
  obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
-obj-$(CONFIG_MTD_NAND_BCM_UMI)		+= bcm_umi_nand.o nand_bcm_umi.o
  obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
  obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
  obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
deleted file mode 100644
index 5914bb3..0000000
--- a/drivers/mtd/nand/bcm_umi_bch.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files
---------------------------------------------------- */
-#include "nand_bcm_umi.h"
-
-/* ---- External Variable Declarations
----------------------------------- */
-/* ---- External Function Prototypes
------------------------------------- */
-/* ---- Public Variables
------------------------------------------------- */
-/* ---- Private Constants and Types
-------------------------------------- */
-
-/* ---- Private Function Prototypes
-------------------------------------- */
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required);
-
-/* ---- Private Variables
------------------------------------------------ */
-
-/*
-** nand_hw_eccoob
-** New oob placement block for use with hardware ecc generation.
-*/
-static struct nand_ecclayout nand_hw_eccoob_512 = {
-	/* Reserve 5 for BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 3)
-		    {.offset = 0, .length = 2}
-#else
-		    {.offset = 0, .length = 5},
-		    {.offset = 6, .length = 7}
-#endif
-		    }
-};
-
-/*
-** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
-** except the BI is at byte 0.
-*/
-static struct nand_ecclayout nand_hw_eccoob_2048 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-#elif (NAND_ECC_NUM_BYTES > 7)
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6}
-#else
-		    {.offset = 1, .length = 8},
-		    {.offset = 16, .length = 9},
-		    {.offset = 32, .length = 9},
-		    {.offset = 48, .length = 9}
-#endif
-		    }
-};
-
-/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
- * except the BI is at byte 0. */
-static struct nand_ecclayout nand_hw_eccoob_4096 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-		    {.offset = 16, .length = 3},
-		    {.offset = 32, .length = 3},
-		    {.offset = 48, .length = 3},
-		    {.offset = 64, .length = 3},
-		    {.offset = 80, .length = 3},
-		    {.offset = 96, .length = 3},
-		    {.offset = 112, .length = 3}
-#else
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6},
-		    {.offset = 64, .length = 6},
-		    {.offset = 80, .length = 6},
-		    {.offset = 96, .length = 6},
-		    {.offset = 112, .length = 6}
-#endif
-		    }
-};
-
-/* ---- Private Functions
------------------------------------------------ */
-/* ==== Public Functions
================================================= */
-
-/****************************************************************************
-*
-*  bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	buffer to store read data
-*  @oob_required:	caller expects OOB data read to chip->oob_poi
-*
-***************************************************************************/
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-				       struct nand_chip *chip, uint8_t * buf,
-				       int oob_required, int page)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	uint8_t *datap = buf;
-	uint8_t eccCalc[NAND_ECC_NUM_BYTES];
-	int sectorOobSize = mtd->oobsize / eccsteps;
-	int stat;
-	unsigned int max_bitflips = 0;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-			sectorIdx++, datap += eccsize) {
-		if (sectorIdx > 0) {
-			/* Seek to page location within sector */
-			chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
-				      -1);
-		}
-
-		/* Enable hardware ECC before reading the buf */
-		nand_bcm_umi_bch_enable_read_hwecc();
-
-		/* Read in data */
-		bcm_umi_nand_read_buf(mtd, datap, eccsize);
-
-		/* Pause hardware ECC after reading the buf */
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		/* Read the OOB ECC */
-		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
-			      mtd->writesize + sectorIdx * sectorOobSize, -1);
-		nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
-					     NAND_ECC_NUM_BYTES,
-					     chip->oob_poi +
-					     sectorIdx * sectorOobSize);
-
-		/* Correct any ECC detected errors */
-		stat =
-		    nand_bcm_umi_bch_correct_page(datap, eccCalc,
-						  NAND_ECC_NUM_BYTES);
-
-		/* Update Stats */
-		if (stat < 0) {
-#if defined(NAND_BCM_UMI_DEBUG)
-			printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
-			       __func__, sectorIdx);
-			printk(KERN_WARNING
-			       "%s data %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x\n",
-			       __func__, datap[0], datap[1], datap[2], datap[3],
-			       datap[4], datap[5], datap[6], datap[7]);
-			printk(KERN_WARNING
-			       "%s ecc  %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x %02x %02x "
-					 "%02x %02x %02x\n",
-			       __func__, eccCalc[0], eccCalc[1], eccCalc[2],
-			       eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
-			       eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
-			       eccCalc[11], eccCalc[12]);
-			BUG();
-#endif
-			mtd->ecc_stats.failed++;
-		} else {
-#if defined(NAND_BCM_UMI_DEBUG)
-			if (stat > 0) {
-				printk(KERN_INFO
-				       "%s %d correctable_errors detected\n",
-				       __func__, stat);
-			}
-#endif
-			mtd->ecc_stats.corrected += stat;
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
-		}
-	}
-	return max_bitflips;
-}
-
-/****************************************************************************
-*
-*  bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	data buffer
-*  @oob_required:	must write chip->oob_poi to OOB
-*
-***************************************************************************/
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	const uint8_t *datap = buf;
-	uint8_t *oobp = chip->oob_poi;
-	int sectorOobSize = mtd->oobsize / eccsteps;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-	     sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
-		/* Enable hardware ECC before writing the buf */
-		nand_bcm_umi_bch_enable_write_hwecc();
-		bcm_umi_nand_write_buf(mtd, datap, eccsize);
-		nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
-					      NAND_ECC_NUM_BYTES);
-	}
-
-	bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
-}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c
b/drivers/mtd/nand/bcm_umi_nand.c
deleted file mode 100644
index c855e7c..0000000
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files
---------------------------------------------------- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/reg_nand.h>
-#include <mach/reg_umi.h>
-
-#include "nand_bcm_umi.h"
-
-#include <mach/memory_settings.h>
-
-#define USE_DMA 1
-#include <mach/dma.h>
-#include <linux/dma-mapping.h>
-#include <linux/completion.h>
-
-/* ---- External Variable Declarations
----------------------------------- */
-/* ---- External Function Prototypes
------------------------------------- */
-/* ---- Public Variables
------------------------------------------------- */
-/* ---- Private Constants and Types
-------------------------------------- */
-static const __devinitconst char gBanner[] = KERN_INFO \
-	"BCM UMI MTD NAND Driver: 1.00\n";
-
-#if NAND_ECC_BCH
-static uint8_t scan_ff_pattern[] = { 0xff };
-
-static struct nand_bbt_descr largepage_bbt = {
-	.options = 0,
-	.offs = 0,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-#endif
-
-/*
-** Preallocate a buffer to avoid having to do this every dma operation.
-** This is the size of the preallocated coherent DMA buffer.
-*/
-#if USE_DMA
-#define DMA_MIN_BUFLEN	512
-#define DMA_MAX_BUFLEN	PAGE_SIZE
-#define USE_DIRECT_IO(len)	(((len) < DMA_MIN_BUFLEN) || \
-	((len) > DMA_MAX_BUFLEN))
-
-/*
- * The current NAND data space goes from 0x80001900 to 0x80001FFF,
- * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
- * size NAND flash. Need to break the DMA down to multiple 1Ks.
- *
- * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
- */
-#define DMA_MAX_LEN             1024
-
-#else /* !USE_DMA */
-#define DMA_MIN_BUFLEN          0
-#define DMA_MAX_BUFLEN          0
-#define USE_DIRECT_IO(len)      1
-#endif
-/* ---- Private Function Prototypes
-------------------------------------- */
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf,
int len);
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char *
buf,
-				   int len);
-
-/* ---- Private Variables
------------------------------------------------ */
-static struct mtd_info *board_mtd;
-static void __iomem *bcm_umi_io_base;
-static void *virtPtr;
-static dma_addr_t physPtr;
-static struct completion nand_comp;
-
-/* ---- Private Functions
------------------------------------------------ */
-#if NAND_ECC_BCH
-#include "bcm_umi_bch.c"
-#else
-#include "bcm_umi_hamming.c"
-#endif
-
-#if USE_DMA
-
-/* Handler called when the DMA finishes. */
-static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
-{
-	complete(&nand_comp);
-}
-
-static int nand_dma_init(void)
-{
-	int rc;
-
-	rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
-		nand_dma_handler, NULL);
-	if (rc != 0) {
-		printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
-		return rc;
-	}
-
-	virtPtr =
-	    dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
-	if (virtPtr == NULL) {
-		printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void nand_dma_term(void)
-{
-	if (virtPtr != NULL)
-		dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
-}
-
-static void nand_dma_read(void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (virtPtr == NULL)
-		panic("nand_dma_read: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_read: physPtr == NULL\n");
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_read: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
-					physPtr + offset, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-
-	if (buf != NULL)
-		memcpy(buf, virtPtr, len);
-}
-
-static void nand_dma_write(const void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (buf == NULL)
-		panic("nand_dma_write: buf == NULL\n");
-
-	if (virtPtr == NULL)
-		panic("nand_dma_write: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_write: physPtr == NULL\n");
-
-	memcpy(virtPtr, buf, len);
-
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_write: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, physPtr + offset,
-					REG_NAND_DATA_PADDR, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-}
-
-#endif
-
-static int nand_dev_ready(struct mtd_info *mtd)
-{
-	return nand_bcm_umi_dev_ready();
-}
-
-/****************************************************************************
-*
-*  bcm_umi_nand_inithw
-*
-*   This routine does the necessary hardware (board-specific)
-*   initializations.  This includes setting up the timings, etc.
-*
-***************************************************************************/
-int bcm_umi_nand_inithw(void)
-{
-	/* Configure nand timing parameters */
-	REG_UMI_NAND_TCR &= ~0x7ffff;
-	REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
-
-#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
-	/* enable software control of CS */
-	REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
-#endif
-
-	/* keep NAND chip select asserted */
-	REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
-
-	REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
-	/* enable writes to flash */
-	REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
-
-	writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
-	nand_bcm_umi_wait_till_ready();
-
-#if NAND_ECC_BCH
-	nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
-#endif
-
-	return 0;
-}
-
-/* Used to turn latch the proper register for access. */
-static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
-				   unsigned int ctrl)
-{
-	/* send command to hardware */
-	struct nand_chip *chip = mtd->priv;
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if (ctrl & NAND_CLE) {
-			chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
-			goto CMD;
-		}
-		if (ctrl & NAND_ALE) {
-			chip->IO_ADDR_W =
-			    bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
-			goto CMD;
-		}
-		chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	}
-
-CMD:
-	/* Send command to chip directly */
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, chip->IO_ADDR_W);
-}
-
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char *
buf,
-				   int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		/* Do it the old way if the buffer is small or too large.
-		 * Probably quicker than starting and checking dma. */
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			writeb(buf[i], this->IO_ADDR_W);
-	}
-#if USE_DMA
-	else
-		nand_dma_write(buf, len);
-#endif
-}
-
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf,
int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			buf[i] = readb(this->IO_ADDR_R);
-	}
-#if USE_DMA
-	else
-		nand_dma_read(buf, len);
-#endif
-}
-
-static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
-static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char *
buf,
-				   int len)
-{
-	/*
-	 * Try to readback page with ECC correction. This is necessary
-	 * for MLC parts which may have permanently stuck bits.
-	 */
-	struct nand_chip *chip = mtd->priv;
-	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
-	if (ret < 0)
-		return -EFAULT;
-	else {
-		if (memcmp(readbackbuf, buf, len) == 0)
-			return 0;
-
-		return -EFAULT;
-	}
-	return 0;
-}
-
-static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
-{
-	struct nand_chip *this;
-	struct resource *r;
-	int err = 0;
-
-	printk(gBanner);
-
-	/* Allocate memory for MTD device structure and private data */
-	board_mtd =
-	    kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
-		    GFP_KERNEL);
-	if (!board_mtd) {
-		printk(KERN_WARNING
-		       "Unable to allocate NAND MTD device structure.\n");
-		return -ENOMEM;
-	}
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	if (!r) {
-		err = -ENXIO;
-		goto out_free;
-	}
-
-	/* map physical address */
-	bcm_umi_io_base = ioremap(r->start, resource_size(r));
-
-	if (!bcm_umi_io_base) {
-		printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
-		err = -EIO;
-		goto out_free;
-	}
-
-	/* Get pointer to private data */
-	this = (struct nand_chip *)(&board_mtd[1]);
-
-	/* Initialize structures */
-	memset((char *)board_mtd, 0, sizeof(struct mtd_info));
-	memset((char *)this, 0, sizeof(struct nand_chip));
-
-	/* Link the private data with the MTD structure */
-	board_mtd->priv = this;
-
-	/* Initialize the NAND hardware.  */
-	if (bcm_umi_nand_inithw() < 0) {
-		printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
-		err = -EIO;
-		goto out_unmap;
-	}
-
-	/* Set address of NAND IO lines */
-	this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-
-	/* Set command delay time, see datasheet for correct value */
-	this->chip_delay = 0;
-	/* Assign the device ready function, if available */
-	this->dev_ready = nand_dev_ready;
-	this->options = 0;
-
-	this->write_buf = bcm_umi_nand_write_buf;
-	this->read_buf = bcm_umi_nand_read_buf;
-	this->verify_buf = bcm_umi_nand_verify_buf;
-
-	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
-	this->ecc.mode = NAND_ECC_HW;
-	this->ecc.size = 512;
-	this->ecc.bytes = NAND_ECC_NUM_BYTES;
-#if NAND_ECC_BCH
-	this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
-	this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
-#else
-	this->ecc.correct = nand_correct_data512;
-	this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
-	this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
-#endif
-
-#if USE_DMA
-	err = nand_dma_init();
-	if (err != 0)
-		goto out_unmap;
-#endif
-
-	/* Figure out the size of the device that we have.
-	 * We need to do this to figure out which ECC
-	 * layout we'll be using.
-	 */
-
-	err = nand_scan_ident(board_mtd, 1, NULL);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Now that we know the nand size, we can setup the ECC layout */
-
-	switch (board_mtd->writesize) {	/* writesize is the pagesize */
-	case 4096:
-		this->ecc.layout = &nand_hw_eccoob_4096;
-		break;
-	case 2048:
-		this->ecc.layout = &nand_hw_eccoob_2048;
-		break;
-	case 512:
-		this->ecc.layout = &nand_hw_eccoob_512;
-		break;
-	default:
-		{
-			printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
-					 board_mtd->writesize);
-			err = -EINVAL;
-			goto out_unmap;
-		}
-	}
-
-#if NAND_ECC_BCH
-	if (board_mtd->writesize > 512) {
-		if (this->bbt_options & NAND_BBT_USE_FLASH)
-			largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
-		this->badblock_pattern = &largepage_bbt;
-	}
-
-	this->ecc.strength = 8;
-
-#endif
-
-	/* Now finish off the scan, now that ecc.layout has been initialized. */
-
-	err = nand_scan_tail(board_mtd);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Register the partitions */
-	board_mtd->name = "bcm_umi-nand";
-	mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
-
-	/* Return happy */
-	return 0;
-out_unmap:
-	iounmap(bcm_umi_io_base);
-out_free:
-	kfree(board_mtd);
-	return err;
-}
-
-static int bcm_umi_nand_remove(struct platform_device *pdev)
-{
-#if USE_DMA
-	nand_dma_term();
-#endif
-
-	/* Release resources, unregister device */
-	nand_release(board_mtd);
-
-	/* unmap physical address */
-	iounmap(bcm_umi_io_base);
-
-	/* Free the MTD device structure */
-	kfree(board_mtd);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static int bcm_umi_nand_suspend(struct platform_device *pdev,
-				pm_message_t state)
-{
-	printk(KERN_ERR "MTD NAND suspend is being called\n");
-	return 0;
-}
-
-static int bcm_umi_nand_resume(struct platform_device *pdev)
-{
-	printk(KERN_ERR "MTD NAND resume is being called\n");
-	return 0;
-}
-#else
-#define bcm_umi_nand_suspend   NULL
-#define bcm_umi_nand_resume    NULL
-#endif
-
-static struct platform_driver nand_driver = {
-	.driver = {
-		   .name = "bcm-nand",
-		   .owner = THIS_MODULE,
-		   },
-	.probe = bcm_umi_nand_probe,
-	.remove = bcm_umi_nand_remove,
-	.suspend = bcm_umi_nand_suspend,
-	.resume = bcm_umi_nand_resume,
-};
-
-module_platform_driver(nand_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Broadcom");
-MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/nand_bcm_umi.c
b/drivers/mtd/nand/nand_bcm_umi.c
deleted file mode 100644
index 46a6bc9..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files
---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include "nand_bcm_umi.h"
-#ifdef BOOT0_BUILD
-#include <uart.h>
-#endif
-
-/* ---- External Variable Declarations
----------------------------------- */
-/* ---- External Function Prototypes
------------------------------------- */
-/* ---- Public Variables
------------------------------------------------- */
-/* ---- Private Constants and Types
-------------------------------------- */
-/* ---- Private Function Prototypes
-------------------------------------- */
-/* ---- Private Variables
------------------------------------------------ */
-/* ---- Private Functions
------------------------------------------------ */
-
-#if NAND_ECC_BCH
-/****************************************************************************
-*  nand_bch_ecc_flip_bit - Routine to flip an errored bit
-*
-*  PURPOSE:
-*     This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
-*     errored bit specified
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*     errorLocation - Location of the bit that needs to be flipped
-*
-*  RETURNS:
-*     None
-****************************************************************************/
-static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int
errorLocation)
-{
-	int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
-	int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
-	int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
-
-	uint8_t errorByte = 0;
-	uint8_t byteMask = 1 << locWithinAByte;
-
-	/* BCH uses big endian, need to change the location
-	 * bits to little endian */
-	locWithinAWord = 3 - locWithinAWord;
-
-	errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
-
-#ifdef BOOT0_BUILD
-	puthexs("\nECC Correct Offset: ",
-		locWithinAPage * sizeof(uint32_t) + locWithinAWord);
-	puthexs(" errorByte:", errorByte);
-	puthex8(" Bit: ", locWithinAByte);
-#endif
-
-	if (errorByte & byteMask) {
-		/* bit needs to be cleared */
-		errorByte &= ~byteMask;
-	} else {
-		/* bit needs to be set */
-		errorByte |= byteMask;
-	}
-
-	/* write back the value with the fixed bit */
-	datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
-}
-
-/****************************************************************************
-*  nand_correct_page_bch - Routine to correct bit errors when reading NAND
-*
-*  PURPOSE:
-*     This routine reads the BCH registers to determine if there are
any bit
-*     errors during the read of the last 512 bytes of data + ECC bytes.  If
-*     errors exists, the routine fixes it.
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*
-*  RETURNS:
-*     0 or greater = Number of errors corrected
-*                    (No errors are found or errors have been fixed)
-*    -1 = Error(s) cannot be fixed
-****************************************************************************/
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes)
-{
-	int numErrors;
-	int errorLocation;
-	int idx;
-	uint32_t regValue;
-
-	/* wait for read ECC to be valid */
-	regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
-
-	/*
-	 * read the control status register to determine if there
-	 * are error'ed bits
-	 * see if errors are correctible
-	 */
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
-		int i;
-
-		for (i = 0; i < numEccBytes; i++) {
-			if (readEccData[i] != 0xff) {
-				/* errors cannot be fixed, return -1 */
-				return -1;
-			}
-		}
-		/* If ECC is unprogrammed then we can't correct,
-		 * assume everything OK */
-		return 0;
-	}
-
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
-		/* no errors */
-		return 0;
-	}
-
-	/*
-	 * Fix errored bits by doing the following:
-	 * 1. Read the number of errors in the control and status register
-	 * 2. Read the error location registers that corresponds to the number
-	 *    of errors reported
-	 * 3. Invert the bit in the data
-	 */
-	numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
-
-	for (idx = 0; idx < numErrors; idx++) {
-		errorLocation =
-		    REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
-
-		/* Flip bit */
-		nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
-	}
-	/* Errors corrected */
-	return numErrors;
-}
-#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h
b/drivers/mtd/nand/nand_bcm_umi.h
deleted file mode 100644
index 198b304..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef NAND_BCM_UMI_H
-#define NAND_BCM_UMI_H
-
-/* ---- Include Files
---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include <mach/reg_nand.h>
-#include <cfg_global.h>
-
-/* ---- Constants and Types
---------------------------------------------- */
-#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
-#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
-#else
-#define NAND_ECC_BCH 0
-#endif
-
-#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES	13
-
-#if NAND_ECC_BCH
-#ifdef BOOT0_BUILD
-#define NAND_ECC_NUM_BYTES 13
-#else
-#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
-#endif
-#else
-#define NAND_ECC_NUM_BYTES 3
-#endif
-
-#define NAND_DATA_ACCESS_SIZE 512
-
-/* ---- Variable Externs ------------------------------------------ */
-/* ---- Function Prototypes --------------------------------------- */
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes);
-
-/* Check in device is ready */
-static inline int nand_bcm_umi_dev_ready(void)
-{
-	return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
-}
-
-/* Wait until device is ready */
-static inline void nand_bcm_umi_wait_till_ready(void)
-{
-	while (nand_bcm_umi_dev_ready() == 0)
-		;
-}
-
-/* Enable Hamming ECC */
-static inline void nand_bcm_umi_hamming_enable_hwecc(void)
-{
-	/* disable and reset ECC, 512 byte page */
-	REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-		REG_UMI_NAND_ECC_CSR_256BYTE);
-	/* enable ECC */
-	REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
-}
-
-#if NAND_ECC_BCH
-/* BCH ECC specifics */
-#define ECC_BITS_PER_CORRECTABLE_BIT 13
-
-/* Enable BCH Read ECC */
-static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Enable BCH Write ECC */
-static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
-}
-
-/* Config number of BCH ECC bytes */
-static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
-{
-	uint32_t nValue;
-	uint32_t tValue;
-	uint32_t kValue;
-	uint32_t numBits = numEccBytes * 8;
-
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-	    REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-
-	/* Every correctible bit requires 13 ECC bits */
-	tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Total data in number of bits for generating and computing BCH ECC */
-	nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
-
-	/* K parameter is used internally.  K = N - (T * 13) */
-	kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Write the settings */
-	REG_UMI_BCH_N = nValue;
-	REG_UMI_BCH_T = tValue;
-	REG_UMI_BCH_K = kValue;
-}
-
-/* Pause during ECC read calculation to skip bytes in OOB */
-static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-	    REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
-}
-
-/* Resume during ECC read calculation after skipping bytes in OOB */
-static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Poll read ECC calc to check when hardware completes */
-static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
-{
-	uint32_t regVal;
-
-	do {
-		/* wait for ECC to be valid */
-		regVal = REG_UMI_BCH_CTRL_STATUS;
-	} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
-
-	return regVal;
-}
-
-/* Poll write ECC calc to check when hardware completes */
-static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
-{
-	/* wait for ECC to be valid */
-	while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
-	       == 0)
-		;
-}
-
-/* Read the OOB and ECC, for kernel write OOB to a buffer */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
-#else
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes)
-#endif
-{
-	int eccPos = 0;
-	int numToRead = 16;	/* There are 16 bytes per sector in the OOB */
-
-	/* ECC is already paused when this function is called */
-	if (pageSize != NAND_DATA_ACCESS_SIZE) {
-		/* skip BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	while (numToRead > numEccBytes) {
-		/* skip free oob region */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* read ECC bytes before BI */
-		nand_bcm_umi_bch_resume_read_ecc_calc();
-
-		while (numToRead > 11) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp = REG_NAND_DATA8;
-			eccCalc[eccPos++] = *oobp;
-			oobp++;
-#else
-			eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		if (numToRead == 11) {
-			/* read BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp++ = REG_NAND_DATA8;
-#else
-			REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-	}
-	/* read ECC bytes */
-	nand_bcm_umi_bch_resume_read_ecc_calc();
-	while (numToRead) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp = REG_NAND_DATA8;
-		eccCalc[eccPos++] = *oobp;
-		oobp++;
-#else
-		eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-}
-
-/* Helper function to write ECC */
-static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
-					  uint8_t *oobp, uint8_t eccVal)
-{
-	if (eccBytePos <= numEccBytes)
-		*oobp = eccVal;
-}
-
-/* Write OOB with ECC */
-static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
-						 uint8_t *oobp, int numEccBytes)
-{
-	uint32_t eccVal = 0xffffffff;
-
-	/* wait for write ECC to be valid */
-	nand_bcm_umi_bch_poll_write_ecc_calc();
-
-	/*
-	 ** Get the hardware ecc from the 32-bit result registers.
-	 ** Read after 512 byte accesses. Format B3B2B1B0
-	 ** where B3 = ecc3, etc.
-	 */
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually we skip CM in oob[0,1] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[2,3,4] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
-			eccVal & 0xff);	/* ECC 12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-
-		/* Always Skip BI in oob[5] */
-	} else {
-		/* Always Skip BI in oob[0] */
-
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually skip CM in oob[1,2] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[3-15] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
-			eccVal & 0xff);	/* ECC12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-	}
-
-	/* Fill in the remainder of ECC locations */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
-		(eccVal >> 8) & 0xff);	/* ECC9 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
-		eccVal & 0xff);	/* ECC8 */
-
-	if (numEccBytes >= 5)
-		eccVal = REG_UMI_BCH_WR_ECC_1;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
-		(eccVal >> 24) & 0xff);	/* ECC7 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
-		(eccVal >> 16) & 0xff);	/* ECC6 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
-		(eccVal >> 8) & 0xff);	/* ECC5 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
-		eccVal & 0xff);	/* ECC4 */
-
-	if (numEccBytes >= 1)
-		eccVal = REG_UMI_BCH_WR_ECC_0;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
-		(eccVal >> 24) & 0xff);	/* ECC3 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
-		(eccVal >> 16) & 0xff);	/* ECC2 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
-		(eccVal >> 8) & 0xff);	/* ECC1 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
-		eccVal & 0xff);	/* ECC0 */
-}
-#endif
-
-#endif /* NAND_BCM_UMI_H */
-- 
1.7.1




From csd at broadcom.com  Thu Sep 13 02:30:22 2012
From: csd at broadcom.com (Christian Daudt)
Date: Wed, 12 Sep 2012 23:30:22 -0700
Subject: [PATCH v2 2/2] ARM: Remove mach-bcmring
Message-ID: <50517D7E.5030406@broadcom.com>

Remove mach-bcmring as this is no longer maintained or used.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
---
  MAINTAINERS                                        |    7 -
  arch/arm/Kconfig                                   |   14 -
  arch/arm/Makefile                                  |    1 -
  arch/arm/configs/bcmring_defconfig                 |   79 -
  arch/arm/mach-bcmring/Kconfig                      |   19 -
  arch/arm/mach-bcmring/Makefile                     |    8 -
  arch/arm/mach-bcmring/Makefile.boot                |    6 -
  arch/arm/mach-bcmring/arch.c                       |  199 ---
  arch/arm/mach-bcmring/clock.c                      |  223 ---
  arch/arm/mach-bcmring/clock.h                      |   33 -
  arch/arm/mach-bcmring/core.c                       |  228 ---
  arch/arm/mach-bcmring/core.h                       |   31 -
  arch/arm/mach-bcmring/csp/Makefile                 |    3 -
  arch/arm/mach-bcmring/csp/chipc/Makefile           |    1 -
  arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |  776 ---------
  arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |  293 ----
  arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |  124 --
  arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |   64 -
  arch/arm/mach-bcmring/csp/dmac/Makefile            |    1 -
  arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |  917 -----------
  arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      | 1017 ------------
  arch/arm/mach-bcmring/csp/tmr/Makefile             |    1 -
  arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |  576 -------
  arch/arm/mach-bcmring/dma.c                        | 1518 
------------------
  arch/arm/mach-bcmring/dma_device.c                 |  593 -------
  arch/arm/mach-bcmring/include/cfg_global.h         |   13 -
  arch/arm/mach-bcmring/include/cfg_global_defines.h |   40 -
  arch/arm/mach-bcmring/include/csp/cache.h          |   35 -
  arch/arm/mach-bcmring/include/csp/delay.h          |   36 -
  arch/arm/mach-bcmring/include/csp/dmacHw.h         |  596 -------
  arch/arm/mach-bcmring/include/csp/errno.h          |   32 -
  arch/arm/mach-bcmring/include/csp/intcHw.h         |   40 -
  arch/arm/mach-bcmring/include/csp/module.h         |   32 -
  arch/arm/mach-bcmring/include/csp/reg.h            |  114 --
  arch/arm/mach-bcmring/include/csp/secHw.h          |   65 -
  arch/arm/mach-bcmring/include/csp/stdint.h         |   30 -
  arch/arm/mach-bcmring/include/csp/string.h         |   34 -
  arch/arm/mach-bcmring/include/csp/tmrHw.h          |  263 ---
  arch/arm/mach-bcmring/include/mach/csp/cap.h       |   63 -
  .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
  .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
  .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 
--------------------
  .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
  arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
  .../mach-bcmring/include/mach/csp/dmacHw_priv.h    |  145 --
  .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
  arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
  .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
  arch/arm/mach-bcmring/include/mach/csp/mm_addr.h   |  101 --
  arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
  arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
  .../mach-bcmring/include/mach/csp/secHw_inline.h   |   79 -
  arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
  arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
  arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
  arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
  arch/arm/mach-bcmring/include/mach/irqs.h          |  132 --
  .../mach-bcmring/include/mach/memory_settings.h    |   67 -
  arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
  arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
  arch/arm/mach-bcmring/include/mach/timer.h         |   77 -
  arch/arm/mach-bcmring/include/mach/timex.h         |   25 -
  arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
  arch/arm/mach-bcmring/irq.c                        |  126 --
  arch/arm/mach-bcmring/mm.c                         |   60 -
  arch/arm/mach-bcmring/timer.c                      |   61 -
  66 files changed, 0 insertions(+), 15768 deletions(-)
  delete mode 100644 arch/arm/configs/bcmring_defconfig
  delete mode 100644 arch/arm/mach-bcmring/Kconfig
  delete mode 100644 arch/arm/mach-bcmring/Makefile
  delete mode 100644 arch/arm/mach-bcmring/Makefile.boot
  delete mode 100644 arch/arm/mach-bcmring/arch.c
  delete mode 100644 arch/arm/mach-bcmring/clock.c
  delete mode 100644 arch/arm/mach-bcmring/clock.h
  delete mode 100644 arch/arm/mach-bcmring/core.c
  delete mode 100644 arch/arm/mach-bcmring/core.h
  delete mode 100644 arch/arm/mach-bcmring/csp/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/tmrHw.c
  delete mode 100644 arch/arm/mach-bcmring/dma.c
  delete mode 100644 arch/arm/mach-bcmring/dma_device.c
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
  delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/irqs.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/memory_settings.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timer.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timex.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
  delete mode 100644 arch/arm/mach-bcmring/irq.c
  delete mode 100644 arch/arm/mach-bcmring/mm.c
  delete mode 100644 arch/arm/mach-bcmring/timer.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 36da5f9..a4b166c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,13 +658,6 @@ W:	http://www.linux4sam.org
  S:	Supported
  F:	arch/arm/mach-at91/
  -ARM/BCMRING ARM ARCHITECTURE
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
-S:	Maintained
-F:	arch/arm/mach-bcmring
-
  ARM/CALXEDA HIGHBANK ARCHITECTURE
  M:	Rob Herring <rob.herring at calxeda.com>
  L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5..e99177a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,18 +350,6 @@ config ARCH_AT91
  	  This enables support for systems based on Atmel
  	  AT91RM9200 and AT91SAM9* processors.
  -config ARCH_BCMRING
-	bool "Broadcom BCMRING"
-	depends on MMU
-	select CPU_V6
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	help
-	  Support for Broadcom's BCMRing platform.
-
  config ARCH_HIGHBANK
  	bool "Calxeda Highbank-based"
  	select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -1031,8 +1019,6 @@ source "arch/arm/mach-mvebu/Kconfig"
   source "arch/arm/mach-at91/Kconfig"
  -source "arch/arm/mach-bcmring/Kconfig"
-
  source "arch/arm/mach-clps711x/Kconfig"
   source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..8383e2e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
  # Machine directory name.  This list is sorted alphanumerically
  # by CONFIG_* macro name.
  machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
  machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
  machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
  machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
diff --git a/arch/arm/configs/bcmring_defconfig 
b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe..0000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16..0000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-	prompt "Processor selection in BCMRING family of devices"
-	depends on ARCH_BCMRING
-	default ARCH_BCM11107
-
-config ARCH_FPGA11107
-	bool "FPGA11107"
-
-config ARCH_BCM11107
-	bool "BCM11107"
-endchoice
-
-menu "BCMRING Options"
-	depends on ARCH_BCMRING
-
-config BCM_ZRELADDR
-	hex "Compressed ZREL ADDR"
-
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fce..0000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot 
b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467..0000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
-
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index 45c97b1..0000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/pmu.h>
-
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <cfg_global.h>
-
-#include "core.h"
-
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-
-/* sysctl */
-static int bcmring_arch_warm_reboot;	/* do a warm reboot on hard reset */
-
-static void bcmring_restart(char mode, const char *cmd)
-{
-	printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-
-	if (mode == 'h') {
-		/* Reboot configured in proc entry */
-		if (bcmring_arch_warm_reboot) {
-			printk("warm reset\n");
-			/* Issue Warm reset (do not reset ethernet switch, keep alive) */
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-		} else {
-			/* Force reset of everything */
-			printk("force reset\n");
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-	} else {
-		/* Force reset of everything */
-		printk("force reset\n");
-		chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-	}
-}
-
-static struct ctl_table_header *bcmring_sysctl_header;
-
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-	{
-	 .procname = "warm",
-	 .data = &bcmring_arch_warm_reboot,
-	 .maxlen = sizeof(int),
-	 .mode = 0644,
-	 .proc_handler = proc_dointvec},
-	{}
-};
-
-static struct ctl_table bcmring_sysctl_reboot[] = {
-	{
-	 .procname = "reboot",
-	 .mode = 0555,
-	 .child = bcmring_sysctl_warm_reboot},
-	{}
-};
-
-static struct resource nand_resource[] = {
-	[0] = {
-		.start = MM_ADDR_IO_NAND,
-		.end = MM_ADDR_IO_NAND + 0x1000 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device nand_device = {
-	.name = "bcm-nand",
-	.id = -1,
-	.resource = nand_resource,
-	.num_resources	= ARRAY_SIZE(nand_resource),
-};
-
-static struct resource pmu_resource = {
-	.start	= IRQ_PMUIRQ,
-	.end	= IRQ_PMUIRQ,
-	.flags	= IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
-	.resource	= &pmu_resource,
-	.num_resources	= 1,
-};
-
-
-static struct platform_device *devices[] __initdata = {
-	&nand_device,
-	&pmu_device,
-};
-
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-
-	bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-
-	/* Enable spread spectrum */
-	chipcHw_enableSpreadSpectrum();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	bcmring_amba_init();
-
-	dma_init();
-}
-
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-	struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-	printk(KERN_NOTICE "bcmring_fixup\n");
-	t->hdr.tag = ATAG_CORE;
-	t->hdr.size = tag_size(tag_core);
-	t->u.core.flags = 0;
-	t->u.core.pagesize = PAGE_SIZE;
-	t->u.core.rootdev = 31 << 8 | 0;
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_MEM;
-	t->hdr.size = tag_size(tag_mem32);
-	t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-	t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_NONE;
-	t->hdr.size = 0;
-#endif
-}
-
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-
-MACHINE_START(BCMRING, "BCMRING")
-	/* Maintainer: Broadcom Corporation */
-	.fixup = bcmring_fixup,
-	.map_io = bcmring_map_io,
-	.init_early = bcmring_init_early,
-	.init_irq = bcmring_init_irq,
-	.timer = &bcmring_timer,
-	.init_machine = bcmring_init_machine,
-	.restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a4..0000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include "clock.h"
-
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	/* enable parent clock first */
-	if (clk->parent)
-		__clk_enable(clk->parent);
-
-	if (clk->use_cnt++ == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Enable(clk->rate_hz, 0);
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Enable(clk->rate_hz);
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockEnable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockEnable(clk->csp_id);
-		}
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	BUG_ON(clk->use_cnt == 0);
-
-	if (--clk->use_cnt == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Disable();
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Disable();
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockDisable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockDisable(clk->csp_id);
-		}
-	}
-
-	if (clk->parent)
-		__clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (!clk)
-		return 0;
-
-	return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-	clk->rate_hz = rate_hz;
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-	if (!clk)
-		return NULL;
-
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	unsigned long flags;
-	struct clk *old_parent;
-
-	if (!clk || !parent)
-		return -EINVAL;
-
-	if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-		return -EINVAL;
-
-	/* if more than one user, parent is not allowed */
-	if (clk->use_cnt > 1)
-		return -EBUSY;
-
-	if (clk->parent == parent)
-		return 0;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	old_parent = clk->parent;
-	clk->parent = parent;
-	if (clk_is_using_xtal(parent))
-		clk->mode |= CLK_MODE_XTAL;
-	else
-		clk->mode &= (~CLK_MODE_XTAL);
-
-	/* if clock is active */
-	if (clk->use_cnt != 0) {
-		clk->use_cnt--;
-		/* enable clock with the new parent */
-		__clk_enable(clk);
-		/* disable the old parent */
-		__clk_disable(old_parent);
-	}
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b981..0000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-
-#define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a 
parent */
-#define CLK_TYPE_PLL1            2	/* PPL1 */
-#define CLK_TYPE_PLL2            4	/* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8	/* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16	/* parent can be changed */
-
-#define CLK_MODE_XTAL            1	/* clock source is from crystal */
-
-struct clk {
-	const char *name;	/* clock name */
-	unsigned int type;	/* clock type */
-	unsigned int mode;	/* current mode */
-	volatile int use_bypass;	/* indicate if it's in bypass mode */
-	chipcHw_CLOCK_e csp_id;	/* clock ID for CSP CHIPC */
-	unsigned long rate_hz;	/* clock rate in Hz */
-	unsigned int use_cnt;	/* usage count */
-	struct clk *parent;	/* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index adbfb19..0000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <cfg_global.h>
-
-#include "clock.h"
-
-#include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, 
{IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, 
{IRQ_UARTB}, NULL);
-
-static struct clk pll1_clk = {
-	.name = "PLL1",
-	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-	.rate_hz = 2000000000,
-	.use_cnt = 7,
-};
-
-static struct clk uart_clk = {
-	.name = "UART",
-	.type = CLK_TYPE_PROGRAMMABLE,
-	.csp_id = chipcHw_CLOCK_UART,
-	.rate_hz = HW_CFG_UART_CLK_HZ,
-	.parent = &pll1_clk,
-};
-
-static struct clk dummy_apb_pclk = {
-	.name = "BUSCLK",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-};
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as 
well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-static struct clk sp804_timer012_clk = {
-	.name = "sp804-timer-0,1,2",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-
-static struct clk sp804_timer3_clk = {
-	.name = "sp804-timer-3",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-
-static struct clk_lookup lookups[] = {
-	{			/* Bus clock */
-		.con_id = "apb_pclk",
-		.clk = &dummy_apb_pclk,
-	}, {			/* UART0 */
-		.dev_id = "uarta",
-		.clk = &uart_clk,
-	}, {			/* UART1 */
-		.dev_id = "uartb",
-		.clk = &uart_clk,
-	}, {			/* SP804 timer 0 */
-		.dev_id = "sp804",
-		.con_id = "timer0",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 1 */
-		.dev_id = "sp804",
-		.con_id = "timer1",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 3 */
-		.dev_id = "sp804",
-		.con_id = "timer3",
-		.clk = &sp804_timer3_clk,
-	}
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	&uartA_device,
-	&uartB_device,
-};
-
-void __init bcmring_amba_init(void)
-{
-	int i;
-	u32 bus_clock;
-
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-			  secHw_BLK_MASK_KEY_SCAN |
-			  secHw_BLK_MASK_TOUCH_SCREEN |
-			  secHw_BLK_MASK_UART0 |
-			  secHw_BLK_MASK_UART1 |
-			  secHw_BLK_MASK_WATCHDOG |
-			  secHw_BLK_MASK_SPUM |
-			  secHw_BLK_MASK_DDR2 |
-			  secHw_BLK_MASK_SPU |
-			  secHw_BLK_MASK_PKA |
-			  secHw_BLK_MASK_RNG |
-			  secHw_BLK_MASK_RTC |
-			  secHw_BLK_MASK_OTP |
-			  secHw_BLK_MASK_BOOT |
-			  secHw_BLK_MASK_MPU |
-			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-
-	/* Only the devices attached to the AMBA bus are enabled just before 
the bus is */
-	/* scanned and the drivers are loaded. The clocks need to be on for 
the AMBA bus */
-	/* driver to access these blocks. The bus is probed, and the drivers 
are loaded. */
-	/* FIXME Need to remove enable of PIF once CLCD clock enable used 
properly in FPGA. */
-	bus_clock = chipcHw_REG_BUS_CLOCK_GE
-	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-
-	chipcHw_busInterfaceClockEnable(bus_clock);
-
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-}
-
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE		((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-
-static int __init bcmring_clocksource_init(void)
-{
-	/* setup timer1 as free-running clocksource */
-	sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-
-	/* setup timer3 as free-running clocksource */
-	sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-
-	return 0;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-	printk(KERN_INFO "bcmring_init_timer\n");
-	/*
-	 * Initialise to a known state (all timers off)
-	 */
-	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-
-	/*
-	 * Make irqs happen for the system timer
-	 */
-	bcmring_clocksource_init();
-
-	sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-
-struct sys_timer bcmring_timer = {
-	.init = bcmring_init_timer,
-};
-
-void __init bcmring_init_early(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c4..0000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile 
b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c037..0000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile 
b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 6739527..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 96273ff..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF	/* Max number of times 
allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10	/* Max number of attempt to 
align the phase */
-
-/* Local definition of clock type */
-#define PLL_CLOCK                      1	/* PLL Clock */
-#define NON_PLL_CLOCK                  2	/* Divider clock */
-
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-	} else {
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz =
-	    chipcHw_XTAL_FREQ_Hz *
-		 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Obtain PLL clock frequency */
-		if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (clock == chipcHw_CLOCK_DDR) {
-			/* DDR frequency is configured in PLLDivider register */
-			return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				vcoHz >>= 1;
-			}
-			/* Obtain PLL clock frequency using VCO dividers */
-			return chipcHw_divide(vcoHz, ((*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-	} else if (pClockCtrl) {
-		/* Obtain divider clock frequency */
-		uint32_t div;
-		uint32_t freq = 0;
-
-		if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (pDependentClock) {
-			/* Identify the dependent clock frequency */
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-					/* Use crystal clock frequency when dependent PLL clock is bypassed */
-					freq = chipcHw_XTAL_FREQ_Hz;
-				} else {
-					/* Obtain PLL clock frequency using VCO dividers */
-					div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-					freq = div ? chipcHw_divide(vcoHz, div) : 0;
-				}
-				break;
-			case NON_PLL_CLOCK:
-				if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-					freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-				} else {
-					if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-						/* Use crystal clock frequency when dependent divider clock is 
bypassed */
-						freq = chipcHw_XTAL_FREQ_Hz;
-					} else {
-						/* Obtain divider clock frequency using XTAL dividers */
-						div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-					}
-				}
-				break;
-			}
-		} else {
-			/* Dependent on crystal clock */
-			freq = chipcHw_XTAL_FREQ_Hz;
-		}
-
-		div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-		return chipcHw_divide(freq, (div ? div : 256));
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t desVcoFreqPll1Hz = 0;	/* Desired VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-	uint32_t desVcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-
-		/* Desired VCO frequency */
-		desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-	} else {
-		vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * 
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		/* Configure the DDR_ctrl:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-			pChipcHw->DDRClock = (pChipcHw->DDRClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		/* Configure the VPM:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Select XTAL as bypass source */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-		reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* For DDR settings use only the PLL divider clock */
-		if (pPLLReg == &pChipcHw->DDRClock) {
-			/* Set M1DIV for PLL1, which controls the DDR clock */
-			reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 
0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				desVcoHz >>= 1;
-				vcoHz >>= 1;
-			}
-			/* Set MDIV to change the frequency */
-			reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-			reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-		/* Wait for for atleast 200ns as per the protocol to change frequency */
-		udelay(1);
-		/* Do not bypass */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* Return the configured frequency */
-		return freq;
-	} else if (pClockCtrl) {
-		uint32_t divider = 0;
-
-		/* Divider clock should not be bypassed  */
-		reg32_modify_and(pClockCtrl,
-				 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-
-		/* Identify the clock source */
-		if (pDependentClock) {
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				divider = chipcHw_divide(chipcHw_divide (desVcoHz, 
(*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-				break;
-			case NON_PLL_CLOCK:
-				{
-					uint32_t sourceClock = 0;
-
-					if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-						sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-					} else {
-						uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div 
: 256));
-					}
-					divider = chipcHw_divide(sourceClock, freq);
-				}
-				break;
-			}
-		} else {
-			divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-		}
-
-		if (divider) {
-			REG_LOCAL_IRQ_SAVE;
-			/* Set the divider to obtain the required frequency */
-			*pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | 
(((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & 
chipcHw_REG_DIV_CLOCK_DIV_MASK);
-			REG_LOCAL_IRQ_RESTORE;
-			return freq;
-		}
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-	uint32_t phaseControl;
-	uint32_t phaseValue;
-	uint32_t prevPhaseComp;
-	int iter = 0;
-	int adjustCount = 0;
-	int count = 0;
-
-	for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT); iter++) {
-		phaseControl = (pChipcHw->VPMClock & 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-		phaseValue = 0;
-		prevPhaseComp = 0;
-
-		/* Step 1: Look for falling PH_COMP transition */
-
-		/* Read the contents of VPM Clock resgister */
-		phaseValue = pChipcHw->VPMClock;
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) ||	/* Look for a transition */
-			  ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&	/* 
Look for a falling edge */
-			 (adjustCount < MAX_PHASE_ADJUST_COUNT)	/* Do not exceed the limit 
while trying */
-		    );
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		/* Step 2: Keep moving forward to make sure falling PH_COMP 
transition was valid */
-
-		for (count = 0; (count < 5) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl + 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 5) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 3: Keep moving backward to make sure falling PH_COMP 
transition was stable */
-
-		for (count = 0; (count < 3) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 3) {
-			/* Detected noisy transition */
-			continue;
-		}
-
-		/* Step 4: Keep moving backward before the original transition took 
place. */
-
-		for (count = 0; (count < 5); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 5: Re discover the valid transition */
-
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^=
-			    chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT));
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-			return -1;
-		} else {
-			/* Valid phase must have detected */
-			break;
-		}
-	}
-
-	/* For VPM Phase should be perfectly aligned. */
-	phaseControl = (((pChipcHw->VPMClock >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
-		/* Load new phase value */
-		pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-	/* Return the status */
-	return (int)adjustCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-
-	if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-		return vpmPhaseAlignA0();
-	} else {
-		uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-		uint32_t phaseValue = 0;
-		int adjustCount = 0;
-
-		/* Disable VPM access */
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-		/* Disable HW VPM phase alignment  */
-		chipcHw_vpmHwPhaseAlignDisable();
-		/* Enable SW VPM phase alignment  */
-		chipcHw_vpmSwPhaseAlignEnable();
-		/* Adjust VPM phase */
-		while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-			phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-
-			/* Adjust phase control value */
-			if (phaseValue > 0xF) {
-				/* Increment phase control value */
-				phaseControl++;
-			} else if (phaseValue < 0xF) {
-				/* Decrement phase control value */
-				phaseControl--;
-			} else {
-				/* Enable VPM access */
-				pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-				/* Return adjust count */
-				return adjustCount;
-			}
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Count adjustment */
-			adjustCount++;
-		}
-	}
-
-	/* Disable VPM access */
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-	return -1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 367df75..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-
-	Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-	for Freq_vco = VCO_FREQ_MHz
-		Freq_ref = chipcHw_XTAL_FREQ_Hz
-		PLL_P1 = PLL_P2 = 1
-		and
-		PLL_NDIV_f = 0
-
-	We get:
-		PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-		Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = 
VCO_FREQ_MHz / PLL_MDIV_x
-
-		PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-
-/* ---- Private Variables 
------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-	uint32_t pllPreDivider2 = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		pChipcHw->PLLConfig2 =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-
-		pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-		    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-		    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider2 = pllPreDivider2;
-		/* Set NDIV Frac */
-		pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
-
-		/* This has to be removed once the default values are fixed for PLL2. */
-		pChipcHw->PLLControl12 = 0x38000700;
-		pChipcHw->PLLControl22 = 0x00000015;
-
-		/* Reset PLL2 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-		REG_LOCAL_IRQ_RESTORE;
-	}
-
-	/* Insert certain amount of delay before deasserting ARESET. */
-	udelay(1);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove analog reset and Power on the PLL */
-		pChipcHw->PLLConfig2 &=
-		    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-		      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-
-		REG_LOCAL_IRQ_RESTORE;
-
-	}
-
-	/* Wait until PLL is locked */
-	while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-		;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove digital reset */
-		pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e 
ssSupport)
-{
-	uint32_t pllPreDivider = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->PLLConfig =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-		/* Setting VCO frequency */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pllPreDivider =
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-			    ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-			      1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		} else {
-			pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-			    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-			     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		}
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider = pllPreDivider;
-		/* Set NDIV Frac */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
-		} else {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f;
-		}
-
-		/* Reset PLL1 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-
-		REG_LOCAL_IRQ_RESTORE;
-
-		/* Insert certain amount of delay before deasserting ARESET. */
-		udelay(1);
-
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Remove analog reset and Power on the PLL */
-			pChipcHw->PLLConfig &=
-			    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-			      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-
-		/* Wait until PLL is locked */
-		while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-		       || !(pChipcHw->
-			    PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-			;
-
-		/* Remove digital reset */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-			REG_LOCAL_IRQ_RESTORE;
-		}
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-	delay_init();
-#endif
-
-	/* Do not program PLL, when warm reset */
-	if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-		chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-				   initParam->ssSupport);
-		chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-	} else {
-		/* Clear sticky bits */
-		chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-	}
-	/* Clear sticky bits */
-	chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-
-	/* Before configuring the ARM clock, atleast we need to make sure BUS 
clock maintains the proper ratio with ARM clock */
-	pChipcHw->ACLKClock =
-	    (pChipcHw->
-	     ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-								 armBusRatio &
-								 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
-
-	/* Set various core component frequencies. The order in which this is 
done is important for some. */
-	/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the 
ARM, and VPM needs to know BUS */
-	/* frequency to find its ratio with the BUS.  Hence we must set the 
ARM first, followed by the BUS,  */
-	/* then VPM and RTBUS. */
-
-	chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-				  initParam->busClockFreqHz *
-				  initParam->armBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-				  initParam->busClockFreqHz *
-				  initParam->vpmBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-				  initParam->busClockFreqHz *
-				  initParam->ddrBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-				  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index 2671d88..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-/* ---- Private Variables 
------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-
-typedef void (*RUNFUNC) (void);
-
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to 
the state
-*   required to execute on reset.  To do so we need to copy the code 
into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-	int i = 0;
-	RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-
-	/* Disable all interrupts */
-	intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-	intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-	intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-			chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-		/* Bypass the PLL clocks before reboot */
-		pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-		pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-
-		/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-		do {
-			((uint32_t *) MM_IO_BASE_ARAM)[i] =
-			    ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
-			i++;
-		} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);	/* 
0xe1a0f00f == asm ("mov r15, r15"); */
-
-		CSP_CACHE_FLUSH_ALL;
-
-		/* run the function from ARAM */
-		runFunc();
-
-		/* Code will never get here, but include it to balance 
REG_LOCAL_IRQ_SAVE above */
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop 
  \n\t"
-		" nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		" MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" BIC      r0,r0,#0xd                                            \n\t"
-		" MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-#endif
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-		" MOV      r2,#0x80000000                                        \n\t"
-		" LDR      r3,[r2,#8]                                            \n\t"
-		" ORR      r3,r3,#0x20000                                        \n\t"
-		" STR      r3,[r2,#8]                                            \n\t"
-
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Issue reset */
-		" MOV      r3,#0x2                                               \n\t"
-		" STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-		" MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-static const char *gMuxStr[] = {
-	"GPIO",			/* 0 */
-	"KeyPad",		/* 1 */
-	"I2C-Host",		/* 2 */
-	"SPI",			/* 3 */
-	"Uart",			/* 4 */
-	"LED-Mtx-P",		/* 5 */
-	"LED-Mtx-S",		/* 6 */
-	"SDIO-0",		/* 7 */
-	"SDIO-1",		/* 8 */
-	"PCM",			/* 9 */
-	"I2S",			/* 10 */
-	"ETM",			/* 11 */
-	"Debug",		/* 12 */
-	"Misc",			/* 13 */
-	"0xE",			/* 14 */
-	"0xF",			/* 15 */
-};
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-	if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-		return "";
-	}
-
-	return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile 
b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104f..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 6b9be2e..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA 
Channel handle */
-    ) {
-	uint32_t val = 0;
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_MISC_t *pMiscReg =
-	    (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
-
-	switch (pCblk->channel) {
-	case 0:
-		val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
-		break;
-	case 1:
-		val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
-		break;
-	case 2:
-		val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
-		break;
-	case 3:
-		val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
-		break;
-	case 4:
-		val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
-		break;
-	case 5:
-		val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
-		break;
-	case 6:
-		val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
-		break;
-	case 7:
-		val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
-		break;
-	}
-
-	if (val <= 0x4) {
-		return 8 << val;
-	} else {
-		dmacHw_ASSERT(0);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pProg;
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Not safe yet to program the channel */
-		return;
-	}
-
-	if (pCblk->varDataStarted) {
-		if (pCblk->descUpdated) {
-			pCblk->descUpdated = 0;
-			pProg =
-			    (dmacHw_DESC_t *) ((uint32_t)
-					       dmacHw_REG_LLP(pCblk->module,
-							      pCblk->channel) +
-					       pRing->virt2PhyOffset);
-
-			/* Load descriptor if not loaded */
-			if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-				dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-					       pProg->sar);
-				dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-					       pProg->dar);
-				dmacHw_REG_CTL_LO(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.lo;
-				dmacHw_REG_CTL_HI(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.hi;
-			} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-				/* Return as end descriptor is processed */
-				return;
-			} else {
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			return;
-		}
-	} else {
-		if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-			/* Do not make a single chain, rather process one descriptor at a 
time */
-			pProg = pRing->pHead;
-			/* Point to the next descriptor for next iteration */
-			dmacHw_NEXT_DESC(pRing, pHead);
-		} else {
-			/* Return if no more pending descriptor */
-			if (pRing->pEnd == NULL) {
-				return;
-			}
-
-			pProg = pRing->pProg;
-			if (pConfig->transferMode ==
-			    dmacHw_TRANSFER_MODE_CONTINUOUS) {
-				/* Make sure a complete ring can be formed */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-					      llp == pRing->pProg);
-				/* Make sure pProg pointing to the pHead */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-					      pRing->pHead);
-				/* Make a complete ring */
-				do {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				} while (pRing->pProg != pRing->pHead);
-			} else {
-				/* Make a single long chain */
-				while (pRing->pProg != pRing->pEnd) {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				}
-			}
-		}
-
-		/* Program the channel registers */
-		dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-		dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-		    pProg->ctl.lo;
-		dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-		    pProg->ctl.hi;
-		if (pRing->pEnd) {
-			/* Remember the descriptor to use next */
-			pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-		}
-		/* Indicate no more pending descriptor  */
-		pRing->pEnd = (dmacHw_DESC_t *) NULL;
-	}
-	/* Start DMA operation */
-	dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-
-	uint32_t i = 0;
-
-	dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-	dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-
-	/* Enable access to the DMA block */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-
-	if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-		dmacHw_ASSERT(0);
-	}
-
-	memset((void *)dmacHw_gCblk, 0,
-	       sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-	for (i = 0; i < dmaChannelCount_0; i++) {
-		dmacHw_gCblk[i].module = 0;
-		dmacHw_gCblk[i].channel = i;
-	}
-	for (i = 0; i < dmaChannelCount_1; i++) {
-		dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-		dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-	/* Disable access to the DMA block */
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    ) {
-	int idx;
-
-	switch ((channelId >> 8)) {
-	case 0:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-		idx = (channelId & 0xff);
-		break;
-	case 1:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-		idx = dmaChannelCount_0 + (channelId & 0xff);
-		break;
-	default:
-		dmacHw_ASSERT(0);
-		return (dmacHw_HANDLE_t) -1;
-	}
-
-	return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	int module = pCblk->module;
-	int channel = pCblk->channel;
-
-	/* Reinitialize the control block */
-	memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-	pCblk->module = module;
-	pCblk->channel = channel;
-
-	/* Enable DMA controller */
-	dmacHw_DMA_ENABLE(pCblk->module);
-	/* Reset DMA channel */
-	dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Mask event specific interrupts */
-	dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/* [ IN ] Number of 
descriptor in the ring */
-    ) {
-	/* Need extra 4 byte to ensure 32 bit alignment  */
-	return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-		sizeof(uint32_t);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    ) {
-	uint32_t i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	/* Check the alignment of the descriptor */
-	if ((uint32_t) pDescriptorVirt & 0x00000003) {
-		dmacHw_ASSERT(0);
-		return -1;
-	}
-
-	/* Check if enough space has been allocated for descriptor ring */
-	if (len < dmacHw_descriptorLen(num)) {
-		return -1;
-	}
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-	pRing->pHead =
-	    (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-	/* Initialize link item chain, starting from the head */
-	pDesc = pRing->pHead;
-	/* Find the offset between virtual to physical address */
-	pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-
-	/* Form the descriptor ring */
-	for (i = 0; i < num - 1; i++) {
-		/* Clear link list item */
-		memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-		/* Point to the next item in the physical address */
-		pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-		/* Point to the next item in the virtual address */
-		pDesc->llp = (uint32_t) (pDesc + 1);
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-
-	/* Clear last link list item */
-	memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-	/* Last item pointing to the first item in the
-	   physical address to complete the ring */
-	pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-	/* Last item pointing to the first item in the
-	   virtual address to complete the ring
-	 */
-	pDesc->llp = (uint32_t) pRing->pHead;
-	/* Mark descriptor is ready to use */
-	pDesc->ctl.hi = dmacHw_DESC_FREE;
-	/* Set the number of descriptors in the ring */
-	pRing->num = num;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	uint32_t cfgHigh = 0;
-	int srcTrSize;
-	int dstTrSize;
-
-	pCblk->varDataStarted = 0;
-	pCblk->userData = NULL;
-
-	/* Configure
-	   - Burst transaction when enough data in available in FIFO
-	   - AHB Access protection 1
-	   - Source and destination peripheral ports
-	 */
-	cfgHigh =
-	    dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-	    dmacHw_SRC_PERI_INTF(pConfig->
-				 srcPeripheralPort) |
-	    dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-	/* Set priority */
-	dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-				    pConfig->channelPriority);
-
-	if (pConfig->dstStatusRegisterAddress != 0) {
-		/* Destination status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-		/* Configure status registers */
-		dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->dstStatusRegisterAddress);
-	}
-
-	if (pConfig->srcStatusRegisterAddress != 0) {
-		/* Source status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-		/* Source status update enable */
-		dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->srcStatusRegisterAddress);
-	}
-	/* Configure the config high register */
-	dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Configure block interrupt */
-	if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure complete transfer interrupt */
-	if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure error interrupt */
-	if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure gather register */
-	if (pConfig->srcGatherWidth) {
-		srcTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-		if (!
-		    ((pConfig->srcGatherWidth % srcTrSize)
-		     && (pConfig->srcGatherJump % srcTrSize))) {
-			dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->srcGatherWidth /
-			      srcTrSize) << 20) | (pConfig->srcGatherJump /
-						   srcTrSize);
-		} else {
-			return -1;
-		}
-	}
-	/* Configure scatter register */
-	if (pConfig->dstScatterWidth) {
-		dstTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-		if (!
-		    ((pConfig->dstScatterWidth % dstTrSize)
-		     && (pConfig->dstScatterJump % dstTrSize))) {
-			dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->dstScatterWidth /
-			      dstTrSize) << 20) | (pConfig->dstScatterJump /
-						   dstTrSize);
-		} else {
-			return -1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_BUSY;
-	} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-		   (0x00000001 << pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_ERROR;
-	}
-
-	return dmacHw_TRANSFER_STATUS_DONE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			     void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-	dmacHw_DESC_t *pProg;
-	int srcTs = 0;
-	int blkTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int count = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if ((pConfig->srcGatherWidth % srcTrSize)
-	    || (pConfig->dstScatterWidth % dstTrSize)) {
-		return -2;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	/* Check the availability of "descCount" discriptors in the ring */
-	pProg = pRing->pHead;
-	for (count = 0; (descCount <= pRing->num) && (count < descCount);
-	     count++) {
-		if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-			/* Sufficient descriptors are not available */
-			return -3;
-		}
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	}
-
-	/* Remember the link list item to program the channel registers */
-	pStart = pProg = pRing->pHead;
-	/* Make a link list with "descCount(=count)" number of descriptors */
-	while (count) {
-		/* Reset channel control information */
-		pProg->ctl.lo = 0;
-		/* Enable source gather if configured */
-		if (pConfig->srcGatherWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-		}
-		/* Enable destination scatter if configured */
-		if (pConfig->dstScatterWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-		}
-		/* Set source and destination address */
-		pProg->sar = (uint32_t) pSrcAddr;
-		pProg->dar = (uint32_t) pDstAddr;
-		/* Use "devCtl" to mark that user memory need to be freed later if 
needed */
-		if (pProg == pRing->pHead) {
-			pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-		} else {
-			pProg->devCtl = 0;
-		}
-
-		blkTs = srcTs;
-
-		/* Special treatmeant for last descriptor */
-		if (count == 1) {
-			/* Mark the last descriptor */
-			pProg->ctl.lo &=
-			    ~(dmacHw_REG_CTL_LLP_DST_EN |
-			      dmacHw_REG_CTL_LLP_SRC_EN);
-			/* Treatment for odd data bytes */
-			if (oddSize) {
-				/* Adjust for single byte transaction width */
-				switch (pConfig->transferType) {
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs =
-					    (oddSize / srcTrSize) +
-					    ((oddSize % srcTrSize) ? 1 : 0);
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-					/* Do not adjust the transaction width  */
-					break;
-				}
-			} else {
-				srcTs -= blkTs;
-			}
-		} else {
-			if (srcTs / maxBlockSize) {
-				blkTs = maxBlockSize;
-			}
-			/* Remaining source transactions for next iteration */
-			srcTs -= blkTs;
-		}
-		/* Must have a valid source transactions */
-		dmacHw_ASSERT(blkTs > 0);
-		/* Set control information */
-		if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-			pProg->ctl.lo |= pConfig->transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		} else {
-			uint32_t transferType = 0;
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-			pProg->ctl.lo |= transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		}
-
-		/* Set block transaction size */
-		pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		/* Look for next descriptor */
-		if (count > 1) {
-			/* Point to the next descriptor */
-			pProg = (dmacHw_DESC_t *) pProg->llp;
-
-			/* Update source and destination address for next iteration */
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-				/* Do not adjust the address */
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			/* At the end of transfer "srcTs" must be zero */
-			dmacHw_ASSERT(srcTs == 0);
-		}
-		count--;
-	}
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pStart;
-	}
-	/* Indicate that the descriptor is updated */
-	pRing->pEnd = pProg;
-	/* Head pointing to the next descriptor */
-	pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-	/* Update Tail pointer if destination is a peripheral,
-	   because no one is going to read from the pTail
-	 */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	switch (attr) {
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-		return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-		return (1 <<
-			 (dmacHw_GET_MAX_BLOCK_SIZE
-			  (pCblk->module, pCblk->module) + 2)) - 8;
-	case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-		return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-		return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-							   pCblk->channel);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-		return GetFifoSize(handle);
-	}
-	dmacHw_ASSERT(0);
-	return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index a1f3283..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* 
Declared in dmacHw.c */
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* ---- Internal Use Function Prototypes 
--------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module,	/*   [ IN ] DMA 
Controller unit  (0-1) */
-				    int channel,	/*   [ IN ] DMA Channel          (0-7) / -1(all) */
-				    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	int chan;
-
-	(*fpPrint) ("Displaying register content \n\n");
-	(*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: SW source req                       0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-	(*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW source last                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: misc config                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-	(*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-	(*fpPrint) ("Module %d: misc ID                             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-	(*fpPrint) ("Module %d: misc test                           0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-
-	if (channel == -1) {
-		for (chan = 0; chan < 8; chan++) {
-			(*fpPrint)
-			    ("--------------------------------------------------\n");
-			(*fpPrint)
-			    ("Module %d: Channel %d Source                   0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Destination              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d LLP                      0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_LLP(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (LO)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (HI)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats               0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (LO)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (HI)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-		}
-	} else {
-		chan = channel;
-		(*fpPrint)
-		    ("--------------------------------------------------\n");
-		(*fpPrint)
-		    ("Module %d: Channel %d Source                   0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Destination              0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d LLP                      0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (LO)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (HI)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats             0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats               0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (LO)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (HI)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,	/*   [ IN ] Descriptor 
buffer */
-			    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-
-	if (pRing->pHead == NULL) {
-		return;
-	}
-
-	pStart = pRing->pHead;
-
-	while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-		if (pStart == pRing->pHead) {
-			(*fpPrint) ("Head\n");
-		}
-		if (pStart == pRing->pTail) {
-			(*fpPrint) ("Tail\n");
-		}
-		if (pStart == pRing->pProg) {
-			(*fpPrint) ("Prog\n");
-		}
-		if (pStart == pRing->pEnd) {
-			(*fpPrint) ("End\n");
-		}
-		if (pStart == pRing->pFree) {
-			(*fpPrint) ("Free\n");
-		}
-		(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-		(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-		(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-		(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-		(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-		(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-		(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-		(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-		(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-
-		pStart = (dmacHw_DESC_t *) pStart->llp;
-	}
-	if (pStart == pRing->pHead) {
-		(*fpPrint) ("Head\n");
-	}
-	if (pStart == pRing->pTail) {
-		(*fpPrint) ("Tail\n");
-	}
-	if (pStart == pRing->pProg) {
-		(*fpPrint) ("Prog\n");
-	}
-	if (pStart == pRing->pEnd) {
-		(*fpPrint) ("End\n");
-	}
-	if (pStart == pRing->pFree) {
-		(*fpPrint) ("Free\n");
-	}
-	(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-	(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-	(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-	(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-	(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-	(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-	(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-	(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-	(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor	/*   [ IN ] 
Descriptor buffer */
-    ) {
-	uint32_t ttfc =
-	    (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-	    lo & dmacHw_REG_CTL_TTFC_MASK;
-
-	switch (ttfc) {
-	case dmacHw_REG_CTL_TTFC_MM_DMAC:
-	case dmacHw_REG_CTL_TTFC_MP_DMAC:
-	case dmacHw_REG_CTL_TTFC_PM_DMAC:
-	case dmacHw_REG_CTL_TTFC_PP_DMAC:
-		return 1;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_DESC_t *pProg;
-	dmacHw_DESC_t *pHead;
-	int srcTs = 0;
-	int srcTrSize = 0;
-
-	pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-	pProg = pHead;
-
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-	srcTs = dataLen / srcTrSize;
-	do {
-		pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	} while (pProg != pHead);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/* [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/* [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-
-	if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_TRANS;
-	}
-	if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-	}
-	if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_ERROR;
-	}
-
-	return status;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-		if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-		     ((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    ) {
-			return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-		}
-	}
-	return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	int srcTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if (pConfig->srcGatherWidth % srcTrSize
-	    || pConfig->dstScatterWidth % dstTrSize) {
-		return -1;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	return descCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	/* Make sure channel is not busy */
-	if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Check if pEnd is not processed */
-		if (pRing->pEnd) {
-			/* Something left for processing */
-			return 1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	/* Stop the channel */
-	dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-		   void (*fpFree) (void *)	/*   [ IN ] Function pointer to free data 
memory */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t count = 0;
-
-	if (fpFree == NULL) {
-		return -1;
-	}
-
-	while ((pRing->pFree != pRing->pTail)
-	       && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-		if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-			/* Identify, which memory to free */
-			if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-				(*fpFree) ((void *)pRing->pFree->dar);
-			} else {
-				/* Destination was a peripheral */
-				(*fpFree) ((void *)pRing->pFree->sar);
-			}
-			/* Unmark user memory to indicate it is freed */
-			pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-		}
-		dmacHw_NEXT_DESC(pRing, pFree);
-
-		count++;
-	}
-
-	return count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*   [ IN 
] DMA Channel handle */
-				     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				     uint32_t srcAddr,	/*   [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*   [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*   [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*   [ IN ] Number of descriptor to set */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_t *pProg = NULL;
-	dmacHw_DESC_t *pLast = NULL;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t dstAddr;
-	uint32_t controlParam;
-	int i;
-
-	dmacHw_ASSERT(pConfig->transferType ==
-		      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-
-	if (num > pRing->num) {
-		return -1;
-	}
-
-	pLast = pRing->pEnd;	/* Last descriptor updated */
-	pProg = pRing->pHead;	/* First descriptor in the new list */
-
-	controlParam = pConfig->srcUpdate |
-	    pConfig->dstUpdate |
-	    pConfig->srcMaxTransactionWidth |
-	    pConfig->dstMaxTransactionWidth |
-	    pConfig->srcMasterInterface |
-	    pConfig->dstMasterInterface |
-	    pConfig->srcMaxBurstWidth |
-	    pConfig->dstMaxBurstWidth |
-	    dmacHw_REG_CTL_TTFC_PM_PERI |
-	    dmacHw_REG_CTL_LLP_DST_EN |
-	    dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-
-	for (i = 0; i < num; i++) {
-		/* Allocate Rx buffer only for idle descriptor */
-		if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-		    ) {
-			/* Rx descriptor is not idle */
-			break;
-		}
-		/* Set source address */
-		pRing->pHead->sar = srcAddr;
-		if (fpAlloc) {
-			/* Allocate memory for buffer in descriptor */
-			dstAddr = (uint32_t) (*fpAlloc) (len);
-			/* Check the destination address */
-			if (dstAddr == 0) {
-				if (i == 0) {
-					/* Not a single descriptor is available */
-					return -1;
-				}
-				break;
-			}
-			/* Set destination address */
-			pRing->pHead->dar = dstAddr;
-		}
-		/* Set control information */
-		pRing->pHead->ctl.lo = controlParam;
-		/* Use "devCtl" to mark the memory that need to be freed later */
-		pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-		/* Descriptor is now owned by the channel */
-		pRing->pHead->ctl.hi = 0;
-		/* Remember the descriptor last updated */
-		pRing->pEnd = pRing->pHead;
-		/* Update next descriptor */
-		dmacHw_NEXT_DESC(pRing, pHead);
-	}
-
-	/* Mark the end of the list */
-	pRing->pEnd->ctl.lo &=
-	    ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-	/* Connect the list */
-	if (pLast != pProg) {
-		pLast->ctl.lo |=
-		    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-	}
-	/* Mark the descriptors are updated */
-	pCblk->descUpdated = 1;
-	if (!pCblk->varDataStarted) {
-		/* LLP must be pointing to the first descriptor */
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		/* Channel, handling variable data started */
-		pCblk->varDataStarted = 1;
-	}
-
-	return i;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       dmacHw_CONFIG_t *pConfig,	/*   [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			       void **ppBbuf,	/*   [ OUT ] Data received */
-			       size_t *pLlen	/*   [ OUT ] Length of the data received */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	(void)handle;
-
-	if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-		if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    (pRing->pTail == pRing->pHead)
-		    ) {
-			/* No receive data available */
-			*ppBbuf = (char *)NULL;
-			*pLlen = 0;
-
-			return 0;
-		}
-	}
-
-	/* Return read buffer and length */
-	*ppBbuf = (char *)pRing->pTail->dar;
-
-	/* Extract length of the received data */
-	if (DmaIsFlowController(pDescriptor)) {
-		uint32_t srcTrSize = 0;
-
-		switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-			srcTrSize = 1;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-			srcTrSize = 2;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-			srcTrSize = 4;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-			srcTrSize = 8;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		/* Calculate length from the block size */
-		*pLlen =
-		    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-		    srcTrSize;
-	} else {
-		/* Extract length from the source peripheral */
-		*pLlen = pRing->pTail->sstat;
-	}
-
-	/* Advance tail to next descriptor */
-	dmacHw_NEXT_DESC(pRing, pTail);
-
-	return 1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				uint32_t ctlAddress,	/*   [ IN ] Address of the device control 
register */
-				uint32_t control	/*   [ IN ] Device control information */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (ctlAddress == 0) {
-		return -1;
-	}
-
-	/* Check the availability of descriptors in the ring */
-	if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-		return -1;
-	}
-	/* Set control information */
-	pRing->pHead->devCtl = control;
-	/* Set source and destination address */
-	pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-	pRing->pHead->dar = ctlAddress;
-	/* Set control parameters */
-	if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-		pRing->pHead->ctl.lo = pConfig->transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-	} else {
-		uint32_t transferType = 0;
-		switch (pConfig->transferType) {
-		case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-			transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-			break;
-		case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-			transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		pRing->pHead->ctl.lo = transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface |
-		    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-	}
-
-	/* Set block transaction size to one 32 bit transaction */
-	pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pRing->pHead;
-	}
-	pRing->pEnd = pRing->pHead;
-
-	/* Advance the descriptor */
-	dmacHw_NEXT_DESC(pRing, pHead);
-
-	/* Update Tail pointer if destination is a peripheral */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       void *userData	/*  [ IN ] User data */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	pCblk->userData = userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	return pCblk->userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    ) {
-	int i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	pDesc = pRing->pHead;
-
-	for (i = 0; i < pRing->num; i++) {
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-	DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile 
b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61a..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c 
b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index 16225e4..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-
-#include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK 
/ tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / 
tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_LOW_256_RESOLUTION_COUNT)
-
-#define tmrHw_HIGH_1_RESOLUTION_COUNT 
(tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / 
tmrHw_HIGH_256_RESOLUTION_COUNT)
-
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-) {
-	switch (capability) {
-	case tmrHw_CAPABILITY_CLOCK:
-		return (timerId <=
-			1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-		    tmrHw_HIGH_RESOLUTION_CLOCK;
-	case tmrHw_CAPABILITY_RESOLUTION:
-		return 32;
-	default:
-		return 0;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer Id */
-) {
-	/* Reset timer */
-	pTmrHw[timerId].LoadValue = 0;
-	pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-	pTmrHw[timerId].Control = 0;
-	pTmrHw[timerId].BackgroundLoad = 0;
-	/* Always configure as a 32 bit timer */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-	/* Clear interrupt only if raw status interrupt is set */
-	if (pTmrHw[timerId].RawInterruptStatus) {
-		pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	uint32_t scale = 0;
-	uint32_t count = 0;
-
-	if (timerId == 0 || timerId == 1) {
-		if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-
-	} else if (timerId == 2 || timerId == 3) {
-		if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-	}
-	return count / scale;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-) {
-	uint32_t resolution = 0;
-	uint32_t count = 0;
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-	/* Set timer in highest resolution */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-
-	if (rate && (timerId == 0 || timerId == 1)) {
-		if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-			return 0;
-		}
-		resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-	} else if (rate && (timerId == 2 || timerId == 3)) {
-		if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-			return 0;
-		} else {
-			resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-		}
-	} else {
-		return 0;
-	}
-	/* Find the counter value */
-	count = resolution / rate;
-	/* Set counter value */
-	pTmrHw[timerId].LoadValue = count;
-	pTmrHw[timerId].BackgroundLoad = count;
-
-	return resolution / count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode oneshot */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) {
-	uint32_t scale = 0;
-
-	ResetTimer(timerId);
-	/* Set timer as free running mode */
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	if (divider >= 64) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-		scale = 256;
-	} else if (divider >= 8) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-		scale = 16;
-	} else {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-		scale = 1;
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-	} else if (timerId == 2 || timerId == 3) {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	/* return 32 bit timer value */
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-	case tmrHw_CONTROL_FREE_RUNNING:
-		if (pTmrHw[timerId].CurrentValue) {
-			return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-		}
-		break;
-	case tmrHw_CONTROL_PERIODIC:
-	case tmrHw_CONTROL_ONESHOT:
-		return pTmrHw[timerId].BackgroundLoad -
-		    pTmrHw[timerId].CurrentValue;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	uint32_t divider = 0;
-
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-	case tmrHw_CONTROL_PRESCALE_1:
-		divider = 1;
-		break;
-	case tmrHw_CONTROL_PRESCALE_16:
-		divider = 16;
-		break;
-	case tmrHw_CONTROL_PRESCALE_256:
-		divider = 256;
-		break;
-	default:
-		tmrHw_ASSERT(0);
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-	} else {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].InterruptClear = 0x1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-) {
-	if (pTmrHw[timerId].InterruptStatus) {
-		return tmrHw_INTERRUPT_STATUS_SET;
-	} else {
-		return tmrHw_INTERRUPT_STATUS_UNSET;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void	/*  void */
-) {
-	int i;
-
-	for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-		if (pTmrHw[i].InterruptStatus) {
-			return i;
-		}
-	}
-
-	return 0xFFFFFFFF;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-) {
-	(*fpPrint) ("Displaying register contents \n\n");
-	(*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-		    pTmrHw[timerId].LoadValue);
-	(*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-		    pTmrHw[timerId].BackgroundLoad);
-	(*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-		    pTmrHw[timerId].Control);
-	(*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptClear);
-	(*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-		    pTmrHw[timerId].RawInterruptStatus);
-	(*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptStatus);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-	tmrHw_RATE_t usec_tick_rate;
-	tmrHw_COUNT_t start_time;
-	tmrHw_COUNT_t delta_time;
-
-	start_time = tmrHw_GetCurrentCount(timerId);
-	usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-	delta_time = usecs * usec_tick_rate;
-
-	/* Busy wait */
-	while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-		;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241..0000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-
-#include <mach/timer.h>
-
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-
-/* ---- Public Variables 
------------------------------------------------- */
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 
4) | (channelIdx))
-
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-
-
-/* ---- Private Variables 
------------------------------------------------ */
-
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-
-#include "dma_device.c"
-
-/* ---- Private Function Prototypes 
-------------------------------------- */
-
-/* ---- Functions 
------------------------------------------------------- */
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-				  int count, int *eof, void *data)
-{
-	int controllerIdx;
-	int channelIdx;
-	int limit = count - 200;
-	int len = 0;
-	DMA_Channel_t *channel;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			if (len >= limit) {
-				break;
-			}
-
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			len +=
-			    sprintf(buf + len, "%d:%d ", controllerIdx,
-				    channelIdx);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				len +=
-				    sprintf(buf + len, "Dedicated for %s ",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-			} else {
-				len += sprintf(buf + len, "Shared ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-				len += sprintf(buf + len, "No ISR ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-				len += sprintf(buf + len, "Fifo: 128 ");
-			} else {
-				len += sprintf(buf + len, "Fifo: 64  ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-				len +=
-				    sprintf(buf + len, "InUse by %s",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-				len +=
-				    sprintf(buf + len, " (%s:%d)",
-					    channel->fileName,
-					    channel->lineNum);
-#endif
-			} else {
-				len += sprintf(buf + len, "Avail ");
-			}
-
-			if (channel->lastDevType != DMA_DEVICE_NONE) {
-				len +=
-				    sprintf(buf + len, "Last use: %s ",
-					    DMA_gDeviceAttribute[channel->
-								 lastDevType].
-					    name);
-			}
-
-			len += sprintf(buf + len, "\n");
-		}
-	}
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-				 int count, int *eof, void *data)
-{
-	int limit = count - 200;
-	int len = 0;
-	int devIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (devAttr->name == NULL) {
-			continue;
-		}
-
-		if (len >= limit) {
-			break;
-		}
-
-		len += sprintf(buf + len, "%-12s ", devAttr->name);
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			len +=
-			    sprintf(buf + len, "Dedicated %d:%d ",
-				    devAttr->dedicatedController,
-				    devAttr->dedicatedChannel);
-		} else {
-			len += sprintf(buf + len, "Shared DMA:");
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-				len += sprintf(buf + len, "0");
-			}
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-				len += sprintf(buf + len, "1");
-			}
-			len += sprintf(buf + len, " ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-			len += sprintf(buf + len, "NoISR ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-			len += sprintf(buf + len, "Allow-128 ");
-		}
-
-		len +=
-		    sprintf(buf + len,
-			    "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-			    devAttr->numTransfers, devAttr->transferTicks,
-			    devAttr->transferBytes,
-			    devAttr->ring.bytesAllocated);
-
-	}
-
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-	return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-	int controllerIdx;
-	int channelIdx;
-
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-	channelIdx = CHANNEL_FROM_HANDLE(handle);
-
-	if ((controllerIdx > DMA_NUM_CONTROLLERS)
-	    || (channelIdx > DMA_NUM_CHANNELS)) {
-		return NULL;
-	}
-	return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int irqStatus;
-
-	channel = (DMA_Channel_t *) dev_id;
-
-	/* Figure out why we were called, and knock down the interrupt */
-
-	irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-	dmacHw_clearInterrupt(channel->dmacHwHandle);
-
-	if ((channel->devType < 0)
-	    || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-		printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-		       channel->devType);
-		return IRQ_NONE;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Update stats */
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-		devAttr->transferTicks +=
-		    (timer_get_tick_count() - devAttr->transferStartTime);
-	}
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-		printk(KERN_ERR
-		       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-		       channel->devType, devAttr->name);
-	} else {
-		devAttr->numTransfers++;
-		devAttr->transferBytes += devAttr->numBytes;
-	}
-
-	/* Call any installed handler */
-
-	if (devAttr->devHandler != NULL) {
-		devAttr->devHandler(channel->devType, irqStatus,
-				    devAttr->userData);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    ) {
-	size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-
-	if ((ring == NULL) || (numDescriptors <= 0)) {
-		return -EINVAL;
-	}
-
-	ring->physAddr = 0;
-	ring->descriptorsAllocated = 0;
-	ring->bytesAllocated = 0;
-
-	ring->virtAddr = dma_alloc_writecombine(NULL,
-						     bytesToAlloc,
-						     &ring->physAddr,
-						     GFP_KERNEL);
-	if (ring->virtAddr == NULL) {
-		return -ENOMEM;
-	}
-
-	ring->bytesAllocated = bytesToAlloc;
-	ring->descriptorsAllocated = numDescriptors;
-
-	return dma_init_descriptor_ring(ring, numDescriptors);
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    ) {
-	if (ring->virtAddr != NULL) {
-		dma_free_writecombine(NULL,
-				      ring->bytesAllocated,
-				      ring->virtAddr, ring->physAddr);
-	}
-
-	ring->bytesAllocated = 0;
-	ring->descriptorsAllocated = 0;
-	ring->virtAddr = NULL;
-	ring->physAddr = 0;
-}
-
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    ) {
-	if (ring->virtAddr == NULL) {
-		return -EINVAL;
-	}
-	if (dmacHw_initDescriptor(ring->virtAddr,
-				  ring->physAddr,
-				  ring->bytesAllocated, numDescriptors) < 0) {
-		printk(KERN_ERR
-		       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int numDescriptors;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR
-		       "dma_calculate_descriptor_count: 
dmacHw_calculateDescriptorCount failed\n");
-		return -EINVAL;
-	}
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int rc;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	rc = dmacHw_setDataDescriptor(&devAttr->config,
-				      ring->virtAddr,
-				      (void *)srcData,
-				      (void *)dstData, numBytes);
-	if (rc < 0) {
-		printk(KERN_ERR
-		       "dma_add_descriptors: dmacHw_setDataDescriptor failed with 
code: %d\n",
-		       rc);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_add_descriptors);
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	/* Free the previously allocated descriptor ring */
-
-	dma_free_descriptor_ring(&devAttr->ring);
-
-	if (ring != NULL) {
-		/* Copy in the new one */
-
-		devAttr->ring = *ring;
-	}
-
-	/* Set things up so that if dma_transfer is called then this descriptor */
-	/* ring will get freed. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	memset(ring, 0, sizeof(*ring));
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	*ring = devAttr->ring;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-static int ConfigChannel(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int controllerIdx;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-		if (devAttr->config.transferType ==
-		    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-			devAttr->config.dstPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		} else if (devAttr->config.transferType ==
-			   dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-			devAttr->config.srcPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		}
-	}
-
-	if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-		printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_init(void)
-{
-	int rc = 0;
-	int controllerIdx;
-	int channelIdx;
-	DMA_Device_t devIdx;
-	DMA_Channel_t *channel;
-	DMA_Handle_t dedicatedHandle;
-
-	memset(&gDMA, 0, sizeof(gDMA));
-
-	sema_init(&gDMA.lock, 0);
-	init_waitqueue_head(&gDMA.freeChannelQ);
-
-	/* Initialize the Hardware */
-
-	dmacHw_initDma();
-
-	/* Start off by marking all of the DMA channels as shared. */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			channel->flags = 0;
-			channel->devType = DMA_DEVICE_NONE;
-			channel->lastDevType = DMA_DEVICE_NONE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-			channel->fileName = "";
-			channel->lineNum = 0;
-#endif
-
-			channel->dmacHwHandle =
-			    dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-						    (controllerIdx,
-						     channelIdx));
-			dmacHw_initChannel(channel->dmacHwHandle);
-		}
-	}
-
-	/* Record any special attributes that channels may have */
-
-	gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-
-	/* Now walk through and record the dedicated channels. */
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-		    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-			printk(KERN_ERR
-			       "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-			       devAttr->name);
-			rc = -EINVAL;
-			goto out;
-		}
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			/* This is a dedicated device. Mark the channel as being reserved. */
-
-			if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Controller %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedController);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Channel %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedChannel);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			dedicatedHandle =
-			    MAKE_HANDLE(devAttr->dedicatedController,
-					devAttr->dedicatedChannel);
-			channel = HandleToChannel(dedicatedHandle);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				printk
-				    ("DMA Device: %s attempting to use same DMA Controller:Channel 
(%d:%d) as %s\n",
-				     devAttr->name,
-				     devAttr->dedicatedController,
-				     devAttr->dedicatedChannel,
-				     DMA_gDeviceAttribute[channel->devType].
-				     name);
-				rc = -EBUSY;
-				goto out;
-			}
-
-			channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-			channel->devType = devIdx;
-
-			if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-				channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-			}
-
-			/* For dedicated channels, we can go ahead and configure the DMA 
channel now */
-			/* as well. */
-
-			ConfigChannel(dedicatedHandle);
-		}
-	}
-
-	/* Go through and register the interrupt handlers */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-				snprintf(channel->name, sizeof(channel->name),
-					 "dma %d:%d %s", controllerIdx,
-					 channelIdx,
-					 channel->devType ==
-					 DMA_DEVICE_NONE ? "" :
-					 DMA_gDeviceAttribute[channel->devType].
-					 name);
-
-				rc =
-				     request_irq(IRQ_DMA0C0 +
-						 (controllerIdx *
-						  DMA_NUM_CHANNELS) +
-						 channelIdx,
-						 dma_interrupt_handler,
-						 IRQF_DISABLED, channel->name,
-						 channel);
-				if (rc != 0) {
-					printk(KERN_ERR
-					       "request_irq for IRQ_DMA%dC%d failed\n",
-					       controllerIdx, channelIdx);
-				}
-			}
-		}
-	}
-
-	/* Create /proc/dma/channels and /proc/dma/devices */
-
-	gDmaDir = proc_mkdir("dma", NULL);
-
-	if (gDmaDir == NULL) {
-		printk(KERN_ERR "Unable to create /proc/dma\n");
-	} else {
-		create_proc_read_entry("channels", 0, gDmaDir,
-				       dma_proc_read_channels, NULL);
-		create_proc_read_entry("devices", 0, gDmaDir,
-				       dma_proc_read_devices, NULL);
-	}
-
-out:
-
-	up(&gDMA.lock);
-
-	return rc;
-}
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-	DMA_Handle_t handle;
-	DMA_DeviceAttribute_t *devAttr;
-	DMA_Channel_t *channel;
-	int controllerIdx;
-	int controllerIdx2;
-	int channelIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-		handle = -ENODEV;
-		goto out;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	{
-		char *s;
-
-		s = strrchr(fileName, '/');
-		if (s != NULL) {
-			fileName = s + 1;
-		}
-	}
-#endif
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-		/* This device has already been requested and not been freed */
-
-		printk(KERN_ERR "%s: device %s is already requested\n",
-		       __func__, devAttr->name);
-		handle = -EBUSY;
-		goto out;
-	}
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-		/* This device has a dedicated channel. */
-
-		channel =
-		    &gDMA.controller[devAttr->dedicatedController].
-		    channel[devAttr->dedicatedChannel];
-		if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-			handle = -EBUSY;
-			goto out;
-		}
-
-		channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-		devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-		channel->fileName = fileName;
-		channel->lineNum = lineNum;
-#endif
-		handle =
-		    MAKE_HANDLE(devAttr->dedicatedController,
-				devAttr->dedicatedChannel);
-		goto out;
-	}
-
-	/* This device needs to use one of the shared channels. */
-
-	handle = DMA_INVALID_HANDLE;
-	while (handle == DMA_INVALID_HANDLE) {
-		/* Scan through the shared channels and see if one is available */
-
-		for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-		     controllerIdx2++) {
-			/* Check to see if we should try on controller 1 first. */
-
-			controllerIdx = controllerIdx2;
-			if ((devAttr->
-			     flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-				controllerIdx = 1 - controllerIdx;
-			}
-
-			/* See if the device is available on the controller being tested */
-
-			if ((devAttr->
-			     flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-			    != 0) {
-				for (channelIdx = 0;
-				     channelIdx < DMA_NUM_CHANNELS;
-				     channelIdx++) {
-					channel =
-					    &gDMA.controller[controllerIdx].
-					    channel[channelIdx];
-
-					if (((channel->
-					      flags &
-					      DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-					     0)
-					    &&
-					    ((channel->
-					      flags & DMA_CHANNEL_FLAG_IN_USE)
-					     == 0)) {
-						if (((channel->
-						      flags &
-						      DMA_CHANNEL_FLAG_LARGE_FIFO)
-						     != 0)
-						    &&
-						    ((devAttr->
-						      flags &
-						      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-						     == 0)) {
-							/* This channel is a large fifo - don't tie it up */
-							/* with devices that we don't want using it. */
-
-							continue;
-						}
-
-						channel->flags |=
-						    DMA_CHANNEL_FLAG_IN_USE;
-						channel->devType = dev;
-						devAttr->flags |=
-						    DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-						channel->fileName = fileName;
-						channel->lineNum = lineNum;
-#endif
-						handle =
-						    MAKE_HANDLE(controllerIdx,
-								channelIdx);
-
-						/* Now that we've reserved the channel - we can go ahead and 
configure it */
-
-						if (ConfigChannel(handle) != 0) {
-							handle = -EIO;
-							printk(KERN_ERR
-							       "dma_request_channel: ConfigChannel failed\n");
-						}
-						goto out;
-					}
-				}
-			}
-		}
-
-		/* No channels are currently available. Let's wait for one to free up. */
-
-		{
-			DEFINE_WAIT(wait);
-
-			prepare_to_wait(&gDMA.freeChannelQ, &wait,
-					TASK_INTERRUPTIBLE);
-			up(&gDMA.lock);
-			schedule();
-			finish_wait(&gDMA.freeChannelQ, &wait);
-
-			if (signal_pending(current)) {
-				/* We don't currently hold gDMA.lock, so we return directly */
-
-				return -ERESTARTSYS;
-			}
-		}
-
-		if (down_interruptible(&gDMA.lock)) {
-			return -ERESTARTSYS;
-		}
-	}
-
-out:
-	up(&gDMA.lock);
-
-	return handle;
-}
-
-/* Create both _dbg and non _dbg functions for modules. */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-	return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t handle	/* DMA handle. */
-    ) {
-	int rc = 0;
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		rc = -EINVAL;
-		goto out;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-		channel->lastDevType = channel->devType;
-		channel->devType = DMA_DEVICE_NONE;
-	}
-	channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-	devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-
-out:
-	up(&gDMA.lock);
-
-	wake_up_interruptible(&gDMA.freeChannelQ);
-
-	return rc;
-}
-
-EXPORT_SYMBOL(dma_free_channel);
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t device	/* Device to check. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, numDescriptors);
-			return rc;
-		}
-		/* Setup the descriptor for this transfer */
-
-		if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-					  devAttr->ring.physAddr,
-					  devAttr->ring.bytesAllocated,
-					  numDescriptors) < 0) {
-			printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-			       __func__);
-			return -EINVAL;
-		}
-	} else {
-		/* We've already got enough ring buffer allocated. All we need to do 
is reset */
-		/* any control information, just in case the previous DMA was stopped. */
-
-		dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Remember the critical information for this transfer so that we can 
eliminate */
-	/* another call to dma_alloc_descriptors if the caller reuses the same 
buffers */
-
-	devAttr->prevSrcData = srcData;
-	devAttr->prevDstData = dstData;
-	devAttr->prevNumBytes = numBytes;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptors);
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDst1Descriptors;
-	int numDst2Descriptors;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDst1Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData1, numBytes);
-	if (numDst1Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDst2Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData2, numBytes);
-	if (numDst2Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDescriptors = numDst1Descriptors + numDst2Descriptors;
-	/* printk("numDescriptors: %d\n", numDescriptors); */
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, ringBytesRequired);
-			return rc;
-		}
-	}
-
-	/* Setup the descriptor for this transfer. Since this function is used 
with */
-	/* CONTINUOUS DMA operations, we need to reinitialize every time, 
otherwise */
-	/* setDataDescriptor will keep trying to append onto the end. */
-
-	if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-				  devAttr->ring.physAddr,
-				  devAttr->ring.bytesAllocated,
-				  numDescriptors) < 0) {
-		printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-		return -EINVAL;
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData1, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData2, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* You should use dma_start_transfer rather than dma_transfer_xxx so 
we don't */
-	/* try to make the 'prev' variables right. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_start_transfer);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	dmacHw_stopTransfer(channel->dmacHwHandle);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_stop_transfer);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	dmacHw_TRANSFER_STATUS_e status;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	while ((status =
-		dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-	       dmacHw_TRANSFER_STATUS_BUSY) {
-		;
-	}
-
-	if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-		printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-		return -EIO;
-	}
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_wait_transfer_done);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* We keep track of the information about the previous request for this */
-	/* device, and if the attributes match, then we can use the 
descriptors we setup */
-	/* the last time, and not have to reinitialize everything. */
-
-	{
-		rc =
-		     dma_alloc_descriptors(handle, transferType, srcData,
-					   dstData, numBytes);
-		if (rc != 0) {
-			return rc;
-		}
-	}
-
-	/* And kick off the transfer */
-
-	devAttr->numBytes = numBytes;
-	devAttr->transferStartTime = timer_get_tick_count();
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_transfer);
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-	unsigned long flags;
-
-	if (!IsDeviceValid(dev)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-	local_irq_save(flags);
-
-	devAttr->userData = userData;
-	devAttr->devHandler = devHandler;
-
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c 
b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad73..0000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-	[DMA_DEVICE_MEM_TO_MEM] =	/* MEM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-mem",
-	 .config = {
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-
-		    },
-	 },
-	[DMA_DEVICE_VPM_MEM_TO_MEM] =	/* VPM */
-	{
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-	 .name = "vpm",
-	 .dedicatedController = 0,
-	 .dedicatedChannel = 0,
-	 /* reserve DMA0:0 for VPM */
-	 },
-	[DMA_DEVICE_NAND_MEM_TO_MEM] =	/* NAND */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "nand",
-	 .config = {
-		    .srcPeripheralPort = 0,
-		    .dstPeripheralPort = 0,
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-		    },
-	 },
-	[DMA_DEVICE_PIF_MEM_TO_DEV] =	/* PIF TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_tx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    /* dstPeripheralPort          = 5 or 14 */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_PIF_DEV_TO_MEM] =	/* PIF RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-	 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_rx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    /* srcPeripheralPort          = 5 or 14 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_DEV_TO_MEM] =	/* I2S RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_rx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: I2S0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_MEM_TO_DEV] =	/* I2S TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: I2S0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_DEV_TO_MEM] =	/* I2S1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: I2S1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_MEM_TO_DEV] =	/* I2S1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: I2S1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_ESW_MEM_TO_DEV] =	/* ESW TX */
-	{
-	 .name = "esw_tx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 3,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: ESW (MTP) */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x30490010,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_ESW_DEV_TO_MEM] =	/* ESW RX */
-	{
-	 .name = "esw_rx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 2,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: ESW (PTM) */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x30480010,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =	/* APM Codec A Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =	/* APM Codec A Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: Codec A Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =	/* APM Codec B Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec B Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =	/* APM Codec B Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 5,	/* DST: Codec B Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =	/* APM Codec C Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "apm_c_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec C Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =	/* PCM0 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_rx",
-	 .config = {
-		    .srcPeripheralPort = 12,	/* SRC: PCM0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =	/* PCM0 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 13,	/* DST: PCM0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =	/* PCM1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_rx",
-	 .config = {
-		    .srcPeripheralPort = 14,	/* SRC: PCM1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =	/* PCM1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 15,	/* DST: PCM1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_DEV_TO_MEM] =	/* SPUM RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_rx",
-	 .config = {
-		    .srcPeripheralPort = 6,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    /* on the RX side, SPU needs to be the flow controller */
-		    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_MEM_TO_DEV] =	/* SPUM TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 7,	/* DST: SPUM */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_MEM_TO_VRAM] =	/* MEM 2 VRAM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-vram",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-	[DMA_DEVICE_VRAM_TO_MEM] =	/* VRAM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "vram-to-mem",
-	 .config = {
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);	/* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h 
b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da87..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY 
CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h 
b/arch/arm/mach-bcmring/include/cfg_global_defines.h
deleted file mode 100644
index b5beb0b..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-
-/* CHIP */
-#define BCM1103 1
-
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h 
b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e5..0000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h 
b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d803..0000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use 
the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h 
b/arch/arm/mach-bcmring/include/csp/dmacHw.h
deleted file mode 100644
index e6a1dc4..0000000
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-
-#include <stddef.h>
-
-#include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
-
-/* Define DMA Channel ID using DMA controller number (m) and channel 
number (c).
-
-   System specific channel ID should be defined as follows
-
-   For example:
-
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-
-typedef enum {
-	dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,	/* 
Channel priority 0. Lowest priority DMA channel */
-	dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,	/* 
Channel priority 1 */
-	dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,	/* 
Channel priority 2 */
-	dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,	/* 
Channel priority 3 */
-	dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,	/* 
Channel priority 4 */
-	dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,	/* 
Channel priority 5 */
-	dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,	/* 
Channel priority 6 */
-	dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7	/* Channel 
priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-
-/* Source destination master interface */
-typedef enum {
-	dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,	/* Source DMA 
master interface 1 */
-	dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,	/* Source DMA 
master interface 2 */
-	dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,	/* Destination 
DMA master interface 1 */
-	dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2	/* Destination 
DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-
-typedef enum {
-	dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8,	/* 
Source 8 bit  (1 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,	/* 
Source 16 bit (2 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,	/* 
Source 32 bit (4 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,	/* 
Source 64 bit (8 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8,	/* 
Destination 8 bit  (1 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,	/* 
Destination 16 bit (2 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,	/* 
Destination 32 bit (4 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64	/* 
Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-
-typedef enum {
-	dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,	/* Source No 
burst */
-	dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,	/* Source 4  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,	/* Source 8  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,	/* Source 16 
X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,	/* Destination 
No burst */
-	dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,	/* Destination 
4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,	/* Destination 
8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16	/* Destination 
16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-
-typedef enum {
-	dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,	/* 
Memory to memory transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, 
/* Peripheral to memory transfer */
-	dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, 
/* Memory to peripheral transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = 
dmacHw_REG_CTL_TTFC_PP_DMAC	/* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-
-typedef enum {
-	dmacHw_TRANSFER_MODE_PERREQUEST,	/* Block transfer per DMA request */
-	dmacHw_TRANSFER_MODE_CONTINUOUS,	/* Continuous transfer of streaming 
data */
-	dmacHw_TRANSFER_MODE_PERIODIC	/* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-
-typedef enum {
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,	/* 
Increment source address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,	/* 
Decrement source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,	/* 
Increment destination address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,	/* 
Decrement destination address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,	/* No 
change in source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC	/* No 
change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-
-typedef enum {
-	dmacHw_FLOW_CONTROL_DMA,	/* DMA working as flow controller (default) */
-	dmacHw_FLOW_CONTROL_PERIPHERAL	/* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-
-typedef enum {
-	dmacHw_TRANSFER_STATUS_BUSY,	/* DMA Transfer ongoing */
-	dmacHw_TRANSFER_STATUS_DONE,	/* DMA Transfer completed */
-	dmacHw_TRANSFER_STATUS_ERROR	/* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_DISABLE,	/* Interrupt disable  */
-	dmacHw_INTERRUPT_ENABLE	/* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_STATUS_NONE = 0x0,	/* No DMA interrupt */
-	dmacHw_INTERRUPT_STATUS_TRANS = 0x1,	/* End of DMA transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,	/* End of block transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_ERROR = 0x4	/* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,	/* Number of DMA channel */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,	/* Maximum channel 
burst size */
-	dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,	/* Number of DMA master 
interface */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,	/* Channel Data bus width */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE	/* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-
-typedef unsigned long dmacHw_HANDLE_t;	/* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;	/* DMA channel Id.  Must be created using
-				   "dmacHw_MAKE_CHANNEL_ID" macro
-				 */
-/* DMA channel configuration parameters */
-typedef struct {
-	uint32_t srcPeripheralPort;	/* Source peripheral port */
-	uint32_t dstPeripheralPort;	/* Destination peripheral port */
-	uint32_t srcStatusRegisterAddress;	/* Source status register address */
-	uint32_t dstStatusRegisterAddress;	/* Destination status register 
address of type  */
-
-	uint32_t srcGatherWidth;	/* Number of bytes gathered before successive 
gather opearation */
-	uint32_t srcGatherJump;	/* Number of bytes jumpped before successive 
gather opearation */
-	uint32_t dstScatterWidth;	/* Number of bytes sacattered before 
successive scatter opearation */
-	uint32_t dstScatterJump;	/* Number of bytes jumpped  before successive 
scatter opearation */
-	uint32_t maxDataPerBlock;	/* Maximum number of bytes to be transferred 
per block/descrptor.
-					   0 = Maximum possible.
-					 */
-
-	dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate;	/* Source address update mode */
-	dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate;	/* Destination address update 
mode */
-	dmacHw_TRANSFER_TYPE_e transferType;	/* DMA transfer type  */
-	dmacHw_TRANSFER_MODE_e transferMode;	/* DMA transfer mode */
-	dmacHw_MASTER_INTERFACE_e srcMasterInterface;	/* DMA source interface  */
-	dmacHw_MASTER_INTERFACE_e dstMasterInterface;	/* DMA destination 
interface */
-	dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;	/* Source 
transaction width   */
-	dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;	/* Destination 
transaction width */
-	dmacHw_BURST_WIDTH_e srcMaxBurstWidth;	/* Source burst width */
-	dmacHw_BURST_WIDTH_e dstMaxBurstWidth;	/* Destination burst width */
-	dmacHw_INTERRUPT_e blockTransferInterrupt;	/* Block trsnafer interrupt */
-	dmacHw_INTERRUPT_e completeTransferInterrupt;	/* Complete DMA trsnafer 
interrupt */
-	dmacHw_INTERRUPT_e errorInterrupt;	/* Error interrupt */
-	dmacHw_CHANNEL_PRIORITY_e channelPriority;	/* Channel priority */
-	dmacHw_FLOW_CONTROL_e flowControler;	/* Data flow controller */
-} dmacHw_CONFIG_t;
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel 
handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/*  [ IN ] Number of 
descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel 
handle  */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			     void *pSrcAddr,	/*  [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*  [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*  [ IN ] Length in bytes   */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				uint32_t ctlAddress,	/*  [ IN ] Address of the device control 
register  */
-				uint32_t control	/*  [ IN ] Device control information */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle    */
-			       dmacHw_CONFIG_t *pConfig,	/*  [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			       void **ppBbuf,	/*  [ OUT ] Data received */
-			       size_t *pLlen	/*  [ OUT ] Length of the data received */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*  [ IN ] 
DMA Channel handle   */
-				     dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-				     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				     uint32_t srcAddr,	/*  [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*  [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*  [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*  [ IN ] Number of descriptor to set */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-		   void (*fpFree) (void *)	/*  [ IN ] Function pointer to free data 
memory */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			       void *userData	/*  [ IN ] User data  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle  */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h 
b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd..0000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h 
b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8..0000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h 
b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5..0000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h 
b/arch/arm/mach-bcmring/include/csp/reg.h
deleted file mode 100644
index 56654d2..0000000
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-
-#ifndef CSP_REG_H
-#define CSP_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-
-/* Macros used to define a sequence of reserved registers. The start / 
end */
-/* are byte offsets in the particular register definition, with the 
"end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / 
sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / 
sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / 
sizeof(uint32_t)]
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-	unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-
-#else
-
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-
-#endif
-
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg &= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg |= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
-				     uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg = (*reg & mask) | value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-	*reg = value;
-}
-
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h 
b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e07..0000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-	secHw_MODE_SECURE = 0x0,	/* Switches processor into secure mode */
-	secHw_MODE_NONSECURE = 0x1	/* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t	/* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE	/* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h 
b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718b..0000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h 
b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e400..0000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h 
b/arch/arm/mach-bcmring/include/csp/tmrHw.h
deleted file mode 100644
index 2cbb530..0000000
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-
-#include <csp/stdint.h>
-
-typedef uint32_t tmrHw_ID_t;	/* Timer ID */
-typedef uint32_t tmrHw_COUNT_t;	/* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;	/* Timer interval */
-typedef uint32_t tmrHw_RATE_t;	/* Timer event (count/interrupt) rate */
-
-typedef enum {
-	tmrHw_INTERRUPT_STATUS_SET,	/* Interrupted  */
-	tmrHw_INTERRUPT_STATUS_UNSET	/* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	tmrHw_CAPABILITY_CLOCK,	/* Clock speed in HHz */
-	tmrHw_CAPABILITY_RESOLUTION	/* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer 
id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs	/*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d5..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_H
-#define CAP_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Public Constants and Types 
--------------------------------------- */
-typedef enum {
-	CAP_NOT_PRESENT = 0,
-	CAP_PRESENT
-} CAP_RC_T;
-
-typedef enum {
-	CAP_VPM,
-	CAP_ETH_PHY,
-	CAP_ETH_GMII,
-	CAP_ETH_SGMII,
-	CAP_USB,
-	CAP_TSC,
-	CAP_EHSS,
-	CAP_SDIO,
-	CAP_UARTB,
-	CAP_KEYPAD,
-	CAP_CLCD,
-	CAP_GE,
-	CAP_LEDM,
-	CAP_BBL,
-	CAP_VDEC,
-	CAP_PIF,
-	CAP_APM,
-	CAP_SPU,
-	CAP_PKA,
-	CAP_RNG,
-} CAP_CAPABILITY_T;
-
-typedef enum {
-	CAP_LCD_WVGA = 0,
-	CAP_LCD_VGA = 0x1,
-	CAP_LCD_WQVGA = 0x2,
-	CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 933ce68..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <cfg_global.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | 
CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS 
| CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | 
CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | 
CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | 
CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | 
CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | 
CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | 
CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index)
-{
-	CAP_RC_T returnVal = CAP_NOT_PRESENT;
-
-	switch (capability) {
-	case CAP_VPM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_PHY:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_GMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_SGMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_USB:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_TSC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_EHSS:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SDIO:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_UARTB:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_KEYPAD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_CLCD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_GE:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_LEDM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_BBL:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_VDEC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PIF:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_APM:
-		{
-			if ((index == 0)
-			    && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 2)
-			    && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SPU:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PKA:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_RNG:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	default:
-		{
-		}
-		break;
-	}
-	return returnVal;
-}
-
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-	return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-	return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-	return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-	return (CAP_LCD_RES_T)
-		((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-		 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 1619733..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-
-typedef uint32_t chipcHw_freq;
-
-/* Configurable miscellaneous clocks */
-typedef enum {
-	chipcHw_CLOCK_DDR,	/* DDR PHY Clock */
-	chipcHw_CLOCK_ARM,	/* ARM Clock */
-	chipcHw_CLOCK_ESW,	/* Ethernet Switch Clock */
-	chipcHw_CLOCK_VPM,	/* VPM Clock */
-	chipcHw_CLOCK_ESW125,	/* Ethernet MII Clock */
-	chipcHw_CLOCK_UART,	/* UART Clock */
-	chipcHw_CLOCK_SDIO0,	/* SDIO 0 Clock */
-	chipcHw_CLOCK_SDIO1,	/* SDIO 1 Clock */
-	chipcHw_CLOCK_SPI,	/* SPI Clock */
-	chipcHw_CLOCK_ETM,	/* ARM ETM Clock */
-
-	chipcHw_CLOCK_BUS,	/* BUS Clock */
-	chipcHw_CLOCK_OTP,	/* OTP Clock */
-	chipcHw_CLOCK_I2C,	/* I2C Host Clock */
-	chipcHw_CLOCK_I2S0,	/* I2S 0 Host Clock */
-	chipcHw_CLOCK_RTBUS,	/* DDR PHY Configuration Clock */
-	chipcHw_CLOCK_APM100,	/* APM100 Clock */
-	chipcHw_CLOCK_TSC,	/* Touch screen Clock */
-	chipcHw_CLOCK_LED,	/* LED Clock */
-
-	chipcHw_CLOCK_USB,	/* USB Clock */
-	chipcHw_CLOCK_LCD,	/* LCD CLock */
-	chipcHw_CLOCK_APM,	/* APM Clock */
-
-	chipcHw_CLOCK_I2S1,	/* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-
-/* System booting strap options */
-typedef enum {
-	chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-	chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-	    chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-	chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-
-/* System booting modes */
-typedef enum {
-	chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-	chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-	chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-	chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-
-/* NAND Flash page size strap options */
-typedef enum {
-	chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-	chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-	chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-	chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-
-/* GPIO Pin function */
-typedef enum {
-	chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-	chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-	chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-	chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-	chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-	chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-	chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-	chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-	chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-	chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-	chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-	chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-	chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-	chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-
-/* PIN Output slew rate */
-typedef enum {
-	chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-	chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-
-/* PIN Current drive strength */
-typedef enum {
-	chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-	chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-	chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-	chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-	chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-	chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-
-/* PIN Pull up register settings */
-typedef enum {
-	chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-	chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-	chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-
-/* PIN input type settings */
-typedef enum {
-	chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-	chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-	chipcHw_SPREAD_SPECTRUM_DISALLOW,	/* Spread spectrum support is not 
allowed */
-	chipcHw_SPREAD_SPECTRUM_ALLOW	/* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-
-typedef struct {
-	chipcHw_SPREAD_SPECTRUM_e ssSupport;	/* Allow/Disalow to support 
spread spectrum.
-						   If supported, call chipcHw_enableSpreadSpectrum ()
-						   to activate the spread spectrum with desired spread. */
-	uint32_t pllVcoFreqHz;	/* PLL VCO frequency in Hz */
-	uint32_t pll2VcoFreqHz;	/* PLL2 VCO frequency in Hz */
-	uint32_t busClockFreqHz;	/* Bus clock frequency in Hz */
-	uint32_t armBusRatio;	/* ARM clock : Bus clock */
-	uint32_t vpmBusRatio;	/* VPM clock : Bus clock */
-	uint32_t ddrBusRatio;	/* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-
-/* CHIP revision number */
-typedef enum {
-	chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-	chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-	chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-	chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-	chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-
-typedef enum {
-	chipcHw_DDR_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_WIDE	/*  Wider margin for DDR phase align 
condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_WIDE	/*  Wider margin for VPM phase align 
condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-
-#define chipcHw_XTAL_FREQ_Hz                    25000000	/* Reference 
clock frequency in Hz */
-
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < 
(chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-									     /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 
0)	/* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 
1)	/* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 
2)	/* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 
3)	/* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 
4)	/* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 
5)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 
6)	/* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 
7)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 
8)	/* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 
9)	/* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 
10)	/* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 
11)	/* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 
12)	/* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 
13)	/* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 
14)	/* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 
15)	/* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 
16)	/* UART Receive */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,	/*  [ IN ] VCO frequency in 
Hz */
-			chipcHw_SPREAD_SPECTRUM_e ssSupport	/*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz	/*  [ IN ] VCO frequency in 
Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock	/* 
[ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock	/* 
  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetDisable(uint64_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetEnable(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlDisable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlEnable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_OTP_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int 
pin	/* GPIO Pin number */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,	/* GPIO Pin 
number */
-					      chipcHw_GPIO_FUNCTION_e func	/* Configuration function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					  chipcHw_PIN_SLEW_RATE_e slewRate	/* Pin slew rate */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,	/* Pin of 
type chipcHw_PIN_XXXXX */
-					       chipcHw_PIN_CURRENT_STRENGTH_e curr	/* Pin current rating */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					chipcHw_PIN_PULL_e pullup	/* Pullup register settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					   chipcHw_PIN_INPUTTYPE_e inputType	/* Pin input type */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t 
vpmRatio,
-			   uint32_t ddrRatio);
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin	/* 
Margin alinging DDR  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin	/* 
Margin alinging VPM  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index 03238c2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-typedef enum {
-	chipcHw_OPTYPE_BYPASS,	/* Bypass operation */
-	chipcHw_OPTYPE_OUTPUT	/* Output operation */
-} chipcHw_OPTYPE_e;
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------- */
-/* ---- Public Function Prototypes 
---------------------------------------- */
-/* ---- Private Function Prototypes 
--------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode);
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-	return pChipcHw->ChipId;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-	if ((pChipcHw->
-	     PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-	    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-		    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-		    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-		     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-		    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-	ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-	return (pChipcHw->
-		 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
-		chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-	return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-	return pChipcHw->BusIntfClock;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-	chipcHw_softResetEnable(mask);
-	chipcHw_softResetDisable(mask);
-}
-
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	/* Deassert module soft reset */
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 ^= ctrl1;
-	pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-	uint32_t unhold = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 |= ctrl1;
-	/* Mask out unhold request bits */
-	pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-
-	/* Process unhold requests */
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-		unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-	}
-
-	if (unhold) {
-		/* Make sure unhold request is effective */
-		pChipcHw->SoftReset1 &= ~unhold;
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-	reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-	reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-	return pChipcHw->Sticky;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask & chipcHw_REG_STICKY_POR_BROM) {
-		bits |= chipcHw_REG_STICKY_POR_BROM;
-	} else {
-		uint32_t sticky;
-		sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-			bits |= chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask &
-	    (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-	     chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-	     chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-		uint32_t sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-			bits = chipcHw_REG_STICKY_BOOT_DONE;
-			mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits | mask;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-	return pChipcHw->SoftStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-	reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-	return pChipcHw->PinStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-	uint32_t softStraps;
-
-	/*
-	 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-	 ** which copies HW straps to soft straps if there is no override
-	 */
-	softStraps = chipcHw_getSoftStraps();
-
-	return softStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-	uint32_t softStraps;
-
-	REG_LOCAL_IRQ_SAVE;
-	softStraps = chipcHw_getSoftStraps();
-
-	if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-		/* Copy HW straps to software straps */
-		chipcHw_setSoftStraps(chipcHw_getPinStraps());
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-	if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-	return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
-		(chipcHw_REG_GPIO_MUX_MASK <<
-		 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
-	    chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-					      chipcHw_GPIO_FUNCTION_e func)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-	    ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-	    func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-					  chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-	    ~(chipcHw_REG_SLEW_RATE_MASK <<
-	      chipcHw_REG_SLEW_RATE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-	    (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-					       chipcHw_PIN_CURRENT_STRENGTH_e
-					       curr)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-	    ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-	    (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, 
chipcHw_PIN_PULL_e pullup)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-	    ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-	    (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-					   chipcHw_PIN_INPUTTYPE_e inputType)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-	    ~(chipcHw_REG_INPUTTYPE_MASK <<
-	      chipcHw_REG_INPUTTYPE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-	    (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain 
device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode)
-{
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			/* PLL clock output enable/disable */
-			if (mode) {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock enable is inverted */
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			} else {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock disable is inverted */
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			/* PLL clock bypass enable/disable */
-			if (mode) {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	} else if (pClockCtrl) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-
-	/* Disable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-
-	/* Enable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-	/* Enable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-	/* Disable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-
-}
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-	return pChipcHw->SoftStraps & 0x00000001;
-}
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-	reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-	reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig2,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig2,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-	return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-	return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig2 |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-	REG_LOCAL_IRQ_SAVE;
-	if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	} else {
-		pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	}
-	pChipcHw->VPMPhaseCtrl2 =
-	    (pChipcHw->
-	     VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-			       chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->DDRPhaseCtrl1 &=
-		    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->DDRPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMPhaseCtrl1 &=
-		    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->VPMPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &=
-	    ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->DDRPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &=
-	    ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->VPMPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_ddrHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_vpmHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index b162448..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-
-typedef struct {
-	uint32_t ChipId;	/* Chip ID */
-	uint32_t DDRClock;	/* PLL1 Channel 1 for DDR clock */
-	uint32_t ARMClock;	/* PLL1 Channel 2 for ARM clock */
-	uint32_t ESWClock;	/* PLL1 Channel 3 for ESW system clock */
-	uint32_t VPMClock;	/* PLL1 Channel 4 for VPM clock */
-	uint32_t ESW125Clock;	/* PLL1 Channel 5 for ESW 125MHz clock */
-	uint32_t UARTClock;	/* PLL1 Channel 6 for UART clock */
-	uint32_t SDIO0Clock;	/* PLL1 Channel 7 for SDIO 0 clock */
-	uint32_t SDIO1Clock;	/* PLL1 Channel 8 for SDIO 1 clock */
-	uint32_t SPIClock;	/* PLL1 Channel 9 for SPI master Clock  */
-	uint32_t ETMClock;	/* PLL1 Channel 10 for ARM ETM Clock  */
-
-	uint32_t ACLKClock;	/* ACLK Clock (Divider) */
-	uint32_t OTPClock;	/* OTP Clock  (Divider) */
-	uint32_t I2CClock;	/* I2C Clock (CK_13m) (Divider) */
-	uint32_t I2S0Clock;	/* I2S0 Clock (Divider) */
-	uint32_t RTBUSClock;	/* RTBUS (DDR PHY Config.) Clock (Divider) */
-	uint32_t pad1;
-	uint32_t APM100Clock;	/* APM 100MHz CLK Clock (Divider) */
-	uint32_t TSCClock;	/* TSC Clock (Divider) */
-	uint32_t LEDClock;	/* LED Clock (Divider) */
-
-	uint32_t USBClock;	/* PLL2 Channel 1 for USB clock */
-	uint32_t LCDClock;	/* PLL2 Channel 2 for LCD clock */
-	uint32_t APMClock;	/* PLL2 Channel 3 for APM 200 MHz clock */
-
-	uint32_t BusIntfClock;	/* Bus interface clock */
-
-	uint32_t PLLStatus;	/* PLL status register (PLL1) */
-	uint32_t PLLConfig;	/* PLL configuration register  (PLL1) */
-	uint32_t PLLPreDivider;	/* PLL pre-divider control register (PLL1) */
-	uint32_t PLLDivider;	/* PLL divider control register (PLL1) */
-	uint32_t PLLControl1;	/* PLL analog control register #1 (PLL1) */
-	uint32_t PLLControl2;	/* PLL analog control register #2 (PLL1) */
-
-	uint32_t I2S1Clock;	/* I2S1 Clock  */
-	uint32_t AudioEnable;	/* Enable/ disable audio channel */
-	uint32_t SoftReset1;	/* Reset blocks */
-	uint32_t SoftReset2;	/* Reset blocks */
-	uint32_t Spare1;	/* Phase align interrupts */
-	uint32_t Sticky;	/* Sticky bits */
-	uint32_t MiscCtrl;	/* Misc. control */
-	uint32_t pad3[3];
-
-	uint32_t PLLStatus2;	/* PLL status register (PLL2) */
-	uint32_t PLLConfig2;	/* PLL configuration register  (PLL2) */
-	uint32_t PLLPreDivider2;	/* PLL pre-divider control register (PLL2) */
-	uint32_t PLLDivider2;	/* PLL divider control register (PLL2) */
-	uint32_t PLLControl12;	/* PLL analog control register #1 (PLL2) */
-	uint32_t PLLControl22;	/* PLL analog control register #2 (PLL2) */
-
-	uint32_t DDRPhaseCtrl1;	/* DDR Clock Phase Alignment control1 */
-	uint32_t VPMPhaseCtrl1;	/* VPM Clock Phase Alignment control1 */
-	uint32_t PhaseAlignStatus;	/* DDR/VPM Clock Phase Alignment Status */
-	uint32_t PhaseCtrlStatus;	/* DDR/VPM Clock HW DDR/VPM ph_ctrl and 
load_ch Status */
-	uint32_t DDRPhaseCtrl2;	/* DDR Clock Phase Alignment control2 */
-	uint32_t VPMPhaseCtrl2;	/* VPM Clock Phase Alignment control2 */
-	uint32_t pad4[9];
-
-	uint32_t SoftOTP1;	/* Software OTP control */
-	uint32_t SoftOTP2;	/* Software OTP control */
-	uint32_t SoftStraps;	/* Software strap */
-	uint32_t PinStraps;	/* Pin Straps */
-	uint32_t DiffOscCtrl;	/* Diff oscillator control */
-	uint32_t DiagsCtrl;	/* Diagnostic control */
-	uint32_t DiagsOutputCtrl;	/* Diagnostic output enable */
-	uint32_t DiagsReadBackCtrl;	/* Diagnostic read back control */
-
-	uint32_t LcdPifMode;	/* LCD/PIF Pin Sharing MUX Mode */
-
-	uint32_t GpioMux_0_7;	/* Pin Sharing MUX0 Control */
-	uint32_t GpioMux_8_15;	/* Pin Sharing MUX1 Control */
-	uint32_t GpioMux_16_23;	/* Pin Sharing MUX2 Control */
-	uint32_t GpioMux_24_31;	/* Pin Sharing MUX3 Control */
-	uint32_t GpioMux_32_39;	/* Pin Sharing MUX4 Control */
-	uint32_t GpioMux_40_47;	/* Pin Sharing MUX5 Control */
-	uint32_t GpioMux_48_55;	/* Pin Sharing MUX6 Control */
-	uint32_t GpioMux_56_63;	/* Pin Sharing MUX7 Control */
-
-	uint32_t GpioSR_0_7;	/* Slew rate for GPIO 0 - 7 */
-	uint32_t GpioSR_8_15;	/* Slew rate for GPIO 8 - 15 */
-	uint32_t GpioSR_16_23;	/* Slew rate for GPIO 16 - 23 */
-	uint32_t GpioSR_24_31;	/* Slew rate for GPIO 24 - 31 */
-	uint32_t GpioSR_32_39;	/* Slew rate for GPIO 32 - 39 */
-	uint32_t GpioSR_40_47;	/* Slew rate for GPIO 40 - 47 */
-	uint32_t GpioSR_48_55;	/* Slew rate for GPIO 48 - 55 */
-	uint32_t GpioSR_56_63;	/* Slew rate for GPIO 56 - 63 */
-	uint32_t MiscSR_0_7;	/* Slew rate for MISC 0 - 7 */
-	uint32_t MiscSR_8_15;	/* Slew rate for MISC 8 - 15 */
-
-	uint32_t GpioPull_0_15;	/* Pull up registers for GPIO 0 - 15 */
-	uint32_t GpioPull_16_31;	/* Pull up registers for GPIO 16 - 31 */
-	uint32_t GpioPull_32_47;	/* Pull up registers for GPIO 32 - 47 */
-	uint32_t GpioPull_48_63;	/* Pull up registers for GPIO 48 - 63 */
-	uint32_t MiscPull_0_15;	/* Pull up registers for MISC 0 - 15 */
-
-	uint32_t GpioInput_0_31;	/* Input type for GPIO 0 - 31 */
-	uint32_t GpioInput_32_63;	/* Input type for GPIO 32 - 63 */
-	uint32_t MiscInput_0_15;	/* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
-
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000	/* 
Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001	/* 
PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008	/* 
Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004	/* 
Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020	/* 
Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010	/* 
Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001	/* 
Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000	/* 
1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000	/* 
VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080	/* 
VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000	/* 
PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000	/* 
Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000	/* 
Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000	/* 
Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000	/* 
PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000	/* 
Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000	/* 
Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000	/* 
Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00	/* 
Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF	/* 
Clock post divider mask
-
-									   00000000 = divide-by-256
-									   00000001 = divide-by-1
-									   00000010 = divide-by-2
-									   00000011 = divide-by-3
-									   00000100 = divide-by-4
-									   00000101 = divide-by-5
-									   00000110 = divide-by-6
-									   .
-									   .
-									   11111011 = divide-by-251
-									   11111100 = divide-by-252
-									   11111101 = divide-by-253
-									   11111110 = divide-by-254
-									 */
-
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000	/* 
NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000	/* 
NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF	/* 
NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000	/* 
NON-PLL clock post-divide by 256 */
-
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000	/* 
Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000	/* 
Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000	/* 
MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000	/* 
MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000	/* 
MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000	/* 
MFB Sigma-Delta Modulator 1/8 Mode */
-
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / 
chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF	/* 
Fractional divider */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)	/* 
To attain spread with max frequency */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0	/* ndiv_frac 
= chipcHw_REG_PLL_DIVIDER_NDIV_f /
-								   chipcHw_REG_PLL_DIVIDER_FRAC
-								   = 0, when SS is disable
-								 */
-
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) 
((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001	/* 
Software Strap Override */
-
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000	/* 8 
bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002	/* 
16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004	/* 
Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006	/* 
16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008	/* 
UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E	/* 
Mask */
-
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000	/* 
Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020	/* 
Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030	/* 
Boot from NOR flash */
-
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000	/* 
NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040	/* 
NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080	/* 
NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0	/* 
NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0	/* 
Mask */
-
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400	/* 
NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800	/* 
Reboot to UART on error */
-
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000	/* 
Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100	/* 
Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200	/* 
Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300	/* 
Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300	/* 
Mask */
-
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000	/* 
I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000	/* 
SPI Slave  */
-
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS 
((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001	/* 
LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002	/* 
LCD pins are used to perform PIF functions  */
-
-#define chipcHw_GPIO_COUNT                              61	/* Number of 
GPIO pin accessible thorugh CHIPC */
-
-/* NOTE: Any changes to these constants will require a corresponding 
change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001	/* 
GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002	/* 
GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003	/* 
GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004	/* 
GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005	/* 
GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006	/* 
GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007	/* 
GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008	/* 
GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009	/* 
GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A	/* 
GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B	/* 
GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C	/* 
GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D	/* 
GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000	/* 
GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin) 
(&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 
0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F	/* 
Mask */
-
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000	/* 
High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008	/* 
Normal slew rate */
-							/* Pins beyond 42 are defined by skipping 8 bits within the 
register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008	/* 
Mask */
-
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001	/* 
Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002	/* 
Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004	/* 
Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005	/* 
Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006	/* 
Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007	/* 
Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-
-#define chipcHw_REG_PULL_NONE                           0x00000000	/* 
No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001	/* 
Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002	/* 
Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? 
(&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : 
(&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? 
((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000	/* 
Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001	/* 
High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : 
(&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001	/* 
Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002	/* 
Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004	/* 
Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008	/* 
Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010	/* 
Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020	/* 
Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040	/* 
Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080	/* 
Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100	/* 
Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200	/* 
Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400	/* 
Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800	/* 
Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000	/* 
Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000	/* 
Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000	/* 
Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000	/* 
Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000	/* 
Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000	/* 
Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000	/* 
Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000	/* 
Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000	/* 
Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000	/* 
Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000	/* 
Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000	/* 
Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000	/* 
Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000	/* 
Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000	/* 
Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000	/* 
Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000	/* 
Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000	/* 
Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000	/* 
Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000	/* 
Bus interface clock for Touch screen */
-
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 
0x0000000080000000ULL	/* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD 
0x0000000040000000ULL	/* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 
0x0000000020000000ULL	/* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM 
0x0000000010000000ULL	/* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD 
0x0000000008000000ULL	/* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED 
0x0000000004000000ULL	/* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU 
0x0000000002000000ULL	/* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG 
0x0000000001000000ULL	/* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA 
0x0000000000800000ULL	/* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD 
0x0000000000400000ULL	/* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF 
0x0000000000200000ULL	/* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS 
0x0000000000100000ULL	/* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH 
0x0000000000080000ULL	/* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1 
0x0000000000040000ULL	/* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0 
0x0000000000020000ULL	/* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL 
0x0000000000010000ULL	/* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1 
0x0000000000008000ULL	/* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0 
0x0000000000004000ULL	/* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS 
0x0000000000002000ULL	/* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH 
0x0000000000001000ULL	/* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1 
0x0000000000000800ULL	/* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0 
0x0000000000000400ULL	/* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1 
0x0000000000000200ULL	/* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0 
0x0000000000000100ULL	/* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI 
0x0000000000000080ULL	/* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG 
0x0000000000000040ULL	/* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR 
0x0000000000000020ULL	/* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM 
0x0000000000000010ULL	/* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD 
0x0000000000000008ULL	/* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM 
0x0000000000000004ULL	/* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM 
0x0000000000000002ULL	/* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 
0x0000000000000001ULL	/* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC 
0x0000100000000000ULL	/* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE 
0x0000080000000000ULL	/* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP 
0x0000040000000000ULL	/* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2 
0x0000020000000000ULL	/* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1 
0x0000010000000000ULL	/* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB 
0x0000008000000000ULL	/* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW 
0x0000004000000000ULL	/* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK 
0x0000002000000000ULL	/* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY 
0x0000001000000000ULL	/* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR 
0x0000000800000000ULL	/* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC 
0x0000000400000000ULL	/* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM 
0x0000000200000000ULL	/* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM 
0x0000200100000000ULL	/* Reset APM device */
-
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 
0x8000000000000000ULL	/* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 
0x4000000000000000ULL	/* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 
0x2000000000000000ULL	/* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 
0xF000000000000000ULL	/* Mask to handle unhold request */
-
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001	/* 
Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002	/* 
Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004	/* 
Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008	/* 
Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010	/* 
Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020	/* 
Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040	/* 
Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080	/* 
Enable APM clock */
-
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000	/* 
Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000	/* 
Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000	/* 
Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000	/* 
Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008	/* 
Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004	/* 
Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002	/* 
Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD	/* 
Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE	/* 
Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001	/* 
Power down USB */
-
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF 
0x0000020000000000ULL	/* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW 
0x0000010000000000ULL	/* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED 
0x0000000600000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1 
0x0000000100000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0 
0x0000000080000000ULL	/* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED 
0x0000000060000000ULL	/* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE 
0x000000001F000000ULL	/* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE 
0x0000000000200000ULL	/* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE 
0x0000000000100000ULL	/* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE 
0x0000000000080000ULL	/* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE 
0x0000000000040000ULL	/* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE 
0x0000000000020000ULL	/* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE 
0x0000000000010000ULL	/* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE 
0x0000000000008000ULL	/* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE 
0x0000000000004000ULL	/* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE 
0x0000000000003000ULL	/* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE 
0x0000000000000C00ULL	/* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE 
0x0000000000000200ULL	/* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE 
0x0000000000000180ULL	/* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE 
0x0000000000000060ULL	/* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE 
0x0000000000000018ULL	/* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE 
0x0000000000000006ULL	/* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE 
0x0000000000000001ULL	/* Disable VPM */
-
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001	/* 
Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002	/* 
ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004	/* 
General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008	/* 
General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010	/* 
General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020	/* 
General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040	/* 
General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080	/* 
Special sticky bit for security - set in BROM to avoid other modes being 
entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100	/* 
ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200	/* 
Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400	/* 
Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800	/* 
Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000	/* 
OTP reset */
-
-							/* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000	/* 
Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000	/* 
Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002	/* 
Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001	/* 
Enable access to DDR using system BUS */
-							/* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F	/* 
DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F	/* 
DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F	/* 
VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F	/* 
VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000	/* 
DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F	/* 
DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000	/* 
DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000	/* 
Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F	/* 
DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000	/* 
VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F	/* 
VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080	/* 
VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040	/* 
Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F	/* 
VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-							/* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-							/* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003	/* 
Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h 
b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index f1b68e2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/reg.h>
-#include <csp/stdint.h>
-
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t memcStatus;
-		uint32_t memcCmd;
-		uint32_t directCmd;
-		uint32_t memoryCfg;
-		uint32_t refreshPrd;
-		uint32_t casLatency;
-		uint32_t writeLatency;
-		uint32_t tMrd;
-		uint32_t tRas;
-		uint32_t tRc;
-		uint32_t tRcd;
-		uint32_t tRfc;
-		uint32_t tRp;
-		uint32_t tRrd;
-		uint32_t tWr;
-		uint32_t tWtr;
-		uint32_t tXp;
-		uint32_t tXsr;
-		uint32_t tEsr;
-		uint32_t memoryCfg2;
-		uint32_t memoryCfg3;
-		uint32_t tFaw;
-	} ddrcReg_CTLR_MEMC_REG_t;
-
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile 
ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_MEMC_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << 
ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)	/* 
@note Not supported in PL341 */
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << 
ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << 
ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << 
ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << 
ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << 
ddrcReg_CTLR_T_MRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << 
ddrcReg_CTLR_T_RAS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << 
ddrcReg_CTLR_T_RC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << 
ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << 
ddrcReg_CTLR_T_RCD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << 
ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << 
ddrcReg_CTLR_T_RFC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << 
ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << 
ddrcReg_CTLR_T_RP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << 
ddrcReg_CTLR_T_RRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << 
ddrcReg_CTLR_T_WR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << 
ddrcReg_CTLR_T_WTR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << 
ddrcReg_CTLR_T_XP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << 
ddrcReg_CTLR_T_XSR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << 
ddrcReg_CTLR_T_ESR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << 
ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << 
ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << 
ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX 
(ddrcReg_CTLR_QOS_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-	} ddrcReg_CTLR_QOS_REG_t;
-
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile 
ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << 
ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << 
ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX 
(ddrcReg_CTLR_CHIP_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-	} ddrcReg_CTLR_CHIP_REG_t;
-
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile 
ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-
-	typedef struct {
-		uint32_t input;
-		uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-		uint32_t feature;
-	} ddrcReg_CTLR_USER_REG_t;
-
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile 
ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << 
ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << 
ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t pmCtl;
-		 REG32_RSVD(0x0008, 0x0010);
-		uint32_t pllStatus;
-		uint32_t pllCfg;
-		uint32_t pllPreDiv;
-		uint32_t pllDiv;
-		uint32_t pllCtl1;
-		uint32_t pllCtl2;
-		uint32_t ssCtl;
-		uint32_t ssCfg;
-		uint32_t vdlStatic;
-		uint32_t vdlDynamic;
-		uint32_t padIdle;
-		uint32_t pvtComp;
-		uint32_t padDrive;
-		uint32_t clkRgltrCtl;
-	} ddrcReg_PHY_ADDR_CTL_REG_t;
-
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile 
ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-
-/* @todo These SS definitions are duplicates of ones below */
-
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10	/* Higher 
the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX 
(ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t vdlCalibrate;
-		uint32_t vdlStatus;
-		 REG32_RSVD(0x000c, 0x0010);
-		uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-		uint32_t readCtl;
-		uint32_t readStatus;
-		uint32_t readClear;
-		uint32_t padIdleCtl;
-		uint32_t padDriveCtl;
-		uint32_t padClkCtl;
-		uint32_t writeCtl;
-		uint32_t clkRegCtl;
-	} ddrcReg_PHY_BYTE_LANE_REG_t;
-
-/* There are 2 instances of the byte Lane registers, one for each byte 
lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-
-/* ----------------------------------------------------- */
-
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step 
value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 
in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some 
definitions for just */
-/* the step setting to simplify things. */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << 
ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << 
ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u 
<< 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 
<< 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 
<< 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 
<< 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 
<< 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 
<< 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 
<< 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 
<< 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 
<< 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 
<< 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 
<< 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 
<< 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 
<< 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 
<< 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 
<< 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 
<< 0)
-
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-
-	typedef struct {
-		uint32_t cfg;
-		uint32_t actMonCnt;
-		uint32_t ctl;
-		uint32_t lbistCtl;
-		uint32_t lbistSeed;
-		uint32_t lbistStatus;
-		uint32_t tieOff;
-		uint32_t actMonClear;
-		uint32_t status;
-		uint32_t user;
-	} ddrcReg_CTLR_PHY_GLUE_REG_t;
-
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP 
((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_PHY_GLUE_OFFSET))
-
-/* ----------------------------------------------------- */
-
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-
-/* Software control of PHY VDL updates from control register settings. 
Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a 
refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control 
must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-
-/* Use these to bypass a pipeline stage. By default the ADDR is off but 
the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE 
(1 << 12)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f 
<< ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#ifdef __cplusplus
-}				/* end extern "C" */
-#endif
-#endif				/* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index d67e2f8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-
-#include <csp/stdint.h>
-
-/* Data type for DMA Link List Item */
-typedef struct {
-	uint32_t sar;		/* Source Address Register.
-				   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-	uint32_t dar;		/* Destination Address Register.
-				   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-	uint32_t llpPhy;	/* LLP contains the physical address of the next 
descriptor for block chaining using linked lists.
-				   Address MUST be aligned to a 32-bit boundary.             */
-	dmacHw_REG64_t ctl;	/* Control Register. 64 bits */
-	uint32_t sstat;		/* Source Status Register */
-	uint32_t dstat;		/* Destination Status Register */
-	uint32_t devCtl;	/* Device specific control information */
-	uint32_t llp;		/* LLP contains the virtual address of the next 
descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-	int num;		/* Number of link items */
-	dmacHw_DESC_t *pHead;	/* Head of descriptor ring (for writing) */
-	dmacHw_DESC_t *pTail;	/* Tail of descriptor ring (for reading) */
-	dmacHw_DESC_t *pProg;	/* Descriptor to program the channel (for 
programming the channel register) */
-	dmacHw_DESC_t *pEnd;	/* End of current descriptor chain */
-	dmacHw_DESC_t *pFree;	/* Descriptor to free memory (freeing dynamic 
memory) */
-	uint32_t virt2PhyOffset;	/* Virtual to physical address offset for the 
descriptor ring */
-} dmacHw_DESC_RING_t;
-
-/*
- *  DMA channel control block
- */
-typedef struct {
-	uint32_t module;	/* DMA controller module (0-1) */
-	uint32_t channel;	/* DMA channel (0-7) */
-	volatile uint32_t varDataStarted;	/* Flag indicating variable data 
channel is enabled */
-	volatile uint32_t descUpdated;	/* Flag to indicate descriptor update 
is complete */
-	void *userData;		/* Channel specifc user data */
-} dmacHw_CBLK_t;
-
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t 
*)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) == 
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == 
dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e 
dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw	/*   [ IN ] Current 
transaction width */
-    ) {
-	if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-	} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-	}
-
-	/* Default return  */
-	return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e 
tw	/*   [ IN ]  Transaction width */
-    ) {
-	int width = 1;
-	switch (tw) {
-	case dmacHw_SRC_TRANSACTION_WIDTH_8:
-		width = 1;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_16:
-	case dmacHw_DST_TRANSACTION_WIDTH_16:
-		width = 2;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_32:
-	case dmacHw_DST_TRANSACTION_WIDTH_32:
-		width = 4;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_64:
-	case dmacHw_DST_TRANSACTION_WIDTH_64:
-		width = 8;
-		break;
-	default:
-		dmacHw_ASSERT(0);
-	}
-
-	/* Default transaction width */
-	return width;
-}
-
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index f1ecf96..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-
-/* Data type for 64 bit little endian register */
-typedef struct {
-	volatile uint32_t lo;	/* Lower 32 bit in little endian mode */
-	volatile uint32_t hi;	/* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-
-/* Data type representing DMA channel registers */
-typedef struct {
-	dmacHw_REG64_t ChannelSar;	/*  Source Address Register. 64 bits (upper 
32 bits are reserved)
-					   Address must be aligned to CTLx.SRC_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelDar;	/*  Destination Address Register.64 bits 
(upper 32 bits are reserved)
-					   Address must be aligned to CTLx.DST_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelLlp;	/*  Link List Pointer.64 bits (upper 32 
bits are reserved)
-					   LLP contains the pointer to the next LLI for block chaining 
using linked lists.
-					   If LLPis set to 0x0, then transfers using linked lists are not 
enabled.
-					   Address MUST be aligned to a 32-bit boundary.
-					 */
-	dmacHw_REG64_t ChannelCtl;	/* Control Register. 64 bits */
-	dmacHw_REG64_t ChannelSstat;	/* Source Status Register */
-	dmacHw_REG64_t ChannelDstat;	/* Destination Status Register */
-	dmacHw_REG64_t ChannelSstatAddr;	/* Source Status Address Register */
-	dmacHw_REG64_t ChannelDstatAddr;	/* Destination Status Address Register */
-	dmacHw_REG64_t ChannelConfig;	/* Channel Configuration Register */
-	dmacHw_REG64_t SrcGather;	/* Source gather register */
-	dmacHw_REG64_t DstScatter;	/* Destination scatter register */
-} dmacHw_CH_REG_t;
-
-/* Data type for RAW interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t RawTfr;	/* Raw Status for IntTfr Interrupt */
-	dmacHw_REG64_t RawBlock;	/* Raw Status for IntBlock Interrupt */
-	dmacHw_REG64_t RawSrcTran;	/* Raw Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t RawDstTran;	/* Raw Status for IntDstTran Interrupt */
-	dmacHw_REG64_t RawErr;	/* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-
-/* Data type for interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t StatusTfr;	/* Status for IntTfr Interrupt */
-	dmacHw_REG64_t StatusBlock;	/* Status for IntBlock Interrupt */
-	dmacHw_REG64_t StatusSrcTran;	/* Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t StatusDstTran;	/* Status for IntDstTran Interrupt */
-	dmacHw_REG64_t StatusErr;	/* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-
-/* Data type for interrupt mask registers*/
-typedef struct {
-	dmacHw_REG64_t MaskTfr;	/* Mask for IntTfr Interrupt */
-	dmacHw_REG64_t MaskBlock;	/* Mask for IntBlock Interrupt */
-	dmacHw_REG64_t MaskSrcTran;	/* Mask for IntSrcTran Interrupt */
-	dmacHw_REG64_t MaskDstTran;	/* Mask for IntDstTran Interrupt */
-	dmacHw_REG64_t MaskErr;	/* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-
-/* Data type for interrupt clear registers */
-typedef struct {
-	dmacHw_REG64_t ClearTfr;	/* Clear for IntTfr Interrupt */
-	dmacHw_REG64_t ClearBlock;	/* Clear for IntBlock Interrupt */
-	dmacHw_REG64_t ClearSrcTran;	/* Clear for IntSrcTran Interrupt */
-	dmacHw_REG64_t ClearDstTran;	/* Clear for IntDstTran Interrupt */
-	dmacHw_REG64_t ClearErr;	/* Clear for IntErr Interrupt */
-	dmacHw_REG64_t StatusInt;	/* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-
-/* Data type for software handshaking registers */
-typedef struct {
-	dmacHw_REG64_t ReqSrcReg;	/* Source Software Transaction Request 
Register */
-	dmacHw_REG64_t ReqDstReg;	/* Destination Software Transaction Request 
Register */
-	dmacHw_REG64_t SglReqSrcReg;	/* Single Source Transaction Request 
Register */
-	dmacHw_REG64_t SglReqDstReg;	/* Single Destination Transaction Request 
Register */
-	dmacHw_REG64_t LstSrcReg;	/* Last Source Transaction Request Register */
-	dmacHw_REG64_t LstDstReg;	/* Last Destination Transaction Request 
Register */
-} dmacHw_SW_HANDSHAKE_t;
-
-/* Data type for misc. registers */
-typedef struct {
-	dmacHw_REG64_t DmaCfgReg;	/* DMA Configuration Register */
-	dmacHw_REG64_t ChEnReg;	/* DMA Channel Enable Register */
-	dmacHw_REG64_t DmaIdReg;	/* DMA ID Register */
-	dmacHw_REG64_t DmaTestReg;	/* DMA Test Register */
-	dmacHw_REG64_t Reserved0;	/* Reserved */
-	dmacHw_REG64_t Reserved1;	/* Reserved */
-	dmacHw_REG64_t CompParm6;	/* Component Parameter 6 */
-	dmacHw_REG64_t CompParm5;	/* Component Parameter 5 */
-	dmacHw_REG64_t CompParm4;	/* Component Parameter 4 */
-	dmacHw_REG64_t CompParm3;	/* Component Parameter 3 */
-	dmacHw_REG64_t CompParm2;	/* Component Parameter 2 */
-	dmacHw_REG64_t CompParm1;	/* Component Parameter 1 */
-	dmacHw_REG64_t CompId;	/* Compoent ID */
-} dmacHw_MISC_t;
-
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0	/* 
DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1	/* 
DMAC 1 module's base address */
-
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) 
((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : 
dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char 
*)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : 
dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char 
*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char 
*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char 
*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char 
*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char 
*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-
-#define dmacHw_REG_CTL_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-
-#define dmacHw_REG_SSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-
-#define dmacHw_REG_CFG_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-
-#define dmacHw_REG_SGR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-
-#define dmacHw_REG_DSR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel) 
(dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-
-/* Bit mask for REG_DMACx_CTL_LO */
-
-#define dmacHw_REG_CTL_INT_EN                       0x00000001	/* 
Channel interrupt enable */
-
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E	/* 
Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000	/* 
Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002	/* 
Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004	/* 
Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006	/* 
Destination transaction width 64 bit */
-
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070	/* 
Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000	/* 
Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010	/* 
Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020	/* 
Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030	/* 
Source transaction width 64 bit */
-
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000	/* 
Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000	/* 
Source gather enable */
-
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180	/* 
Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000	/* 
Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080	/* 
Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100	/* 
Destination address no change */
-
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600	/* 
Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000	/* 
Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200	/* 
Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400	/* 
Source address no change */
-
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800	/* 
Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000	/* No 
Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800	/* 
Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000	/* 
Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800	/* 
Destination burst transaction length 16 */
-
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000	/* 
Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000	/* No 
Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000	/* 
Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000	/* 
Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000	/* 
Source burst transaction length 16 */
-
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000	/* 
Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000	/* 
Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000	/* 
Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000	/* 
Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000	/* 
Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000	/* 
Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000	/* 
Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000	/* 
Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000	/* 
Peripheral to Peripheral with Destination Peripheral as flow controller */
-
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000	/* 
Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000	/* 
Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000	/* 
Destination AHB master interface 2 */
-
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000	/* 
Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000	/* 
Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000	/* 
Source AHB master interface 2 */
-
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000	/* Block 
chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000	/* Block 
chaining enable for source side */
-
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF	/* Block 
transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000	/* Block 
trasnfer done */
-
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5	/* 
Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0	/* 
Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000	/* 
Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020	/* 
Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040	/* 
Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060	/* 
Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080	/* 
Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0	/* 
Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0	/* 
Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0	/* 
Channel priority 7 */
-
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100	/* 
Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200	/* 
Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400	/* 
Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800	/* 
Source channel SW handshaking */
-
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000	/* 
Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000	/* 
Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000	/* 
Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000	/* 
Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000	/* 
Channel lock enable */
-
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000	/* Bus 
locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000	/* Bus 
lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000	/* Bus 
lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000	/* Bus 
lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000	/* Bus 
lock enable */
-
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000	/* 
Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000	/* 
Source channel handshaking signal polarity low */
-
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000	/* 
Maximum AMBA burst length */
-
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000	/* 
Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000	/* 
Destination address auto reload */
-
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001	/* 
Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002	/* 
Initiate burst transaction when enough data in available in FIFO */
-
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C	/* AHB 
protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004	/* AHB 
protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008	/* AHB 
protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010	/* AHB 
protection 3 */
-
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020	/* 
Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040	/* 
Source status update enable */
-
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780	/* 
Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800	/* 
Destination peripheral hardware interface mask */
-
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700	/* 
Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800	/* 
Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f	/* 
Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000	/* Data 
transfer width */
-
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr) 
(dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr) 
(dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr) 
(dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-
-#define dmacHw_GET_SSTAT(module, channel) 
(dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel) 
(dmacHw_REG_DSTAT((module), (channel)))
-
-#define dmacHw_SET_SSTATAR(module, channel, addr) 
(dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr) 
(dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl) 
(dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)))
-
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl) 
(dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)))
-
-#define dmacHw_GET_BLOCK_SIZE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg) 
(dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 
20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect) 
(dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg) 
(dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & 
dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) 
& dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-
-#define dmacHw_DMA_START(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 0)
-
-#define dmacHw_TRAN_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-
-#define dmacHw_TRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-
-#define dmacHw_TRAN_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-
-#define dmacHw_GET_NUM_CHANNEL(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & 
dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h 
b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index cfa91be..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
-
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-
-/* Some items that can be defined externally, but will be set to 
default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS 
is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and 
Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR 
clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_HW_CFG_H */
-
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index 0aeb6a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define INTCHW_NUM_IRQ_PER_INTC   32	/* Maximum number of interrupt 
controllers */
-#define INTCHW_NUM_INTC           3
-
-/* Defines for interrupt controllers. This simplifies and cleans up the 
function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
-
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31	/* Peripheral interface 
interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30	/* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29	/* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28	/* Audio process module 
interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27	/* Ethernet switch 
interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26	/* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25	/* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24	/* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23	/* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22	/* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21	/* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20	/* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19	/* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18	/* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17	/* USB host2/device2 
interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16	/* Voice process module 
interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15	/* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14	/* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13	/* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12	/* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11	/* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10	/* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9	/* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8	/* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7	/* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6	/* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5	/* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4	/* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3	/* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2	/* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1	/* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0	/* DMA0 channel 0 interrupt */
-
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27	/* DDR and VPM PLL clock 
phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26	/* DDR and VPM HW phase 
align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26	/* DDR and PLL clock phase 
relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25	/* Real time clock tamper 
interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24	/* Hantro Video Decoder 
interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits 
in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23	/* Secure process module 
interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22	/* Real time clock 
one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21	/* Real time clock 
periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20	/* Random number generator 
interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19	/* Flash memory parition 
unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18	/* VRAM memory partition 
interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17	/* DDR2 memory partition 
interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16	/* Key pad controller 
interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15	/* Touch screen controller 
interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14	/* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13	/* Watchdog timer interrupt */
-
-#define INTCHW_INTC1_UART1_BITNUM         12	/* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11	/* ARM performance monitor 
interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10	/* ARM DDC receive 
interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9	/* ARM DDC transmit 
interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8	/* Flash controller 
interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7	/* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6	/* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5	/* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4	/* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3	/* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2	/* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1	/* GPIO bit 64//32 
combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0	/* GPIO bit 31//0 combined 
interrupt */
-
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15	/* Real time clock tamper 
interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14	/* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13	/* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12	/* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11	/* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10	/* Secure process module 
interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9	/* Real time clock 
one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8	/* Real time clock 
periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7	/* Random number generator 
interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6	/* Flash memory parition 
unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5	/* VRAM memory partition 
interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4	/* DDR2 memory partition 
interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3	/* Key pad controller 
interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2	/* Touch screen controller 
interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1	/* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0	/* Watchdog timer interrupt */
-
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00	/* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04	/* FIQ status register */
-#define INTCHW_RAWINTR        0x08	/* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c	/* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10	/* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14	/* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18	/* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c	/* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20	/* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24	/* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28	/* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100	/* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200	/* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00	/* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0	/* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0	/* PrimeCell ID Register 0-3 */
-
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENCLEAR) = mask;
-}
-
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENABLE) = mask;
-}
-
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index ad58cf8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*  Memory Map address definitions */
-
-#define MM_ADDR_DDR                0x00000000
-
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000	/* 16 MB - Reserved 
external memory for VPM use */
-
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000	/* 64 KB - extra cycle 
latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000	/* 64 KB  - security 
block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index de92ec6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_IO_H
-#define _MM_IO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(CONFIG_MMU)
-
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 
0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == 
MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-			(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | 
((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? 
MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-			((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
-#endif
-#endif
-
-#else
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-
-#endif
-
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-
-#define MM_IO_START MM_ADDR_IO_FLASHC	/* Physical beginning of IO 
mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC	/* Virtual beginning of IO mapped 
memory */
-
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-
-#define MM_IO_BASE_VPM_EXTMEM_RSVD 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-
-#include <mach/csp/mm_io.h>
-
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-
-/* Trustzone register set */
-typedef struct {
-	volatile uint32_t status;	/* read only - reflects status of writes of 
2 write registers */
-	volatile uint32_t setUnsecure;	/* write only. reads back as 0 */
-	volatile uint32_t setSecure;	/* write only. reads back as 0 */
-} secHw_TZREG_t;
-
-/* There are 2 register sets. The first is for the lower 16 bits, the 
2nd */
-/* is for the higher 16 bits. */
-
-typedef enum {
-	secHw_IDX_LS = 0,
-	secHw_IDX_MS = 1,
-	secHw_IDX_NUM
-} secHw_IDX_e;
-
-typedef struct {
-	volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-
-#include <mach/csp/secHw_inline.h>
-
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 9cd6a03..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-	}
-
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
-	}
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-
-/*
-This platform has four different timers running at different clock speed
-
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25	/* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150	/* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)	/* maximum number 
of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)	/* Number of timer module 
supported */
-
-typedef struct {
-	uint32_t LoadValue;	/* Load value for timer */
-	uint32_t CurrentValue;	/* Current value for timer */
-	uint32_t Control;	/* Control register */
-	uint32_t InterruptClear;	/* Interrupt clear register */
-	uint32_t RawInterruptStatus;	/* Raw interrupt status */
-	uint32_t InterruptStatus;	/* Masked interrupt status */
-	uint32_t BackgroundLoad;	/* Background load value */
-	uint32_t padding;	/* Padding register */
-} tmrHw_REG_t;
-
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | 
tmrHw_CONTROL_ONESHOT)
-
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h 
b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 7254378..0000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
-#include <mach/timer.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the 
filename */
-/* and line number of the reservation request will be recorded in the 
channel table */
-
-#define DMA_DEBUG_TRACK_RESERVATION   1
-
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8	/* per controller */
-
-typedef enum {
-	DMA_DEVICE_MEM_TO_MEM,	/* For memory to memory transfers */
-	DMA_DEVICE_I2S0_DEV_TO_MEM,
-	DMA_DEVICE_I2S0_MEM_TO_DEV,
-	DMA_DEVICE_I2S1_DEV_TO_MEM,
-	DMA_DEVICE_I2S1_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,	/* Additional mic input for 
beam-forming */
-	DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-	DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-	DMA_DEVICE_SPUM_DEV_TO_MEM,
-	DMA_DEVICE_SPUM_MEM_TO_DEV,
-	DMA_DEVICE_SPIH_DEV_TO_MEM,
-	DMA_DEVICE_SPIH_MEM_TO_DEV,
-	DMA_DEVICE_UART_A_DEV_TO_MEM,
-	DMA_DEVICE_UART_A_MEM_TO_DEV,
-	DMA_DEVICE_UART_B_DEV_TO_MEM,
-	DMA_DEVICE_UART_B_MEM_TO_DEV,
-	DMA_DEVICE_PIF_MEM_TO_DEV,
-	DMA_DEVICE_PIF_DEV_TO_MEM,
-	DMA_DEVICE_ESW_DEV_TO_MEM,
-	DMA_DEVICE_ESW_MEM_TO_DEV,
-	DMA_DEVICE_VPM_MEM_TO_MEM,
-	DMA_DEVICE_CLCD_MEM_TO_MEM,
-	DMA_DEVICE_NAND_MEM_TO_MEM,
-	DMA_DEVICE_MEM_TO_VRAM,
-	DMA_DEVICE_VRAM_TO_MEM,
-
-	/* Add new entries before this line. */
-
-	DMA_NUM_DEVICE_ENTRIES,
-	DMA_DEVICE_NONE = 0xff,	/* Special value to indicate that no device is 
currently assigned. */
-
-} DMA_Device_t;
-
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-
-typedef int DMA_Handle_t;
-
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-
-typedef struct {
-	void *virtAddr;		/* Virtual Address of the descriptor ring */
-	dma_addr_t physAddr;	/* Physical address of the descriptor ring */
-	int descriptorsAllocated;	/* Number of descriptors allocated in the 
descriptor ring */
-	size_t bytesAllocated;	/* Number of bytes allocated in the descriptor 
ring */
-
-} DMA_DescriptorRing_t;
-
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-
-/* The device handler is called whenever a DMA operation completes. The 
reaon */
-/* for it to be called will be a bitmask with one or more of the 
following bits */
-/* set. */
-
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE 
dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE 
dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR 
dmacHw_INTERRUPT_STATUS_ERROR
-
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-				     void *userData);
-
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004	/* If set, it 
means that the port used on DMAC0 is different from the port used on 
DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008	/* If set, 
allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800	/* If set, 
device is in use on a channel */
-
-/* Note: Some DMA devices can be used from multiple DMA Controllers. 
The bitmask is used to */
-/*       determine which DMA controllers a given device can be used 
from, and the interface */
-/*       array determeines the actual interface number to use for a 
given controller. */
-
-typedef struct {
-	uint32_t flags;		/* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-	uint8_t dedicatedController;	/* Controller number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	uint8_t dedicatedChannel;	/* Channel number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	const char *name;	/* Will show up in the /proc entry */
-
-	uint32_t dmacPort[DMA_NUM_CONTROLLERS];	/* Specifies the port number 
when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-
-	dmacHw_CONFIG_t config;	/* Configuration to use when DMA'ing using 
this device */
-
-	void *userData;		/* Passed to the devHandler */
-	DMA_DeviceHandler_t devHandler;	/* Called when DMA operations finish. */
-
-	timer_tick_count_t transferStartTime;	/* Time the current transfer was 
started */
-
-	/* The following statistical information will be collected and 
presented in a proc entry. */
-	/* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 
years to overflow */
-	/*       a 64 bit counter. */
-
-	uint64_t numTransfers;	/* Number of DMA transfers performed */
-	uint64_t transferTicks;	/* Total time spent doing DMA transfers 
(measured in timer_tick_count_t's) */
-	uint64_t transferBytes;	/* Total bytes transferred */
-	uint32_t timesBlocked;	/* Number of times a channel was unavailable */
-	uint32_t numBytes;	/* Last transfer size */
-
-	/* It's not possible to free memory which is allocated for the 
descriptors from within */
-	/* the ISR. So make the presumption that a given device will tend to 
use the */
-	/* same sized buffers over and over again, and we keep them around. */
-
-	DMA_DescriptorRing_t ring;	/* Ring of descriptors allocated for this 
device */
-
-	/* We stash away some of the information from the previous transfer. 
If back-to-back */
-	/* transfers are performed from the same buffer, then we don't have to 
keep re-initializing */
-	/* the descriptor buffers. */
-
-	uint32_t prevNumBytes;
-	dma_addr_t prevSrcData;
-	dma_addr_t prevDstData;
-
-} DMA_DeviceAttribute_t;
-
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out 
into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA 
channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-
-typedef struct {
-	uint32_t flags;		/* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-	DMA_Device_t devType;	/* Device this channel is currently reserved for */
-	DMA_Device_t lastDevType;	/* Device type that used this previously */
-	char name[20];		/* Name passed onto request_irq */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	const char *fileName;	/* Place where channel reservation took place */
-	int lineNum;		/* Place where channel reservation took place */
-#endif
-	dmacHw_HANDLE_t dmacHwHandle;	/* low level channel handle. */
-
-} DMA_Channel_t;
-
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA 
controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-
-typedef struct {
-	DMA_Channel_t channel[DMA_NUM_CHANNELS];
-
-} DMA_Controller_t;
-
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-
-typedef struct {
-	struct semaphore lock;	/* acquired when manipulating table entries */
-	wait_queue_head_t freeChannelQ;
-
-	DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-
-} DMA_Global_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-#if defined(__KERNEL__)
-
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-
-int dma_init(void);
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char 
*fileName,
-				     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, 
__FILE__, __LINE__)
-#else
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-DMA_Handle_t dma_request_channel(DMA_Device_t dev	/* Device to use with 
the allocated channel. */
-    );
-#endif
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t channel	/* DMA handle. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t dev	/* Device to check. */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    );
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    );
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    );
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_to_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					 dma_addr_t srcData,	/* Place to get data to write to device 
(physical address) */
-					 dma_addr_t dstData,	/* Pointer to device data address (physical 
address) */
-					 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_from_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					   dma_addr_t srcData,	/* Pointer to the device data address 
(physical address) */
-					   dma_addr_t dstData,	/* Place to store data retrieved from the 
device (physical address) */
-					   size_t numBytes	/* Number of bytes to retrieve from the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,	/* DMA 
Handle */
-					  dma_addr_t srcData,	/* Place to transfer data from (physical 
address) */
-					  dma_addr_t dstData,	/* Place to transfer data to (physical 
address) */
-					  size_t numBytes	/* Number of bytes to transfer */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    );
-
-#endif
-
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S 
b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0..0000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =(MM_IO_BASE_INTC0)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC0_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_INTC1)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC1_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_SINTC)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #0xffffffff             @ code meaning no interrupt bits set
-		cmp	\irqstat, #0
-		beq	1002f
-
-		mov	\irqnr, #IRQ_SINTC_START        @ something is set, so fixup 
return value
-
-1001:
-		movs	\tmp, \irqstat, lsl #16
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #16
-
-		movs	\tmp, \irqstat, lsl #8
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #8
-
-		movs	\tmp, \irqstat, lsl #4
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #4
-
-		movs	\tmp, \irqstat, lsl #2
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #2
-
-		movs	\tmp, \irqstat, lsl #1
-		addeq	\irqnr, \irqnr, #1
-		orrs	\base, \base, #1
-
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-		.endm
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h 
b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index 6ae20a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <cfg_global.h>
-#include <mach/csp/mm_io.h>
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-
-#define RAM_SIZE 
(CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-
-/* Macros to make managing spinlocks a bit more controlled in terms of 
naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name) 
DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t 
bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val) 
spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val) 
spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h 
b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b82..0000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0	/* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1	/* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2	/* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3	/* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4	/* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5	/* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6	/* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7	/* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8	/* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9	/* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10	/* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11	/* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12	/* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13	/* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14	/* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15	/* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16	/* Voice process module interrupt */
-#define IRQ_USBHD2         17	/* USB host2/device2 interrupt */
-#define IRQ_USBH1          18	/* USB1 host interrupt */
-#define IRQ_USBD           19	/* USB device interrupt */
-#define IRQ_SDIOH0         20	/* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21	/* SDIO1 host interrupt */
-#define IRQ_TIMER0         22	/* Timer0 interrupt */
-#define IRQ_TIMER1         23	/* Timer1 interrupt */
-#define IRQ_TIMER2         24	/* Timer2 interrupt */
-#define IRQ_TIMER3         25	/* Timer3 interrupt */
-#define IRQ_SPIH           26	/* SPI host interrupt */
-#define IRQ_ESW            27	/* Ethernet switch interrupt */
-#define IRQ_APM            28	/* Audio process module interrupt */
-#define IRQ_GE             29	/* Graphic engine interrupt */
-#define IRQ_CLCD           30	/* LCD Controller interrupt */
-#define IRQ_PIF            31	/* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32	/*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33	/*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34	/*  2 I2S0 interrupt */
-#define IRQ_I2S1           35	/*  3 I2S1 interrupt */
-#define IRQ_I2CH           36	/*  4 I2C host interrupt */
-#define IRQ_I2CS           37	/*  5 I2C slave interrupt */
-#define IRQ_SPIS           38	/*  6 SPI slave interrupt */
-#define IRQ_GPHY           39	/*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40	/*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41	/*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42	/* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43	/* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44	/* 12 UARTB */
-#define IRQ_WATCHDOG       45	/* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46	/* 14 UARTA */
-#define IRQ_TSC            47	/* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48	/* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49	/* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50	/* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51	/* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52	/* 20 Random number generator interrupt */
-#define IRQ_RTC0           53	/* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54	/* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55	/* 23 Secure process module interrupt */
-#define IRQ_VDEC           56	/* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57	/* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58	/* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59	/*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60	/*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61	/*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62	/*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63	/*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64	/*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65	/*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66	/*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67	/*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68	/*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69	/* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70	/* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71	/* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72	/* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73	/* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74	/* 15 Real time clock tamper interrupt */
-
-#define IRQ_SINTC_END      74
-
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs 
could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio 
based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-
-#define IRQ_GPIO_0                  100
-
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I 
hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-
-#define IRQ_UNKNOWN                 -1
-
-/* Tune these bits to preclude noisy or unsupported interrupt sources 
as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h 
b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16..0000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)	/* Bus turnaround cycle (n) 
0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)	/* Write pulse width cycle (n+1) 
0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)	/* Write recovery cycle (n+1) 
0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)	/* Write address setup cycle (n+1) 
0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)	/* Output enable delay cycle (n) 
0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)	/* Read access cycle (n+2) 
0-31 (50 ns) */
-
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-	| HW_CFG_NAND_tWP  \
-	| HW_CFG_NAND_tWR  \
-	| HW_CFG_NAND_tAS  \
-	| HW_CFG_NAND_tOE  \
-	| HW_CFG_NAND_tRC)
-
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)	/* Page read access cycle / 
Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)	/* Bus turnaround cycle (n) 
                             (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)	/* Write pulse width cycle (n+1) 
                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)	/* Write recovery cycle (n+1) 
                            (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)	/* Write address setup cycle 
(n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)	/* Output enable delay cycle (n) 
                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)	/* Read access cycle / Burst 
read latency (n+2 / n+1)       (100ns)    */
-
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-	| HW_CFG_NOR_TBTA      \
-	| HW_CFG_NOR_TWP       \
-	| HW_CFG_NOR_TWR       \
-	| HW_CFG_NOR_TAS       \
-	| HW_CFG_NOR_TOE       \
-	| HW_CFG_NOR_TRC_TLC)
-
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules 
[8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000	/* Total memory, not 
per device size */
-
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h 
b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index 387376f..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/reg_umi.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-#define HW_NAND_BASE       MM_IO_BASE_NAND	/* NAND Flash */
-
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h 
b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 0992842..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst 
flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 
+ (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h 
b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb..0000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-
-#if defined(__KERNEL__)
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Constants and Types 
---------------------------------------------- */
-
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h 
b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033e..0000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE		100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h 
b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b..0000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA 
+ 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	/* Send out UARTA */
-	while (BCMRING_UART_0_FR & (1 << 5))
-		;
-
-	BCMRING_UART_0_DR = c;
-}
-
-
-static inline void flush(void)
-{
-	/* Wait for the tx fifo to be empty */
-	while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-		;
-
-	/* Wait for the final character to be sent on the txd line */
-	while (BCMRING_UART_0_FR & (1 << 3))
-		;
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa68..0000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-
-static struct irq_chip bcmring_irq0_chip = {
-	.name = "ARM-INTC0",
-	.irq_ack = bcmring_mask_irq0,
-	.irq_mask = bcmring_mask_irq0,	/* mask a specific interrupt, blocking 
its delivery. */
-	.irq_unmask = bcmring_unmask_irq0,	/* unmaks an interrupt */
-};
-
-static struct irq_chip bcmring_irq1_chip = {
-	.name = "ARM-INTC1",
-	.irq_ack = bcmring_mask_irq1,
-	.irq_mask = bcmring_mask_irq1,
-	.irq_unmask = bcmring_unmask_irq1,
-};
-
-static struct irq_chip bcmring_irq2_chip = {
-	.name = "ARM-SINTC",
-	.irq_ack = bcmring_mask_irq2,
-	.irq_mask = bcmring_mask_irq2,
-	.irq_unmask = bcmring_unmask_irq2,
-};
-
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-		     unsigned int irq_start, unsigned int vic_sources)
-{
-	unsigned int i;
-	for (i = 0; i < 32; i++) {
-		unsigned int irq = irq_start + i;
-		irq_set_chip(irq, chip);
-		irq_set_chip_data(irq, base);
-
-		if (vic_sources & (1 << i)) {
-			irq_set_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-	writel(0, base + INTCHW_INTSELECT);
-	writel(0, base + INTCHW_INTENABLE);
-	writel(~0, base + INTCHW_INTENCLEAR);
-	writel(0, base + INTCHW_IRQSTATUS);
-	writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-
-void __init bcmring_init_irq(void)
-{
-	vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-		 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-		 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-		 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-
-	/* special cases */
-	if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-	}
-	if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-	}
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 1adec78..0000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-#define IO_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_DEVICE }
-
-#define MEM_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_MEMORY }
-
-static struct map_desc bcmring_io_desc[] __initdata = {
-	IO_DESC(MM_IO_BASE_NAND, SZ_64K),	/* phys:0x28000000-0x28000FFF 
virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_UMI, SZ_64K),	/* phys:0x2C000000-0x2C000FFF 
virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
-	IO_DESC(MM_IO_BASE_BROM, SZ_64K),	/* phys:0x30000000-0x3000FFFF 
virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-	MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),	/* phys:0x31000000-0x31FFFFFF 
virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA0, SZ_1M),	/* phys:0x32000000-0x32FFFFFF 
virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA1, SZ_1M),	/* phys:0x33000000-0x33FFFFFF 
virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_ESW, SZ_1M),	/* phys:0x34000000-0x34FFFFFF 
virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_CLCD, SZ_1M),	/* phys:0x35000000-0x35FFFFFF 
virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_APM, SZ_1M),	/* phys:0x36000000-0x36FFFFFF 
virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_SPUM, SZ_1M),	/* phys:0x37000000-0x37FFFFFF 
virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),	/* phys:0x38000000-0x38FFFFFF 
virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),	/* phys:0x3A000000-0x3AFFFFFF 
virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
-	IO_DESC(MM_IO_BASE_VRAM, SZ_64K),	/* phys:0x40000000-0x4000FFFF 
virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),	/* phys:0x80000000-0x80FFFFFF 
virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-		SZ_16M),	/* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF 
size:0x01000000 */
-};
-
-void __init bcmring_map_io(void)
-{
-
-	iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-	/* Maximum DMA memory allowed is 14M */
-	init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index af9c3d7..0000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <csp/tmrHw.h>
-
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM 
timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread 
spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-
-#define PROF_TIMER 1
-
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-	return tmrHw_getCountRate(PROF_TIMER);
-}
-
-timer_tick_count_t timer_get_tick_count(void)
-{
-	return tmrHw_GetCurrentCount(PROF_TIMER);	/* change downcounter to 
upcounter */
-}
-
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-	static int tickRateMsec;
-
-	if (tickRateMsec == 0) {
-		tickRateMsec = timer_get_tick_rate() / 1000;
-	}
-
-	return ticks / tickRateMsec;
-}
-
-timer_msec_t timer_get_msec(void)
-{
-	return timer_ticks_to_msec(timer_get_tick_count());
-}
-
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
-- 
1.7.1






Received: from SJEXCHHUB01.corp.ad.broadcom.com (10.16.192.224) by
  sjexchcas02.corp.ad.broadcom.com (10.16.192.37) with Microsoft SMTP Server
  (TLS) id 14.1.355.2; Wed, 12 Sep 2012 22:55:13 -0700
Received: from IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) by
  SJEXCHHUB01.corp.ad.broadcom.com (10.16.192.224) with Microsoft SMTP 
Server
  (TLS) id 8.2.247.2; Wed, 12 Sep 2012 22:55:09 -0700
Received: from mail-irva-13.broadcom.com (10.11.16.103) by
  IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP 
Server
  id 8.2.247.2; Wed, 12 Sep 2012 22:55:08 -0700
Received: from godzilla.ric.broadcom.com (godzilla.ric.broadcom.com
  [10.136.18.140])	by mail-irva-13.broadcom.com (Postfix) with ESMTP id
  118729F9F7	for <csd at broadcom.com>; Wed, 12 Sep 2012 22:55:07 -0700 (PDT)
From: Christian Daudt <csd at broadcom.com>
To: csd <csd at broadcom.com>
CC: Christian Daudt <csd at broadcom.com>
Subject: [PATCH 2/2] ARM: Remove mach-bcmring
Date: Wed, 12 Sep 2012 22:48:55 -0700
Message-ID: <1347515335-22474-1-git-send-email-csd at broadcom.com>
X-Mailer: git-send-email 1.7.1
Content-Type: text/plain
Return-Path: csd at broadcom.com
X-MS-Exchange-Organization-AVStamp-Mailbox: SYMANTEC;455868672;0;info
X-MS-Exchange-Organization-AuthSource: IRVEXCHHUB01.corp.ad.broadcom.com
X-MS-Exchange-Organization-AuthAs: Anonymous
MIME-Version: 1.0

Remove mach-bcmring as this is no longer maintained or used.

Signed-off-by: Christian Daudt <csd at broadcom.com>
---
  MAINTAINERS                                        |    7 -
  arch/arm/Kconfig                                   |   14 -
  arch/arm/Makefile                                  |    1 -
  arch/arm/configs/bcmring_defconfig                 |   79 -
  arch/arm/mach-bcmring/Kconfig                      |   19 -
  arch/arm/mach-bcmring/Makefile                     |    8 -
  arch/arm/mach-bcmring/Makefile.boot                |    6 -
  arch/arm/mach-bcmring/arch.c                       |  199 ---
  arch/arm/mach-bcmring/clock.c                      |  223 ---
  arch/arm/mach-bcmring/clock.h                      |   33 -
  arch/arm/mach-bcmring/core.c                       |  228 ---
  arch/arm/mach-bcmring/core.h                       |   31 -
  arch/arm/mach-bcmring/csp/Makefile                 |    3 -
  arch/arm/mach-bcmring/csp/chipc/Makefile           |    1 -
  arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |  776 ---------
  arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |  293 ----
  arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |  124 --
  arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |   64 -
  arch/arm/mach-bcmring/csp/dmac/Makefile            |    1 -
  arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |  917 -----------
  arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      | 1017 ------------
  arch/arm/mach-bcmring/csp/tmr/Makefile             |    1 -
  arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |  576 -------
  arch/arm/mach-bcmring/dma.c                        | 1518 
------------------
  arch/arm/mach-bcmring/dma_device.c                 |  593 -------
  arch/arm/mach-bcmring/include/cfg_global.h         |   13 -
  arch/arm/mach-bcmring/include/cfg_global_defines.h |   40 -
  arch/arm/mach-bcmring/include/csp/cache.h          |   35 -
  arch/arm/mach-bcmring/include/csp/delay.h          |   36 -
  arch/arm/mach-bcmring/include/csp/dmacHw.h         |  596 -------
  arch/arm/mach-bcmring/include/csp/errno.h          |   32 -
  arch/arm/mach-bcmring/include/csp/intcHw.h         |   40 -
  arch/arm/mach-bcmring/include/csp/module.h         |   32 -
  arch/arm/mach-bcmring/include/csp/reg.h            |  114 --
  arch/arm/mach-bcmring/include/csp/secHw.h          |   65 -
  arch/arm/mach-bcmring/include/csp/stdint.h         |   30 -
  arch/arm/mach-bcmring/include/csp/string.h         |   34 -
  arch/arm/mach-bcmring/include/csp/tmrHw.h          |  263 ---
  arch/arm/mach-bcmring/include/mach/csp/cap.h       |   63 -
  .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
  .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
  .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 
--------------------
  .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
  arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
  .../mach-bcmring/include/mach/csp/dmacHw_priv.h    |  145 --
  .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
  arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
  .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
  arch/arm/mach-bcmring/include/mach/csp/mm_addr.h   |  101 --
  arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
  arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
  .../mach-bcmring/include/mach/csp/secHw_inline.h   |   79 -
  arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
  arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
  arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
  arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
  arch/arm/mach-bcmring/include/mach/irqs.h          |  132 --
  .../mach-bcmring/include/mach/memory_settings.h    |   67 -
  arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
  arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
  arch/arm/mach-bcmring/include/mach/timer.h         |   77 -
  arch/arm/mach-bcmring/include/mach/timex.h         |   25 -
  arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
  arch/arm/mach-bcmring/irq.c                        |  126 --
  arch/arm/mach-bcmring/mm.c                         |   60 -
  arch/arm/mach-bcmring/timer.c                      |   61 -
  66 files changed, 0 insertions(+), 15768 deletions(-)
  delete mode 100644 arch/arm/configs/bcmring_defconfig
  delete mode 100644 arch/arm/mach-bcmring/Kconfig
  delete mode 100644 arch/arm/mach-bcmring/Makefile
  delete mode 100644 arch/arm/mach-bcmring/Makefile.boot
  delete mode 100644 arch/arm/mach-bcmring/arch.c
  delete mode 100644 arch/arm/mach-bcmring/clock.c
  delete mode 100644 arch/arm/mach-bcmring/clock.h
  delete mode 100644 arch/arm/mach-bcmring/core.c
  delete mode 100644 arch/arm/mach-bcmring/core.h
  delete mode 100644 arch/arm/mach-bcmring/csp/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
  delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw.c
  delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/Makefile
  delete mode 100644 arch/arm/mach-bcmring/csp/tmr/tmrHw.c
  delete mode 100644 arch/arm/mach-bcmring/dma.c
  delete mode 100644 arch/arm/mach-bcmring/dma_device.c
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h
  delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h
  delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
  delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/irqs.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/memory_settings.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timer.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/timex.h
  delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
  delete mode 100644 arch/arm/mach-bcmring/irq.c
  delete mode 100644 arch/arm/mach-bcmring/mm.c
  delete mode 100644 arch/arm/mach-bcmring/timer.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 36da5f9..a4b166c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,13 +658,6 @@ W:	http://www.linux4sam.org
  S:	Supported
  F:	arch/arm/mach-at91/
  -ARM/BCMRING ARM ARCHITECTURE
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
-S:	Maintained
-F:	arch/arm/mach-bcmring
-
  ARM/CALXEDA HIGHBANK ARCHITECTURE
  M:	Rob Herring <rob.herring at calxeda.com>
  L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5..e99177a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,18 +350,6 @@ config ARCH_AT91
  	  This enables support for systems based on Atmel
  	  AT91RM9200 and AT91SAM9* processors.
  -config ARCH_BCMRING
-	bool "Broadcom BCMRING"
-	depends on MMU
-	select CPU_V6
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	help
-	  Support for Broadcom's BCMRing platform.
-
  config ARCH_HIGHBANK
  	bool "Calxeda Highbank-based"
  	select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -1031,8 +1019,6 @@ source "arch/arm/mach-mvebu/Kconfig"
   source "arch/arm/mach-at91/Kconfig"
  -source "arch/arm/mach-bcmring/Kconfig"
-
  source "arch/arm/mach-clps711x/Kconfig"
   source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..8383e2e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
  # Machine directory name.  This list is sorted alphanumerically
  # by CONFIG_* macro name.
  machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
  machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
  machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
  machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
diff --git a/arch/arm/configs/bcmring_defconfig 
b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe..0000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16..0000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-	prompt "Processor selection in BCMRING family of devices"
-	depends on ARCH_BCMRING
-	default ARCH_BCM11107
-
-config ARCH_FPGA11107
-	bool "FPGA11107"
-
-config ARCH_BCM11107
-	bool "BCM11107"
-endchoice
-
-menu "BCMRING Options"
-	depends on ARCH_BCMRING
-
-config BCM_ZRELADDR
-	hex "Compressed ZREL ADDR"
-
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fce..0000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot 
b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467..0000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
-
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index 45c97b1..0000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/pmu.h>
-
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <cfg_global.h>
-
-#include "core.h"
-
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-
-/* sysctl */
-static int bcmring_arch_warm_reboot;	/* do a warm reboot on hard reset */
-
-static void bcmring_restart(char mode, const char *cmd)
-{
-	printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-
-	if (mode == 'h') {
-		/* Reboot configured in proc entry */
-		if (bcmring_arch_warm_reboot) {
-			printk("warm reset\n");
-			/* Issue Warm reset (do not reset ethernet switch, keep alive) */
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-		} else {
-			/* Force reset of everything */
-			printk("force reset\n");
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-	} else {
-		/* Force reset of everything */
-		printk("force reset\n");
-		chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-	}
-}
-
-static struct ctl_table_header *bcmring_sysctl_header;
-
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-	{
-	 .procname = "warm",
-	 .data = &bcmring_arch_warm_reboot,
-	 .maxlen = sizeof(int),
-	 .mode = 0644,
-	 .proc_handler = proc_dointvec},
-	{}
-};
-
-static struct ctl_table bcmring_sysctl_reboot[] = {
-	{
-	 .procname = "reboot",
-	 .mode = 0555,
-	 .child = bcmring_sysctl_warm_reboot},
-	{}
-};
-
-static struct resource nand_resource[] = {
-	[0] = {
-		.start = MM_ADDR_IO_NAND,
-		.end = MM_ADDR_IO_NAND + 0x1000 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device nand_device = {
-	.name = "bcm-nand",
-	.id = -1,
-	.resource = nand_resource,
-	.num_resources	= ARRAY_SIZE(nand_resource),
-};
-
-static struct resource pmu_resource = {
-	.start	= IRQ_PMUIRQ,
-	.end	= IRQ_PMUIRQ,
-	.flags	= IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
-	.resource	= &pmu_resource,
-	.num_resources	= 1,
-};
-
-
-static struct platform_device *devices[] __initdata = {
-	&nand_device,
-	&pmu_device,
-};
-
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-
-	bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-
-	/* Enable spread spectrum */
-	chipcHw_enableSpreadSpectrum();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	bcmring_amba_init();
-
-	dma_init();
-}
-
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-	struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-	printk(KERN_NOTICE "bcmring_fixup\n");
-	t->hdr.tag = ATAG_CORE;
-	t->hdr.size = tag_size(tag_core);
-	t->u.core.flags = 0;
-	t->u.core.pagesize = PAGE_SIZE;
-	t->u.core.rootdev = 31 << 8 | 0;
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_MEM;
-	t->hdr.size = tag_size(tag_mem32);
-	t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-	t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_NONE;
-	t->hdr.size = 0;
-#endif
-}
-
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-
-MACHINE_START(BCMRING, "BCMRING")
-	/* Maintainer: Broadcom Corporation */
-	.fixup = bcmring_fixup,
-	.map_io = bcmring_map_io,
-	.init_early = bcmring_init_early,
-	.init_irq = bcmring_init_irq,
-	.timer = &bcmring_timer,
-	.init_machine = bcmring_init_machine,
-	.restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a4..0000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include "clock.h"
-
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	/* enable parent clock first */
-	if (clk->parent)
-		__clk_enable(clk->parent);
-
-	if (clk->use_cnt++ == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Enable(clk->rate_hz, 0);
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Enable(clk->rate_hz);
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockEnable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockEnable(clk->csp_id);
-		}
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	BUG_ON(clk->use_cnt == 0);
-
-	if (--clk->use_cnt == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Disable();
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Disable();
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockDisable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockDisable(clk->csp_id);
-		}
-	}
-
-	if (clk->parent)
-		__clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (!clk)
-		return 0;
-
-	return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-	clk->rate_hz = rate_hz;
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-	if (!clk)
-		return NULL;
-
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	unsigned long flags;
-	struct clk *old_parent;
-
-	if (!clk || !parent)
-		return -EINVAL;
-
-	if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-		return -EINVAL;
-
-	/* if more than one user, parent is not allowed */
-	if (clk->use_cnt > 1)
-		return -EBUSY;
-
-	if (clk->parent == parent)
-		return 0;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	old_parent = clk->parent;
-	clk->parent = parent;
-	if (clk_is_using_xtal(parent))
-		clk->mode |= CLK_MODE_XTAL;
-	else
-		clk->mode &= (~CLK_MODE_XTAL);
-
-	/* if clock is active */
-	if (clk->use_cnt != 0) {
-		clk->use_cnt--;
-		/* enable clock with the new parent */
-		__clk_enable(clk);
-		/* disable the old parent */
-		__clk_disable(old_parent);
-	}
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b981..0000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-
-#define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a 
parent */
-#define CLK_TYPE_PLL1            2	/* PPL1 */
-#define CLK_TYPE_PLL2            4	/* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8	/* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16	/* parent can be changed */
-
-#define CLK_MODE_XTAL            1	/* clock source is from crystal */
-
-struct clk {
-	const char *name;	/* clock name */
-	unsigned int type;	/* clock type */
-	unsigned int mode;	/* current mode */
-	volatile int use_bypass;	/* indicate if it's in bypass mode */
-	chipcHw_CLOCK_e csp_id;	/* clock ID for CSP CHIPC */
-	unsigned long rate_hz;	/* clock rate in Hz */
-	unsigned int use_cnt;	/* usage count */
-	struct clk *parent;	/* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index adbfb19..0000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <cfg_global.h>
-
-#include "clock.h"
-
-#include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, 
{IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, 
{IRQ_UARTB}, NULL);
-
-static struct clk pll1_clk = {
-	.name = "PLL1",
-	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-	.rate_hz = 2000000000,
-	.use_cnt = 7,
-};
-
-static struct clk uart_clk = {
-	.name = "UART",
-	.type = CLK_TYPE_PROGRAMMABLE,
-	.csp_id = chipcHw_CLOCK_UART,
-	.rate_hz = HW_CFG_UART_CLK_HZ,
-	.parent = &pll1_clk,
-};
-
-static struct clk dummy_apb_pclk = {
-	.name = "BUSCLK",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-};
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as 
well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-static struct clk sp804_timer012_clk = {
-	.name = "sp804-timer-0,1,2",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-
-static struct clk sp804_timer3_clk = {
-	.name = "sp804-timer-3",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-
-static struct clk_lookup lookups[] = {
-	{			/* Bus clock */
-		.con_id = "apb_pclk",
-		.clk = &dummy_apb_pclk,
-	}, {			/* UART0 */
-		.dev_id = "uarta",
-		.clk = &uart_clk,
-	}, {			/* UART1 */
-		.dev_id = "uartb",
-		.clk = &uart_clk,
-	}, {			/* SP804 timer 0 */
-		.dev_id = "sp804",
-		.con_id = "timer0",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 1 */
-		.dev_id = "sp804",
-		.con_id = "timer1",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 3 */
-		.dev_id = "sp804",
-		.con_id = "timer3",
-		.clk = &sp804_timer3_clk,
-	}
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	&uartA_device,
-	&uartB_device,
-};
-
-void __init bcmring_amba_init(void)
-{
-	int i;
-	u32 bus_clock;
-
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-			  secHw_BLK_MASK_KEY_SCAN |
-			  secHw_BLK_MASK_TOUCH_SCREEN |
-			  secHw_BLK_MASK_UART0 |
-			  secHw_BLK_MASK_UART1 |
-			  secHw_BLK_MASK_WATCHDOG |
-			  secHw_BLK_MASK_SPUM |
-			  secHw_BLK_MASK_DDR2 |
-			  secHw_BLK_MASK_SPU |
-			  secHw_BLK_MASK_PKA |
-			  secHw_BLK_MASK_RNG |
-			  secHw_BLK_MASK_RTC |
-			  secHw_BLK_MASK_OTP |
-			  secHw_BLK_MASK_BOOT |
-			  secHw_BLK_MASK_MPU |
-			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-
-	/* Only the devices attached to the AMBA bus are enabled just before 
the bus is */
-	/* scanned and the drivers are loaded. The clocks need to be on for 
the AMBA bus */
-	/* driver to access these blocks. The bus is probed, and the drivers 
are loaded. */
-	/* FIXME Need to remove enable of PIF once CLCD clock enable used 
properly in FPGA. */
-	bus_clock = chipcHw_REG_BUS_CLOCK_GE
-	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-
-	chipcHw_busInterfaceClockEnable(bus_clock);
-
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-}
-
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE		((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-
-static int __init bcmring_clocksource_init(void)
-{
-	/* setup timer1 as free-running clocksource */
-	sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-
-	/* setup timer3 as free-running clocksource */
-	sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-
-	return 0;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-	printk(KERN_INFO "bcmring_init_timer\n");
-	/*
-	 * Initialise to a known state (all timers off)
-	 */
-	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-
-	/*
-	 * Make irqs happen for the system timer
-	 */
-	bcmring_clocksource_init();
-
-	sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-
-struct sys_timer bcmring_timer = {
-	.init = bcmring_init_timer,
-};
-
-void __init bcmring_init_early(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c4..0000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile 
b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c037..0000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile 
b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 6739527..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 96273ff..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF	/* Max number of times 
allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10	/* Max number of attempt to 
align the phase */
-
-/* Local definition of clock type */
-#define PLL_CLOCK                      1	/* PLL Clock */
-#define NON_PLL_CLOCK                  2	/* Divider clock */
-
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-	} else {
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz =
-	    chipcHw_XTAL_FREQ_Hz *
-		 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Obtain PLL clock frequency */
-		if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (clock == chipcHw_CLOCK_DDR) {
-			/* DDR frequency is configured in PLLDivider register */
-			return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				vcoHz >>= 1;
-			}
-			/* Obtain PLL clock frequency using VCO dividers */
-			return chipcHw_divide(vcoHz, ((*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-	} else if (pClockCtrl) {
-		/* Obtain divider clock frequency */
-		uint32_t div;
-		uint32_t freq = 0;
-
-		if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (pDependentClock) {
-			/* Identify the dependent clock frequency */
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-					/* Use crystal clock frequency when dependent PLL clock is bypassed */
-					freq = chipcHw_XTAL_FREQ_Hz;
-				} else {
-					/* Obtain PLL clock frequency using VCO dividers */
-					div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-					freq = div ? chipcHw_divide(vcoHz, div) : 0;
-				}
-				break;
-			case NON_PLL_CLOCK:
-				if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-					freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-				} else {
-					if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-						/* Use crystal clock frequency when dependent divider clock is 
bypassed */
-						freq = chipcHw_XTAL_FREQ_Hz;
-					} else {
-						/* Obtain divider clock frequency using XTAL dividers */
-						div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-					}
-				}
-				break;
-			}
-		} else {
-			/* Dependent on crystal clock */
-			freq = chipcHw_XTAL_FREQ_Hz;
-		}
-
-		div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-		return chipcHw_divide(freq, (div ? div : 256));
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t desVcoFreqPll1Hz = 0;	/* Desired VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-	uint32_t desVcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != 
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
(chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-
-		/* Desired VCO frequency */
-		desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-	} else {
-		vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * 
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, 
chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		/* Configure the DDR_ctrl:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-			pChipcHw->DDRClock = (pChipcHw->DDRClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		/* Configure the VPM:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, 
chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Select XTAL as bypass source */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-		reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* For DDR settings use only the PLL divider clock */
-		if (pPLLReg == &pChipcHw->DDRClock) {
-			/* Set M1DIV for PLL1, which controls the DDR clock */
-			reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 
0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) 
 >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && 
(chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				desVcoHz >>= 1;
-				vcoHz >>= 1;
-			}
-			/* Set MDIV to change the frequency */
-			reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-			reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & 
chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-		/* Wait for for atleast 200ns as per the protocol to change frequency */
-		udelay(1);
-		/* Do not bypass */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* Return the configured frequency */
-		return freq;
-	} else if (pClockCtrl) {
-		uint32_t divider = 0;
-
-		/* Divider clock should not be bypassed  */
-		reg32_modify_and(pClockCtrl,
-				 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-
-		/* Identify the clock source */
-		if (pDependentClock) {
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				divider = chipcHw_divide(chipcHw_divide (desVcoHz, 
(*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-				break;
-			case NON_PLL_CLOCK:
-				{
-					uint32_t sourceClock = 0;
-
-					if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-						sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-					} else {
-						uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div 
: 256));
-					}
-					divider = chipcHw_divide(sourceClock, freq);
-				}
-				break;
-			}
-		} else {
-			divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-		}
-
-		if (divider) {
-			REG_LOCAL_IRQ_SAVE;
-			/* Set the divider to obtain the required frequency */
-			*pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | 
(((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & 
chipcHw_REG_DIV_CLOCK_DIV_MASK);
-			REG_LOCAL_IRQ_RESTORE;
-			return freq;
-		}
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-	uint32_t phaseControl;
-	uint32_t phaseValue;
-	uint32_t prevPhaseComp;
-	int iter = 0;
-	int adjustCount = 0;
-	int count = 0;
-
-	for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT); iter++) {
-		phaseControl = (pChipcHw->VPMClock & 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-		phaseValue = 0;
-		prevPhaseComp = 0;
-
-		/* Step 1: Look for falling PH_COMP transition */
-
-		/* Read the contents of VPM Clock resgister */
-		phaseValue = pChipcHw->VPMClock;
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) ||	/* Look for a transition */
-			  ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&	/* 
Look for a falling edge */
-			 (adjustCount < MAX_PHASE_ADJUST_COUNT)	/* Do not exceed the limit 
while trying */
-		    );
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		/* Step 2: Keep moving forward to make sure falling PH_COMP 
transition was valid */
-
-		for (count = 0; (count < 5) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl + 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 5) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 3: Keep moving backward to make sure falling PH_COMP 
transition was stable */
-
-		for (count = 0; (count < 3) && ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 3) {
-			/* Detected noisy transition */
-			continue;
-		}
-
-		/* Step 4: Keep moving backward before the original transition took 
place. */
-
-		for (count = 0; (count < 5); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 5: Re discover the valid transition */
-
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^=
-			    chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is 
not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & 
chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < 
MAX_PHASE_ADJUST_COUNT));
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-			return -1;
-		} else {
-			/* Valid phase must have detected */
-			break;
-		}
-	}
-
-	/* For VPM Phase should be perfectly aligned. */
-	phaseControl = (((pChipcHw->VPMClock >> 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMClock = (pChipcHw->VPMClock & 
~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
-		/* Load new phase value */
-		pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-	/* Return the status */
-	return (int)adjustCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-
-	if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-		return vpmPhaseAlignA0();
-	} else {
-		uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-		uint32_t phaseValue = 0;
-		int adjustCount = 0;
-
-		/* Disable VPM access */
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-		/* Disable HW VPM phase alignment  */
-		chipcHw_vpmHwPhaseAlignDisable();
-		/* Enable SW VPM phase alignment  */
-		chipcHw_vpmSwPhaseAlignEnable();
-		/* Adjust VPM phase */
-		while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-			phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-
-			/* Adjust phase control value */
-			if (phaseValue > 0xF) {
-				/* Increment phase control value */
-				phaseControl++;
-			} else if (phaseValue < 0xF) {
-				/* Decrement phase control value */
-				phaseControl--;
-			} else {
-				/* Enable VPM access */
-				pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-				/* Return adjust count */
-				return adjustCount;
-			}
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & 
(~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << 
chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Count adjustment */
-			adjustCount++;
-		}
-	}
-
-	/* Disable VPM access */
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-	return -1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 367df75..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-
-	Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-	for Freq_vco = VCO_FREQ_MHz
-		Freq_ref = chipcHw_XTAL_FREQ_Hz
-		PLL_P1 = PLL_P2 = 1
-		and
-		PLL_NDIV_f = 0
-
-	We get:
-		PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-		Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = 
VCO_FREQ_MHz / PLL_MDIV_x
-
-		PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-
-/* ---- Private Variables 
------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-	uint32_t pllPreDivider2 = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		pChipcHw->PLLConfig2 =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-
-		pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-		    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-		    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider2 = pllPreDivider2;
-		/* Set NDIV Frac */
-		pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
-
-		/* This has to be removed once the default values are fixed for PLL2. */
-		pChipcHw->PLLControl12 = 0x38000700;
-		pChipcHw->PLLControl22 = 0x00000015;
-
-		/* Reset PLL2 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-		REG_LOCAL_IRQ_RESTORE;
-	}
-
-	/* Insert certain amount of delay before deasserting ARESET. */
-	udelay(1);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove analog reset and Power on the PLL */
-		pChipcHw->PLLConfig2 &=
-		    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-		      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-
-		REG_LOCAL_IRQ_RESTORE;
-
-	}
-
-	/* Wait until PLL is locked */
-	while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-		;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove digital reset */
-		pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e 
ssSupport)
-{
-	uint32_t pllPreDivider = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->PLLConfig =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-		/* Setting VCO frequency */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pllPreDivider =
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-			    ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-			      1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		} else {
-			pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-			    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-			     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		}
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider = pllPreDivider;
-		/* Set NDIV Frac */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
-		} else {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f;
-		}
-
-		/* Reset PLL1 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-
-		REG_LOCAL_IRQ_RESTORE;
-
-		/* Insert certain amount of delay before deasserting ARESET. */
-		udelay(1);
-
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Remove analog reset and Power on the PLL */
-			pChipcHw->PLLConfig &=
-			    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-			      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-
-		/* Wait until PLL is locked */
-		while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-		       || !(pChipcHw->
-			    PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-			;
-
-		/* Remove digital reset */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-			REG_LOCAL_IRQ_RESTORE;
-		}
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-	delay_init();
-#endif
-
-	/* Do not program PLL, when warm reset */
-	if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-		chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-				   initParam->ssSupport);
-		chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-	} else {
-		/* Clear sticky bits */
-		chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-	}
-	/* Clear sticky bits */
-	chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-
-	/* Before configuring the ARM clock, atleast we need to make sure BUS 
clock maintains the proper ratio with ARM clock */
-	pChipcHw->ACLKClock =
-	    (pChipcHw->
-	     ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-								 armBusRatio &
-								 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
-
-	/* Set various core component frequencies. The order in which this is 
done is important for some. */
-	/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the 
ARM, and VPM needs to know BUS */
-	/* frequency to find its ratio with the BUS.  Hence we must set the 
ARM first, followed by the BUS,  */
-	/* then VPM and RTBUS. */
-
-	chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-				  initParam->busClockFreqHz *
-				  initParam->armBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-				  initParam->busClockFreqHz *
-				  initParam->vpmBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-				  initParam->busClockFreqHz *
-				  initParam->ddrBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-				  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index 2671d88..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-/* ---- Private Variables 
------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-
-typedef void (*RUNFUNC) (void);
-
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to 
the state
-*   required to execute on reset.  To do so we need to copy the code 
into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-	int i = 0;
-	RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-
-	/* Disable all interrupts */
-	intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-	intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-	intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-			chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-		/* Bypass the PLL clocks before reboot */
-		pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-		pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-
-		/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-		do {
-			((uint32_t *) MM_IO_BASE_ARAM)[i] =
-			    ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
-			i++;
-		} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);	/* 
0xe1a0f00f == asm ("mov r15, r15"); */
-
-		CSP_CACHE_FLUSH_ALL;
-
-		/* run the function from ARAM */
-		runFunc();
-
-		/* Code will never get here, but include it to balance 
REG_LOCAL_IRQ_SAVE above */
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop 
  \n\t"
-		" nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		" MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" BIC      r0,r0,#0xd                                            \n\t"
-		" MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-#endif
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-		" MOV      r2,#0x80000000                                        \n\t"
-		" LDR      r3,[r2,#8]                                            \n\t"
-		" ORR      r3,r3,#0x20000                                        \n\t"
-		" STR      r3,[r2,#8]                                            \n\t"
-
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Issue reset */
-		" MOV      r3,#0x2                                               \n\t"
-		" STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-		" MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c 
b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-
-static const char *gMuxStr[] = {
-	"GPIO",			/* 0 */
-	"KeyPad",		/* 1 */
-	"I2C-Host",		/* 2 */
-	"SPI",			/* 3 */
-	"Uart",			/* 4 */
-	"LED-Mtx-P",		/* 5 */
-	"LED-Mtx-S",		/* 6 */
-	"SDIO-0",		/* 7 */
-	"SDIO-1",		/* 8 */
-	"PCM",			/* 9 */
-	"I2S",			/* 10 */
-	"ETM",			/* 11 */
-	"Debug",		/* 12 */
-	"Misc",			/* 13 */
-	"0xE",			/* 14 */
-	"0xF",			/* 15 */
-};
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-	if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-		return "";
-	}
-
-	return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile 
b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104f..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 6b9be2e..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA 
Channel handle */
-    ) {
-	uint32_t val = 0;
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_MISC_t *pMiscReg =
-	    (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
-
-	switch (pCblk->channel) {
-	case 0:
-		val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
-		break;
-	case 1:
-		val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
-		break;
-	case 2:
-		val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
-		break;
-	case 3:
-		val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
-		break;
-	case 4:
-		val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
-		break;
-	case 5:
-		val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
-		break;
-	case 6:
-		val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
-		break;
-	case 7:
-		val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
-		break;
-	}
-
-	if (val <= 0x4) {
-		return 8 << val;
-	} else {
-		dmacHw_ASSERT(0);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pProg;
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Not safe yet to program the channel */
-		return;
-	}
-
-	if (pCblk->varDataStarted) {
-		if (pCblk->descUpdated) {
-			pCblk->descUpdated = 0;
-			pProg =
-			    (dmacHw_DESC_t *) ((uint32_t)
-					       dmacHw_REG_LLP(pCblk->module,
-							      pCblk->channel) +
-					       pRing->virt2PhyOffset);
-
-			/* Load descriptor if not loaded */
-			if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-				dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-					       pProg->sar);
-				dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-					       pProg->dar);
-				dmacHw_REG_CTL_LO(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.lo;
-				dmacHw_REG_CTL_HI(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.hi;
-			} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-				/* Return as end descriptor is processed */
-				return;
-			} else {
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			return;
-		}
-	} else {
-		if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-			/* Do not make a single chain, rather process one descriptor at a 
time */
-			pProg = pRing->pHead;
-			/* Point to the next descriptor for next iteration */
-			dmacHw_NEXT_DESC(pRing, pHead);
-		} else {
-			/* Return if no more pending descriptor */
-			if (pRing->pEnd == NULL) {
-				return;
-			}
-
-			pProg = pRing->pProg;
-			if (pConfig->transferMode ==
-			    dmacHw_TRANSFER_MODE_CONTINUOUS) {
-				/* Make sure a complete ring can be formed */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-					      llp == pRing->pProg);
-				/* Make sure pProg pointing to the pHead */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-					      pRing->pHead);
-				/* Make a complete ring */
-				do {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				} while (pRing->pProg != pRing->pHead);
-			} else {
-				/* Make a single long chain */
-				while (pRing->pProg != pRing->pEnd) {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				}
-			}
-		}
-
-		/* Program the channel registers */
-		dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-		dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-		    pProg->ctl.lo;
-		dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-		    pProg->ctl.hi;
-		if (pRing->pEnd) {
-			/* Remember the descriptor to use next */
-			pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-		}
-		/* Indicate no more pending descriptor  */
-		pRing->pEnd = (dmacHw_DESC_t *) NULL;
-	}
-	/* Start DMA operation */
-	dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-
-	uint32_t i = 0;
-
-	dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-	dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-
-	/* Enable access to the DMA block */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-
-	if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-		dmacHw_ASSERT(0);
-	}
-
-	memset((void *)dmacHw_gCblk, 0,
-	       sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-	for (i = 0; i < dmaChannelCount_0; i++) {
-		dmacHw_gCblk[i].module = 0;
-		dmacHw_gCblk[i].channel = i;
-	}
-	for (i = 0; i < dmaChannelCount_1; i++) {
-		dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-		dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-	/* Disable access to the DMA block */
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    ) {
-	int idx;
-
-	switch ((channelId >> 8)) {
-	case 0:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-		idx = (channelId & 0xff);
-		break;
-	case 1:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-		idx = dmaChannelCount_0 + (channelId & 0xff);
-		break;
-	default:
-		dmacHw_ASSERT(0);
-		return (dmacHw_HANDLE_t) -1;
-	}
-
-	return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	int module = pCblk->module;
-	int channel = pCblk->channel;
-
-	/* Reinitialize the control block */
-	memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-	pCblk->module = module;
-	pCblk->channel = channel;
-
-	/* Enable DMA controller */
-	dmacHw_DMA_ENABLE(pCblk->module);
-	/* Reset DMA channel */
-	dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Mask event specific interrupts */
-	dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/* [ IN ] Number of 
descriptor in the ring */
-    ) {
-	/* Need extra 4 byte to ensure 32 bit alignment  */
-	return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-		sizeof(uint32_t);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    ) {
-	uint32_t i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	/* Check the alignment of the descriptor */
-	if ((uint32_t) pDescriptorVirt & 0x00000003) {
-		dmacHw_ASSERT(0);
-		return -1;
-	}
-
-	/* Check if enough space has been allocated for descriptor ring */
-	if (len < dmacHw_descriptorLen(num)) {
-		return -1;
-	}
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-	pRing->pHead =
-	    (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-	/* Initialize link item chain, starting from the head */
-	pDesc = pRing->pHead;
-	/* Find the offset between virtual to physical address */
-	pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-
-	/* Form the descriptor ring */
-	for (i = 0; i < num - 1; i++) {
-		/* Clear link list item */
-		memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-		/* Point to the next item in the physical address */
-		pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-		/* Point to the next item in the virtual address */
-		pDesc->llp = (uint32_t) (pDesc + 1);
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-
-	/* Clear last link list item */
-	memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-	/* Last item pointing to the first item in the
-	   physical address to complete the ring */
-	pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-	/* Last item pointing to the first item in the
-	   virtual address to complete the ring
-	 */
-	pDesc->llp = (uint32_t) pRing->pHead;
-	/* Mark descriptor is ready to use */
-	pDesc->ctl.hi = dmacHw_DESC_FREE;
-	/* Set the number of descriptors in the ring */
-	pRing->num = num;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	uint32_t cfgHigh = 0;
-	int srcTrSize;
-	int dstTrSize;
-
-	pCblk->varDataStarted = 0;
-	pCblk->userData = NULL;
-
-	/* Configure
-	   - Burst transaction when enough data in available in FIFO
-	   - AHB Access protection 1
-	   - Source and destination peripheral ports
-	 */
-	cfgHigh =
-	    dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-	    dmacHw_SRC_PERI_INTF(pConfig->
-				 srcPeripheralPort) |
-	    dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-	/* Set priority */
-	dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-				    pConfig->channelPriority);
-
-	if (pConfig->dstStatusRegisterAddress != 0) {
-		/* Destination status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-		/* Configure status registers */
-		dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->dstStatusRegisterAddress);
-	}
-
-	if (pConfig->srcStatusRegisterAddress != 0) {
-		/* Source status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-		/* Source status update enable */
-		dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->srcStatusRegisterAddress);
-	}
-	/* Configure the config high register */
-	dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Configure block interrupt */
-	if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure complete transfer interrupt */
-	if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure error interrupt */
-	if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure gather register */
-	if (pConfig->srcGatherWidth) {
-		srcTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-		if (!
-		    ((pConfig->srcGatherWidth % srcTrSize)
-		     && (pConfig->srcGatherJump % srcTrSize))) {
-			dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->srcGatherWidth /
-			      srcTrSize) << 20) | (pConfig->srcGatherJump /
-						   srcTrSize);
-		} else {
-			return -1;
-		}
-	}
-	/* Configure scatter register */
-	if (pConfig->dstScatterWidth) {
-		dstTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-		if (!
-		    ((pConfig->dstScatterWidth % dstTrSize)
-		     && (pConfig->dstScatterJump % dstTrSize))) {
-			dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->dstScatterWidth /
-			      dstTrSize) << 20) | (pConfig->dstScatterJump /
-						   dstTrSize);
-		} else {
-			return -1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_BUSY;
-	} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-		   (0x00000001 << pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_ERROR;
-	}
-
-	return dmacHw_TRANSFER_STATUS_DONE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			     void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-	dmacHw_DESC_t *pProg;
-	int srcTs = 0;
-	int blkTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int count = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if ((pConfig->srcGatherWidth % srcTrSize)
-	    || (pConfig->dstScatterWidth % dstTrSize)) {
-		return -2;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	/* Check the availability of "descCount" discriptors in the ring */
-	pProg = pRing->pHead;
-	for (count = 0; (descCount <= pRing->num) && (count < descCount);
-	     count++) {
-		if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-			/* Sufficient descriptors are not available */
-			return -3;
-		}
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	}
-
-	/* Remember the link list item to program the channel registers */
-	pStart = pProg = pRing->pHead;
-	/* Make a link list with "descCount(=count)" number of descriptors */
-	while (count) {
-		/* Reset channel control information */
-		pProg->ctl.lo = 0;
-		/* Enable source gather if configured */
-		if (pConfig->srcGatherWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-		}
-		/* Enable destination scatter if configured */
-		if (pConfig->dstScatterWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-		}
-		/* Set source and destination address */
-		pProg->sar = (uint32_t) pSrcAddr;
-		pProg->dar = (uint32_t) pDstAddr;
-		/* Use "devCtl" to mark that user memory need to be freed later if 
needed */
-		if (pProg == pRing->pHead) {
-			pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-		} else {
-			pProg->devCtl = 0;
-		}
-
-		blkTs = srcTs;
-
-		/* Special treatmeant for last descriptor */
-		if (count == 1) {
-			/* Mark the last descriptor */
-			pProg->ctl.lo &=
-			    ~(dmacHw_REG_CTL_LLP_DST_EN |
-			      dmacHw_REG_CTL_LLP_SRC_EN);
-			/* Treatment for odd data bytes */
-			if (oddSize) {
-				/* Adjust for single byte transaction width */
-				switch (pConfig->transferType) {
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs =
-					    (oddSize / srcTrSize) +
-					    ((oddSize % srcTrSize) ? 1 : 0);
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-					/* Do not adjust the transaction width  */
-					break;
-				}
-			} else {
-				srcTs -= blkTs;
-			}
-		} else {
-			if (srcTs / maxBlockSize) {
-				blkTs = maxBlockSize;
-			}
-			/* Remaining source transactions for next iteration */
-			srcTs -= blkTs;
-		}
-		/* Must have a valid source transactions */
-		dmacHw_ASSERT(blkTs > 0);
-		/* Set control information */
-		if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-			pProg->ctl.lo |= pConfig->transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		} else {
-			uint32_t transferType = 0;
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-			pProg->ctl.lo |= transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		}
-
-		/* Set block transaction size */
-		pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		/* Look for next descriptor */
-		if (count > 1) {
-			/* Point to the next descriptor */
-			pProg = (dmacHw_DESC_t *) pProg->llp;
-
-			/* Update source and destination address for next iteration */
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-				/* Do not adjust the address */
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			/* At the end of transfer "srcTs" must be zero */
-			dmacHw_ASSERT(srcTs == 0);
-		}
-		count--;
-	}
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pStart;
-	}
-	/* Indicate that the descriptor is updated */
-	pRing->pEnd = pProg;
-	/* Head pointing to the next descriptor */
-	pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-	/* Update Tail pointer if destination is a peripheral,
-	   because no one is going to read from the pTail
-	 */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	switch (attr) {
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-		return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-		return (1 <<
-			 (dmacHw_GET_MAX_BLOCK_SIZE
-			  (pCblk->module, pCblk->module) + 2)) - 8;
-	case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-		return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-		return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-							   pCblk->channel);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-		return GetFifoSize(handle);
-	}
-	dmacHw_ASSERT(0);
-	return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c 
b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index a1f3283..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* 
Declared in dmacHw.c */
-
-/* ---- External Function Prototypes 
------------------------------------- */
-
-/* ---- Internal Use Function Prototypes 
--------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module,	/*   [ IN ] DMA 
Controller unit  (0-1) */
-				    int channel,	/*   [ IN ] DMA Channel          (0-7) / -1(all) */
-				    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	int chan;
-
-	(*fpPrint) ("Displaying register content \n\n");
-	(*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: SW source req                       0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-	(*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW source last                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: misc config                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-	(*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-	(*fpPrint) ("Module %d: misc ID                             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-	(*fpPrint) ("Module %d: misc test                           0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-
-	if (channel == -1) {
-		for (chan = 0; chan < 8; chan++) {
-			(*fpPrint)
-			    ("--------------------------------------------------\n");
-			(*fpPrint)
-			    ("Module %d: Channel %d Source                   0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Destination              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d LLP                      0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_LLP(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (LO)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (HI)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats               0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (LO)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (HI)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-		}
-	} else {
-		chan = channel;
-		(*fpPrint)
-		    ("--------------------------------------------------\n");
-		(*fpPrint)
-		    ("Module %d: Channel %d Source                   0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Destination              0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d LLP                      0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (LO)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (HI)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats             0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats               0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (LO)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (HI)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,	/*   [ IN ] Descriptor 
buffer */
-			    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the 
print function */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-
-	if (pRing->pHead == NULL) {
-		return;
-	}
-
-	pStart = pRing->pHead;
-
-	while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-		if (pStart == pRing->pHead) {
-			(*fpPrint) ("Head\n");
-		}
-		if (pStart == pRing->pTail) {
-			(*fpPrint) ("Tail\n");
-		}
-		if (pStart == pRing->pProg) {
-			(*fpPrint) ("Prog\n");
-		}
-		if (pStart == pRing->pEnd) {
-			(*fpPrint) ("End\n");
-		}
-		if (pStart == pRing->pFree) {
-			(*fpPrint) ("Free\n");
-		}
-		(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-		(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-		(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-		(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-		(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-		(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-		(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-		(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-		(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-
-		pStart = (dmacHw_DESC_t *) pStart->llp;
-	}
-	if (pStart == pRing->pHead) {
-		(*fpPrint) ("Head\n");
-	}
-	if (pStart == pRing->pTail) {
-		(*fpPrint) ("Tail\n");
-	}
-	if (pStart == pRing->pProg) {
-		(*fpPrint) ("Prog\n");
-	}
-	if (pStart == pRing->pEnd) {
-		(*fpPrint) ("End\n");
-	}
-	if (pStart == pRing->pFree) {
-		(*fpPrint) ("Free\n");
-	}
-	(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-	(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-	(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-	(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-	(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-	(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-	(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-	(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-	(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor	/*   [ IN ] 
Descriptor buffer */
-    ) {
-	uint32_t ttfc =
-	    (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-	    lo & dmacHw_REG_CTL_TTFC_MASK;
-
-	switch (ttfc) {
-	case dmacHw_REG_CTL_TTFC_MM_DMAC:
-	case dmacHw_REG_CTL_TTFC_MP_DMAC:
-	case dmacHw_REG_CTL_TTFC_PM_DMAC:
-	case dmacHw_REG_CTL_TTFC_PP_DMAC:
-		return 1;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_DESC_t *pProg;
-	dmacHw_DESC_t *pHead;
-	int srcTs = 0;
-	int srcTrSize = 0;
-
-	pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-	pProg = pHead;
-
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-	srcTs = dataLen / srcTrSize;
-	do {
-		pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	} while (pProg != pHead);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/* [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/* [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-
-	if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_TRANS;
-	}
-	if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-	}
-	if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_ERROR;
-	}
-
-	return status;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-		if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-		     ((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    ) {
-			return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-		}
-	}
-	return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	int srcTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if (pConfig->srcGatherWidth % srcTrSize
-	    || pConfig->dstScatterWidth % dstTrSize) {
-		return -1;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination 
addresses are
-	   not properly aligned with the channel's transaction width. So, for 
successful
-	   DMA transfer, transaction width must be set according to the 
alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not 
aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned 
properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA 
transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single 
byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	return descCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	/* Make sure channel is not busy */
-	if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Check if pEnd is not processed */
-		if (pRing->pEnd) {
-			/* Something left for processing */
-			return 1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    ) {
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	/* Stop the channel */
-	dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-		   void (*fpFree) (void *)	/*   [ IN ] Function pointer to free data 
memory */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t count = 0;
-
-	if (fpFree == NULL) {
-		return -1;
-	}
-
-	while ((pRing->pFree != pRing->pTail)
-	       && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-		if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-			/* Identify, which memory to free */
-			if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-				(*fpFree) ((void *)pRing->pFree->dar);
-			} else {
-				/* Destination was a peripheral */
-				(*fpFree) ((void *)pRing->pFree->sar);
-			}
-			/* Unmark user memory to indicate it is freed */
-			pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-		}
-		dmacHw_NEXT_DESC(pRing, pFree);
-
-		count++;
-	}
-
-	return count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*   [ IN 
] DMA Channel handle */
-				     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				     uint32_t srcAddr,	/*   [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*   [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*   [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*   [ IN ] Number of descriptor to set */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_t *pProg = NULL;
-	dmacHw_DESC_t *pLast = NULL;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t dstAddr;
-	uint32_t controlParam;
-	int i;
-
-	dmacHw_ASSERT(pConfig->transferType ==
-		      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-
-	if (num > pRing->num) {
-		return -1;
-	}
-
-	pLast = pRing->pEnd;	/* Last descriptor updated */
-	pProg = pRing->pHead;	/* First descriptor in the new list */
-
-	controlParam = pConfig->srcUpdate |
-	    pConfig->dstUpdate |
-	    pConfig->srcMaxTransactionWidth |
-	    pConfig->dstMaxTransactionWidth |
-	    pConfig->srcMasterInterface |
-	    pConfig->dstMasterInterface |
-	    pConfig->srcMaxBurstWidth |
-	    pConfig->dstMaxBurstWidth |
-	    dmacHw_REG_CTL_TTFC_PM_PERI |
-	    dmacHw_REG_CTL_LLP_DST_EN |
-	    dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-
-	for (i = 0; i < num; i++) {
-		/* Allocate Rx buffer only for idle descriptor */
-		if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-		    ) {
-			/* Rx descriptor is not idle */
-			break;
-		}
-		/* Set source address */
-		pRing->pHead->sar = srcAddr;
-		if (fpAlloc) {
-			/* Allocate memory for buffer in descriptor */
-			dstAddr = (uint32_t) (*fpAlloc) (len);
-			/* Check the destination address */
-			if (dstAddr == 0) {
-				if (i == 0) {
-					/* Not a single descriptor is available */
-					return -1;
-				}
-				break;
-			}
-			/* Set destination address */
-			pRing->pHead->dar = dstAddr;
-		}
-		/* Set control information */
-		pRing->pHead->ctl.lo = controlParam;
-		/* Use "devCtl" to mark the memory that need to be freed later */
-		pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-		/* Descriptor is now owned by the channel */
-		pRing->pHead->ctl.hi = 0;
-		/* Remember the descriptor last updated */
-		pRing->pEnd = pRing->pHead;
-		/* Update next descriptor */
-		dmacHw_NEXT_DESC(pRing, pHead);
-	}
-
-	/* Mark the end of the list */
-	pRing->pEnd->ctl.lo &=
-	    ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-	/* Connect the list */
-	if (pLast != pProg) {
-		pLast->ctl.lo |=
-		    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-	}
-	/* Mark the descriptors are updated */
-	pCblk->descUpdated = 1;
-	if (!pCblk->varDataStarted) {
-		/* LLP must be pointing to the first descriptor */
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		/* Channel, handling variable data started */
-		pCblk->varDataStarted = 1;
-	}
-
-	return i;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       dmacHw_CONFIG_t *pConfig,	/*   [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			       void **ppBbuf,	/*   [ OUT ] Data received */
-			       size_t *pLlen	/*   [ OUT ] Length of the data received */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	(void)handle;
-
-	if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-		if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    (pRing->pTail == pRing->pHead)
-		    ) {
-			/* No receive data available */
-			*ppBbuf = (char *)NULL;
-			*pLlen = 0;
-
-			return 0;
-		}
-	}
-
-	/* Return read buffer and length */
-	*ppBbuf = (char *)pRing->pTail->dar;
-
-	/* Extract length of the received data */
-	if (DmaIsFlowController(pDescriptor)) {
-		uint32_t srcTrSize = 0;
-
-		switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-			srcTrSize = 1;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-			srcTrSize = 2;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-			srcTrSize = 4;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-			srcTrSize = 8;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		/* Calculate length from the block size */
-		*pLlen =
-		    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-		    srcTrSize;
-	} else {
-		/* Extract length from the source peripheral */
-		*pLlen = pRing->pTail->sstat;
-	}
-
-	/* Advance tail to next descriptor */
-	dmacHw_NEXT_DESC(pRing, pTail);
-
-	return 1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				uint32_t ctlAddress,	/*   [ IN ] Address of the device control 
register */
-				uint32_t control	/*   [ IN ] Device control information */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (ctlAddress == 0) {
-		return -1;
-	}
-
-	/* Check the availability of descriptors in the ring */
-	if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-		return -1;
-	}
-	/* Set control information */
-	pRing->pHead->devCtl = control;
-	/* Set source and destination address */
-	pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-	pRing->pHead->dar = ctlAddress;
-	/* Set control parameters */
-	if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-		pRing->pHead->ctl.lo = pConfig->transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-	} else {
-		uint32_t transferType = 0;
-		switch (pConfig->transferType) {
-		case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-			transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-			break;
-		case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-			transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		pRing->pHead->ctl.lo = transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface |
-		    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-	}
-
-	/* Set block transaction size to one 32 bit transaction */
-	pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pRing->pHead;
-	}
-	pRing->pEnd = pRing->pHead;
-
-	/* Advance the descriptor */
-	dmacHw_NEXT_DESC(pRing, pHead);
-
-	/* Update Tail pointer if destination is a peripheral */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			       void *userData	/*  [ IN ] User data */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	pCblk->userData = userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	return pCblk->userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    ) {
-	int i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	pDesc = pRing->pHead;
-
-	for (i = 0; i < pRing->num; i++) {
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle */
-			   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-	DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile 
b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61a..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c 
b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index 16225e4..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-
-#include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK 
/ tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / 
tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT 
(tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_LOW_256_RESOLUTION_COUNT)
-
-#define tmrHw_HIGH_1_RESOLUTION_COUNT 
(tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / 
tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / 
tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT 
(tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / 
tmrHw_HIGH_256_RESOLUTION_COUNT)
-
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-) {
-	switch (capability) {
-	case tmrHw_CAPABILITY_CLOCK:
-		return (timerId <=
-			1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-		    tmrHw_HIGH_RESOLUTION_CLOCK;
-	case tmrHw_CAPABILITY_RESOLUTION:
-		return 32;
-	default:
-		return 0;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer Id */
-) {
-	/* Reset timer */
-	pTmrHw[timerId].LoadValue = 0;
-	pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-	pTmrHw[timerId].Control = 0;
-	pTmrHw[timerId].BackgroundLoad = 0;
-	/* Always configure as a 32 bit timer */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-	/* Clear interrupt only if raw status interrupt is set */
-	if (pTmrHw[timerId].RawInterruptStatus) {
-		pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	uint32_t scale = 0;
-	uint32_t count = 0;
-
-	if (timerId == 0 || timerId == 1) {
-		if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-
-	} else if (timerId == 2 || timerId == 3) {
-		if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-	}
-	return count / scale;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-) {
-	uint32_t resolution = 0;
-	uint32_t count = 0;
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-	/* Set timer in highest resolution */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-
-	if (rate && (timerId == 0 || timerId == 1)) {
-		if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-			return 0;
-		}
-		resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-	} else if (rate && (timerId == 2 || timerId == 3)) {
-		if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-			return 0;
-		} else {
-			resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-		}
-	} else {
-		return 0;
-	}
-	/* Find the counter value */
-	count = resolution / rate;
-	/* Set counter value */
-	pTmrHw[timerId].LoadValue = count;
-	pTmrHw[timerId].BackgroundLoad = count;
-
-	return resolution / count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode oneshot */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) {
-	uint32_t scale = 0;
-
-	ResetTimer(timerId);
-	/* Set timer as free running mode */
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	if (divider >= 64) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-		scale = 256;
-	} else if (divider >= 8) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-		scale = 16;
-	} else {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-		scale = 1;
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-	} else if (timerId == 2 || timerId == 3) {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	/* return 32 bit timer value */
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-	case tmrHw_CONTROL_FREE_RUNNING:
-		if (pTmrHw[timerId].CurrentValue) {
-			return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-		}
-		break;
-	case tmrHw_CONTROL_PERIODIC:
-	case tmrHw_CONTROL_ONESHOT:
-		return pTmrHw[timerId].BackgroundLoad -
-		    pTmrHw[timerId].CurrentValue;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	uint32_t divider = 0;
-
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-	case tmrHw_CONTROL_PRESCALE_1:
-		divider = 1;
-		break;
-	case tmrHw_CONTROL_PRESCALE_16:
-		divider = 16;
-		break;
-	case tmrHw_CONTROL_PRESCALE_256:
-		divider = 256;
-		break;
-	default:
-		tmrHw_ASSERT(0);
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-	} else {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].InterruptClear = 0x1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-) {
-	if (pTmrHw[timerId].InterruptStatus) {
-		return tmrHw_INTERRUPT_STATUS_SET;
-	} else {
-		return tmrHw_INTERRUPT_STATUS_UNSET;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void	/*  void */
-) {
-	int i;
-
-	for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-		if (pTmrHw[i].InterruptStatus) {
-			return i;
-		}
-	}
-
-	return 0xFFFFFFFF;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-) {
-	(*fpPrint) ("Displaying register contents \n\n");
-	(*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-		    pTmrHw[timerId].LoadValue);
-	(*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-		    pTmrHw[timerId].BackgroundLoad);
-	(*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-		    pTmrHw[timerId].Control);
-	(*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptClear);
-	(*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-		    pTmrHw[timerId].RawInterruptStatus);
-	(*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptStatus);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-	tmrHw_RATE_t usec_tick_rate;
-	tmrHw_COUNT_t start_time;
-	tmrHw_COUNT_t delta_time;
-
-	start_time = tmrHw_GetCurrentCount(timerId);
-	usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-	delta_time = usecs * usec_tick_rate;
-
-	/* Busy wait */
-	while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-		;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241..0000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-
-#include <mach/timer.h>
-
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-
-/* ---- Public Variables 
------------------------------------------------- */
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 
4) | (channelIdx))
-
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-
-
-/* ---- Private Variables 
------------------------------------------------ */
-
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-
-#include "dma_device.c"
-
-/* ---- Private Function Prototypes 
-------------------------------------- */
-
-/* ---- Functions 
------------------------------------------------------- */
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-				  int count, int *eof, void *data)
-{
-	int controllerIdx;
-	int channelIdx;
-	int limit = count - 200;
-	int len = 0;
-	DMA_Channel_t *channel;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			if (len >= limit) {
-				break;
-			}
-
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			len +=
-			    sprintf(buf + len, "%d:%d ", controllerIdx,
-				    channelIdx);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				len +=
-				    sprintf(buf + len, "Dedicated for %s ",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-			} else {
-				len += sprintf(buf + len, "Shared ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-				len += sprintf(buf + len, "No ISR ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-				len += sprintf(buf + len, "Fifo: 128 ");
-			} else {
-				len += sprintf(buf + len, "Fifo: 64  ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-				len +=
-				    sprintf(buf + len, "InUse by %s",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-				len +=
-				    sprintf(buf + len, " (%s:%d)",
-					    channel->fileName,
-					    channel->lineNum);
-#endif
-			} else {
-				len += sprintf(buf + len, "Avail ");
-			}
-
-			if (channel->lastDevType != DMA_DEVICE_NONE) {
-				len +=
-				    sprintf(buf + len, "Last use: %s ",
-					    DMA_gDeviceAttribute[channel->
-								 lastDevType].
-					    name);
-			}
-
-			len += sprintf(buf + len, "\n");
-		}
-	}
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-				 int count, int *eof, void *data)
-{
-	int limit = count - 200;
-	int len = 0;
-	int devIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (devAttr->name == NULL) {
-			continue;
-		}
-
-		if (len >= limit) {
-			break;
-		}
-
-		len += sprintf(buf + len, "%-12s ", devAttr->name);
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			len +=
-			    sprintf(buf + len, "Dedicated %d:%d ",
-				    devAttr->dedicatedController,
-				    devAttr->dedicatedChannel);
-		} else {
-			len += sprintf(buf + len, "Shared DMA:");
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-				len += sprintf(buf + len, "0");
-			}
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-				len += sprintf(buf + len, "1");
-			}
-			len += sprintf(buf + len, " ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-			len += sprintf(buf + len, "NoISR ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-			len += sprintf(buf + len, "Allow-128 ");
-		}
-
-		len +=
-		    sprintf(buf + len,
-			    "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-			    devAttr->numTransfers, devAttr->transferTicks,
-			    devAttr->transferBytes,
-			    devAttr->ring.bytesAllocated);
-
-	}
-
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-	return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-	int controllerIdx;
-	int channelIdx;
-
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-	channelIdx = CHANNEL_FROM_HANDLE(handle);
-
-	if ((controllerIdx > DMA_NUM_CONTROLLERS)
-	    || (channelIdx > DMA_NUM_CHANNELS)) {
-		return NULL;
-	}
-	return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int irqStatus;
-
-	channel = (DMA_Channel_t *) dev_id;
-
-	/* Figure out why we were called, and knock down the interrupt */
-
-	irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-	dmacHw_clearInterrupt(channel->dmacHwHandle);
-
-	if ((channel->devType < 0)
-	    || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-		printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-		       channel->devType);
-		return IRQ_NONE;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Update stats */
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-		devAttr->transferTicks +=
-		    (timer_get_tick_count() - devAttr->transferStartTime);
-	}
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-		printk(KERN_ERR
-		       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-		       channel->devType, devAttr->name);
-	} else {
-		devAttr->numTransfers++;
-		devAttr->transferBytes += devAttr->numBytes;
-	}
-
-	/* Call any installed handler */
-
-	if (devAttr->devHandler != NULL) {
-		devAttr->devHandler(channel->devType, irqStatus,
-				    devAttr->userData);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    ) {
-	size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-
-	if ((ring == NULL) || (numDescriptors <= 0)) {
-		return -EINVAL;
-	}
-
-	ring->physAddr = 0;
-	ring->descriptorsAllocated = 0;
-	ring->bytesAllocated = 0;
-
-	ring->virtAddr = dma_alloc_writecombine(NULL,
-						     bytesToAlloc,
-						     &ring->physAddr,
-						     GFP_KERNEL);
-	if (ring->virtAddr == NULL) {
-		return -ENOMEM;
-	}
-
-	ring->bytesAllocated = bytesToAlloc;
-	ring->descriptorsAllocated = numDescriptors;
-
-	return dma_init_descriptor_ring(ring, numDescriptors);
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    ) {
-	if (ring->virtAddr != NULL) {
-		dma_free_writecombine(NULL,
-				      ring->bytesAllocated,
-				      ring->virtAddr, ring->physAddr);
-	}
-
-	ring->bytesAllocated = 0;
-	ring->descriptorsAllocated = 0;
-	ring->virtAddr = NULL;
-	ring->physAddr = 0;
-}
-
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    ) {
-	if (ring->virtAddr == NULL) {
-		return -EINVAL;
-	}
-	if (dmacHw_initDescriptor(ring->virtAddr,
-				  ring->physAddr,
-				  ring->bytesAllocated, numDescriptors) < 0) {
-		printk(KERN_ERR
-		       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int numDescriptors;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR
-		       "dma_calculate_descriptor_count: 
dmacHw_calculateDescriptorCount failed\n");
-		return -EINVAL;
-	}
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int rc;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	rc = dmacHw_setDataDescriptor(&devAttr->config,
-				      ring->virtAddr,
-				      (void *)srcData,
-				      (void *)dstData, numBytes);
-	if (rc < 0) {
-		printk(KERN_ERR
-		       "dma_add_descriptors: dmacHw_setDataDescriptor failed with 
code: %d\n",
-		       rc);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_add_descriptors);
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	/* Free the previously allocated descriptor ring */
-
-	dma_free_descriptor_ring(&devAttr->ring);
-
-	if (ring != NULL) {
-		/* Copy in the new one */
-
-		devAttr->ring = *ring;
-	}
-
-	/* Set things up so that if dma_transfer is called then this descriptor */
-	/* ring will get freed. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	memset(ring, 0, sizeof(*ring));
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	*ring = devAttr->ring;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-static int ConfigChannel(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int controllerIdx;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-		if (devAttr->config.transferType ==
-		    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-			devAttr->config.dstPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		} else if (devAttr->config.transferType ==
-			   dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-			devAttr->config.srcPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		}
-	}
-
-	if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-		printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_init(void)
-{
-	int rc = 0;
-	int controllerIdx;
-	int channelIdx;
-	DMA_Device_t devIdx;
-	DMA_Channel_t *channel;
-	DMA_Handle_t dedicatedHandle;
-
-	memset(&gDMA, 0, sizeof(gDMA));
-
-	sema_init(&gDMA.lock, 0);
-	init_waitqueue_head(&gDMA.freeChannelQ);
-
-	/* Initialize the Hardware */
-
-	dmacHw_initDma();
-
-	/* Start off by marking all of the DMA channels as shared. */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			channel->flags = 0;
-			channel->devType = DMA_DEVICE_NONE;
-			channel->lastDevType = DMA_DEVICE_NONE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-			channel->fileName = "";
-			channel->lineNum = 0;
-#endif
-
-			channel->dmacHwHandle =
-			    dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-						    (controllerIdx,
-						     channelIdx));
-			dmacHw_initChannel(channel->dmacHwHandle);
-		}
-	}
-
-	/* Record any special attributes that channels may have */
-
-	gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-
-	/* Now walk through and record the dedicated channels. */
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-		    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-			printk(KERN_ERR
-			       "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-			       devAttr->name);
-			rc = -EINVAL;
-			goto out;
-		}
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			/* This is a dedicated device. Mark the channel as being reserved. */
-
-			if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Controller %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedController);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Channel %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedChannel);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			dedicatedHandle =
-			    MAKE_HANDLE(devAttr->dedicatedController,
-					devAttr->dedicatedChannel);
-			channel = HandleToChannel(dedicatedHandle);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				printk
-				    ("DMA Device: %s attempting to use same DMA Controller:Channel 
(%d:%d) as %s\n",
-				     devAttr->name,
-				     devAttr->dedicatedController,
-				     devAttr->dedicatedChannel,
-				     DMA_gDeviceAttribute[channel->devType].
-				     name);
-				rc = -EBUSY;
-				goto out;
-			}
-
-			channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-			channel->devType = devIdx;
-
-			if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-				channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-			}
-
-			/* For dedicated channels, we can go ahead and configure the DMA 
channel now */
-			/* as well. */
-
-			ConfigChannel(dedicatedHandle);
-		}
-	}
-
-	/* Go through and register the interrupt handlers */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-				snprintf(channel->name, sizeof(channel->name),
-					 "dma %d:%d %s", controllerIdx,
-					 channelIdx,
-					 channel->devType ==
-					 DMA_DEVICE_NONE ? "" :
-					 DMA_gDeviceAttribute[channel->devType].
-					 name);
-
-				rc =
-				     request_irq(IRQ_DMA0C0 +
-						 (controllerIdx *
-						  DMA_NUM_CHANNELS) +
-						 channelIdx,
-						 dma_interrupt_handler,
-						 IRQF_DISABLED, channel->name,
-						 channel);
-				if (rc != 0) {
-					printk(KERN_ERR
-					       "request_irq for IRQ_DMA%dC%d failed\n",
-					       controllerIdx, channelIdx);
-				}
-			}
-		}
-	}
-
-	/* Create /proc/dma/channels and /proc/dma/devices */
-
-	gDmaDir = proc_mkdir("dma", NULL);
-
-	if (gDmaDir == NULL) {
-		printk(KERN_ERR "Unable to create /proc/dma\n");
-	} else {
-		create_proc_read_entry("channels", 0, gDmaDir,
-				       dma_proc_read_channels, NULL);
-		create_proc_read_entry("devices", 0, gDmaDir,
-				       dma_proc_read_devices, NULL);
-	}
-
-out:
-
-	up(&gDMA.lock);
-
-	return rc;
-}
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-	DMA_Handle_t handle;
-	DMA_DeviceAttribute_t *devAttr;
-	DMA_Channel_t *channel;
-	int controllerIdx;
-	int controllerIdx2;
-	int channelIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-		handle = -ENODEV;
-		goto out;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	{
-		char *s;
-
-		s = strrchr(fileName, '/');
-		if (s != NULL) {
-			fileName = s + 1;
-		}
-	}
-#endif
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-		/* This device has already been requested and not been freed */
-
-		printk(KERN_ERR "%s: device %s is already requested\n",
-		       __func__, devAttr->name);
-		handle = -EBUSY;
-		goto out;
-	}
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-		/* This device has a dedicated channel. */
-
-		channel =
-		    &gDMA.controller[devAttr->dedicatedController].
-		    channel[devAttr->dedicatedChannel];
-		if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-			handle = -EBUSY;
-			goto out;
-		}
-
-		channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-		devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-		channel->fileName = fileName;
-		channel->lineNum = lineNum;
-#endif
-		handle =
-		    MAKE_HANDLE(devAttr->dedicatedController,
-				devAttr->dedicatedChannel);
-		goto out;
-	}
-
-	/* This device needs to use one of the shared channels. */
-
-	handle = DMA_INVALID_HANDLE;
-	while (handle == DMA_INVALID_HANDLE) {
-		/* Scan through the shared channels and see if one is available */
-
-		for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-		     controllerIdx2++) {
-			/* Check to see if we should try on controller 1 first. */
-
-			controllerIdx = controllerIdx2;
-			if ((devAttr->
-			     flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-				controllerIdx = 1 - controllerIdx;
-			}
-
-			/* See if the device is available on the controller being tested */
-
-			if ((devAttr->
-			     flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-			    != 0) {
-				for (channelIdx = 0;
-				     channelIdx < DMA_NUM_CHANNELS;
-				     channelIdx++) {
-					channel =
-					    &gDMA.controller[controllerIdx].
-					    channel[channelIdx];
-
-					if (((channel->
-					      flags &
-					      DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-					     0)
-					    &&
-					    ((channel->
-					      flags & DMA_CHANNEL_FLAG_IN_USE)
-					     == 0)) {
-						if (((channel->
-						      flags &
-						      DMA_CHANNEL_FLAG_LARGE_FIFO)
-						     != 0)
-						    &&
-						    ((devAttr->
-						      flags &
-						      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-						     == 0)) {
-							/* This channel is a large fifo - don't tie it up */
-							/* with devices that we don't want using it. */
-
-							continue;
-						}
-
-						channel->flags |=
-						    DMA_CHANNEL_FLAG_IN_USE;
-						channel->devType = dev;
-						devAttr->flags |=
-						    DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-						channel->fileName = fileName;
-						channel->lineNum = lineNum;
-#endif
-						handle =
-						    MAKE_HANDLE(controllerIdx,
-								channelIdx);
-
-						/* Now that we've reserved the channel - we can go ahead and 
configure it */
-
-						if (ConfigChannel(handle) != 0) {
-							handle = -EIO;
-							printk(KERN_ERR
-							       "dma_request_channel: ConfigChannel failed\n");
-						}
-						goto out;
-					}
-				}
-			}
-		}
-
-		/* No channels are currently available. Let's wait for one to free up. */
-
-		{
-			DEFINE_WAIT(wait);
-
-			prepare_to_wait(&gDMA.freeChannelQ, &wait,
-					TASK_INTERRUPTIBLE);
-			up(&gDMA.lock);
-			schedule();
-			finish_wait(&gDMA.freeChannelQ, &wait);
-
-			if (signal_pending(current)) {
-				/* We don't currently hold gDMA.lock, so we return directly */
-
-				return -ERESTARTSYS;
-			}
-		}
-
-		if (down_interruptible(&gDMA.lock)) {
-			return -ERESTARTSYS;
-		}
-	}
-
-out:
-	up(&gDMA.lock);
-
-	return handle;
-}
-
-/* Create both _dbg and non _dbg functions for modules. */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-	return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t handle	/* DMA handle. */
-    ) {
-	int rc = 0;
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		rc = -EINVAL;
-		goto out;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-		channel->lastDevType = channel->devType;
-		channel->devType = DMA_DEVICE_NONE;
-	}
-	channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-	devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-
-out:
-	up(&gDMA.lock);
-
-	wake_up_interruptible(&gDMA.freeChannelQ);
-
-	return rc;
-}
-
-EXPORT_SYMBOL(dma_free_channel);
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t device	/* Device to check. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, numDescriptors);
-			return rc;
-		}
-		/* Setup the descriptor for this transfer */
-
-		if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-					  devAttr->ring.physAddr,
-					  devAttr->ring.bytesAllocated,
-					  numDescriptors) < 0) {
-			printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-			       __func__);
-			return -EINVAL;
-		}
-	} else {
-		/* We've already got enough ring buffer allocated. All we need to do 
is reset */
-		/* any control information, just in case the previous DMA was stopped. */
-
-		dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Remember the critical information for this transfer so that we can 
eliminate */
-	/* another call to dma_alloc_descriptors if the caller reuses the same 
buffers */
-
-	devAttr->prevSrcData = srcData;
-	devAttr->prevDstData = dstData;
-	devAttr->prevNumBytes = numBytes;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptors);
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDst1Descriptors;
-	int numDst2Descriptors;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDst1Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData1, numBytes);
-	if (numDst1Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDst2Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData2, numBytes);
-	if (numDst2Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDescriptors = numDst1Descriptors + numDst2Descriptors;
-	/* printk("numDescriptors: %d\n", numDescriptors); */
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we 
need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt 
context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the 
descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, ringBytesRequired);
-			return rc;
-		}
-	}
-
-	/* Setup the descriptor for this transfer. Since this function is used 
with */
-	/* CONTINUOUS DMA operations, we need to reinitialize every time, 
otherwise */
-	/* setDataDescriptor will keep trying to append onto the end. */
-
-	if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-				  devAttr->ring.physAddr,
-				  devAttr->ring.bytesAllocated,
-				  numDescriptors) < 0) {
-		printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-		return -EINVAL;
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to 
be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData1, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData2, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* You should use dma_start_transfer rather than dma_transfer_xxx so 
we don't */
-	/* try to make the 'prev' variables right. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_start_transfer);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	dmacHw_stopTransfer(channel->dmacHwHandle);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_stop_transfer);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	dmacHw_TRANSFER_STATUS_e status;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	while ((status =
-		dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-	       dmacHw_TRANSFER_STATUS_BUSY) {
-		;
-	}
-
-	if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-		printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-		return -EIO;
-	}
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_wait_transfer_done);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* We keep track of the information about the previous request for this */
-	/* device, and if the attributes match, then we can use the 
descriptors we setup */
-	/* the last time, and not have to reinitialize everything. */
-
-	{
-		rc =
-		     dma_alloc_descriptors(handle, transferType, srcData,
-					   dstData, numBytes);
-		if (rc != 0) {
-			return rc;
-		}
-	}
-
-	/* And kick off the transfer */
-
-	devAttr->numBytes = numBytes;
-	devAttr->transferStartTime = timer_get_tick_count();
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_transfer);
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-	unsigned long flags;
-
-	if (!IsDeviceValid(dev)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-	local_irq_save(flags);
-
-	devAttr->userData = userData;
-	devAttr->devHandler = devHandler;
-
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c 
b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad73..0000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-	[DMA_DEVICE_MEM_TO_MEM] =	/* MEM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-mem",
-	 .config = {
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-
-		    },
-	 },
-	[DMA_DEVICE_VPM_MEM_TO_MEM] =	/* VPM */
-	{
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-	 .name = "vpm",
-	 .dedicatedController = 0,
-	 .dedicatedChannel = 0,
-	 /* reserve DMA0:0 for VPM */
-	 },
-	[DMA_DEVICE_NAND_MEM_TO_MEM] =	/* NAND */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "nand",
-	 .config = {
-		    .srcPeripheralPort = 0,
-		    .dstPeripheralPort = 0,
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-		    },
-	 },
-	[DMA_DEVICE_PIF_MEM_TO_DEV] =	/* PIF TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_tx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    /* dstPeripheralPort          = 5 or 14 */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_PIF_DEV_TO_MEM] =	/* PIF RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-	 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_rx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    /* srcPeripheralPort          = 5 or 14 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_DEV_TO_MEM] =	/* I2S RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_rx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: I2S0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_MEM_TO_DEV] =	/* I2S TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: I2S0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_DEV_TO_MEM] =	/* I2S1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: I2S1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_MEM_TO_DEV] =	/* I2S1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: I2S1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_ESW_MEM_TO_DEV] =	/* ESW TX */
-	{
-	 .name = "esw_tx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 3,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: ESW (MTP) */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x30490010,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_ESW_DEV_TO_MEM] =	/* ESW RX */
-	{
-	 .name = "esw_rx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 2,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: ESW (PTM) */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x30480010,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =	/* APM Codec A Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =	/* APM Codec A Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: Codec A Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =	/* APM Codec B Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec B Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =	/* APM Codec B Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 5,	/* DST: Codec B Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =	/* APM Codec C Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "apm_c_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec C Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =	/* PCM0 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_rx",
-	 .config = {
-		    .srcPeripheralPort = 12,	/* SRC: PCM0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =	/* PCM0 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 13,	/* DST: PCM0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =	/* PCM1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_rx",
-	 .config = {
-		    .srcPeripheralPort = 14,	/* SRC: PCM1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =	/* PCM1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 15,	/* DST: PCM1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_DEV_TO_MEM] =	/* SPUM RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_rx",
-	 .config = {
-		    .srcPeripheralPort = 6,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    /* on the RX side, SPU needs to be the flow controller */
-		    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_MEM_TO_DEV] =	/* SPUM TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 7,	/* DST: SPUM */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_MEM_TO_VRAM] =	/* MEM 2 VRAM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-vram",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-	[DMA_DEVICE_VRAM_TO_MEM] =	/* VRAM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "vram-to-mem",
-	 .config = {
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);	/* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h 
b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da87..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY 
CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h 
b/arch/arm/mach-bcmring/include/cfg_global_defines.h
deleted file mode 100644
index b5beb0b..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-
-/* CHIP */
-#define BCM1103 1
-
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h 
b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e5..0000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h 
b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d803..0000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use 
the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h 
b/arch/arm/mach-bcmring/include/csp/dmacHw.h
deleted file mode 100644
index e6a1dc4..0000000
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-
-#include <stddef.h>
-
-#include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
-
-/* Define DMA Channel ID using DMA controller number (m) and channel 
number (c).
-
-   System specific channel ID should be defined as follows
-
-   For example:
-
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID 
dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-
-typedef enum {
-	dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,	/* 
Channel priority 0. Lowest priority DMA channel */
-	dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,	/* 
Channel priority 1 */
-	dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,	/* 
Channel priority 2 */
-	dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,	/* 
Channel priority 3 */
-	dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,	/* 
Channel priority 4 */
-	dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,	/* 
Channel priority 5 */
-	dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,	/* 
Channel priority 6 */
-	dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7	/* Channel 
priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-
-/* Source destination master interface */
-typedef enum {
-	dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,	/* Source DMA 
master interface 1 */
-	dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,	/* Source DMA 
master interface 2 */
-	dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,	/* Destination 
DMA master interface 1 */
-	dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2	/* Destination 
DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-
-typedef enum {
-	dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8,	/* 
Source 8 bit  (1 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,	/* 
Source 16 bit (2 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,	/* 
Source 32 bit (4 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,	/* 
Source 64 bit (8 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8,	/* 
Destination 8 bit  (1 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,	/* 
Destination 16 bit (2 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,	/* 
Destination 32 bit (4 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64	/* 
Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-
-typedef enum {
-	dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,	/* Source No 
burst */
-	dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,	/* Source 4  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,	/* Source 8  X 
dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,	/* Source 16 
X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,	/* Destination 
No burst */
-	dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,	/* Destination 
4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,	/* Destination 
8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16	/* Destination 
16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-
-typedef enum {
-	dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,	/* 
Memory to memory transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, 
/* Peripheral to memory transfer */
-	dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, 
/* Memory to peripheral transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = 
dmacHw_REG_CTL_TTFC_PP_DMAC	/* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-
-typedef enum {
-	dmacHw_TRANSFER_MODE_PERREQUEST,	/* Block transfer per DMA request */
-	dmacHw_TRANSFER_MODE_CONTINUOUS,	/* Continuous transfer of streaming 
data */
-	dmacHw_TRANSFER_MODE_PERIODIC	/* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-
-typedef enum {
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,	/* 
Increment source address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,	/* 
Decrement source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,	/* 
Increment destination address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,	/* 
Decrement destination address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,	/* No 
change in source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC	/* No 
change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-
-typedef enum {
-	dmacHw_FLOW_CONTROL_DMA,	/* DMA working as flow controller (default) */
-	dmacHw_FLOW_CONTROL_PERIPHERAL	/* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-
-typedef enum {
-	dmacHw_TRANSFER_STATUS_BUSY,	/* DMA Transfer ongoing */
-	dmacHw_TRANSFER_STATUS_DONE,	/* DMA Transfer completed */
-	dmacHw_TRANSFER_STATUS_ERROR	/* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_DISABLE,	/* Interrupt disable  */
-	dmacHw_INTERRUPT_ENABLE	/* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_STATUS_NONE = 0x0,	/* No DMA interrupt */
-	dmacHw_INTERRUPT_STATUS_TRANS = 0x1,	/* End of DMA transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,	/* End of block transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_ERROR = 0x4	/* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,	/* Number of DMA channel */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,	/* Maximum channel 
burst size */
-	dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,	/* Number of DMA master 
interface */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,	/* Channel Data bus width */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE	/* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-
-typedef unsigned long dmacHw_HANDLE_t;	/* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;	/* DMA channel Id.  Must be created using
-				   "dmacHw_MAKE_CHANNEL_ID" macro
-				 */
-/* DMA channel configuration parameters */
-typedef struct {
-	uint32_t srcPeripheralPort;	/* Source peripheral port */
-	uint32_t dstPeripheralPort;	/* Destination peripheral port */
-	uint32_t srcStatusRegisterAddress;	/* Source status register address */
-	uint32_t dstStatusRegisterAddress;	/* Destination status register 
address of type  */
-
-	uint32_t srcGatherWidth;	/* Number of bytes gathered before successive 
gather opearation */
-	uint32_t srcGatherJump;	/* Number of bytes jumpped before successive 
gather opearation */
-	uint32_t dstScatterWidth;	/* Number of bytes sacattered before 
successive scatter opearation */
-	uint32_t dstScatterJump;	/* Number of bytes jumpped  before successive 
scatter opearation */
-	uint32_t maxDataPerBlock;	/* Maximum number of bytes to be transferred 
per block/descrptor.
-					   0 = Maximum possible.
-					 */
-
-	dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate;	/* Source address update mode */
-	dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate;	/* Destination address update 
mode */
-	dmacHw_TRANSFER_TYPE_e transferType;	/* DMA transfer type  */
-	dmacHw_TRANSFER_MODE_e transferMode;	/* DMA transfer mode */
-	dmacHw_MASTER_INTERFACE_e srcMasterInterface;	/* DMA source interface  */
-	dmacHw_MASTER_INTERFACE_e dstMasterInterface;	/* DMA destination 
interface */
-	dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;	/* Source 
transaction width   */
-	dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;	/* Destination 
transaction width */
-	dmacHw_BURST_WIDTH_e srcMaxBurstWidth;	/* Source burst width */
-	dmacHw_BURST_WIDTH_e dstMaxBurstWidth;	/* Destination burst width */
-	dmacHw_INTERRUPT_e blockTransferInterrupt;	/* Block trsnafer interrupt */
-	dmacHw_INTERRUPT_e completeTransferInterrupt;	/* Complete DMA trsnafer 
interrupt */
-	dmacHw_INTERRUPT_e errorInterrupt;	/* Error interrupt */
-	dmacHw_CHANNEL_PRIORITY_e channelPriority;	/* Channel priority */
-	dmacHw_FLOW_CONTROL_e flowControler;	/* Data flow controller */
-} dmacHw_CONFIG_t;
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a 
particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] 
DMA Channel Id */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel 
handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA 
transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN 
] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) 
address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual 
address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of 
pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/*  [ IN ] Number of 
descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel 
handle  */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-			     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			     void *pSrcAddr,	/*  [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*  [ IN ] Destination (Peripheral/Memory) 
address */
-			     size_t dataLen	/*  [ IN ] Length in bytes   */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t 
handle	/*   [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to 
the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] 
Configuration settings */
-				void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				uint32_t ctlAddress,	/*  [ IN ] Address of the device control 
register  */
-				uint32_t control	/*  [ IN ] Device control information */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while 
transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle    */
-			       dmacHw_CONFIG_t *pConfig,	/*  [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			       void **ppBbuf,	/*  [ OUT ] Data received */
-			       size_t *pLlen	/*  [ OUT ] Length of the data received */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as 
a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, 
when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*  [ IN ] 
DMA Channel handle   */
-				     dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-				     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				     uint32_t srcAddr,	/*  [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*  [ IN ] Function pointer  that 
provides destination memory */
-				     int len,	/*  [ IN ] Number of bytes "fpAlloc" will allocate 
for destination */
-				     int num	/*  [ IN ] Number of descriptor to set */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this 
function
-*     - This function should also be called from ISR to program the 
channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA 
Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] 
Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this 
function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel 
handle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] 
DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed 
successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination 
address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration 
settings */
-		   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-		   void (*fpFree) (void *)	/*  [ IN ] Function pointer to free data 
memory */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of 
interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t 
handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type 
dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after 
calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			       void *userData	/*  [ IN ] User data  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA 
Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control 
parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA 
Channel handle  */
-			   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ 
IN ]  DMA Channel handle  */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller 
attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h 
b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd..0000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h 
b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8..0000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h 
b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5..0000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h 
b/arch/arm/mach-bcmring/include/csp/reg.h
deleted file mode 100644
index 56654d2..0000000
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-
-#ifndef CSP_REG_H
-#define CSP_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-
-/* Macros used to define a sequence of reserved registers. The start / 
end */
-/* are byte offsets in the particular register definition, with the 
"end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / 
sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / 
sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / 
sizeof(uint32_t)]
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-	unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-
-#else
-
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-
-#endif
-
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg &= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg |= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
-				     uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg = (*reg & mask) | value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-	*reg = value;
-}
-
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h 
b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e07..0000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-	secHw_MODE_SECURE = 0x0,	/* Switches processor into secure mode */
-	secHw_MODE_NONSECURE = 0x1	/* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t	/* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE	/* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h 
b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718b..0000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h 
b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e400..0000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h 
b/arch/arm/mach-bcmring/include/csp/tmrHw.h
deleted file mode 100644
index 2cbb530..0000000
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-
-#include <csp/stdint.h>
-
-typedef uint32_t tmrHw_ID_t;	/* Timer ID */
-typedef uint32_t tmrHw_COUNT_t;	/* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;	/* Timer interval */
-typedef uint32_t tmrHw_RATE_t;	/* Timer event (count/interrupt) rate */
-
-typedef enum {
-	tmrHw_INTERRUPT_STATUS_SET,	/* Interrupted  */
-	tmrHw_INTERRUPT_STATUS_UNSET	/* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	tmrHw_CAPABILITY_CLOCK,	/* Clock speed in HHz */
-	tmrHw_CAPABILITY_RESOLUTION	/* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer 
Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific 
number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/* 
  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt 
just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single 
ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/* 
[ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] 
Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer 
id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/* 
  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after 
calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback 
function */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs	/*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d5..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_H
-#define CAP_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Public Constants and Types 
--------------------------------------- */
-typedef enum {
-	CAP_NOT_PRESENT = 0,
-	CAP_PRESENT
-} CAP_RC_T;
-
-typedef enum {
-	CAP_VPM,
-	CAP_ETH_PHY,
-	CAP_ETH_GMII,
-	CAP_ETH_SGMII,
-	CAP_USB,
-	CAP_TSC,
-	CAP_EHSS,
-	CAP_SDIO,
-	CAP_UARTB,
-	CAP_KEYPAD,
-	CAP_CLCD,
-	CAP_GE,
-	CAP_LEDM,
-	CAP_BBL,
-	CAP_VDEC,
-	CAP_PIF,
-	CAP_APM,
-	CAP_SPU,
-	CAP_PKA,
-	CAP_RNG,
-} CAP_CAPABILITY_T;
-
-typedef enum {
-	CAP_LCD_WVGA = 0,
-	CAP_LCD_VGA = 0x1,
-	CAP_LCD_WQVGA = 0x2,
-	CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 933ce68..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <cfg_global.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << 
CAP_CONFIG1_CLCD_RES_SHIFT)
-
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | 
CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS 
| CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | 
CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | 
CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | 
CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | 
CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | 
CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | 
CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | 
CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | 
CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int 
index)
-{
-	CAP_RC_T returnVal = CAP_NOT_PRESENT;
-
-	switch (capability) {
-	case CAP_VPM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_PHY:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_GMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_SGMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_USB:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_TSC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_EHSS:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SDIO:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_UARTB:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_KEYPAD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_CLCD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_GE:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_LEDM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_BBL:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_VDEC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PIF:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_APM:
-		{
-			if ((index == 0)
-			    && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 2)
-			    && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SPU:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PKA:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_RNG:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	default:
-		{
-		}
-		break;
-	}
-	return returnVal;
-}
-
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-	return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-	return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || 
(CFG_GLOBAL_CHIP == FPGA11107))
-	return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) 
|| (CFG_GLOBAL_CHIP == BCM11110))
-	return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-	return (CAP_LCD_RES_T)
-		((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-		 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 1619733..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-
-typedef uint32_t chipcHw_freq;
-
-/* Configurable miscellaneous clocks */
-typedef enum {
-	chipcHw_CLOCK_DDR,	/* DDR PHY Clock */
-	chipcHw_CLOCK_ARM,	/* ARM Clock */
-	chipcHw_CLOCK_ESW,	/* Ethernet Switch Clock */
-	chipcHw_CLOCK_VPM,	/* VPM Clock */
-	chipcHw_CLOCK_ESW125,	/* Ethernet MII Clock */
-	chipcHw_CLOCK_UART,	/* UART Clock */
-	chipcHw_CLOCK_SDIO0,	/* SDIO 0 Clock */
-	chipcHw_CLOCK_SDIO1,	/* SDIO 1 Clock */
-	chipcHw_CLOCK_SPI,	/* SPI Clock */
-	chipcHw_CLOCK_ETM,	/* ARM ETM Clock */
-
-	chipcHw_CLOCK_BUS,	/* BUS Clock */
-	chipcHw_CLOCK_OTP,	/* OTP Clock */
-	chipcHw_CLOCK_I2C,	/* I2C Host Clock */
-	chipcHw_CLOCK_I2S0,	/* I2S 0 Host Clock */
-	chipcHw_CLOCK_RTBUS,	/* DDR PHY Configuration Clock */
-	chipcHw_CLOCK_APM100,	/* APM100 Clock */
-	chipcHw_CLOCK_TSC,	/* Touch screen Clock */
-	chipcHw_CLOCK_LED,	/* LED Clock */
-
-	chipcHw_CLOCK_USB,	/* USB Clock */
-	chipcHw_CLOCK_LCD,	/* LCD CLock */
-	chipcHw_CLOCK_APM,	/* APM Clock */
-
-	chipcHw_CLOCK_I2S1,	/* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-
-/* System booting strap options */
-typedef enum {
-	chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-	chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-	    chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-	chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-
-/* System booting modes */
-typedef enum {
-	chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-	chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-	chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-	chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-
-/* NAND Flash page size strap options */
-typedef enum {
-	chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-	chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-	chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-	chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-
-/* GPIO Pin function */
-typedef enum {
-	chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-	chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-	chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-	chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-	chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-	chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-	chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-	chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-	chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-	chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-	chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-	chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-	chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-	chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-
-/* PIN Output slew rate */
-typedef enum {
-	chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-	chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-
-/* PIN Current drive strength */
-typedef enum {
-	chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-	chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-	chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-	chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-	chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-	chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-
-/* PIN Pull up register settings */
-typedef enum {
-	chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-	chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-	chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-
-/* PIN input type settings */
-typedef enum {
-	chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-	chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-	chipcHw_SPREAD_SPECTRUM_DISALLOW,	/* Spread spectrum support is not 
allowed */
-	chipcHw_SPREAD_SPECTRUM_ALLOW	/* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-
-typedef struct {
-	chipcHw_SPREAD_SPECTRUM_e ssSupport;	/* Allow/Disalow to support 
spread spectrum.
-						   If supported, call chipcHw_enableSpreadSpectrum ()
-						   to activate the spread spectrum with desired spread. */
-	uint32_t pllVcoFreqHz;	/* PLL VCO frequency in Hz */
-	uint32_t pll2VcoFreqHz;	/* PLL2 VCO frequency in Hz */
-	uint32_t busClockFreqHz;	/* Bus clock frequency in Hz */
-	uint32_t armBusRatio;	/* ARM clock : Bus clock */
-	uint32_t vpmBusRatio;	/* VPM clock : Bus clock */
-	uint32_t ddrBusRatio;	/* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-
-/* CHIP revision number */
-typedef enum {
-	chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-	chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-	chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-	chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-	chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-
-typedef enum {
-	chipcHw_DDR_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for DDR phase 
align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_WIDE	/*  Wider margin for DDR phase align 
condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for VPM phase 
align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_WIDE	/*  Wider margin for VPM phase align 
condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-
-#define chipcHw_XTAL_FREQ_Hz                    25000000	/* Reference 
clock frequency in Hz */
-
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < 
(chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-									     /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 
0)	/* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 
1)	/* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 
2)	/* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 
3)	/* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 
4)	/* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 
5)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 
6)	/* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 
7)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 
8)	/* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 
9)	/* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 
10)	/* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 
11)	/* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 
12)	/* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 
13)	/* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 
14)	/* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 
15)	/* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 
16)	/* UART Receive */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip 
initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,	/*  [ IN ] VCO frequency in 
Hz */
-			chipcHw_SPREAD_SPECTRUM_e ssSupport	/*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz	/*  [ IN ] VCO frequency in 
Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] 
Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN 
] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock	/*  [ 
IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock	/* 
[ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock	/* 
  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask	/*  [ 
IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask	/*  [ IN ] 
Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetDisable(uint64_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetEnable(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask	/*  [ IN ] Bit map 
of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlDisable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlEnable(uint32_t mask	/*  [ IN ] 
Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_OTP_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask	/*  [ IN ] Bit 
map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int 
pin	/* GPIO Pin number */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,	/* GPIO Pin 
number */
-					      chipcHw_GPIO_FUNCTION_e func	/* Configuration function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					  chipcHw_PIN_SLEW_RATE_e slewRate	/* Pin slew rate */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,	/* Pin of 
type chipcHw_PIN_XXXXX */
-					       chipcHw_PIN_CURRENT_STRENGTH_e curr	/* Pin current rating */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					chipcHw_PIN_PULL_e pullup	/* Pullup register settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,	/* Pin of type 
chipcHw_PIN_XXXXX */
-					   chipcHw_PIN_INPUTTYPE_e inputType	/* Pin input type */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t 
vpmRatio,
-			   uint32_t ddrRatio);
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin	/* 
Margin alinging DDR  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void 
chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin	/* 
Margin alinging VPM  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle	/* 
Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-
-/* ---- Private Constants and Types 
-------------------------------------- */
-
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index 03238c2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-
-/* ---- Include Files 
----------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-
-/* ---- Private Constants and Types 
--------------------------------------- */
-typedef enum {
-	chipcHw_OPTYPE_BYPASS,	/* Bypass operation */
-	chipcHw_OPTYPE_OUTPUT	/* Output operation */
-} chipcHw_OPTYPE_e;
-
-/* ---- Public Constants and Types 
---------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------- */
-/* ---- Public Function Prototypes 
---------------------------------------- */
-/* ---- Private Function Prototypes 
--------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode);
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-	return pChipcHw->ChipId;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-	if ((pChipcHw->
-	     PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-	    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-		    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-		    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-		     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-		    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-	ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-	return (pChipcHw->
-		 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
-		chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-	return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-	return pChipcHw->BusIntfClock;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-	chipcHw_softResetEnable(mask);
-	chipcHw_softResetDisable(mask);
-}
-
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	/* Deassert module soft reset */
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 ^= ctrl1;
-	pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-	uint32_t unhold = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 |= ctrl1;
-	/* Mask out unhold request bits */
-	pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-
-	/* Process unhold requests */
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-		unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-	}
-
-	if (unhold) {
-		/* Make sure unhold request is effective */
-		pChipcHw->SoftReset1 &= ~unhold;
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-	reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-	reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-	return pChipcHw->Sticky;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask & chipcHw_REG_STICKY_POR_BROM) {
-		bits |= chipcHw_REG_STICKY_POR_BROM;
-	} else {
-		uint32_t sticky;
-		sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-			bits |= chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask &
-	    (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-	     chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-	     chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-		uint32_t sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-			bits = chipcHw_REG_STICKY_BOOT_DONE;
-			mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits | mask;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-	return pChipcHw->SoftStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-	reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-	return pChipcHw->PinStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-	uint32_t softStraps;
-
-	/*
-	 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-	 ** which copies HW straps to soft straps if there is no override
-	 */
-	softStraps = chipcHw_getSoftStraps();
-
-	return softStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to 
soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-	uint32_t softStraps;
-
-	REG_LOCAL_IRQ_SAVE;
-	softStraps = chipcHw_getSoftStraps();
-
-	if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-		/* Copy HW straps to software straps */
-		chipcHw_setSoftStraps(chipcHw_getPinStraps());
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-	if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF 
operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for 
GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-	return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
-		(chipcHw_REG_GPIO_MUX_MASK <<
-		 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
-	    chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-					      chipcHw_GPIO_FUNCTION_e func)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-	    ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-	    func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-					  chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-	    ~(chipcHw_REG_SLEW_RATE_MASK <<
-	      chipcHw_REG_SLEW_RATE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-	    (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define 
this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-					       chipcHw_PIN_CURRENT_STRENGTH_e
-					       curr)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-	    ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-	    (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, 
chipcHw_PIN_PULL_e pullup)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-	    ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-	    (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-					   chipcHw_PIN_INPUTTYPE_e inputType)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-	    ~(chipcHw_REG_INPUTTYPE_MASK <<
-	      chipcHw_REG_INPUTTYPE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-	    (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain 
device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode)
-{
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			/* PLL clock output enable/disable */
-			if (mode) {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock enable is inverted */
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			} else {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock disable is inverted */
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			/* PLL clock bypass enable/disable */
-			if (mode) {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	} else if (pClockCtrl) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-
-	/* Disable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-
-	/* Enable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-	/* Enable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-	/* Disable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-
-}
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-	return pChipcHw->SoftStraps & 0x00000001;
-}
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-	reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-	reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig2,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig2,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-	return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-	return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig2 |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-	REG_LOCAL_IRQ_SAVE;
-	if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	} else {
-		pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	}
-	pChipcHw->VPMPhaseCtrl2 =
-	    (pChipcHw->
-	     VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-			       chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->DDRPhaseCtrl1 &=
-		    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->DDRPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMPhaseCtrl1 &=
-		    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->VPMPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &=
-	    ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->DDRPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &=
-	    ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->VPMPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_ddrHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_vpmHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index b162448..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-
-typedef struct {
-	uint32_t ChipId;	/* Chip ID */
-	uint32_t DDRClock;	/* PLL1 Channel 1 for DDR clock */
-	uint32_t ARMClock;	/* PLL1 Channel 2 for ARM clock */
-	uint32_t ESWClock;	/* PLL1 Channel 3 for ESW system clock */
-	uint32_t VPMClock;	/* PLL1 Channel 4 for VPM clock */
-	uint32_t ESW125Clock;	/* PLL1 Channel 5 for ESW 125MHz clock */
-	uint32_t UARTClock;	/* PLL1 Channel 6 for UART clock */
-	uint32_t SDIO0Clock;	/* PLL1 Channel 7 for SDIO 0 clock */
-	uint32_t SDIO1Clock;	/* PLL1 Channel 8 for SDIO 1 clock */
-	uint32_t SPIClock;	/* PLL1 Channel 9 for SPI master Clock  */
-	uint32_t ETMClock;	/* PLL1 Channel 10 for ARM ETM Clock  */
-
-	uint32_t ACLKClock;	/* ACLK Clock (Divider) */
-	uint32_t OTPClock;	/* OTP Clock  (Divider) */
-	uint32_t I2CClock;	/* I2C Clock (CK_13m) (Divider) */
-	uint32_t I2S0Clock;	/* I2S0 Clock (Divider) */
-	uint32_t RTBUSClock;	/* RTBUS (DDR PHY Config.) Clock (Divider) */
-	uint32_t pad1;
-	uint32_t APM100Clock;	/* APM 100MHz CLK Clock (Divider) */
-	uint32_t TSCClock;	/* TSC Clock (Divider) */
-	uint32_t LEDClock;	/* LED Clock (Divider) */
-
-	uint32_t USBClock;	/* PLL2 Channel 1 for USB clock */
-	uint32_t LCDClock;	/* PLL2 Channel 2 for LCD clock */
-	uint32_t APMClock;	/* PLL2 Channel 3 for APM 200 MHz clock */
-
-	uint32_t BusIntfClock;	/* Bus interface clock */
-
-	uint32_t PLLStatus;	/* PLL status register (PLL1) */
-	uint32_t PLLConfig;	/* PLL configuration register  (PLL1) */
-	uint32_t PLLPreDivider;	/* PLL pre-divider control register (PLL1) */
-	uint32_t PLLDivider;	/* PLL divider control register (PLL1) */
-	uint32_t PLLControl1;	/* PLL analog control register #1 (PLL1) */
-	uint32_t PLLControl2;	/* PLL analog control register #2 (PLL1) */
-
-	uint32_t I2S1Clock;	/* I2S1 Clock  */
-	uint32_t AudioEnable;	/* Enable/ disable audio channel */
-	uint32_t SoftReset1;	/* Reset blocks */
-	uint32_t SoftReset2;	/* Reset blocks */
-	uint32_t Spare1;	/* Phase align interrupts */
-	uint32_t Sticky;	/* Sticky bits */
-	uint32_t MiscCtrl;	/* Misc. control */
-	uint32_t pad3[3];
-
-	uint32_t PLLStatus2;	/* PLL status register (PLL2) */
-	uint32_t PLLConfig2;	/* PLL configuration register  (PLL2) */
-	uint32_t PLLPreDivider2;	/* PLL pre-divider control register (PLL2) */
-	uint32_t PLLDivider2;	/* PLL divider control register (PLL2) */
-	uint32_t PLLControl12;	/* PLL analog control register #1 (PLL2) */
-	uint32_t PLLControl22;	/* PLL analog control register #2 (PLL2) */
-
-	uint32_t DDRPhaseCtrl1;	/* DDR Clock Phase Alignment control1 */
-	uint32_t VPMPhaseCtrl1;	/* VPM Clock Phase Alignment control1 */
-	uint32_t PhaseAlignStatus;	/* DDR/VPM Clock Phase Alignment Status */
-	uint32_t PhaseCtrlStatus;	/* DDR/VPM Clock HW DDR/VPM ph_ctrl and 
load_ch Status */
-	uint32_t DDRPhaseCtrl2;	/* DDR Clock Phase Alignment control2 */
-	uint32_t VPMPhaseCtrl2;	/* VPM Clock Phase Alignment control2 */
-	uint32_t pad4[9];
-
-	uint32_t SoftOTP1;	/* Software OTP control */
-	uint32_t SoftOTP2;	/* Software OTP control */
-	uint32_t SoftStraps;	/* Software strap */
-	uint32_t PinStraps;	/* Pin Straps */
-	uint32_t DiffOscCtrl;	/* Diff oscillator control */
-	uint32_t DiagsCtrl;	/* Diagnostic control */
-	uint32_t DiagsOutputCtrl;	/* Diagnostic output enable */
-	uint32_t DiagsReadBackCtrl;	/* Diagnostic read back control */
-
-	uint32_t LcdPifMode;	/* LCD/PIF Pin Sharing MUX Mode */
-
-	uint32_t GpioMux_0_7;	/* Pin Sharing MUX0 Control */
-	uint32_t GpioMux_8_15;	/* Pin Sharing MUX1 Control */
-	uint32_t GpioMux_16_23;	/* Pin Sharing MUX2 Control */
-	uint32_t GpioMux_24_31;	/* Pin Sharing MUX3 Control */
-	uint32_t GpioMux_32_39;	/* Pin Sharing MUX4 Control */
-	uint32_t GpioMux_40_47;	/* Pin Sharing MUX5 Control */
-	uint32_t GpioMux_48_55;	/* Pin Sharing MUX6 Control */
-	uint32_t GpioMux_56_63;	/* Pin Sharing MUX7 Control */
-
-	uint32_t GpioSR_0_7;	/* Slew rate for GPIO 0 - 7 */
-	uint32_t GpioSR_8_15;	/* Slew rate for GPIO 8 - 15 */
-	uint32_t GpioSR_16_23;	/* Slew rate for GPIO 16 - 23 */
-	uint32_t GpioSR_24_31;	/* Slew rate for GPIO 24 - 31 */
-	uint32_t GpioSR_32_39;	/* Slew rate for GPIO 32 - 39 */
-	uint32_t GpioSR_40_47;	/* Slew rate for GPIO 40 - 47 */
-	uint32_t GpioSR_48_55;	/* Slew rate for GPIO 48 - 55 */
-	uint32_t GpioSR_56_63;	/* Slew rate for GPIO 56 - 63 */
-	uint32_t MiscSR_0_7;	/* Slew rate for MISC 0 - 7 */
-	uint32_t MiscSR_8_15;	/* Slew rate for MISC 8 - 15 */
-
-	uint32_t GpioPull_0_15;	/* Pull up registers for GPIO 0 - 15 */
-	uint32_t GpioPull_16_31;	/* Pull up registers for GPIO 16 - 31 */
-	uint32_t GpioPull_32_47;	/* Pull up registers for GPIO 32 - 47 */
-	uint32_t GpioPull_48_63;	/* Pull up registers for GPIO 48 - 63 */
-	uint32_t MiscPull_0_15;	/* Pull up registers for MISC 0 - 15 */
-
-	uint32_t GpioInput_0_31;	/* Input type for GPIO 0 - 31 */
-	uint32_t GpioInput_32_63;	/* Input type for GPIO 32 - 63 */
-	uint32_t MiscInput_0_15;	/* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
-
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000	/* 
Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001	/* 
PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008	/* 
Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004	/* 
Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020	/* 
Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010	/* 
Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001	/* 
Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000	/* 
1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000	/* 
VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080	/* 
VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000	/* 
PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000	/* 
Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000	/* 
Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000	/* 
Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000	/* 
PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000	/* 
Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000	/* 
Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000	/* 
Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8	/* Number of 
bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00	/* 
Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF	/* 
Clock post divider mask
-
-									   00000000 = divide-by-256
-									   00000001 = divide-by-1
-									   00000010 = divide-by-2
-									   00000011 = divide-by-3
-									   00000100 = divide-by-4
-									   00000101 = divide-by-5
-									   00000110 = divide-by-6
-									   .
-									   .
-									   11111011 = divide-by-251
-									   11111100 = divide-by-252
-									   11111101 = divide-by-253
-									   11111110 = divide-by-254
-									 */
-
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000	/* 
NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000	/* 
NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000	/* 
NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF	/* 
NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000	/* 
NON-PLL clock post-divide by 256 */
-
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000	/* 
Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000	/* 
Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000	/* 
MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000	/* 
MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000	/* 
MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000	/* 
MFB Sigma-Delta Modulator 1/8 Mode */
-
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / 
chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF	/* 
Fractional divider */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)	/* 
To attain spread with max frequency */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0	/* ndiv_frac 
= chipcHw_REG_PLL_DIVIDER_NDIV_f /
-								   chipcHw_REG_PLL_DIVIDER_FRAC
-								   = 0, when SS is disable
-								 */
-
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) 
((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001	/* 
Software Strap Override */
-
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000	/* 8 
bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002	/* 
16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004	/* 
Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006	/* 
16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008	/* 
UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E	/* 
Mask */
-
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000	/* 
Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020	/* 
Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030	/* 
Boot from NOR flash */
-
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000	/* 
NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040	/* 
NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080	/* 
NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0	/* 
NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0	/* 
Mask */
-
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400	/* 
NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800	/* 
Reboot to UART on error */
-
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000	/* 
Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100	/* 
Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200	/* 
Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300	/* 
Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300	/* 
Mask */
-
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000	/* 
I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000	/* 
SPI Slave  */
-
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS 
((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001	/* 
LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002	/* 
LCD pins are used to perform PIF functions  */
-
-#define chipcHw_GPIO_COUNT                              61	/* Number of 
GPIO pin accessible thorugh CHIPC */
-
-/* NOTE: Any changes to these constants will require a corresponding 
change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001	/* 
GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002	/* 
GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003	/* 
GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004	/* 
GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005	/* 
GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006	/* 
GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007	/* 
GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008	/* 
GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009	/* 
GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A	/* 
GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B	/* 
GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C	/* 
GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D	/* 
GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000	/* 
GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin) 
(&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 
0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F	/* 
Mask */
-
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000	/* 
High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008	/* 
Normal slew rate */
-							/* Pins beyond 42 are defined by skipping 8 bits within the 
register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008	/* 
Mask */
-
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001	/* 
Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002	/* 
Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004	/* 
Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005	/* 
Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006	/* 
Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007	/* 
Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? 
(&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + 
((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? 
((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-
-#define chipcHw_REG_PULL_NONE                           0x00000000	/* 
No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001	/* 
Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002	/* 
Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? 
(&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : 
(&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? 
((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000	/* 
Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001	/* 
High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001	/* 
Mask */
-							/* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? 
(&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : 
(&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? 
((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001	/* 
Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002	/* 
Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004	/* 
Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008	/* 
Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010	/* 
Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020	/* 
Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040	/* 
Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080	/* 
Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100	/* 
Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200	/* 
Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400	/* 
Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800	/* 
Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000	/* 
Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000	/* 
Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000	/* 
Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000	/* 
Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000	/* 
Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000	/* 
Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000	/* 
Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000	/* 
Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000	/* 
Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000	/* 
Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000	/* 
Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000	/* 
Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000	/* 
Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000	/* 
Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000	/* 
Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000	/* 
Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000	/* 
Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000	/* 
Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000	/* 
Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000	/* 
Bus interface clock for Touch screen */
-
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 
0x0000000080000000ULL	/* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD 
0x0000000040000000ULL	/* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 
0x0000000020000000ULL	/* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM 
0x0000000010000000ULL	/* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD 
0x0000000008000000ULL	/* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED 
0x0000000004000000ULL	/* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU 
0x0000000002000000ULL	/* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG 
0x0000000001000000ULL	/* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA 
0x0000000000800000ULL	/* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD 
0x0000000000400000ULL	/* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF 
0x0000000000200000ULL	/* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS 
0x0000000000100000ULL	/* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH 
0x0000000000080000ULL	/* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1 
0x0000000000040000ULL	/* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0 
0x0000000000020000ULL	/* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL 
0x0000000000010000ULL	/* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1 
0x0000000000008000ULL	/* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0 
0x0000000000004000ULL	/* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS 
0x0000000000002000ULL	/* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH 
0x0000000000001000ULL	/* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1 
0x0000000000000800ULL	/* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0 
0x0000000000000400ULL	/* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1 
0x0000000000000200ULL	/* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0 
0x0000000000000100ULL	/* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI 
0x0000000000000080ULL	/* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG 
0x0000000000000040ULL	/* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR 
0x0000000000000020ULL	/* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM 
0x0000000000000010ULL	/* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD 
0x0000000000000008ULL	/* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM 
0x0000000000000004ULL	/* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM 
0x0000000000000002ULL	/* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT 
0x0000000000000001ULL	/* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC 
0x0000100000000000ULL	/* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE 
0x0000080000000000ULL	/* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP 
0x0000040000000000ULL	/* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2 
0x0000020000000000ULL	/* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1 
0x0000010000000000ULL	/* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB 
0x0000008000000000ULL	/* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW 
0x0000004000000000ULL	/* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK 
0x0000002000000000ULL	/* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY 
0x0000001000000000ULL	/* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR 
0x0000000800000000ULL	/* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC 
0x0000000400000000ULL	/* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM 
0x0000000200000000ULL	/* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM 
0x0000200100000000ULL	/* Reset APM device */
-
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 
0x8000000000000000ULL	/* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 
0x4000000000000000ULL	/* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 
0x2000000000000000ULL	/* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 
0xF000000000000000ULL	/* Mask to handle unhold request */
-
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001	/* 
Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002	/* 
Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004	/* 
Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008	/* 
Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010	/* 
Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020	/* 
Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040	/* 
Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080	/* 
Enable APM clock */
-
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000	/* 
Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000	/* 
Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000	/* 
Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000	/* 
Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000	/* 
Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008	/* 
Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004	/* 
Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002	/* 
Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD	/* 
Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE	/* 
Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001	/* 
Power down USB */
-
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF 
0x0000020000000000ULL	/* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW 
0x0000010000000000ULL	/* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED 
0x0000000600000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1 
0x0000000100000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0 
0x0000000080000000ULL	/* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED 
0x0000000060000000ULL	/* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE 
0x000000001F000000ULL	/* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE 
0x0000000000200000ULL	/* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE 
0x0000000000100000ULL	/* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE 
0x0000000000080000ULL	/* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE 
0x0000000000040000ULL	/* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE 
0x0000000000020000ULL	/* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE 
0x0000000000010000ULL	/* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE 
0x0000000000008000ULL	/* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE 
0x0000000000004000ULL	/* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE 
0x0000000000003000ULL	/* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE 
0x0000000000000C00ULL	/* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE 
0x0000000000000200ULL	/* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE 
0x0000000000000180ULL	/* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE 
0x0000000000000060ULL	/* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE 
0x0000000000000018ULL	/* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE 
0x0000000000000006ULL	/* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE 
0x0000000000000001ULL	/* Disable VPM */
-
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001	/* 
Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002	/* 
ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004	/* 
General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008	/* 
General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010	/* 
General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020	/* 
General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040	/* 
General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080	/* 
Special sticky bit for security - set in BROM to avoid other modes being 
entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100	/* 
ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200	/* 
Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400	/* 
Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800	/* 
Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000	/* 
OTP reset */
-
-							/* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000	/* 
Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000	/* 
Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002	/* 
Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001	/* 
Enable access to DDR using system BUS */
-							/* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F	/* 
DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F	/* 
DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000	/* 
Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000	/* 
Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F	/* 
VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F	/* 
VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* 
BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000	/* 
DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F	/* 
DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000	/* 
DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000	/* 
Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F	/* 
DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000	/* 
VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F	/* 
VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080	/* 
VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040	/* 
Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F	/* 
VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-							/* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-							/* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003	/* 
Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << 
chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000	/* 
Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000	/* 
Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* 
Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* 
Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* 
Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h 
b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index f1b68e2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <csp/reg.h>
-#include <csp/stdint.h>
-
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t memcStatus;
-		uint32_t memcCmd;
-		uint32_t directCmd;
-		uint32_t memoryCfg;
-		uint32_t refreshPrd;
-		uint32_t casLatency;
-		uint32_t writeLatency;
-		uint32_t tMrd;
-		uint32_t tRas;
-		uint32_t tRc;
-		uint32_t tRcd;
-		uint32_t tRfc;
-		uint32_t tRp;
-		uint32_t tRrd;
-		uint32_t tWr;
-		uint32_t tWtr;
-		uint32_t tXp;
-		uint32_t tXsr;
-		uint32_t tEsr;
-		uint32_t memoryCfg2;
-		uint32_t memoryCfg3;
-		uint32_t tFaw;
-	} ddrcReg_CTLR_MEMC_REG_t;
-
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile 
ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_MEMC_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << 
ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << 
ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)	/* 
@note Not supported in PL341 */
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << 
ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << 
ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << 
ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << 
ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << 
ddrcReg_CTLR_T_MRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << 
ddrcReg_CTLR_T_RAS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << 
ddrcReg_CTLR_T_RC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << 
ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << 
ddrcReg_CTLR_T_RCD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << 
ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << 
ddrcReg_CTLR_T_RFC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << 
ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << 
ddrcReg_CTLR_T_RP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << 
ddrcReg_CTLR_T_RRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << 
ddrcReg_CTLR_T_WR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << 
ddrcReg_CTLR_T_WTR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << 
ddrcReg_CTLR_T_XP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << 
ddrcReg_CTLR_T_XSR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << 
ddrcReg_CTLR_T_ESR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << 
ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << 
ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << 
ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX 
(ddrcReg_CTLR_QOS_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-	} ddrcReg_CTLR_QOS_REG_t;
-
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile 
ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << 
ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << 
ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX 
(ddrcReg_CTLR_CHIP_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-	} ddrcReg_CTLR_CHIP_REG_t;
-
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile 
ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << 
ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-
-	typedef struct {
-		uint32_t input;
-		uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-		uint32_t feature;
-	} ddrcReg_CTLR_USER_REG_t;
-
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile 
ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << 
ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << 
ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t pmCtl;
-		 REG32_RSVD(0x0008, 0x0010);
-		uint32_t pllStatus;
-		uint32_t pllCfg;
-		uint32_t pllPreDiv;
-		uint32_t pllDiv;
-		uint32_t pllCtl1;
-		uint32_t pllCtl2;
-		uint32_t ssCtl;
-		uint32_t ssCfg;
-		uint32_t vdlStatic;
-		uint32_t vdlDynamic;
-		uint32_t padIdle;
-		uint32_t pvtComp;
-		uint32_t padDrive;
-		uint32_t clkRgltrCtl;
-	} ddrcReg_PHY_ADDR_CTL_REG_t;
-
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile 
ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-
-/* @todo These SS definitions are duplicates of ones below */
-
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10	/* Higher 
the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << 
ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << 
ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << 
ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << 
ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << 
ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << 
ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX 
(ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t vdlCalibrate;
-		uint32_t vdlStatus;
-		 REG32_RSVD(0x000c, 0x0010);
-		uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-		uint32_t readCtl;
-		uint32_t readStatus;
-		uint32_t readClear;
-		uint32_t padIdleCtl;
-		uint32_t padDriveCtl;
-		uint32_t padClkCtl;
-		uint32_t writeCtl;
-		uint32_t clkRegCtl;
-	} ddrcReg_PHY_BYTE_LANE_REG_t;
-
-/* There are 2 instances of the byte Lane registers, one for each byte 
lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile 
ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << 
ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-
-/* ----------------------------------------------------- */
-
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step 
value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 
in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some 
definitions for just */
-/* the step setting to simplify things. */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << 
ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << 
ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << 
ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << 
ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u 
<< 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 
<< 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 
<< 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 
<< 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 
<< 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 
<< 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 
<< 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 
<< 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 
<< 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 
<< 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 
<< 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 
<< 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 
<< 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 
<< 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 
<< 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 
<< 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 
<< 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 
<< 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 
<< 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 
<< 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 
<< 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 
<< 0)
-
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-
-	typedef struct {
-		uint32_t cfg;
-		uint32_t actMonCnt;
-		uint32_t ctl;
-		uint32_t lbistCtl;
-		uint32_t lbistSeed;
-		uint32_t lbistStatus;
-		uint32_t tieOff;
-		uint32_t actMonClear;
-		uint32_t status;
-		uint32_t user;
-	} ddrcReg_CTLR_PHY_GLUE_REG_t;
-
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP 
((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + 
ddrcReg_CTLR_PHY_GLUE_OFFSET))
-
-/* ----------------------------------------------------- */
-
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << 
ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED 
ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED 
ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-
-/* Software control of PHY VDL updates from control register settings. 
Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a 
refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control 
must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-
-/* Use these to bypass a pipeline stage. By default the ADDR is off but 
the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE 
(1 << 12)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define 
ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << 
ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << 
ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f 
<< ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#ifdef __cplusplus
-}				/* end extern "C" */
-#endif
-#endif				/* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index d67e2f8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-
-#include <csp/stdint.h>
-
-/* Data type for DMA Link List Item */
-typedef struct {
-	uint32_t sar;		/* Source Address Register.
-				   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-	uint32_t dar;		/* Destination Address Register.
-				   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-	uint32_t llpPhy;	/* LLP contains the physical address of the next 
descriptor for block chaining using linked lists.
-				   Address MUST be aligned to a 32-bit boundary.             */
-	dmacHw_REG64_t ctl;	/* Control Register. 64 bits */
-	uint32_t sstat;		/* Source Status Register */
-	uint32_t dstat;		/* Destination Status Register */
-	uint32_t devCtl;	/* Device specific control information */
-	uint32_t llp;		/* LLP contains the virtual address of the next 
descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-	int num;		/* Number of link items */
-	dmacHw_DESC_t *pHead;	/* Head of descriptor ring (for writing) */
-	dmacHw_DESC_t *pTail;	/* Tail of descriptor ring (for reading) */
-	dmacHw_DESC_t *pProg;	/* Descriptor to program the channel (for 
programming the channel register) */
-	dmacHw_DESC_t *pEnd;	/* End of current descriptor chain */
-	dmacHw_DESC_t *pFree;	/* Descriptor to free memory (freeing dynamic 
memory) */
-	uint32_t virt2PhyOffset;	/* Virtual to physical address offset for the 
descriptor ring */
-} dmacHw_DESC_RING_t;
-
-/*
- *  DMA channel control block
- */
-typedef struct {
-	uint32_t module;	/* DMA controller module (0-1) */
-	uint32_t channel;	/* DMA channel (0-7) */
-	volatile uint32_t varDataStarted;	/* Flag indicating variable data 
channel is enabled */
-	volatile uint32_t descUpdated;	/* Flag to indicate descriptor update 
is complete */
-	void *userData;		/* Channel specifc user data */
-} dmacHw_CBLK_t;
-
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t 
*)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) == 
dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == 
dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e 
dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw	/*   [ IN ] Current 
transaction width */
-    ) {
-	if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-	} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-	}
-
-	/* Default return  */
-	return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e 
tw	/*   [ IN ]  Transaction width */
-    ) {
-	int width = 1;
-	switch (tw) {
-	case dmacHw_SRC_TRANSACTION_WIDTH_8:
-		width = 1;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_16:
-	case dmacHw_DST_TRANSACTION_WIDTH_16:
-		width = 2;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_32:
-	case dmacHw_DST_TRANSACTION_WIDTH_32:
-		width = 4;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_64:
-	case dmacHw_DST_TRANSACTION_WIDTH_64:
-		width = 8;
-		break;
-	default:
-		dmacHw_ASSERT(0);
-	}
-
-	/* Default transaction width */
-	return width;
-}
-
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index f1ecf96..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-
-/* Data type for 64 bit little endian register */
-typedef struct {
-	volatile uint32_t lo;	/* Lower 32 bit in little endian mode */
-	volatile uint32_t hi;	/* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-
-/* Data type representing DMA channel registers */
-typedef struct {
-	dmacHw_REG64_t ChannelSar;	/*  Source Address Register. 64 bits (upper 
32 bits are reserved)
-					   Address must be aligned to CTLx.SRC_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelDar;	/*  Destination Address Register.64 bits 
(upper 32 bits are reserved)
-					   Address must be aligned to CTLx.DST_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelLlp;	/*  Link List Pointer.64 bits (upper 32 
bits are reserved)
-					   LLP contains the pointer to the next LLI for block chaining 
using linked lists.
-					   If LLPis set to 0x0, then transfers using linked lists are not 
enabled.
-					   Address MUST be aligned to a 32-bit boundary.
-					 */
-	dmacHw_REG64_t ChannelCtl;	/* Control Register. 64 bits */
-	dmacHw_REG64_t ChannelSstat;	/* Source Status Register */
-	dmacHw_REG64_t ChannelDstat;	/* Destination Status Register */
-	dmacHw_REG64_t ChannelSstatAddr;	/* Source Status Address Register */
-	dmacHw_REG64_t ChannelDstatAddr;	/* Destination Status Address Register */
-	dmacHw_REG64_t ChannelConfig;	/* Channel Configuration Register */
-	dmacHw_REG64_t SrcGather;	/* Source gather register */
-	dmacHw_REG64_t DstScatter;	/* Destination scatter register */
-} dmacHw_CH_REG_t;
-
-/* Data type for RAW interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t RawTfr;	/* Raw Status for IntTfr Interrupt */
-	dmacHw_REG64_t RawBlock;	/* Raw Status for IntBlock Interrupt */
-	dmacHw_REG64_t RawSrcTran;	/* Raw Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t RawDstTran;	/* Raw Status for IntDstTran Interrupt */
-	dmacHw_REG64_t RawErr;	/* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-
-/* Data type for interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t StatusTfr;	/* Status for IntTfr Interrupt */
-	dmacHw_REG64_t StatusBlock;	/* Status for IntBlock Interrupt */
-	dmacHw_REG64_t StatusSrcTran;	/* Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t StatusDstTran;	/* Status for IntDstTran Interrupt */
-	dmacHw_REG64_t StatusErr;	/* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-
-/* Data type for interrupt mask registers*/
-typedef struct {
-	dmacHw_REG64_t MaskTfr;	/* Mask for IntTfr Interrupt */
-	dmacHw_REG64_t MaskBlock;	/* Mask for IntBlock Interrupt */
-	dmacHw_REG64_t MaskSrcTran;	/* Mask for IntSrcTran Interrupt */
-	dmacHw_REG64_t MaskDstTran;	/* Mask for IntDstTran Interrupt */
-	dmacHw_REG64_t MaskErr;	/* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-
-/* Data type for interrupt clear registers */
-typedef struct {
-	dmacHw_REG64_t ClearTfr;	/* Clear for IntTfr Interrupt */
-	dmacHw_REG64_t ClearBlock;	/* Clear for IntBlock Interrupt */
-	dmacHw_REG64_t ClearSrcTran;	/* Clear for IntSrcTran Interrupt */
-	dmacHw_REG64_t ClearDstTran;	/* Clear for IntDstTran Interrupt */
-	dmacHw_REG64_t ClearErr;	/* Clear for IntErr Interrupt */
-	dmacHw_REG64_t StatusInt;	/* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-
-/* Data type for software handshaking registers */
-typedef struct {
-	dmacHw_REG64_t ReqSrcReg;	/* Source Software Transaction Request 
Register */
-	dmacHw_REG64_t ReqDstReg;	/* Destination Software Transaction Request 
Register */
-	dmacHw_REG64_t SglReqSrcReg;	/* Single Source Transaction Request 
Register */
-	dmacHw_REG64_t SglReqDstReg;	/* Single Destination Transaction Request 
Register */
-	dmacHw_REG64_t LstSrcReg;	/* Last Source Transaction Request Register */
-	dmacHw_REG64_t LstDstReg;	/* Last Destination Transaction Request 
Register */
-} dmacHw_SW_HANDSHAKE_t;
-
-/* Data type for misc. registers */
-typedef struct {
-	dmacHw_REG64_t DmaCfgReg;	/* DMA Configuration Register */
-	dmacHw_REG64_t ChEnReg;	/* DMA Channel Enable Register */
-	dmacHw_REG64_t DmaIdReg;	/* DMA ID Register */
-	dmacHw_REG64_t DmaTestReg;	/* DMA Test Register */
-	dmacHw_REG64_t Reserved0;	/* Reserved */
-	dmacHw_REG64_t Reserved1;	/* Reserved */
-	dmacHw_REG64_t CompParm6;	/* Component Parameter 6 */
-	dmacHw_REG64_t CompParm5;	/* Component Parameter 5 */
-	dmacHw_REG64_t CompParm4;	/* Component Parameter 4 */
-	dmacHw_REG64_t CompParm3;	/* Component Parameter 3 */
-	dmacHw_REG64_t CompParm2;	/* Component Parameter 2 */
-	dmacHw_REG64_t CompParm1;	/* Component Parameter 1 */
-	dmacHw_REG64_t CompId;	/* Compoent ID */
-} dmacHw_MISC_t;
-
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0	/* 
DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1	/* 
DMAC 1 module's base address */
-
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) 
((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : 
dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char 
*)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : 
dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) 
dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char 
*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t 
*) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char 
*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) 
dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char 
*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t 
*) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char 
*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) 
dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module) 
(((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char 
*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) 
dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-
-#define dmacHw_REG_CTL_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-
-#define dmacHw_REG_SSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-
-#define dmacHw_REG_CFG_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-
-#define dmacHw_REG_SGR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-
-#define dmacHw_REG_DSR_LO(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan) 
(dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel) 
(dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-
-/* Bit mask for REG_DMACx_CTL_LO */
-
-#define dmacHw_REG_CTL_INT_EN                       0x00000001	/* 
Channel interrupt enable */
-
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E	/* 
Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000	/* 
Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002	/* 
Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004	/* 
Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006	/* 
Destination transaction width 64 bit */
-
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070	/* 
Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000	/* 
Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010	/* 
Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020	/* 
Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030	/* 
Source transaction width 64 bit */
-
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000	/* 
Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000	/* 
Source gather enable */
-
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180	/* 
Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000	/* 
Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080	/* 
Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100	/* 
Destination address no change */
-
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600	/* 
Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000	/* 
Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200	/* 
Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400	/* 
Source address no change */
-
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800	/* 
Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000	/* No 
Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800	/* 
Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000	/* 
Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800	/* 
Destination burst transaction length 16 */
-
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000	/* 
Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000	/* No 
Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000	/* 
Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000	/* 
Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000	/* 
Source burst transaction length 16 */
-
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000	/* 
Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000	/* 
Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000	/* 
Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000	/* 
Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000	/* 
Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000	/* 
Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000	/* 
Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000	/* 
Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000	/* 
Peripheral to Peripheral with Destination Peripheral as flow controller */
-
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000	/* 
Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000	/* 
Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000	/* 
Destination AHB master interface 2 */
-
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000	/* 
Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000	/* 
Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000	/* 
Source AHB master interface 2 */
-
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000	/* Block 
chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000	/* Block 
chaining enable for source side */
-
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF	/* Block 
transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000	/* Block 
trasnfer done */
-
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5	/* 
Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0	/* 
Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000	/* 
Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020	/* 
Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040	/* 
Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060	/* 
Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080	/* 
Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0	/* 
Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0	/* 
Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0	/* 
Channel priority 7 */
-
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100	/* 
Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200	/* 
Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400	/* 
Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800	/* 
Source channel SW handshaking */
-
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000	/* 
Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000	/* 
Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000	/* 
Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000	/* 
Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000	/* 
Channel lock enable */
-
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000	/* Bus 
locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000	/* Bus 
lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000	/* Bus 
lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000	/* Bus 
lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000	/* Bus 
lock enable */
-
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000	/* 
Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000	/* 
Source channel handshaking signal polarity low */
-
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000	/* 
Maximum AMBA burst length */
-
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000	/* 
Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000	/* 
Destination address auto reload */
-
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001	/* 
Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002	/* 
Initiate burst transaction when enough data in available in FIFO */
-
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C	/* AHB 
protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004	/* AHB 
protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008	/* AHB 
protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010	/* AHB 
protection 3 */
-
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020	/* 
Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040	/* 
Source status update enable */
-
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780	/* 
Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800	/* 
Destination peripheral hardware interface mask */
-
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700	/* 
Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800	/* 
Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f	/* 
Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000	/* Data 
transfer width */
-
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr) 
(dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr) 
(dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr) 
(dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-
-#define dmacHw_GET_SSTAT(module, channel) 
(dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel) 
(dmacHw_REG_DSTAT((module), (channel)))
-
-#define dmacHw_SET_SSTATAR(module, channel, addr) 
(dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr) 
(dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl) 
(dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel) 
(dmacHw_REG_CTL_LO((module), (channel)))
-
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl) 
(dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)))
-
-#define dmacHw_GET_BLOCK_SIZE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel) 
(dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg) 
(dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel) 
(dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 
20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) 
(dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), 
(channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect) 
(dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg) 
(dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel) 
(dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & 
dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) 
& dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) 
(dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), 
(channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) 
& dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-
-#define dmacHw_DMA_START(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel) 
(dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module) 
(dmacHw_REG_MISC_CFG((module)) = 0)
-
-#define dmacHw_TRAN_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | 
(0x00000001 << (channel)))
-
-#define dmacHw_TRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel) 
(dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-
-#define dmacHw_TRAN_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel) 
(dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-
-#define dmacHw_GET_NUM_CHANNEL(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module) 
(((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & 
dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) 
((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & 
dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h 
b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index cfa91be..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
-
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-
-/* Some items that can be defined externally, but will be set to 
default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS 
is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and 
Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR 
clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-
-#endif /* CSP_HW_CFG_H */
-
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index 0aeb6a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#define INTCHW_NUM_IRQ_PER_INTC   32	/* Maximum number of interrupt 
controllers */
-#define INTCHW_NUM_INTC           3
-
-/* Defines for interrupt controllers. This simplifies and cleans up the 
function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
-
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31	/* Peripheral interface 
interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30	/* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29	/* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28	/* Audio process module 
interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27	/* Ethernet switch 
interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26	/* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25	/* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24	/* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23	/* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22	/* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21	/* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20	/* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19	/* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18	/* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17	/* USB host2/device2 
interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16	/* Voice process module 
interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15	/* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14	/* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13	/* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12	/* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11	/* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10	/* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9	/* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8	/* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7	/* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6	/* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5	/* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4	/* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3	/* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2	/* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1	/* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0	/* DMA0 channel 0 interrupt */
-
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27	/* DDR and VPM PLL clock 
phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26	/* DDR and VPM HW phase 
align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26	/* DDR and PLL clock phase 
relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25	/* Real time clock tamper 
interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24	/* Hantro Video Decoder 
interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits 
in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23	/* Secure process module 
interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22	/* Real time clock 
one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21	/* Real time clock 
periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20	/* Random number generator 
interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19	/* Flash memory parition 
unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18	/* VRAM memory partition 
interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17	/* DDR2 memory partition 
interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16	/* Key pad controller 
interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15	/* Touch screen controller 
interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14	/* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13	/* Watchdog timer interrupt */
-
-#define INTCHW_INTC1_UART1_BITNUM         12	/* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11	/* ARM performance monitor 
interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10	/* ARM DDC receive 
interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9	/* ARM DDC transmit 
interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8	/* Flash controller 
interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7	/* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6	/* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5	/* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4	/* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3	/* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2	/* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1	/* GPIO bit 64//32 
combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0	/* GPIO bit 31//0 combined 
interrupt */
-
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15	/* Real time clock tamper 
interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14	/* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13	/* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12	/* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11	/* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10	/* Secure process module 
interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9	/* Real time clock 
one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8	/* Real time clock 
periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7	/* Random number generator 
interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6	/* Flash memory parition 
unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5	/* VRAM memory partition 
interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4	/* DDR2 memory partition 
interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3	/* Key pad controller 
interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2	/* Touch screen controller 
interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1	/* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0	/* Watchdog timer interrupt */
-
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00	/* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04	/* FIQ status register */
-#define INTCHW_RAWINTR        0x08	/* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c	/* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10	/* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14	/* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18	/* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c	/* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20	/* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24	/* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28	/* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100	/* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200	/* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00	/* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0	/* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0	/* PrimeCell ID Register 0-3 */
-
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENCLEAR) = mask;
-}
-
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENABLE) = mask;
-}
-
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index ad58cf8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-/*  Memory Map address definitions */
-
-#define MM_ADDR_DDR                0x00000000
-
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000	/* 16 MB - Reserved 
external memory for VPM use */
-
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000	/* 64 KB - extra cycle 
latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000	/* 64 KB  - security 
block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h 
b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index de92ec6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_IO_H
-#define _MM_IO_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types 
--------------------------------------- */
-
-#if defined(CONFIG_MMU)
-
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 
0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == 
MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-			(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | 
((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? 
MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-			((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
-#endif
-#endif
-
-#else
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-
-#endif
-
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-
-#define MM_IO_START MM_ADDR_IO_FLASHC	/* Physical beginning of IO 
mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC	/* Virtual beginning of IO mapped 
memory */
-
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-
-#define MM_IO_BASE_VPM_EXTMEM_RSVD 
MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-
-/* ---- Public Variable Externs 
------------------------------------------ */
-/* ---- Public Function Prototypes 
--------------------------------------- */
-
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-
-#include <mach/csp/mm_io.h>
-
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-
-/* Trustzone register set */
-typedef struct {
-	volatile uint32_t status;	/* read only - reflects status of writes of 
2 write registers */
-	volatile uint32_t setUnsecure;	/* write only. reads back as 0 */
-	volatile uint32_t setSecure;	/* write only. reads back as 0 */
-} secHw_TZREG_t;
-
-/* There are 2 register sets. The first is for the lower 16 bits, the 
2nd */
-/* is for the higher 16 bits. */
-
-typedef enum {
-	secHw_IDX_LS = 0,
-	secHw_IDX_MS = 1,
-	secHw_IDX_NUM
-} secHw_IDX_e;
-
-typedef struct {
-	volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-
-#include <mach/csp/secHw_inline.h>
-
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h 
b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 9cd6a03..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-	}
-
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type 
secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
-	}
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 
0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h 
b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-
-/*
-This platform has four different timers running at different clock speed
-
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25	/* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150	/* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)	/* maximum number 
of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)	/* Number of timer module 
supported */
-
-typedef struct {
-	uint32_t LoadValue;	/* Load value for timer */
-	uint32_t CurrentValue;	/* Current value for timer */
-	uint32_t Control;	/* Control register */
-	uint32_t InterruptClear;	/* Interrupt clear register */
-	uint32_t RawInterruptStatus;	/* Raw interrupt status */
-	uint32_t InterruptStatus;	/* Masked interrupt status */
-	uint32_t BackgroundLoad;	/* Background load value */
-	uint32_t padding;	/* Padding register */
-} tmrHw_REG_t;
-
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | 
tmrHw_CONTROL_ONESHOT)
-
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h 
b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 7254378..0000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
-#include <mach/timer.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the 
filename */
-/* and line number of the reservation request will be recorded in the 
channel table */
-
-#define DMA_DEBUG_TRACK_RESERVATION   1
-
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8	/* per controller */
-
-typedef enum {
-	DMA_DEVICE_MEM_TO_MEM,	/* For memory to memory transfers */
-	DMA_DEVICE_I2S0_DEV_TO_MEM,
-	DMA_DEVICE_I2S0_MEM_TO_DEV,
-	DMA_DEVICE_I2S1_DEV_TO_MEM,
-	DMA_DEVICE_I2S1_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,	/* Additional mic input for 
beam-forming */
-	DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-	DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-	DMA_DEVICE_SPUM_DEV_TO_MEM,
-	DMA_DEVICE_SPUM_MEM_TO_DEV,
-	DMA_DEVICE_SPIH_DEV_TO_MEM,
-	DMA_DEVICE_SPIH_MEM_TO_DEV,
-	DMA_DEVICE_UART_A_DEV_TO_MEM,
-	DMA_DEVICE_UART_A_MEM_TO_DEV,
-	DMA_DEVICE_UART_B_DEV_TO_MEM,
-	DMA_DEVICE_UART_B_MEM_TO_DEV,
-	DMA_DEVICE_PIF_MEM_TO_DEV,
-	DMA_DEVICE_PIF_DEV_TO_MEM,
-	DMA_DEVICE_ESW_DEV_TO_MEM,
-	DMA_DEVICE_ESW_MEM_TO_DEV,
-	DMA_DEVICE_VPM_MEM_TO_MEM,
-	DMA_DEVICE_CLCD_MEM_TO_MEM,
-	DMA_DEVICE_NAND_MEM_TO_MEM,
-	DMA_DEVICE_MEM_TO_VRAM,
-	DMA_DEVICE_VRAM_TO_MEM,
-
-	/* Add new entries before this line. */
-
-	DMA_NUM_DEVICE_ENTRIES,
-	DMA_DEVICE_NONE = 0xff,	/* Special value to indicate that no device is 
currently assigned. */
-
-} DMA_Device_t;
-
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-
-typedef int DMA_Handle_t;
-
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-
-typedef struct {
-	void *virtAddr;		/* Virtual Address of the descriptor ring */
-	dma_addr_t physAddr;	/* Physical address of the descriptor ring */
-	int descriptorsAllocated;	/* Number of descriptors allocated in the 
descriptor ring */
-	size_t bytesAllocated;	/* Number of bytes allocated in the descriptor 
ring */
-
-} DMA_DescriptorRing_t;
-
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-
-/* The device handler is called whenever a DMA operation completes. The 
reaon */
-/* for it to be called will be a bitmask with one or more of the 
following bits */
-/* set. */
-
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE 
dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE 
dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR 
dmacHw_INTERRUPT_STATUS_ERROR
-
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-				     void *userData);
-
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004	/* If set, it 
means that the port used on DMAC0 is different from the port used on 
DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008	/* If set, 
allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800	/* If set, 
device is in use on a channel */
-
-/* Note: Some DMA devices can be used from multiple DMA Controllers. 
The bitmask is used to */
-/*       determine which DMA controllers a given device can be used 
from, and the interface */
-/*       array determeines the actual interface number to use for a 
given controller. */
-
-typedef struct {
-	uint32_t flags;		/* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-	uint8_t dedicatedController;	/* Controller number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	uint8_t dedicatedChannel;	/* Channel number to use if 
DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	const char *name;	/* Will show up in the /proc entry */
-
-	uint32_t dmacPort[DMA_NUM_CONTROLLERS];	/* Specifies the port number 
when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-
-	dmacHw_CONFIG_t config;	/* Configuration to use when DMA'ing using 
this device */
-
-	void *userData;		/* Passed to the devHandler */
-	DMA_DeviceHandler_t devHandler;	/* Called when DMA operations finish. */
-
-	timer_tick_count_t transferStartTime;	/* Time the current transfer was 
started */
-
-	/* The following statistical information will be collected and 
presented in a proc entry. */
-	/* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 
years to overflow */
-	/*       a 64 bit counter. */
-
-	uint64_t numTransfers;	/* Number of DMA transfers performed */
-	uint64_t transferTicks;	/* Total time spent doing DMA transfers 
(measured in timer_tick_count_t's) */
-	uint64_t transferBytes;	/* Total bytes transferred */
-	uint32_t timesBlocked;	/* Number of times a channel was unavailable */
-	uint32_t numBytes;	/* Last transfer size */
-
-	/* It's not possible to free memory which is allocated for the 
descriptors from within */
-	/* the ISR. So make the presumption that a given device will tend to 
use the */
-	/* same sized buffers over and over again, and we keep them around. */
-
-	DMA_DescriptorRing_t ring;	/* Ring of descriptors allocated for this 
device */
-
-	/* We stash away some of the information from the previous transfer. 
If back-to-back */
-	/* transfers are performed from the same buffer, then we don't have to 
keep re-initializing */
-	/* the descriptor buffers. */
-
-	uint32_t prevNumBytes;
-	dma_addr_t prevSrcData;
-	dma_addr_t prevDstData;
-
-} DMA_DeviceAttribute_t;
-
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out 
into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA 
channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-
-typedef struct {
-	uint32_t flags;		/* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-	DMA_Device_t devType;	/* Device this channel is currently reserved for */
-	DMA_Device_t lastDevType;	/* Device type that used this previously */
-	char name[20];		/* Name passed onto request_irq */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	const char *fileName;	/* Place where channel reservation took place */
-	int lineNum;		/* Place where channel reservation took place */
-#endif
-	dmacHw_HANDLE_t dmacHwHandle;	/* low level channel handle. */
-
-} DMA_Channel_t;
-
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA 
controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-
-typedef struct {
-	DMA_Channel_t channel[DMA_NUM_CHANNELS];
-
-} DMA_Controller_t;
-
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-
-typedef struct {
-	struct semaphore lock;	/* acquired when manipulating table entries */
-	wait_queue_head_t freeChannelQ;
-
-	DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-
-} DMA_Global_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-#if defined(__KERNEL__)
-
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-
-int dma_init(void);
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char 
*fileName,
-				     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, 
__FILE__, __LINE__)
-#else
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-DMA_Handle_t dma_request_channel(DMA_Device_t dev	/* Device to use with 
the allocated channel. */
-    );
-#endif
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t channel	/* DMA handle. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t dev	/* Device to check. */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of 
descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be 
allocated. */
-    );
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor 
ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor 
to release */
-    );
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient 
space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor 
ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be 
retrieved.
-*   DMA parameters such as transfer width, and whether this is a 
memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of 
descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the 
indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device 
that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring 
to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ 
functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to 
update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors 
to */
-    );
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to 
retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done 
automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular 
buffer.
-*
-*   This is primarily intended to be used for things like the ingress 
samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination 
buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination 
buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx 
functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA 
operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being 
performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_to_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					 dma_addr_t srcData,	/* Place to get data to write to device 
(physical address) */
-					 dma_addr_t dstData,	/* Pointer to device data address (physical 
address) */
-					 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_from_device(DMA_Handle_t handle,	/* DMA 
Handle */
-					   dma_addr_t srcData,	/* Pointer to the device data address 
(physical address) */
-					   dma_addr_t dstData,	/* Place to store data retrieved from the 
device (physical address) */
-					   size_t numBytes	/* Number of bytes to retrieve from the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,	/* DMA 
Handle */
-					  dma_addr_t srcData,	/* Place to transfer data from (physical 
address) */
-					  dma_addr_t dstData,	/* Place to transfer data to (physical 
address) */
-					  size_t numBytes	/* Number of bytes to transfer */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer 
completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the 
callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA 
completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    );
-
-#endif
-
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S 
b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0..0000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =(MM_IO_BASE_INTC0)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC0_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_INTC1)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC1_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_SINTC)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with 
enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #0xffffffff             @ code meaning no interrupt bits set
-		cmp	\irqstat, #0
-		beq	1002f
-
-		mov	\irqnr, #IRQ_SINTC_START        @ something is set, so fixup 
return value
-
-1001:
-		movs	\tmp, \irqstat, lsl #16
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #16
-
-		movs	\tmp, \irqstat, lsl #8
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #8
-
-		movs	\tmp, \irqstat, lsl #4
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #4
-
-		movs	\tmp, \irqstat, lsl #2
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #2
-
-		movs	\tmp, \irqstat, lsl #1
-		addeq	\irqnr, \irqnr, #1
-		orrs	\base, \base, #1
-
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-		.endm
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h 
b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index 6ae20a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <cfg_global.h>
-#include <mach/csp/mm_io.h>
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-
-#define RAM_SIZE 
(CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-
-/* Macros to make managing spinlocks a bit more controlled in terms of 
naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name) 
DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t 
bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val) 
spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val) 
spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h 
b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b82..0000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0	/* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1	/* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2	/* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3	/* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4	/* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5	/* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6	/* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7	/* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8	/* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9	/* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10	/* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11	/* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12	/* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13	/* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14	/* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15	/* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16	/* Voice process module interrupt */
-#define IRQ_USBHD2         17	/* USB host2/device2 interrupt */
-#define IRQ_USBH1          18	/* USB1 host interrupt */
-#define IRQ_USBD           19	/* USB device interrupt */
-#define IRQ_SDIOH0         20	/* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21	/* SDIO1 host interrupt */
-#define IRQ_TIMER0         22	/* Timer0 interrupt */
-#define IRQ_TIMER1         23	/* Timer1 interrupt */
-#define IRQ_TIMER2         24	/* Timer2 interrupt */
-#define IRQ_TIMER3         25	/* Timer3 interrupt */
-#define IRQ_SPIH           26	/* SPI host interrupt */
-#define IRQ_ESW            27	/* Ethernet switch interrupt */
-#define IRQ_APM            28	/* Audio process module interrupt */
-#define IRQ_GE             29	/* Graphic engine interrupt */
-#define IRQ_CLCD           30	/* LCD Controller interrupt */
-#define IRQ_PIF            31	/* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32	/*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33	/*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34	/*  2 I2S0 interrupt */
-#define IRQ_I2S1           35	/*  3 I2S1 interrupt */
-#define IRQ_I2CH           36	/*  4 I2C host interrupt */
-#define IRQ_I2CS           37	/*  5 I2C slave interrupt */
-#define IRQ_SPIS           38	/*  6 SPI slave interrupt */
-#define IRQ_GPHY           39	/*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40	/*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41	/*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42	/* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43	/* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44	/* 12 UARTB */
-#define IRQ_WATCHDOG       45	/* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46	/* 14 UARTA */
-#define IRQ_TSC            47	/* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48	/* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49	/* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50	/* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51	/* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52	/* 20 Random number generator interrupt */
-#define IRQ_RTC0           53	/* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54	/* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55	/* 23 Secure process module interrupt */
-#define IRQ_VDEC           56	/* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57	/* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58	/* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59	/*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60	/*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61	/*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62	/*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63	/*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64	/*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65	/*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66	/*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67	/*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68	/*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69	/* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70	/* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71	/* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72	/* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73	/* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74	/* 15 Real time clock tamper interrupt */
-
-#define IRQ_SINTC_END      74
-
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs 
could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio 
based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-
-#define IRQ_GPIO_0                  100
-
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I 
hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-
-#define IRQ_UNKNOWN                 -1
-
-/* Tune these bits to preclude noisy or unsupported interrupt sources 
as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h 
b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16..0000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)	/* Bus turnaround cycle (n) 
0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)	/* Write pulse width cycle (n+1) 
0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)	/* Write recovery cycle (n+1) 
0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)	/* Write address setup cycle (n+1) 
0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)	/* Output enable delay cycle (n) 
0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)	/* Read access cycle (n+2) 
0-31 (50 ns) */
-
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-	| HW_CFG_NAND_tWP  \
-	| HW_CFG_NAND_tWR  \
-	| HW_CFG_NAND_tAS  \
-	| HW_CFG_NAND_tOE  \
-	| HW_CFG_NAND_tRC)
-
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)	/* Page read access cycle / 
Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)	/* Bus turnaround cycle (n) 
                             (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)	/* Write pulse width cycle (n+1) 
                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)	/* Write recovery cycle (n+1) 
                            (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)	/* Write address setup cycle 
(n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)	/* Output enable delay cycle (n) 
                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)	/* Read access cycle / Burst 
read latency (n+2 / n+1)       (100ns)    */
-
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-	| HW_CFG_NOR_TBTA      \
-	| HW_CFG_NOR_TWP       \
-	| HW_CFG_NOR_TWR       \
-	| HW_CFG_NOR_TAS       \
-	| HW_CFG_NOR_TOE       \
-	| HW_CFG_NOR_TRC_TLC)
-
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values 
[400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules 
[8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000	/* Total memory, not 
per device size */
-
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h 
b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index 387376f..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/reg_umi.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-#define HW_NAND_BASE       MM_IO_BASE_NAND	/* NAND Flash */
-
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h 
b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 0992842..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-
-/* ---- Include Files 
---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Constants and Types 
---------------------------------------------- */
-
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst 
flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 
+ (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h 
b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb..0000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-
-#if defined(__KERNEL__)
-
-/* ---- Include Files 
---------------------------------------------------- */
-/* ---- Constants and Types 
---------------------------------------------- */
-
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-
-/* ---- Variable Externs 
------------------------------------------------- */
-/* ---- Function Prototypes 
---------------------------------------------- */
-
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h 
b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033e..0000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE		100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h 
b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b..0000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA 
+ 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	/* Send out UARTA */
-	while (BCMRING_UART_0_FR & (1 << 5))
-		;
-
-	BCMRING_UART_0_DR = c;
-}
-
-
-static inline void flush(void)
-{
-	/* Wait for the tx fifo to be empty */
-	while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-		;
-
-	/* Wait for the final character to be sent on the txd line */
-	while (BCMRING_UART_0_FR & (1 << 3))
-		;
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa68..0000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 
  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-
-static struct irq_chip bcmring_irq0_chip = {
-	.name = "ARM-INTC0",
-	.irq_ack = bcmring_mask_irq0,
-	.irq_mask = bcmring_mask_irq0,	/* mask a specific interrupt, blocking 
its delivery. */
-	.irq_unmask = bcmring_unmask_irq0,	/* unmaks an interrupt */
-};
-
-static struct irq_chip bcmring_irq1_chip = {
-	.name = "ARM-INTC1",
-	.irq_ack = bcmring_mask_irq1,
-	.irq_mask = bcmring_mask_irq1,
-	.irq_unmask = bcmring_unmask_irq1,
-};
-
-static struct irq_chip bcmring_irq2_chip = {
-	.name = "ARM-SINTC",
-	.irq_ack = bcmring_mask_irq2,
-	.irq_mask = bcmring_mask_irq2,
-	.irq_unmask = bcmring_unmask_irq2,
-};
-
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-		     unsigned int irq_start, unsigned int vic_sources)
-{
-	unsigned int i;
-	for (i = 0; i < 32; i++) {
-		unsigned int irq = irq_start + i;
-		irq_set_chip(irq, chip);
-		irq_set_chip_data(irq, base);
-
-		if (vic_sources & (1 << i)) {
-			irq_set_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-	writel(0, base + INTCHW_INTSELECT);
-	writel(0, base + INTCHW_INTENABLE);
-	writel(~0, base + INTCHW_INTENCLEAR);
-	writel(0, base + INTCHW_IRQSTATUS);
-	writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-
-void __init bcmring_init_irq(void)
-{
-	vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-		 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-		 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-		 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-
-	/* special cases */
-	if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-	}
-	if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-	}
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 1adec78..0000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-#define IO_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_DEVICE }
-
-#define MEM_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_MEMORY }
-
-static struct map_desc bcmring_io_desc[] __initdata = {
-	IO_DESC(MM_IO_BASE_NAND, SZ_64K),	/* phys:0x28000000-0x28000FFF 
virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_UMI, SZ_64K),	/* phys:0x2C000000-0x2C000FFF 
virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
-	IO_DESC(MM_IO_BASE_BROM, SZ_64K),	/* phys:0x30000000-0x3000FFFF 
virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-	MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),	/* phys:0x31000000-0x31FFFFFF 
virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA0, SZ_1M),	/* phys:0x32000000-0x32FFFFFF 
virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA1, SZ_1M),	/* phys:0x33000000-0x33FFFFFF 
virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_ESW, SZ_1M),	/* phys:0x34000000-0x34FFFFFF 
virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_CLCD, SZ_1M),	/* phys:0x35000000-0x35FFFFFF 
virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_APM, SZ_1M),	/* phys:0x36000000-0x36FFFFFF 
virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_SPUM, SZ_1M),	/* phys:0x37000000-0x37FFFFFF 
virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),	/* phys:0x38000000-0x38FFFFFF 
virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),	/* phys:0x3A000000-0x3AFFFFFF 
virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
-	IO_DESC(MM_IO_BASE_VRAM, SZ_64K),	/* phys:0x40000000-0x4000FFFF 
virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),	/* phys:0x80000000-0x80FFFFFF 
virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-		SZ_16M),	/* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF 
size:0x01000000 */
-};
-
-void __init bcmring_map_io(void)
-{
-
-	iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-	/* Maximum DMA memory allowed is 14M */
-	init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index af9c3d7..0000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed 
to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <csp/tmrHw.h>
-
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM 
timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread 
spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-
-#define PROF_TIMER 1
-
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-	return tmrHw_getCountRate(PROF_TIMER);
-}
-
-timer_tick_count_t timer_get_tick_count(void)
-{
-	return tmrHw_GetCurrentCount(PROF_TIMER);	/* change downcounter to 
upcounter */
-}
-
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-	static int tickRateMsec;
-
-	if (tickRateMsec == 0) {
-		tickRateMsec = timer_get_tick_rate() / 1000;
-	}
-
-	return ticks / tickRateMsec;
-}
-
-timer_msec_t timer_get_msec(void)
-{
-	return timer_ticks_to_msec(timer_get_tick_count());
-}
-
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
-- 
1.7.1




From olof at lixom.net  Thu Sep 13 02:41:51 2012
From: olof at lixom.net (Olof Johansson)
Date: Wed, 12 Sep 2012 23:41:51 -0700
Subject: [PATCH v2 2/2] ARM: Remove mach-bcmring
In-Reply-To: <50517D7E.5030406@broadcom.com>
References: <50517D7E.5030406@broadcom.com>
Message-ID: <20120913064151.GA5375@quad.lixom.net>

On Wed, Sep 12, 2012 at 11:30:22PM -0700, Christian Daudt wrote:
> Remove mach-bcmring as this is no longer maintained or used.
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

Hi,

It looks like your patch has been line wrapped so it can't be applied.

Did you use git send-email to send it, or some other way? Check
Documentation/email-clients.txt for some guidance on how to configure
other mail readers, but by far easiest is to use send-email.


-Olof


From b32955 at freescale.com  Thu Sep 13 02:57:51 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:51 +0800
Subject: [PATCH v2 0/9] add EDO feature for gpmi-nand driver
Message-ID: <1347519480-31106-1-git-send-email-b32955@freescale.com>

The ONFI nand supports the EDO (extended data out) feature in 
asynchronous mode when the host controller(such as gpmi-nand)
uses a tRC of less then 30ns.

The gpmi can supports this EDO feature.
This patch set adds the EDO support the gpmi-nand driver.

patch 1 ~ patch 2: 
	 These two patches provide the infrastructure for the EDO feature.
         They add necessary MTD helpers for the ONFI nand set/get features,
	 and the help to get the supportted timing mode.
	 These two patches are new version. The init version has been
	 reviewed by Vikram & Florian.

patch 3 ~ patch 7:
         These patches are clean-ups for the gpmi-nand's timing code.
	 Also they make the some preparations for the EDO patch.

patch 8: add the EDO feature to the gpmi-nand.


patch 9: a small optimization for the timing. 
         only set the timing registers one time.

I tested this patch set on the IMX6Q-arm2 board with several Micron's
ONFI nand chips. Some chips only can supports to mode 4, some chips
can supports to mode 5.

The performance is much improved. Take Micron MT29F32G08MAA for example
(in mode 5, 100MHz):

1) The test result BEFORE we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 3632 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 3554 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 3592 KiB/s
.......................................
=================================================

2) The test result AFTER we add the EDO feature:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
			page size 4096, count of eraseblocks 400,
			pages per eraseblock 128, OOB size 218
.......................................
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19555 KiB/s
.......................................
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17319 KiB/s
.......................................
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 18339 KiB/s
.......................................
=================================================

The read data performance is much improved by more then 5 times.

---
ChangLog:
v1 --> v2:
	[1] fix the wrong macro for busy timeout
	[2] use the NSEC_PER_SEC to replace the `1000000000`.
	[3] fix the wrong macro type for WRN_DLY_SEL.
	[4] fix some comments.
	[5] misc

Huang Shijie (9):
  mtd: add helpers to set/get features for ONFI nand
  mtd: add helpers to get the supportted ONFI timing mode
  mtd: gpmi: add a new field for HW_GPMI_TIMING1
  mtd: gpmi: do not get the clock frequency in gpmi_begin()
  mtd: gpmi: add a new field for HW_GPMI_CTRL1
  mtd: gpmi: simplify the setting DLL code
  mtd: gpmi: do not set the default values for the extra clocks
  mtd: gpmi: add EDO feature for imx6q
  mtd: gpmi: initialize the timing registers only one time

 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |  275 ++++++++++++++++++++++++++++---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   23 ++--
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |   19 +++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |   12 ++
 drivers/mtd/nand/nand_base.c           |   50 ++++++
 include/linux/mtd/nand.h               |   39 +++++
 6 files changed, 381 insertions(+), 37 deletions(-)




From b32955 at freescale.com  Thu Sep 13 02:57:53 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:53 +0800
Subject: [PATCH v2 2/9] mtd: add helpers to get the supportted ONFI timing mode
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-3-git-send-email-b32955@freescale.com>

add onfi_get_async_timing_mode() to get the supportted asynchronous
timing mode.

add onfi_get_sync_timing_mode() to get the supportted synchronous
timing mode.

Also add the neccessary macros : the timing modes.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 include/linux/mtd/nand.h |   25 +++++++++++++++++++++++++
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 537f59c..7a7b246 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -231,6 +231,15 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI timing mode, used in both asynchronous and synchronous mode */
+#define ONFI_TIMING_MODE_0		(1 << 0)
+#define ONFI_TIMING_MODE_1		(1 << 1)
+#define ONFI_TIMING_MODE_2		(1 << 2)
+#define ONFI_TIMING_MODE_3		(1 << 3)
+#define ONFI_TIMING_MODE_4		(1 << 4)
+#define ONFI_TIMING_MODE_5		(1 << 5)
+#define ONFI_TIMING_MODE_UNKNOWN	(1 << 6)
+
 /* ONFI feature address */
 #define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
 
@@ -682,4 +691,20 @@ struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 	return chip->priv;
 }
 
+/* return the supported asynchronous timing mode. */
+static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.async_timing_mode);
+}
+
+/* return the supported synchronous timing mode. */
+static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
+{
+	if (!chip->onfi_version)
+		return ONFI_TIMING_MODE_UNKNOWN;
+	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
+}
+
 #endif /* __LINUX_MTD_NAND_H */
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:52 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:52 +0800
Subject: [PATCH v2 1/9] mtd: add helpers to set/get features for ONFI nand
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-2-git-send-email-b32955@freescale.com>

Add the set-features(0xef)/get-features(0xee) helpers for ONFI nand.
Also add the necessary macros.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/nand_base.c |   50 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/nand.h     |   14 +++++++++++
 2 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 88f671c..d06a80d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2700,6 +2700,50 @@ static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
 }
 
 /**
+ * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	int status;
+
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
+	chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	status = chip->waitfunc(mtd, chip);
+	if (status & NAND_STATUS_FAIL)
+		return -EIO;
+	return 0;
+}
+
+/**
+ * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
+ * @mtd: MTD device structure
+ * @chip: nand chip info structure
+ * @addr: feature address.
+ * @subfeature_param: the subfeature parameters, a four bytes array.
+ */
+static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
+			int addr, uint8_t *subfeature_param)
+{
+	if (!chip->onfi_version)
+		return -EINVAL;
+
+	/* clear the sub feature parameters */
+	memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
+
+	chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
+	chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
+	return 0;
+}
+
+/**
  * nand_suspend - [MTD Interface] Suspend the NAND flash
  * @mtd: MTD device structure
  */
@@ -3223,6 +3267,12 @@ int nand_scan_tail(struct mtd_info *mtd)
 	if (!chip->write_page)
 		chip->write_page = nand_write_page;
 
+	/* set for ONFI nand */
+	if (!chip->onfi_set_features)
+		chip->onfi_set_features = nand_onfi_set_features;
+	if (!chip->onfi_get_features)
+		chip->onfi_get_features = nand_onfi_get_features;
+
 	/*
 	 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
 	 * selected and we have 256 byte pagesize fallback to software ECC
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 8f99d36..537f59c 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -92,6 +92,8 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 #define NAND_CMD_READID		0x90
 #define NAND_CMD_ERASE2		0xd0
 #define NAND_CMD_PARAM		0xec
+#define NAND_CMD_GET_FEATURES	0xee
+#define NAND_CMD_SET_FEATURES	0xef
 #define NAND_CMD_RESET		0xff
 
 #define NAND_CMD_LOCK		0x2a
@@ -229,6 +231,12 @@ typedef enum {
 /* Keep gcc happy */
 struct nand_chip;
 
+/* ONFI feature address */
+#define ONFI_FEATURE_ADDR_TIMING_MODE	0x1
+
+/* ONFI subfeature parameters length */
+#define ONFI_SUBFEATURE_PARAM_LEN	4
+
 struct nand_onfi_params {
 	/* rev info and features block */
 	/* 'O' 'N' 'F' 'I'  */
@@ -452,6 +460,8 @@ struct nand_buffers {
  *			non 0 if ONFI supported.
  * @onfi_params:	[INTERN] holds the ONFI page parameter when ONFI is
  *			supported, 0 otherwise.
+ * @onfi_set_features	[REPLACEABLE] set the features for ONFI nand
+ * @onfi_get_features	[REPLACEABLE] get the features for ONFI nand
  * @ecclayout:		[REPLACEABLE] the default ECC placement scheme
  * @bbt:		[INTERN] bad block table pointer
  * @bbt_td:		[REPLACEABLE] bad block table descriptor for flash
@@ -494,6 +504,10 @@ struct nand_chip {
 	int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 			const uint8_t *buf, int oob_required, int page,
 			int cached, int raw);
+	int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
+	int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
+			int feature_addr, uint8_t *subfeature_para);
 
 	int chip_delay;
 	unsigned int options;
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:55 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:55 +0800
Subject: [PATCH v2 4/9] mtd: gpmi: do not get the clock frequency in
 gpmi_begin()
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-5-git-send-email-b32955@freescale.com>

The current code will gets the clock frequency which is used by
gpmi_nfc_compute_hardware_timing(). It makes the code a little mess.

So move the `get clock frequency` code to the
gpmi_nfc_compute_hardware_timing() itself. This makes the code tidy
and clean.

This patch also uses the macro NSE_PER_SEC to replace the `1000000000`.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index c95dbe8..41e905d 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -293,6 +293,7 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 					struct gpmi_nfc_hardware_timing *hw)
 {
 	struct timing_threshod *nfc = &timing_default_threshold;
+	struct resources *r = &this->resources;
 	struct nand_chip *nand = &this->nand;
 	struct nand_timing target = this->timing;
 	bool improved_timing_is_available;
@@ -332,8 +333,9 @@ static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
 		(target.tRHOH_in_ns >= 0) ;
 
 	/* Inspect the clock. */
+	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 	clock_frequency_in_hz = nfc->clock_frequency_in_hz;
-	clock_period_in_ns    = 1000000000 / clock_frequency_in_hz;
+	clock_period_in_ns    = NSEC_PER_SEC / clock_frequency_in_hz;
 
 	/*
 	 * The NFC quantizes setup and hold parameters in terms of clock cycles.
@@ -738,7 +740,6 @@ return_results:
 void gpmi_begin(struct gpmi_nand_data *this)
 {
 	struct resources *r = &this->resources;
-	struct timing_threshod *nfc = &timing_default_threshold;
 	void __iomem *gpmi_regs = r->gpmi_regs;
 	unsigned int   clock_period_in_ns;
 	uint32_t       reg;
@@ -753,10 +754,6 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	/* Get the timing information we need. */
-	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
-	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
-
 	gpmi_nfc_compute_hardware_timing(this, &hw);
 
 	/* [1] Set HW_GPMI_TIMING0 */
@@ -801,6 +798,7 @@ void gpmi_begin(struct gpmi_nand_data *this)
 	 *
 	 * Calculate the amount of time we need to wait, in microseconds.
 	 */
+	clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
 	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
 
 	if (!dll_wait_time_in_us)
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:54 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:54 +0800
Subject: [PATCH v2 3/9] mtd: gpmi: add a new field for HW_GPMI_TIMING1
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-4-git-send-email-b32955@freescale.com>

The gpmi_nfc_compute_hardware_timing{} should contains all the
fields setting for gpmi timing registers. It already contains the fields
for HW_GPMI_TIMING0 and HW_GPMI_CTRL1.

So it is better to add a new field setting for HW_GPMI_TIMING1 in
this data structure. This makes the code more clear in logic.

This patch also changes some comments to make the code more readable.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |   17 +++++++++--------
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |   10 ++++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    3 +++
 3 files changed, 22 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 2289cf8..c95dbe8 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -728,6 +728,7 @@ return_results:
 	hw->address_setup_in_cycles = address_setup_in_cycles;
 	hw->use_half_periods        = dll_use_half_periods;
 	hw->sample_delay_factor     = sample_delay_factor;
+	hw->device_busy_timeout     = GPMI_DEFAULT_BUSY_TIMEOUT;
 
 	/* Return success. */
 	return 0;
@@ -752,26 +753,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	/* set ready/busy timeout */
-	writel(0x500 << BP_GPMI_TIMING1_BUSY_TIMEOUT,
-		gpmi_regs + HW_GPMI_TIMING1);
-
 	/* Get the timing information we need. */
 	nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
 	clock_period_in_ns = 1000000000 / nfc->clock_frequency_in_hz;
 
 	gpmi_nfc_compute_hardware_timing(this, &hw);
 
-	/* Set up all the simple timing parameters. */
+	/* [1] Set HW_GPMI_TIMING0 */
 	reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
 		BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles)         |
 		BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles)       ;
 
 	writel(reg, gpmi_regs + HW_GPMI_TIMING0);
 
-	/*
-	 * DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD.
-	 */
+	/* [2] Set HW_GPMI_TIMING1 */
+	writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
+		gpmi_regs + HW_GPMI_TIMING1);
+
+	/* [3] The following code is to set the HW_GPMI_CTRL1. */
+
+	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* Clear out the DLL control fields. */
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 1f61217..c814bdd 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -189,14 +189,24 @@ struct gpmi_nand_data {
  * @data_setup_in_cycles:      The data setup time, in cycles.
  * @data_hold_in_cycles:       The data hold time, in cycles.
  * @address_setup_in_cycles:   The address setup time, in cycles.
+ * @device_busy_timeout:       The timeout waiting for NAND Ready/Busy,
+ *                             this value is the number of cycles multiplied
+ *                             by 4096.
  * @use_half_periods:          Indicates the clock is running slowly, so the
  *                             NFC DLL should use half-periods.
  * @sample_delay_factor:       The sample delay factor.
  */
 struct gpmi_nfc_hardware_timing {
+	/* for HW_GPMI_TIMING0 */
 	uint8_t  data_setup_in_cycles;
 	uint8_t  data_hold_in_cycles;
 	uint8_t  address_setup_in_cycles;
+
+	/* for HW_GPMI_TIMING1 */
+	uint16_t device_busy_timeout;
+#define GPMI_DEFAULT_BUSY_TIMEOUT	0x500 /* default busy timeout value.*/
+
+	/* for HW_GPMI_CTRL1 */
 	bool     use_half_periods;
 	uint8_t  sample_delay_factor;
 };
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 8343124..8994e20 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -154,6 +154,9 @@
 
 #define HW_GPMI_TIMING1					0x00000080
 #define BP_GPMI_TIMING1_BUSY_TIMEOUT			16
+#define BM_GPMI_TIMING1_BUSY_TIMEOUT	(0xffff << BP_GPMI_TIMING1_BUSY_TIMEOUT)
+#define BF_GPMI_TIMING1_BUSY_TIMEOUT(v)		\
+	(((v) << BP_GPMI_TIMING1_BUSY_TIMEOUT) & BM_GPMI_TIMING1_BUSY_TIMEOUT)
 
 #define HW_GPMI_TIMING2					0x00000090
 #define HW_GPMI_DATA					0x000000a0
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:57 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:57 +0800
Subject: [PATCH v2 6/9] mtd: gpmi: simplify the setting DLL code
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-7-git-send-email-b32955@freescale.com>

The setting DLL code is a little mess.
Just simplify the code and the comments.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c |   22 +++++++++-------------
 1 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 2d1f77c..010665c 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -779,30 +779,26 @@ void gpmi_begin(struct gpmi_nand_data *this)
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* Clear out the DLL control fields. */
-	writel(BM_GPMI_CTRL1_RDN_DELAY,   gpmi_regs + HW_GPMI_CTRL1_CLR);
-	writel(BM_GPMI_CTRL1_HALF_PERIOD, gpmi_regs + HW_GPMI_CTRL1_CLR);
+	reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
+	writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
 	/* If no sample delay is called for, return immediately. */
 	if (!hw.sample_delay_factor)
 		return;
 
-	/* Configure the HALF_PERIOD flag. */
-	if (hw.use_half_periods)
-		writel(BM_GPMI_CTRL1_HALF_PERIOD,
-						gpmi_regs + HW_GPMI_CTRL1_SET);
+	/* Set RDN_DELAY or HALF_PERIOD. */
+	reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
+		| BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
 
-	/* Set the delay factor. */
-	writel(BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor),
-						gpmi_regs + HW_GPMI_CTRL1_SET);
+	writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
 
-	/* Enable the DLL. */
+	/* At last, we enable the DLL. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
 
 	/*
 	 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
-	 * we can use the GPMI.
-	 *
-	 * Calculate the amount of time we need to wait, in microseconds.
+	 * we can use the GPMI. Calculate the amount of time we need to wait,
+	 * in microseconds.
 	 */
 	clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
 	dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:59 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:59 +0800
Subject: [PATCH v2 8/9] mtd: gpmi: add EDO feature for imx6q
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-9-git-send-email-b32955@freescale.com>

When the frequency on the nand chip pins is above 33MHz,
the nand EDO(extended Data Out) timing could be applied.
The GPMI implements a Feedback read strobe to sample the read data in
the EDO timing mode.

This patch adds the EDO feature for the gpmi-nand driver.

For some onfi nand chips, the mode 4 is the fastest;
while for other onfi nand chips, the mode 5 is the fastest.
This patch only adds the support for the fastest asynchronous timing mode.
So this patch only supports the mode 4 and mode 5.

I tested several Micron's ONFI nand chips with EDO enabled,
take Micron MT29F32G08MAA for example (in mode 5, 100MHz):

1) The test result BEFORE we add the EDO feature:
	=================================================
	mtd_speedtest: MTD device: 2
	mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
				page size 4096, count of eraseblocks 400,
				pages per eraseblock 128, OOB size 218
	.......................................
	mtd_speedtest: testing eraseblock read speed
	mtd_speedtest: eraseblock read speed is 3632 KiB/s
	.......................................
	mtd_speedtest: testing page read speed
	mtd_speedtest: page read speed is 3554 KiB/s
	.......................................
	mtd_speedtest: testing 2 page read speed
	mtd_speedtest: 2 page read speed is 3592 KiB/s
	.......................................
	=================================================

2) The test result AFTER we add the EDO feature:
	=================================================
	mtd_speedtest: MTD device: 2
	mtd_speedtest: MTD device size 209715200, eraseblock size 524288,
				page size 4096, count of eraseblocks 400,
				pages per eraseblock 128, OOB size 218
	.......................................
	mtd_speedtest: testing eraseblock read speed
	mtd_speedtest: eraseblock read speed is 19555 KiB/s
	.......................................
	mtd_speedtest: testing page read speed
	mtd_speedtest: page read speed is 17319 KiB/s
	.......................................
	mtd_speedtest: testing 2 page read speed
	mtd_speedtest: 2 page read speed is 18339 KiB/s
	.......................................
	=================================================

3) The read data performance is much improved by more then 5 times.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |  214 +++++++++++++++++++++++++++++++-
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    8 ++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    6 +
 3 files changed, 227 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 010665c..c036e51 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -737,6 +737,215 @@ return_results:
 	return 0;
 }
 
+/*
+ * <1> Firstly, we should know what's the GPMI-clock means.
+ *     The GPMI-clock is the internal clock in the gpmi nand controller.
+ *     If you set 100MHz to gpmi nand controller, the GPMI-clock's period
+ *     is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
+ *
+ * <2> Secondly, we should know what's the frequency on the nand chip pins.
+ *     The frequency on the nand chip pins is derived from the GPMI-clock.
+ *     We can get it from the following equation:
+ *
+ *         F = G / (DS + DH)
+ *
+ *         F  : the frequency on the nand chip pins.
+ *         G  : the GPMI clock, such as 100MHz.
+ *         DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
+ *         DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
+ *
+ * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
+ *     the nand EDO(extended Data Out) timing could be applied.
+ *     The GPMI implements a feedback read strobe to sample the read data.
+ *     The feedback read strobe can be delayed to support the nand EDO timing
+ *     where the read strobe may deasserts before the read data is valid, and
+ *     read data is valid for some time after read strobe.
+ *
+ *     The following figure illustrates some aspects of a NAND Flash read:
+ *
+ *                   |<---tREA---->|
+ *                   |             |
+ *                   |         |   |
+ *                   |<--tRP-->|   |
+ *                   |         |   |
+ *                  __          ___|__________________________________
+ *     RDN            \________/   |
+ *                                 |
+ *                                 /---------\
+ *     Read Data    --------------<           >---------
+ *                                 \---------/
+ *                                |     |
+ *                                |<-D->|
+ *     FeedbackRDN  ________             ____________
+ *                          \___________/
+ *
+ *          D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
+ *
+ *
+ * <4> Now, we begin to describe how to compute the right RDN_DELAY.
+ *
+ *  4.1) From the aspect of the nand chip pins:
+ *        Delay = (tREA + C - tRP)               {1}
+ *
+ *        tREA : the maximum read access time. From the ONFI nand standards,
+ *               we know that tREA is 16ns in mode 5, tREA is 20ns is mode 4.
+ *               Please check it in : www.onfi.org
+ *        C    : a constant for adjust the delay. default is 4.
+ *        tRP  : the read pulse width.
+ *               Specified by the HW_GPMI_TIMING0:DATA_SETUP:
+ *                    tRP = (GPMI-clock-period) * DATA_SETUP
+ *
+ *  4.2) From the aspect of the GPMI nand controller:
+ *         Delay = RDN_DELAY * 0.125 * RP        {2}
+ *
+ *         RP   : the DLL reference period.
+ *            if (GPMI-clock-period > DLL_THRETHOLD)
+ *                   RP = GPMI-clock-period / 2;
+ *            else
+ *                   RP = GPMI-clock-period;
+ *
+ *            Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
+ *            is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
+ *            is 16ns, but in mx6q, we use 12ns.
+ *
+ *  4.3) since {1} equals {2}, we get:
+ *
+ *                    (tREA + 4 - tRP) * 8
+ *         RDN_DELAY = ---------------------     {3}
+ *                           RP
+ *
+ *  4.4) We only support the fastest asynchronous mode of ONFI nand.
+ *       For some ONFI nand, the mode 4 is the fastest mode;
+ *       while for some ONFI nand, the mode 5 is the fastest mode.
+ *       So we only support the mode 4 and mode 5. It is no need to
+ *       support other modes.
+ */
+static void gpmi_compute_edo_timing(struct gpmi_nand_data *this,
+			struct gpmi_nfc_hardware_timing *hw)
+{
+	struct resources *r = &this->resources;
+	unsigned long rate = clk_get_rate(r->clock[0]);
+	int mode = this->timing_mode;
+	int dll_threshold = 16; /* in ns */
+	unsigned long delay;
+	unsigned long clk_period;
+	int t_rea;
+	int c = 4;
+	int t_rp;
+	int rp;
+
+	/*
+	 * [1] for GPMI_HW_GPMI_TIMING0:
+	 *     The async mode requires 40MHz for mode 4, 50MHz for mode 5.
+	 *     The GPMI can support 100MHz at most. So if we want to
+	 *     get the 40MHz or 50MHz, we have to set DS=1, DH=1.
+	 *     Set the ADDRESS_SETUP to 0 in mode 4.
+	 */
+	hw->data_setup_in_cycles = 1;
+	hw->data_hold_in_cycles = 1;
+	hw->address_setup_in_cycles = ((mode == 5) ? 1 : 0);
+
+	/* [2] for GPMI_HW_GPMI_TIMING1 */
+	hw->device_busy_timeout = 0x9000;
+
+	/* [3] for GPMI_HW_GPMI_CTRL1 */
+	hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
+
+	if (GPMI_IS_MX6Q(this))
+		dll_threshold = 12;
+
+	/*
+	 * Enlarge 10 times for the numerator and denominator in {3}.
+	 * This make us to get more accurate result.
+	 */
+	clk_period = NSEC_PER_SEC / (rate / 10);
+	dll_threshold *= 10;
+	t_rea = ((mode == 5) ? 16 : 20) * 10;
+	c *= 10;
+
+	t_rp = clk_period * 1; /* DATA_SETUP is 1 */
+
+	if (clk_period > dll_threshold) {
+		hw->use_half_periods = 1;
+		rp = clk_period / 2;
+	} else {
+		hw->use_half_periods = 0;
+		rp = clk_period;
+	}
+
+	/*
+	 * Multiply the numerator with 10, we could do a round off:
+	 *      7.8 round up to 8; 7.4 round down to 7.
+	 */
+	delay  = (((t_rea + c - t_rp) * 8) * 10) / rp;
+	delay = (delay + 5) / 10;
+
+	hw->sample_delay_factor = delay;
+}
+
+static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
+{
+	struct resources  *r = &this->resources;
+	struct nand_chip *nand = &this->nand;
+	struct mtd_info	 *mtd = &this->mtd;
+	uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
+	unsigned long rate;
+	int ret;
+
+	nand->select_chip(mtd, 0);
+
+	/* [1] send SET FEATURE commond to NAND */
+	feature[0] = mode;
+	ret = nand->onfi_set_features(mtd, nand,
+				ONFI_FEATURE_ADDR_TIMING_MODE, feature);
+	if (ret)
+		goto err_out;
+
+	/* [2] send GET FEATURE command to double-check the timing mode */
+	memset(feature, 0, ONFI_SUBFEATURE_PARAM_LEN);
+	ret = nand->onfi_get_features(mtd, nand,
+				ONFI_FEATURE_ADDR_TIMING_MODE, feature);
+	if (ret || feature[0] != mode)
+		goto err_out;
+
+	nand->select_chip(mtd, -1);
+
+	/* [3] set the main IO clock, 100MHz for mode 5, 80MHz for mode 4. */
+	rate = (mode == 5) ? 100000000 : 80000000;
+	clk_set_rate(r->clock[0], rate);
+
+	this->flags |= GPMI_ASYNC_EDO_ENABLED;
+	this->timing_mode = mode;
+	dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
+	return 0;
+
+err_out:
+	nand->select_chip(mtd, -1);
+	dev_err(this->dev, "mode:%d ,failed in set feature.\n", mode);
+	return -EINVAL;
+}
+
+int gpmi_extra_init(struct gpmi_nand_data *this)
+{
+	struct nand_chip *chip = &this->nand;
+
+	/* Enable the asynchronous EDO feature. */
+	if (GPMI_IS_MX6Q(this) && chip->onfi_version) {
+		int mode = onfi_get_async_timing_mode(chip);
+
+		/* We only support the timing mode 4 and mode 5. */
+		if (mode & ONFI_TIMING_MODE_5)
+			mode = 5;
+		else if (mode & ONFI_TIMING_MODE_4)
+			mode = 4;
+		else
+			return 0;
+
+		return enable_edo_mode(this, mode);
+	}
+	return 0;
+}
+
 /* Begin the I/O */
 void gpmi_begin(struct gpmi_nand_data *this)
 {
@@ -755,7 +964,10 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
-	gpmi_nfc_compute_hardware_timing(this, &hw);
+	if (this->flags & GPMI_ASYNC_EDO_ENABLED)
+		gpmi_compute_edo_timing(this, &hw);
+	else
+		gpmi_nfc_compute_hardware_timing(this, &hw);
 
 	/* [1] Set HW_GPMI_TIMING0 */
 	reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index cc74ebf..684c456 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -1514,6 +1514,14 @@ static int gpmi_scan_bbt(struct mtd_info *mtd)
 	if (ret)
 		return ret;
 
+	/*
+	 * Can we enable the extra features? such as EDO or Sync mode.
+	 *
+	 * We do not check the return value now. That's means if we fail in
+	 * enable the extra features, we still can run in the normal way.
+	 */
+	gpmi_extra_init(this);
+
 	/* use the default BBT implementation */
 	return nand_default_bbt(mtd);
 }
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 5c11e76..5b6d546 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -122,6 +122,10 @@ struct nand_timing {
 };
 
 struct gpmi_nand_data {
+	/* flags */
+#define GPMI_ASYNC_EDO_ENABLED	(1 << 0)
+	int			flags;
+
 	/* System Interface */
 	struct device		*dev;
 	struct platform_device	*pdev;
@@ -132,6 +136,7 @@ struct gpmi_nand_data {
 
 	/* Flash Hardware */
 	struct nand_timing	timing;
+	int			timing_mode;
 
 	/* BCH */
 	struct bch_geometry	bch_geometry;
@@ -259,6 +264,7 @@ extern int start_dma_with_bch_irq(struct gpmi_nand_data *,
 
 /* GPMI-NAND helper function library */
 extern int gpmi_init(struct gpmi_nand_data *);
+extern int gpmi_extra_init(struct gpmi_nand_data *);
 extern void gpmi_clear_bch(struct gpmi_nand_data *);
 extern void gpmi_dump_info(struct gpmi_nand_data *);
 extern int bch_set_geometry(struct gpmi_nand_data *);
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:56 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:56 +0800
Subject: [PATCH v2 5/9] mtd: gpmi: add a new field for HW_GPMI_CTRL1
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-6-git-send-email-b32955@freescale.com>

add the WRN_DLY_SEL field for HW_GPMI_CTRL1.
This field is used as delay for gpmi write strobe.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    6 ++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    2 ++
 drivers/mtd/nand/gpmi-nand/gpmi-regs.h |    9 +++++++++
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index 41e905d..2d1f77c 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -731,6 +731,7 @@ return_results:
 	hw->use_half_periods        = dll_use_half_periods;
 	hw->sample_delay_factor     = sample_delay_factor;
 	hw->device_busy_timeout     = GPMI_DEFAULT_BUSY_TIMEOUT;
+	hw->wrn_dly_sel             = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
 
 	/* Return success. */
 	return 0;
@@ -769,6 +770,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
 
 	/* [3] The following code is to set the HW_GPMI_CTRL1. */
 
+	/* Set the WRN_DLY_SEL */
+	writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
+	writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
+					gpmi_regs + HW_GPMI_CTRL1_SET);
+
 	/* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
 	writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
 
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index c814bdd..5c11e76 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -195,6 +195,7 @@ struct gpmi_nand_data {
  * @use_half_periods:          Indicates the clock is running slowly, so the
  *                             NFC DLL should use half-periods.
  * @sample_delay_factor:       The sample delay factor.
+ * @wrn_dly_sel:               The delay on the GPMI write strobe.
  */
 struct gpmi_nfc_hardware_timing {
 	/* for HW_GPMI_TIMING0 */
@@ -209,6 +210,7 @@ struct gpmi_nfc_hardware_timing {
 	/* for HW_GPMI_CTRL1 */
 	bool     use_half_periods;
 	uint8_t  sample_delay_factor;
+	uint8_t  wrn_dly_sel;
 };
 
 /**
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
index 8994e20..53397cc 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-regs.h
@@ -108,6 +108,15 @@
 #define HW_GPMI_CTRL1_CLR				0x00000068
 #define HW_GPMI_CTRL1_TOG				0x0000006c
 
+#define BP_GPMI_CTRL1_WRN_DLY_SEL			22
+#define BM_GPMI_CTRL1_WRN_DLY_SEL	(0x3 << BP_GPMI_CTRL1_WRN_DLY_SEL)
+#define BF_GPMI_CTRL1_WRN_DLY_SEL(v)  \
+	(((v) << BP_GPMI_CTRL1_WRN_DLY_SEL) & BM_GPMI_CTRL1_WRN_DLY_SEL)
+#define BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS		0x0
+#define BV_GPMI_CTRL1_WRN_DLY_SEL_6_TO_10NS		0x1
+#define BV_GPMI_CTRL1_WRN_DLY_SEL_7_TO_12NS		0x2
+#define BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY		0x3
+
 #define BM_GPMI_CTRL1_BCH_MODE				(1 << 18)
 
 #define BP_GPMI_CTRL1_DLL_ENABLE			17
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:57:58 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:57:58 +0800
Subject: [PATCH v2 7/9] mtd: gpmi: do not set the default values for the extra
 clocks
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-8-git-send-email-b32955@freescale.com>

The default frequencies of the extra clocks are 200MHz.
The current code sets the extra clocks to 44.5MHz.

When i add the EDO feature to gpmi, i have to revert the extra clocks
to 200MHz.

So it is better that we do not set the default values for the extra
clocks. The driver runs well even when we do not set the default values for
extra clocks.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   15 +++++----------
 1 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index c46be6c..cc74ebf 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -513,20 +513,15 @@ static int __devinit gpmi_get_clks(struct gpmi_nand_data *this)
 		r->clock[i] = clk;
 	}
 
-	if (GPMI_IS_MX6Q(this)) {
+	if (GPMI_IS_MX6Q(this))
 		/*
-		 * Set the default values for the clocks in mx6q:
-		 *    The main clock(enfc) : 22MHz
-		 *    The others           : 44.5MHz
+		 * Set the default value for the gpmi clock in mx6q:
 		 *
-		 * These are just the default values. If you want to use
-		 * the ONFI nand which is in the Synchronous Mode, you should
-		 * change the clocks's frequencies as you need.
+		 * If you want to use the ONFI nand which is in the
+		 * Synchronous Mode, you should change the clock as you need.
 		 */
 		clk_set_rate(r->clock[0], 22000000);
-		for (i = 1; i < GPMI_CLK_MAX && r->clock[i]; i++)
-			clk_set_rate(r->clock[i], 44500000);
-	}
+
 	return 0;
 
 err_clock:
-- 
1.7.0.4




From b32955 at freescale.com  Thu Sep 13 02:58:00 2012
From: b32955 at freescale.com (Huang Shijie)
Date: Thu, 13 Sep 2012 14:58:00 +0800
Subject: [PATCH v2 9/9] mtd: gpmi: initialize the timing registers only one
 time
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1347519480-31106-10-git-send-email-b32955@freescale.com>

The current code initializes the timing registers at very time
we call the gpmi_begin(). This really wastes the cpu cycles.

Add a new flag to let the gpmi driver initializes the timing registers
only one time.

Signed-off-by: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-lib.c  |    8 ++++++++
 drivers/mtd/nand/gpmi-nand/gpmi-nand.h |    1 +
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
index c036e51..3502acc 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c
@@ -914,6 +914,9 @@ static int enable_edo_mode(struct gpmi_nand_data *this, int mode)
 	rate = (mode == 5) ? 100000000 : 80000000;
 	clk_set_rate(r->clock[0], rate);
 
+	/* Let the gpmi_begin() re-compute the timing again. */
+	this->flags &= ~GPMI_TIMING_INIT_OK;
+
 	this->flags |= GPMI_ASYNC_EDO_ENABLED;
 	this->timing_mode = mode;
 	dev_info(this->dev, "enable the asynchronous EDO mode %d\n", mode);
@@ -964,6 +967,11 @@ void gpmi_begin(struct gpmi_nand_data *this)
 		goto err_out;
 	}
 
+	/* Only initialize the timing once */
+	if (this->flags & GPMI_TIMING_INIT_OK)
+		return;
+	this->flags |= GPMI_TIMING_INIT_OK;
+
 	if (this->flags & GPMI_ASYNC_EDO_ENABLED)
 		gpmi_compute_edo_timing(this, &hw);
 	else
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
index 5b6d546..7ac25c1 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.h
@@ -124,6 +124,7 @@ struct nand_timing {
 struct gpmi_nand_data {
 	/* flags */
 #define GPMI_ASYNC_EDO_ENABLED	(1 << 0)
+#define GPMI_TIMING_INIT_OK	(1 << 1)
 	int			flags;
 
 	/* System Interface */
-- 
1.7.0.4




From prabhakar at freescale.com  Thu Sep 13 04:54:49 2012
From: prabhakar at freescale.com (Prabhakar Kushwaha)
Date: Thu, 13 Sep 2012 14:24:49 +0530
Subject: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any write
Message-ID: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>

IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
implemented in IFC for any "system side write" into sram buffer. Reading an
uninitialized memory results in ECC Error from sram wrapper.

Hence we must initialize/prefill SRAM buffer by any data before writing
anything in SRAM from system side. To initialize SRAM user can use "READID"
NAND command with read bytes equal to SRAM size. It will be a one time
activity post boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
---
 Based upon git://git.infradead.org/linux-mtd.git branch master
 The compilation of this patch depends upon following patch.
 http://patchwork.ozlabs.org/patch/177893/
 This patch is currently applied on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
 branch next and status is "Awaiting Upstream"


 drivers/mtd/nand/fsl_ifc_nand.c |   56 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 1f71b54..3d15b92 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -31,6 +31,7 @@
 #include <linux/mtd/nand_ecc.h>
 #include <asm/fsl_ifc.h>
 
+#define FSL_IFC_V1_1_0	0x01010000
 #define ERR_BYTE		0xFF /* Value returned for read
 					bytes when read failed	*/
 #define IFC_TIMEOUT_MSECS	500  /* Maximum number of mSecs to wait
@@ -775,13 +776,62 @@ static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
 	return 0;
 }
 
+static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
+{
+	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
+	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
+	uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
+	uint32_t cs = priv->bank;
+
+	/* Save CSOR and CSOR_ext */
+	csor = in_be32(&ifc->csor_cs[cs].csor);
+	csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext);
+
+	/* chage PageSize 8K and SpareSize 1K*/
+	csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
+	out_be32(&ifc->csor_cs[cs].csor, csor_8k);
+	out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400);
+
+	/* READID */
+	out_be32(&ifc->ifc_nand.nand_fir0,
+			(IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) |
+			(IFC_FIR_OP_UA  << IFC_NAND_FIR0_OP1_SHIFT) |
+			(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
+	out_be32(&ifc->ifc_nand.nand_fcr0,
+			NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
+	out_be32(&ifc->ifc_nand.row3, 0x0);
+
+	out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
+
+	/* Program ROW0/COL0 */
+	out_be32(&ifc->ifc_nand.row0, 0x0);
+	out_be32(&ifc->ifc_nand.col0, 0x0);
+
+	/* set the chip select for NAND Transaction */
+	out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT);
+
+	/* start read seq */
+	out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
+
+	/* wait for command complete flag or timeout */
+	wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
+			   IFC_TIMEOUT_MSECS * HZ/1000);
+
+	if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
+		printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
+
+	/* Restore CSOR and CSOR_ext */
+	out_be32(&ifc->csor_cs[cs].csor, csor);
+	out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext);
+}
+
 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 {
 	struct fsl_ifc_ctrl *ctrl = priv->ctrl;
 	struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
 	struct nand_chip *chip = &priv->chip;
 	struct nand_ecclayout *layout;
-	u32 csor;
+	u32 csor, ver;
 
 	/* Fill in fsl_ifc_mtd structure */
 	priv->mtd.priv = chip;
@@ -875,6 +925,10 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
 		chip->ecc.mode = NAND_ECC_SOFT;
 	}
 
+	ver = in_be32(&ifc->ifc_rev);
+	if (ver == FSL_IFC_V1_1_0)
+		fsl_ifc_sram_init(priv);
+
 	return 0;
 }
 
-- 
1.7.9.5





From galak at kernel.crashing.org  Thu Sep 13 08:53:34 2012
From: galak at kernel.crashing.org (Kumar Gala)
Date: Thu, 13 Sep 2012 07:53:34 -0500
Subject: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any
 write
In-Reply-To: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
References: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
Message-ID: <68738277-B1F2-4455-B8FD-67F2DD9E1310@kernel.crashing.org>


On Sep 13, 2012, at 3:54 AM, Prabhakar Kushwaha wrote:

> IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
> SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
> implemented in IFC for any "system side write" into sram buffer. Reading an
> uninitialized memory results in ECC Error from sram wrapper.
> 
> Hence we must initialize/prefill SRAM buffer by any data before writing
> anything in SRAM from system side. To initialize SRAM user can use "READID"
> NAND command with read bytes equal to SRAM size. It will be a one time
> activity post boot.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> ---
> Based upon git://git.infradead.org/linux-mtd.git branch master
> The compilation of this patch depends upon following patch.
> http://patchwork.ozlabs.org/patch/177893/
> This patch is currently applied on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
> branch next and status is "Awaiting Upstream"
> 
> 
> drivers/mtd/nand/fsl_ifc_nand.c |   56 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 1 deletion(-)

If MTD maintainers ack, I'm happy to pull this in via PPC tree.

- k

From raph at 8d.com  Thu Sep 13 11:06:15 2012
From: raph at 8d.com (Raphael Assenat)
Date: Thu, 13 Sep 2012 11:06:15 -0400
Subject: [PATCH] mtd: nand: omap2: Fix the nand-disk led trigger
Message-ID: <20120913150614.GC22993@renkinjitsu.usine.8d.com>

When the omap2 nand flash driver is used, the nand-disk led trigger does not
work due to nand_wait_ready not being called.

This patch exports the trigger from nand_base.c, letting specific drivers
such omap2 control the led as appropriate.

Signed-off-by: Raphael Assenat <raph at 8d.com>

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index a11253a..b967c45 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -103,7 +103,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  * For devices which display every fart in the system on a separate LED. Is
  * compiled away when LED support is disabled.
  */
-DEFINE_LED_TRIGGER(nand_led_trigger);
+DEFINE_LED_TRIGGER_GLOBAL(nand_led_trigger);
 
 static int check_offs_len(struct mtd_info *mtd,
 					loff_t ofs, uint64_t len)
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index ac4fd75..6aa683f 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -19,6 +19,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/leds.h>
 #include <linux/omap-dma.h>
 #include <linux/io.h>
 #include <linux/slab.h>
@@ -254,6 +255,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 	int ret = 0;
 	u32 *p = (u32 *)buf;
 
+	led_trigger_event(nand_led_trigger, LED_FULL);
+
 	/* take care of subpage reads */
 	if (len % 4) {
 		if (info->nand.options & NAND_BUSWIDTH_16)
@@ -284,6 +287,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
 		/* disable and stop the PFPW engine */
 		gpmc_prefetch_reset(info->gpmc_cs);
 	}
+
+	led_trigger_event(nand_led_trigger, LED_OFF);
 }
 
 /**
@@ -302,6 +307,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
 	u16 *p = (u16 *)buf;
 	unsigned long tim, limit;
 
+	led_trigger_event(nand_led_trigger, LED_FULL);
+
 	/* take care of subpage writes */
 	if (len % 2 != 0) {
 		writeb(*buf, info->nand.IO_ADDR_W);
@@ -335,6 +342,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
 		/* disable and stop the PFPW engine */
 		gpmc_prefetch_reset(info->gpmc_cs);
 	}
+
+	led_trigger_event(nand_led_trigger, LED_OFF);
 }
 
 /*
@@ -366,6 +375,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 	unsigned n;
 	int ret;
 
+	led_trigger_event(nand_led_trigger, LED_FULL);
+
 	if (addr >= high_memory) {
 		struct page *p1;
 
@@ -417,6 +428,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
 	gpmc_prefetch_reset(info->gpmc_cs);
 
 	dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
+	
+	led_trigger_event(nand_led_trigger, LED_OFF);
 	return 0;
 
 out_copy_unmap:
@@ -428,6 +441,9 @@ out_copy:
 	else
 		is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
 			: omap_write_buf8(mtd, (u_char *) addr, len);
+	
+	led_trigger_event(nand_led_trigger, LED_OFF);
+
 	return 0;
 }
 
@@ -886,6 +902,8 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 	else
 		timeo += (HZ * 20) / 1000;
 
+	led_trigger_event(nand_led_trigger, LED_FULL);
+
 	gpmc_nand_write(info->gpmc_cs,
 			GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
 	while (time_before(jiffies, timeo)) {
@@ -894,6 +912,7 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
 			break;
 		cond_resched();
 	}
+	led_trigger_event(nand_led_trigger, LED_OFF);
 
 	status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
 	return status;
@@ -909,6 +928,8 @@ static int omap_dev_ready(struct mtd_info *mtd)
 	struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
 							mtd);
 
+	led_trigger_event(nand_led_trigger, LED_FULL);
+
 	val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 	if ((val & 0x100) == 0x100) {
 		/* Clear IRQ Interrupt */
@@ -923,6 +944,8 @@ static int omap_dev_ready(struct mtd_info *mtd)
 			val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
 		}
 	}
+	
+	led_trigger_event(nand_led_trigger, LED_OFF);
 
 	return 1;
 }
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 57977c6..321b7ef 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -23,6 +23,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/flashchip.h>
 #include <linux/mtd/bbm.h>
+#include <linux/leds.h>
 
 struct mtd_info;
 struct nand_flash_dev;
@@ -48,6 +49,9 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 /* unlocks specified locked blocks */
 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
 
+/* LED trigger for NAND drivers not using nand_wait_ready. */
+extern DEFINE_LED_TRIGGER_GLOBAL(nand_led_trigger);
+
 /* The maximum number of NAND chips in an array */
 #define NAND_MAX_CHIPS		8
 


From kim.phillips at freescale.com  Thu Sep 13 19:56:07 2012
From: kim.phillips at freescale.com (Kim Phillips)
Date: Thu, 13 Sep 2012 18:56:07 -0500
Subject: [PATCH] mtd: fsl_ifc_nand: fix cast removes address space of
 expression warnings
Message-ID: <20120913185607.af76965cb973dfb1059c842f@freescale.com>

found by sparse.

Signed-off-by: Kim Phillips <kim.phillips at freescale.com>
---
 drivers/mtd/nand/fsl_ifc_nand.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index e92d223..1be83dc 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -193,7 +193,7 @@ static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
 	struct nand_chip *chip = mtd->priv;
 	struct fsl_ifc_mtd *priv = chip->priv;
 	u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
-	u32 __iomem *mainarea = (u32 *)addr;
+	u32 __iomem *mainarea = (u32 __iomem *)addr;
 	u8 __iomem *oob = addr + mtd->writesize;
 	int i;
 
@@ -591,8 +591,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
 	 * next byte.
 	 */
 	if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
-		data = in_be16((uint16_t *)&ifc_nand_ctrl->
-					addr[ifc_nand_ctrl->index]);
+		data = in_be16((uint16_t __iomem *)&ifc_nand_ctrl->
+			       addr[ifc_nand_ctrl->index]);
 		ifc_nand_ctrl->index += 2;
 		return (uint8_t) data;
 	}
-- 
1.7.12




From stigge at antcom.de  Fri Sep 14 05:52:00 2012
From: stigge at antcom.de (Roland Stigge)
Date: Fri, 14 Sep 2012 11:52:00 +0200
Subject: [GIT PULL] ARM: LPC32xx: core update
In-Reply-To: <201209131155.16756.arnd@arndb.de>
References: <50488FD6.4080402@antcom.de> <201209131155.16756.arnd@arndb.de>
Message-ID: <5052FE40.2030305@antcom.de>

Hi Arnd,

On 13/09/12 13:55, Arnd Bergmann wrote:
> On Thursday 06 September 2012, Roland Stigge wrote:
>>       ARM: LPC32xx: Provide DMA filter callbacks via platform data
> 
> This patch results in build errors in the for-next branch with lpc32xx_defconfig:
> 
> arch/arm/mach-lpc32xx/phy3250.c:40:35: fatal error: linux/mtd/lpc32xx_slc.h: No such file or directory
> arch/arm/mach-lpc32xx/phy3250.c:41:35: fatal error: linux/mtd/lpc32xx_mlc.h: No such file or directory
> arch/arm/mach-lpc32xx/phy3250.c:226:15: error: variable 'lpc32xx_slc_data' has initializer but incomplete type
> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: unknown field 'dma_filter' specified in initializer
> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: excess elements in struct initializer [-Werror]
> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: (near initialization for 'lpc32xx_slc_data') [-Werror]
> arch/arm/mach-lpc32xx/phy3250.c:230:15: error: variable 'lpc32xx_mlc_data' has initializer but incomplete type
> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: unknown field 'dma_filter' specified in initializer
> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: excess elements in struct initializer [-Werror]
> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: (near initialization for 'lpc32xx_mlc_data') [-Werror]
> 
> It seems that we're missing a dependency. Which tree did the patch to add
> these go through? Can we add that to the same branch in arm-soc?

Right - there is a dependency on l2-mtd.git here.

Since they didn't request pull for 3.6, there is quite some stuff
pending in their tree (but I wonder why it isn't already part of
linux-next, so the above error at least shouldn't occur in linux-next).

So we have several alternative options here:

* If it is possible, include l2-mtd.git as a dependency in arm-soc.git
* Merge the following 2 patches as minimal dependency:
http://git.infradead.org/users/dedekind/l2-mtd-2.6.git/commitdiff/c47bc5c84a65c31f41a555706363f9e350ca6338
http://git.infradead.org/users/dedekind/l2-mtd-2.6.git/commitdiff/f5e87dd7350c98a34aa7041264c337f0f33c02ff
You actually only need the two .h files, ignore the patches for yet
non-existing .c mtd driver files in arm-soc.git.
* Defer the above (single) patch in arm-soc until l2-mtd is merged
linux-next or mainline. Maybe l2-mtd.git will appear in linux-next soon,
otherwise we will need to defer the above patch for lpc32xx/core for 3.8?

Sorry for the confusion,

Roland


From sachin.kamat at linaro.org  Fri Sep 14 11:32:08 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Fri, 14 Sep 2012 21:02:08 +0530
Subject: [PATCH] mtd: nand/gpio: Use module_platform_driver macro
In-Reply-To: <1346839292-31001-1-git-send-email-sachin.kamat@linaro.org>
References: <1346839292-31001-1-git-send-email-sachin.kamat@linaro.org>
Message-ID: <CAK9yfHwP-XOUfPjyi7xUzcWPg_EKLKhhG5z_JktHwf7sDVa--g@mail.gmail.com>

ping..

On 5 September 2012 15:31, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> module_platform_driver simplifies the code by eliminating
> module_init and module_exit calls.
>
> Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
> ---
>  drivers/mtd/nand/gpio.c |   15 +--------------
>  1 files changed, 1 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/nand/gpio.c b/drivers/mtd/nand/gpio.c
> index ce6a284..bc73bc5 100644
> --- a/drivers/mtd/nand/gpio.c
> +++ b/drivers/mtd/nand/gpio.c
> @@ -417,20 +417,7 @@ static struct platform_driver gpio_nand_driver = {
>         },
>  };
>
> -static int __init gpio_nand_init(void)
> -{
> -       printk(KERN_INFO "GPIO NAND driver, ? 2004 Simtec Electronics\n");
> -
> -       return platform_driver_register(&gpio_nand_driver);
> -}
> -
> -static void __exit gpio_nand_exit(void)
> -{
> -       platform_driver_unregister(&gpio_nand_driver);
> -}
> -
> -module_init(gpio_nand_init);
> -module_exit(gpio_nand_exit);
> +module_platform_driver(gpio_nand_driver);
>
>  MODULE_LICENSE("GPL");
>  MODULE_AUTHOR("Ben Dooks <ben at simtec.co.uk>");
> --
> 1.7.4.1
>



-- 
With warm regards,
Sachin


From peterhuewe at gmx.de  Fri Sep 14 18:41:09 2012
From: peterhuewe at gmx.de (Peter Huewe)
Date: Sat, 15 Sep 2012 00:41:09 +0200
Subject: [PATCH] mtd/nand/docg4: Add missing HAS_IOMEM dependency
Message-ID: <1347662469-1604-1-git-send-email-peterhuewe@gmx.de>

While building an allyesconfig for UML I received this error message(s):
 drivers/mtd/nand/docg4.c: In function 'probe_docg4':
 drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function
 'ioremap' [-Werror=implicit-function-declaration]
 drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from
 integer without a cast [enabled by default]
 drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function
 'iounmap' [-Werror=implicit-function-declaration]

which is caused by the missing implementations on UML.

This patch adds this missing HAS_IOMEM dependency and prevents the driver from
being build on platforms with no HAS_IOMEM

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
---
 drivers/mtd/nand/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..3e2f75d 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -356,7 +356,7 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
 
 config MTD_NAND_DOCG4
 	tristate "Support for DiskOnChip G4 (EXPERIMENTAL)"
-	depends on EXPERIMENTAL
+	depends on EXPERIMENTAL && HAS_IOMEM
 	select BCH
 	select BITREVERSE
 	help
-- 
1.7.8.6



From computersforpeace at gmail.com  Fri Sep 14 23:11:41 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 14 Sep 2012 20:11:41 -0700
Subject: [PATCH] NAND BBT: use NAND_BBT_SCAN_MAXBLOCKS
In-Reply-To: <1347371454-17107-1-git-send-email-richard.genoud@gmail.com>
References: <1347371454-17107-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <CAN8TOE_adrO32vo5c8P6fadhRqchFday302fo9F=kr4njfsaoA@mail.gmail.com>

Hi,

On Tue, Sep 11, 2012 at 6:50 AM, Richard Genoud
<richard.genoud at gmail.com> wrote:
> In nand_bbt.c, a hardcoded value was used instead of the define meant
> for that, so we use the define.
>
> There's no functionnal change.

s/functionnal/functional

> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

> -       .maxblocks = 4,
> +       .maxblocks = NAND_BBT_SCAN_MAXBLOCKS,

On a more important note: why was this define ever included in the
first place? It seems to have been included without a real user in
this commit:

Author: Kyungmin Park <kyungmin.park at samsung.com>
Date:   Tue Sep 27 11:26:39 2005 +0100

    [MTD] OneNAND: Add missing files

In the end, the real question is: does the macro have real value? I
suppose it makes it slightly easier to change the parameter across all
the version of the BBT (main/mirror and oob/no_oob). So I'll ack:

Acked-by: Brian Norris <computersforpeace at gmail.com>

Thanks,
Brian


From computersforpeace at gmail.com  Fri Sep 14 23:20:55 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 14 Sep 2012 20:20:55 -0700
Subject: [PATCH] mtd: nand: docg4: ecc.read_page() returns 0 on
 uncorrectible errors
In-Reply-To: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>
References: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>
Message-ID: <CAN8TOE9--TGMshgGuWvz=5=TuBDe=Qw-bDn0OfAs_OOujzsDjQ@mail.gmail.com>

On Tue, Sep 11, 2012 at 8:50 AM, Mike Dunn <mikedunn at newsguy.com> wrote:
> diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
> index 793921e..deb718c 100644
> --- a/drivers/mtd/nand/docg4.c
> +++ b/drivers/mtd/nand/docg4.c
> @@ -776,6 +776,8 @@ static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
>         }
>
>         writew(0, docptr + DOC_DATAEND);
> +       if (bits_corrected == -EBADMSG)   /* uncorrectible errors */

s/uncorrectible/uncorrectable/

> +               return 0;
>         return bits_corrected;
>  }
>

With that change:

Acked-by: Brian Norris <computersforpeace at gmail.com>

Also, not a blocker for this patch, but this made me look elsewhere in docg4.c:

static int __init read_factory_bbt(struct mtd_info *mtd)
{
...
        status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
        if (status)
                goto exit;

This could cause problems if there are ever bitflips on the BBT page.
Can the factory BBT contain bitflips?

Brian


From computersforpeace at gmail.com  Fri Sep 14 23:59:25 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 14 Sep 2012 20:59:25 -0700
Subject: ARM: LPC32XX SLC ECC Handling
In-Reply-To: <503E0274.7000205@antcom.de>
References: <50222E55.5070204@embedded-brains.de>
 <1345808311.2848.286.camel@sauron.fi.intel.com>
 <50377989.1050401@antcom.de>
 <1346229208.2848.441.camel@sauron.fi.intel.com>
 <503E0274.7000205@antcom.de>
Message-ID: <CAN8TOE-7e5CuLz6bQduif9m7gv_d_WY4JWA1_P887+29R3mWjQ@mail.gmail.com>

Hi,

On Wed, Aug 29, 2012 at 4:52 AM, Roland Stigge <stigge at antcom.de> wrote:
> On 08/29/2012 10:33 AM, Artem Bityutskiy wrote:
>>>>> the LPC32XX SLC controller has a ECC feature that covers only
>>>>> the main data area, but not the OOB data.  Is it the
>>>>> responsibility of the user to protect its OOB data via an
>>>>> ECC?  The LPC32XX MLC controller on the other hand covers the
>>>>> complete OOB data with its ECC.  How can a user determine if
>>>>> it has to protect its OOB data?

I haven't dealt with this question, since I basically don't support
user data in OOB on my system. I'm basically using only UBI. But see
my other comments below.

>>>> I guess it is good idea to CC the author of the drivers.
>>>
>>> Thanks for CC'ing, would have missed it.
>>>
>>> Yes, it's exactly as Sebastian described - only the MLC
>>> controller covers OOB in ECC.
>>>
>>> At this point, I need to give back the question to the MTD
>>> maintainers: Is there an API how we can help users at this point?
>>> I would be happy to implement it.
>>
>> Well, I guess from the user's POW the driver either protects OOB
>> data with ECC or not. There is no interface for detecting this in
>> MTD, but I do not see why someone could not create it.
>>
>> Am I right that we are talking about the situation when OOB and
>> data areas are covered by different ECCs, or this is about user
>> writing data +oob at one go, and everything is covered by the same
>> ECC?
>
> In the above case of LPC32xx/MLC NAND (not sure if this is common with
> other controllers),

By my experience in interacting with the community, few controllers
have support for protecting OOB with ECC, and even fewer drivers
actual implement it. I think my (out-of-tree) driver was the only one
that could ever reported bitflips for OOB transactions. And for
instance, I added the read_oob/read_oob_raw and
write_oob/write_oob_raw clarification in nand_ecc_ctrl, but there are
no in-tree users that differentiate the two...

> the controller covers 512 (sub)pages plus some OOB
> bytes with a single ECC operation, storing it behind those covered OOB.

My controller is basically the same.

Brian


From computersforpeace at gmail.com  Sat Sep 15 00:39:43 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 14 Sep 2012 21:39:43 -0700
Subject: [PATCH] mtd : add parsing code for one kind of Hynix's nand chip
In-Reply-To: <5031D2D5.7050801@freescale.com>
References: <1334026606-18327-1-git-send-email-b32955@freescale.com>
 <CAN8TOE8xz+t1X-JVC1sOy70k64_gRDU-6DkrnqtDkvdbELHQLQ@mail.gmail.com>
 <502E0417.3040708@freescale.com>
 <CAN8TOE99ncoBgzpDjKXAWuMQ9O25JZhzLixbXtJA+c2T=mro-A@mail.gmail.com>
 <5031D2D5.7050801@freescale.com>
Message-ID: <CAN8TOE-gEvc2Gej=OY=107kq-6h1XTj8WYTb3DzcJ1Lr=pVSuw@mail.gmail.com>

On Sun, Aug 19, 2012 at 11:01 PM, Huang Shijie <b32955 at freescale.com> wrote:
> ? 2012?08?18? 10:51, Brian Norris ??:
>
>> agreed there was no good way to detect these chips without practically
>> hard-coding the ID + parameter configuration. If that's the case, then
>
> Yes, we have to hard-coding the ID for Hynix. But there is already a
> hard-coding for SAMSUNG.

It's not exactly hard-coding, as there is a recognizable pattern that
covers a class of different chips: all Samsung MLC with 6-byte ID
strings.

> so I think the hard-coding is accecpted, aren't we?

We try to do as little hard-coding as possible, as it can blow up as a
larger maintainability problem. But as we see, we may need real
hard-coding.

Brian


From computersforpeace at gmail.com  Sat Sep 15 01:27:42 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Fri, 14 Sep 2012 22:27:42 -0700
Subject: [PATCH] mtd : add parsing code for one kind of Hynix's nand chip
In-Reply-To: <4F8E72B3.1090205@freescale.com>
References: <1334026606-18327-1-git-send-email-b32955@freescale.com>
 <CAN8TOE8xz+t1X-JVC1sOy70k64_gRDU-6DkrnqtDkvdbELHQLQ@mail.gmail.com>
 <4F86416B.4090501@freescale.com>
 <CAN8TOE_yhvB+xnyS_UZn0ko+QySFZJsYBk5w0PB_O37eZaQj9g@mail.gmail.com>
 <4F8E72B3.1090205@freescale.com>
Message-ID: <CAN8TOE9a7vF0D8hGFubLdg+wQAzA2H+mF_QKawnLEj=rj7GumQ@mail.gmail.com>

Hi Huang,

Sorry (again) that this is sitting for a while. I did some more work
this evening on it, and I think I could have a solution. But I still
don't have any real samples, so I'd like you help.

On Wed, Apr 18, 2012 at 12:52 AM, Huang Shijie <b32955 at freescale.com> wrote:
> ? 2012?04?18? 13:00, Brian Norris ??:
> I only have the H27UBG8T2A nand chip in my hand, and test it in the imx28
> board.
> I do not have other nand chips which may also follow the same parsing code
> as the H27UBG8T2A.

Can you capture a full ID string for any Hynix parts you have?
Especially of interest are this H27UBG8T2A and other MLC.

I want to check the ID length and wraparound behavior, since I think
that we can write a rule such that we use this data table for all
Hynix MLC with 6-byte ID strings. I have info for 3 type of Hynix MLC
that follow the 6-byte pattern, and a few 5-byte Hynix MLC that follow
existing patterns.

I appreciate the help and the patience.

Thanks,
Brian


From festevam at gmail.com  Sat Sep 15 09:33:25 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sat, 15 Sep 2012 10:33:25 -0300
Subject: [PATCH 2/2] mtd: mxc_nand: Convert to platform driver
In-Reply-To: <1346855725-31726-2-git-send-email-festevam@gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
 <1346855725-31726-2-git-send-email-festevam@gmail.com>
Message-ID: <CAOMZO5Ct4RNz7F0mnH3RJbO83mDYsckqQANSipqZajj4dnBH_A@mail.gmail.com>

Hi Artem,

On Wed, Sep 5, 2012 at 11:35 AM, Fabio Estevam <festevam at gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
>
> Using module_platform_driver() makes the code smaller and cleaner.
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---

Does this series look fine?

Thanks,

Fabio Estevam


From webde78u at att.net  Sat Sep 15 10:44:49 2012
From: webde78u at att.net (ewfwfe dscdsd)
Date: Sat, 15 Sep 2012 07:44:49 -0700 (PDT)
Subject: Fw: GOOD NEWS!!! OPEN THE ATTACHED FILE FOR MORE DETAILS
Message-ID: <1347720289.61084.YahooMailRC@web184903.mail.gq1.yahoo.com>

An HTML attachment was scrubbed...
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120915/d8a9e445/attachment-0001.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: YAHOO MSN AND BBC LOTTERY BOARD.doc
Type: application/msword
Size: 417280 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120915/d8a9e445/attachment-0001.doc>

From mikedunn at newsguy.com  Sat Sep 15 14:08:07 2012
From: mikedunn at newsguy.com (Mike Dunn)
Date: Sat, 15 Sep 2012 11:08:07 -0700
Subject: [PATCH] mtd: nand: docg4: ecc.read_page() returns 0 on
 uncorrectible errors
In-Reply-To: <CAN8TOE9--TGMshgGuWvz=5=TuBDe=Qw-bDn0OfAs_OOujzsDjQ@mail.gmail.com>
References: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>
 <CAN8TOE9--TGMshgGuWvz=5=TuBDe=Qw-bDn0OfAs_OOujzsDjQ@mail.gmail.com>
Message-ID: <5054C407.1030507@newsguy.com>

Hi Brian, thanks for the Ack.  It seems I was careless with my own driver when I
did the bitflip patches.

BTW, the consequence of this oversight was seen when using mtdchar (e.g.,
mtd-utils 'nanddump') when uncorrectAble bitflips occurred.  The userspace app
just kept repeating the read call, because the prior call indicated that no data
was read.


On 09/14/2012 08:20 PM, Brian Norris wrote:
>> +       if (bits_corrected == -EBADMSG)   /* uncorrectible errors */
> 
> s/uncorrectible/uncorrectable/


Ha!  I actualy looked the word up in the dictionary, and either spelling is
correct.  But yours is more common.


> 
>> +               return 0;
>>         return bits_corrected;
>>  }
>>
> 
> With that change:
> 
> Acked-by: Brian Norris <computersforpeace at gmail.com>
> 
> Also, not a blocker for this patch, but this made me look elsewhere in docg4.c:
> 
> static int __init read_factory_bbt(struct mtd_info *mtd)
> {
> ...
>         status = docg4_read_page(mtd, nand, buf, 0, DOCG4_FACTORY_BBT_PAGE);
>         if (status)
>                 goto exit;
> 
> This could cause problems if there are ever bitflips on the BBT page.
> Can the factory BBT contain bitflips?


Ah, yes, thank you for catching that!!  Overlooked when docg4_read_page() was
changed to return max bitflips; status should be tested for negative value.
Should also try to recover from uncorrectable bitflips (I believe that table is
stored redundantly).

Thanks again,
Mike


From mikedunn at newsguy.com  Sat Sep 15 14:23:33 2012
From: mikedunn at newsguy.com (Mike Dunn)
Date: Sat, 15 Sep 2012 11:23:33 -0700
Subject: [PATCH] mtd/nand/docg4: Add missing HAS_IOMEM dependency
In-Reply-To: <1347662469-1604-1-git-send-email-peterhuewe@gmx.de>
References: <1347662469-1604-1-git-send-email-peterhuewe@gmx.de>
Message-ID: <5054C7A5.5010308@newsguy.com>

Acked-by: Mike Dunn <mikedunn at newsguy.com>

Sorry for the oversight.

Mike


On 09/14/2012 03:41 PM, Peter Huewe wrote:
> While building an allyesconfig for UML I received this error message(s):
>  drivers/mtd/nand/docg4.c: In function 'probe_docg4':
>  drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function
>  'ioremap' [-Werror=implicit-function-declaration]
>  drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from
>  integer without a cast [enabled by default]
>  drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function
>  'iounmap' [-Werror=implicit-function-declaration]
> 
> which is caused by the missing implementations on UML.
> 
> This patch adds this missing HAS_IOMEM dependency and prevents the driver from
> being build on platforms with no HAS_IOMEM
> 
> Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
> ---
>  drivers/mtd/nand/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 8ca4176..3e2f75d 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -356,7 +356,7 @@ config MTD_NAND_DISKONCHIP_BBTWRITE
>  
>  config MTD_NAND_DOCG4
>  	tristate "Support for DiskOnChip G4 (EXPERIMENTAL)"
> -	depends on EXPERIMENTAL
> +	depends on EXPERIMENTAL && HAS_IOMEM
>  	select BCH
>  	select BITREVERSE
>  	help



From mikedunn at newsguy.com  Sat Sep 15 15:26:45 2012
From: mikedunn at newsguy.com (Mike Dunn)
Date: Sat, 15 Sep 2012 12:26:45 -0700
Subject: [PATCH v2] mtd: nand: docg4: ecc.read_page() returns 0 on
 uncorrectable errors
Message-ID: <1347737205-17019-1-git-send-email-mikedunn@newsguy.com>

v2 fixes spelling error

Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectible
bitflips occur.  This is wrong; 0 should be returned in this case.  An error
code should only be returned by this method in the case of a hardware error
(probably -EIO).

Signed-off-by: Mike Dunn <mikedunn at newsguy.com>
Acked-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/docg4.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/docg4.c b/drivers/mtd/nand/docg4.c
index 793921e..deb718c 100644
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -776,6 +776,8 @@ static int read_page(struct mtd_info *mtd, struct nand_chip *nand,
 	}
 
 	writew(0, docptr + DOC_DATAEND);
+	if (bits_corrected == -EBADMSG)	  /* uncorrectable errors */
+		return 0;
 	return bits_corrected;
 }
 
-- 
1.7.3.4



From digbyzunkerbb at yahoo.com  Sun Sep 16 05:20:05 2012
From: digbyzunkerbb at yahoo.com (Obdulia Reading)
Date: Sun, 16 Sep 2012 10:20:05 +0100 (BST)
Subject: Interesting conversation or usual day without anything new? I would
 rather choose the first one. What do u think?)
Message-ID: <1347787205.45047.YahooMailNeo@web132206.mail.ird.yahoo.com>

Hello, 
Name of mine is Obdulia - naughty female with tons of mad ideas in a head! 
What I'm looking for here? You know, I am not sure about this question! It could be just smart conversations with males, maybe flirt, maybe sex or maybe some stuff like building serious relations if we are lucky. Who knows, maybe u r the pal I need?!  
Ok, so long, answer me, hot man. I'll be waiting! 
Obdulia


From dedekind1 at gmail.com  Sun Sep 16 07:43:49 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 16 Sep 2012 14:43:49 +0300
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <20120911132117.GA7015@tuxdriver.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
 <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
 <1347361186.26206.5.camel@sauron.fi.intel.com>
 <20120911132117.GA7015@tuxdriver.com>
Message-ID: <1347795829.2032.1.camel@kyv>

On Tue, 2012-09-11 at 09:21 -0400, John W. Linville wrote:
> OTOH, those exact commits are already in wireless-next (and in
> net-next).  That tree will not be rebased, so you can pull from it
> if you so choose.  But, it would generally be better if you only pull
> from head commits that are already in net-next "just in case". :-)

Thanks, I've pulled 'net-next' to my 'l2-mtd' tree instead, up to the
commit Rafa? needs:

commit 70f389f0fbbde0d00a5ec4ba4817c09e80a3ae47
Merge: 44e42b9 371a004
Author: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date:   Sun Sep 16 14:42:38 2012 +0300

    Merge commit '371a00448f95adaa612cf1a0b31a11e7093bc706' of 'git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git'
    
    We need the following 2 patches from the 'net-next' tree for the BCMA flash
    driver:
    
    371a004 bcma: detect and register NAND flash device
    d57ef3a bcma: detect and register serial flash device
    
    and this is why we are merging the net-next tree (presumably persistent)
    up to commit '371a004'.
    
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120916/da2f05e1/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 16 07:49:49 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 16 Sep 2012 14:49:49 +0300
Subject: [PATCH V2] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
References: <1346699237-414-1-git-send-email-zajec5@gmail.com>
 <1347358840.21359.67.camel@sauron.fi.intel.com>
 <CACna6ryroY=Xbv7+VsRfBYdhRd9P6uz935b9scQqCmTjneM7sQ@mail.gmail.com>
Message-ID: <1347796189.2032.7.camel@kyv>

On Tue, 2012-09-11 at 12:35 +0200, Rafa? Mi?ecki wrote:
> 2012/9/11 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Mon, 2012-09-03 at 21:07 +0200, Rafa? Mi?ecki wrote:
> >> This registers MTD driver for serial flash platform device. Right now it
> >> supports reading only, writing still has to be implemented.
> >> At this point it's marked as BROKEN, because it requires code present in
> >> net tree that wasn't mainlined yet.
> >>
> >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> >
> > What are exactly the changes it depends on? URL? Are they staged for
> > 3.7?
> 
> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=23cb3b2121323443834296a8ecb582b8aeb78d75
> http://git.kernel.org/?p=linux/kernel/git/linville/wireless-testing.git;a=commitdiff;h=d57ef3a6a2eeb88df47e892c66692e3f59722ffe

Please, remove "BROKEN" and re-send the compilable patch against the
l2-mtd.git tree. I've pulled Dave Miller's tree with your patches into
l2-mtd.git. Thanks!

> Well, I just didn't implement writing yet (it's more complicated than
> that trivial reads) and I didn't know the correct values for the above
> ones. I just set writesize to 1 to avoid some WARN/BUG (not remember
> right now).

OK. Just add 'mtd->writebufsize = mtd->writesize = 1; for now.

> In case some other driver handling platform device was loaded earlier.
> Is that wrong?

I do not really understand why you need this - can the general code
really call the removal method and the platform data be NULL? If not,
kill this check - if this happens, this is a bug and we'll end up with
an oops. If it can, please, explain in more details how this can
happen. 

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120916/705c4f24/attachment.sig>

From shawn.guo at linaro.org  Mon Sep 17 01:34:29 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 17 Sep 2012 13:34:29 +0800
Subject: [PATCH 00/34] i.MX multi-platform support
Message-ID: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>

The series enables multi-platform support for imx.  Since the required
frameworks (clk, pwm) and spare_irq have already been adopted on imx,
the series is all about cleaning up mach/* headers.  Along with the
changes, arch/arm/plat-mxc gets merged into arch/arm/mach-imx.

It's based on a bunch of branches (works from others), Rob's initial
multi-platform series, Arnd's platform-data and smp_ops (Marc's) and
imx 3.7 material (Sascha and myself).

It's available on branch below.

  git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform

It's been tested on imx5 and imx6, and only compile-tested on imx2 and
imx3, so testing on imx2/3 are appreciated.

Subsystem maintainers,

I plan to send the whole series via arm-soc tree at the end of 3.7
merge window when all dependant bits hit mainline.  Please have a
look at the patches you get copied and provide ACKs if the changes
are good.  Thanks.

Shawn Guo (34):
  ARM: imx: include board headers in the same folder
  ASoC: mx27vis: retrieve gpio numbers from platform_data
  ARM: imx: move iomux drivers and headers into mach-imx
  ARM: imx: remove unnecessary inclusion from device-imx*.h
  ARM: imx: move platform device code into mach-imx
  ARM: imx: merge plat-mxc into mach-imx
  ARM: imx: include common.h rather than mach/common.h
  ARM: imx: ARM: imx: include cpuidle.h rather than mach/cpuidle.h
  ARM: imx: include iim.h rather than mach/iim.h
  ARM: imx: include iram.h rather than mach/iram.h
  ARM: imx: include ulpi.h rather than mach/ulpi.h
  media: mx1_camera: remove the driver
  ARM: imx: remove mach/dma-mx1-mx2.h
  dma: ipu: rename mach/ipu.h to include/linux/dma/ipu-dma.h
  dma: imx-sdma: remove unneeded mach/hardware.h inclusion
  ASoC: imx-ssi: remove unneeded mach/hardware.h inclusion
  usb: ehci-mxc: remove unneeded mach/hardware.h inclusion
  video: mx3fb: remove unneeded mach/hardware.h inclusion
  watchdog: imx2_wdt: remove unneeded mach/hardware.h inclusion
  i2c: imx: remove mach/hardware.h inclusion
  mtd: mxc_nand: remove mach/hardware.h inclusion
  rtc: mxc_rtc: remove mach/hardware.h inclusion
  dma: imx-dma: use devm_kzalloc and devm_request_irq
  dma: imx-dma: retrieve MEM and IRQ from resources
  dma: imx-dma: remove mach/hardware.h inclusion
  media: mx2_camera: remove dead code in mx2_camera_add_device
  media: mx2_camera: use managed functions to clean up code
  media: mx2_camera: remove mach/hardware.h inclusion
  mmc: mxcmmc: remove mach/hardware.h inclusion
  video: imxfb: remove mach/hardware.h inclusion
  ARM: imx: move debug macros to include/debug
  ARM: imx: include hardware.h rather than mach/hardware.h
  ARM: imx: remove header file mach/irqs.h
  ARM: imx: enable multi-platform build

 .../devicetree/bindings/i2c/fsl-imx-i2c.txt        |    4 +-
 arch/arm/Kconfig                                   |   15 +-
 arch/arm/Kconfig.debug                             |    8 +
 arch/arm/Makefile                                  |    1 -
 arch/arm/boot/dts/imx27.dtsi                       |    4 +-
 arch/arm/boot/dts/imx51.dtsi                       |    4 +-
 arch/arm/boot/dts/imx53.dtsi                       |    6 +-
 arch/arm/boot/dts/imx6q.dtsi                       |    6 +-
 .../mach/debug-macro.S => include/debug/imx.S}     |   33 +-
 arch/arm/{plat-mxc => mach-imx}/3ds_debugboard.c   |    2 +-
 .../include/mach => mach-imx}/3ds_debugboard.h     |    0
 arch/arm/mach-imx/Kconfig                          |   86 ++
 arch/arm/mach-imx/Makefile                         |   23 +-
 arch/arm/{plat-mxc => mach-imx}/avic.c             |    5 +-
 .../include/mach => mach-imx}/board-mx31lilly.h    |    0
 .../include/mach => mach-imx}/board-mx31lite.h     |    0
 .../include/mach => mach-imx}/board-mx31moboard.h  |    0
 .../include/mach => mach-imx}/board-pcm038.h       |    0
 arch/arm/mach-imx/clk-imx1.c                       |   15 +-
 arch/arm/mach-imx/clk-imx21.c                      |   14 +-
 arch/arm/mach-imx/clk-imx25.c                      |   26 +-
 arch/arm/mach-imx/clk-imx27.c                      |   36 +-
 arch/arm/mach-imx/clk-imx31.c                      |   21 +-
 arch/arm/mach-imx/clk-imx35.c                      |   13 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |   15 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    3 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    4 +-
 .../{plat-mxc/include/mach => mach-imx}/common.h   |    0
 arch/arm/mach-imx/cpu-imx25.c                      |    5 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    7 +-
 arch/arm/mach-imx/cpu-imx35.c                      |    5 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpu.c              |    3 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpufreq.c          |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpuidle.c          |    0
 .../{plat-mxc/include/mach => mach-imx}/cpuidle.h  |    0
 arch/arm/mach-imx/devices-imx1.h                   |    3 +-
 arch/arm/mach-imx/devices-imx21.h                  |    3 +-
 arch/arm/mach-imx/devices-imx25.h                  |    3 +-
 arch/arm/mach-imx/devices-imx27.h                  |    3 +-
 arch/arm/mach-imx/devices-imx31.h                  |    3 +-
 arch/arm/mach-imx/devices-imx35.h                  |    3 +-
 arch/arm/mach-imx/devices-imx50.h                  |    3 +-
 arch/arm/mach-imx/devices-imx51.h                  |    3 +-
 arch/arm/{plat-mxc => mach-imx}/devices/Kconfig    |    3 -
 arch/arm/{plat-mxc => mach-imx}/devices/Makefile   |    3 +-
 .../mach => mach-imx/devices}/devices-common.h     |   19 +-
 arch/arm/{plat-mxc => mach-imx/devices}/devices.c  |    1 -
 .../devices/platform-ahci-imx.c                    |    5 +-
 .../{plat-mxc => mach-imx}/devices/platform-fec.c  |    5 +-
 .../devices/platform-flexcan.c                     |    4 +-
 .../devices/platform-fsl-usb2-udc.c                |    5 +-
 .../devices/platform-gpio-mxc.c                    |    2 +-
 .../devices/platform-gpio_keys.c                   |    5 +-
 .../devices/platform-imx-dma.c                     |   23 +-
 .../devices/platform-imx-fb.c                      |   16 +-
 .../devices/platform-imx-i2c.c                     |   31 +-
 .../devices/platform-imx-keypad.c                  |    4 +-
 .../devices/platform-imx-ssi.c                     |    4 +-
 .../devices/platform-imx-uart.c                    |    4 +-
 .../devices/platform-imx2-wdt.c                    |    5 +-
 .../devices/platform-imx21-hcd.c                   |    4 +-
 .../devices/platform-imx_udc.c                     |    4 +-
 .../devices/platform-imxdi_rtc.c                   |    5 +-
 .../devices/platform-ipu-core.c                    |    5 +-
 .../devices/platform-mx2-camera.c                  |   16 +-
 .../devices/platform-mxc-ehci.c                    |    5 +-
 .../devices/platform-mxc-mmc.c                     |   20 +-
 .../devices/platform-mxc_nand.c                    |   25 +-
 .../devices/platform-mxc_pwm.c                     |    4 +-
 .../devices/platform-mxc_rnga.c                    |    4 +-
 .../devices/platform-mxc_rtc.c                     |   13 +-
 .../devices/platform-mxc_w1.c                      |    4 +-
 .../devices/platform-pata_imx.c                    |    4 +-
 .../devices/platform-sdhci-esdhc-imx.c             |    5 +-
 .../devices/platform-spi_imx.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/{plat-mxc => mach-imx}/epit.c             |    6 +-
 .../include/mach => mach-imx}/eukrea-baseboards.h  |    0
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    7 +-
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    7 +-
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    7 +-
 .../{plat-mxc/include/mach => mach-imx}/hardware.h |   26 +-
 arch/arm/mach-imx/hotplug.c                        |    3 +-
 arch/arm/{plat-mxc/include/mach => mach-imx}/iim.h |    0
 arch/arm/mach-imx/imx27-dt.c                       |   11 +-
 arch/arm/mach-imx/imx31-dt.c                       |    5 +-
 arch/arm/mach-imx/imx51-dt.c                       |    9 +-
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h       |   10 -
 arch/arm/mach-imx/iomux-imx31.c                    |    5 +-
 .../include/mach => mach-imx}/iomux-mx1.h          |    2 +-
 .../include/mach => mach-imx}/iomux-mx21.h         |    4 +-
 .../include/mach => mach-imx}/iomux-mx25.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx27.h         |    4 +-
 .../include/mach => mach-imx}/iomux-mx2x.h         |    0
 .../include/mach => mach-imx}/iomux-mx3.h          |    0
 .../include/mach => mach-imx}/iomux-mx35.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx50.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx51.h         |    2 +-
 arch/arm/{plat-mxc => mach-imx}/iomux-v1.c         |    5 +-
 .../{plat-mxc/include/mach => mach-imx}/iomux-v1.h |    0
 arch/arm/{plat-mxc => mach-imx}/iomux-v3.c         |    5 +-
 .../{plat-mxc/include/mach => mach-imx}/iomux-v3.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/iram.h |    0
 arch/arm/{plat-mxc => mach-imx}/iram_alloc.c       |    3 +-
 arch/arm/{plat-mxc => mach-imx}/irq-common.c       |    0
 arch/arm/{plat-mxc => mach-imx}/irq-common.h       |    3 +
 arch/arm/mach-imx/lluart.c                         |    3 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    7 +-
 arch/arm/mach-imx/mach-armadillo5x0.c              |    9 +-
 arch/arm/mach-imx/mach-bug.c                       |    7 +-
 arch/arm/mach-imx/mach-cpuimx27.c                  |   11 +-
 arch/arm/mach-imx/mach-cpuimx35.c                  |    9 +-
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    9 +-
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |   48 +-
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +-
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +-
 arch/arm/mach-imx/mach-imx53.c                     |   11 +-
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +-
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    7 +-
 arch/arm/mach-imx/mach-mx1ads.c                    |    7 +-
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   12 +-
 arch/arm/mach-imx/mach-mx31ads.c                   |    5 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   11 +-
 arch/arm/mach-imx/mach-mx31lite.c                  |   11 +-
 arch/arm/mach-imx/mach-mx31moboard.c               |   14 +-
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    7 +-
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    9 +-
 arch/arm/mach-imx/mach-mx51_babbage.c              |    7 +-
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +-
 arch/arm/mach-imx/mach-pca100.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037_eet.c                |    5 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   13 +-
 arch/arm/mach-imx/mach-pcm043.c                    |    9 +-
 arch/arm/mach-imx/mach-qong.c                      |    6 +-
 arch/arm/mach-imx/mach-scb9328.c                   |    7 +-
 arch/arm/mach-imx/mach-vpr200.c                    |    7 +-
 arch/arm/mach-imx/mm-imx1.c                        |    9 +-
 arch/arm/mach-imx/mm-imx21.c                       |   12 +-
 arch/arm/mach-imx/mm-imx25.c                       |   10 +-
 arch/arm/mach-imx/mm-imx27.c                       |   12 +-
 arch/arm/mach-imx/mm-imx3.c                        |    9 +-
 arch/arm/mach-imx/mm-imx5.c                        |    8 +-
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |   18 -
 arch/arm/mach-imx/mx1-camera-fiq.S                 |   35 -
 arch/arm/{plat-mxc/include/mach => mach-imx}/mx1.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx21.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx25.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx27.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx2x.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx31.h |    0
 arch/arm/mach-imx/mx31lilly-db.c                   |    9 +-
 arch/arm/mach-imx/mx31lite-db.c                    |    9 +-
 arch/arm/mach-imx/mx31moboard-devboard.c           |    9 +-
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    9 +-
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   11 +-
 .../arm/{plat-mxc/include/mach => mach-imx}/mx35.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx3x.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx50.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx51.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx53.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx6q.h |    0
 arch/arm/{plat-mxc/include/mach => mach-imx}/mxc.h |    0
 arch/arm/mach-imx/pcm970-baseboard.c               |    7 +-
 arch/arm/mach-imx/platsmp.c                        |    5 +-
 arch/arm/mach-imx/pm-imx27.c                       |    3 +-
 arch/arm/mach-imx/pm-imx3.c                        |    7 +-
 arch/arm/mach-imx/pm-imx5.c                        |    7 +-
 arch/arm/mach-imx/pm-imx6q.c                       |    5 +-
 arch/arm/{plat-mxc => mach-imx}/ssi-fiq-ksym.c     |    0
 arch/arm/{plat-mxc => mach-imx}/ssi-fiq.S          |    0
 arch/arm/{plat-mxc => mach-imx}/system.c           |    5 +-
 arch/arm/{plat-mxc => mach-imx}/time.c             |    5 +-
 arch/arm/{plat-mxc => mach-imx}/tzic.c             |    6 +-
 arch/arm/{plat-mxc => mach-imx}/ulpi.c             |    2 +-
 .../arm/{plat-mxc/include/mach => mach-imx}/ulpi.h |    0
 arch/arm/plat-mxc/Kconfig                          |   89 --
 arch/arm/plat-mxc/Makefile                         |   24 -
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |   42 -
 arch/arm/plat-mxc/include/mach/irqs.h              |   21 -
 arch/arm/plat-mxc/include/mach/timex.h             |   22 -
 arch/arm/plat-mxc/include/mach/uncompress.h        |  132 ---
 drivers/dma/imx-dma.c                              |  137 +--
 drivers/dma/imx-sdma.c                             |    1 -
 drivers/dma/ipu/ipu_idmac.c                        |    3 +-
 drivers/dma/ipu/ipu_irq.c                          |    3 +-
 drivers/i2c/busses/i2c-imx.c                       |   40 +-
 drivers/media/video/Kconfig                        |   12 -
 drivers/media/video/Makefile                       |    1 -
 drivers/media/video/mx1_camera.c                   |  889 --------------------
 drivers/media/video/mx2_camera.c                   |  240 +++---
 drivers/media/video/mx3_camera.c                   |    2 +-
 drivers/mmc/host/mxcmmc.c                          |   31 +-
 drivers/mtd/nand/mxc_nand.c                        |   86 +-
 drivers/rtc/rtc-mxc.c                              |   34 +-
 drivers/usb/host/ehci-mxc.c                        |    1 -
 drivers/video/imxfb.c                              |   38 +-
 drivers/video/mx3fb.c                              |    3 +-
 drivers/watchdog/imx2_wdt.c                        |    1 -
 .../mach/ipu.h => include/linux/dma/ipu-dma.h      |    6 +-
 include/linux/platform_data/asoc-mx27vis.h         |   11 +
 include/linux/platform_data/camera-mx1.h           |   35 -
 sound/soc/fsl/imx-pcm-fiq.c                        |    3 +-
 sound/soc/fsl/imx-ssi.c                            |    1 -
 sound/soc/fsl/mx27vis-aic32x4.c                    |   42 +-
 219 files changed, 1149 insertions(+), 2170 deletions(-)
 rename arch/arm/{plat-mxc/include/mach/debug-macro.S => include/debug/imx.S} (59%)
 rename arch/arm/{plat-mxc => mach-imx}/3ds_debugboard.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/3ds_debugboard.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/avic.c (98%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31lilly.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31lite.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31moboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-pcm038.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/common.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/cpu.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/cpufreq.c (99%)
 rename arch/arm/{plat-mxc => mach-imx}/cpuidle.c (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/cpuidle.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/Kconfig (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/Makefile (96%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/devices}/devices-common.h (96%)
 rename arch/arm/{plat-mxc => mach-imx/devices}/devices.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-ahci-imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-fec.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-flexcan.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-fsl-usb2-udc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-gpio-mxc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-gpio_keys.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-dma.c (63%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-fb.c (79%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-i2c.c (77%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-keypad.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-ssi.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-uart.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx2-wdt.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx21-hcd.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx_udc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imxdi_rtc.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-ipu-core.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mx2-camera.c (83%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc-ehci.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc-mmc.c (76%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_nand.c (74%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_pwm.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_rnga.c (95%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_rtc.c (77%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_w1.c (95%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-pata_imx.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-sdhci-esdhc-imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-spi_imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/epit.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/eukrea-baseboards.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/hardware.h (94%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iim.h (100%)
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx1.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx21.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx25.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx27.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx35.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx50.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx51.h (99%)
 rename arch/arm/{plat-mxc => mach-imx}/iomux-v1.c (98%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-v1.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/iomux-v3.c (97%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-v3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iram.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/iram_alloc.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/irq-common.c (100%)
 rename arch/arm/{plat-mxc => mach-imx}/irq-common.h (94%)
 delete mode 100644 arch/arm/mach-imx/mx1-camera-fiq-ksym.c
 delete mode 100644 arch/arm/mach-imx/mx1-camera-fiq.S
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx31.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx3x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx6q.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mxc.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/ssi-fiq-ksym.c (100%)
 rename arch/arm/{plat-mxc => mach-imx}/ssi-fiq.S (100%)
 rename arch/arm/{plat-mxc => mach-imx}/system.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/time.c (99%)
 rename arch/arm/{plat-mxc => mach-imx}/tzic.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/ulpi.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/ulpi.h (100%)
 delete mode 100644 arch/arm/plat-mxc/Kconfig
 delete mode 100644 arch/arm/plat-mxc/Makefile
 delete mode 100644 arch/arm/plat-mxc/devices/platform-mx1-camera.c
 delete mode 100644 arch/arm/plat-mxc/include/mach/irqs.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/timex.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/uncompress.h
 delete mode 100644 drivers/media/video/mx1_camera.c
 rename arch/arm/plat-mxc/include/mach/ipu.h => include/linux/dma/ipu-dma.h (97%)
 create mode 100644 include/linux/platform_data/asoc-mx27vis.h
 delete mode 100644 include/linux/platform_data/camera-mx1.h

-- 
1.7.9.5



From shawn.guo at linaro.org  Mon Sep 17 01:34:50 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Mon, 17 Sep 2012 13:34:50 +0800
Subject: [PATCH 21/34] mtd: mxc_nand: remove mach/hardware.h inclusion
In-Reply-To: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1347860103-4141-22-git-send-email-shawn.guo@linaro.org>

It changes the driver to use platform_device_id rather than cpu_is_xxx
to determine the controller type, and updates the platform code
accordingly.

As the result, mach/hardware.h inclusion gets removed from the driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: linux-mtd at lists.infradead.org
---
 arch/arm/mach-imx/clk-imx21.c                 |    2 +-
 arch/arm/mach-imx/clk-imx25.c                 |    2 +-
 arch/arm/mach-imx/clk-imx27.c                 |    2 +-
 arch/arm/mach-imx/clk-imx31.c                 |    2 +-
 arch/arm/mach-imx/clk-imx35.c                 |    2 +-
 arch/arm/mach-imx/clk-imx51-imx53.c           |    2 +-
 arch/arm/mach-imx/devices/devices-common.h    |    1 +
 arch/arm/mach-imx/devices/platform-mxc_nand.c |   20 +++---
 arch/arm/mach-imx/imx27-dt.c                  |    2 +-
 drivers/mtd/nand/mxc_nand.c                   |   86 +++++++++++++++----------
 10 files changed, 71 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 09fc31c..96a4788 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -162,7 +162,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
 	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
 	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
 	clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 54edac0..1aea073 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -198,7 +198,7 @@ int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-	clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
 	/* i.mx25 has the i.mx35 type cspi */
 	clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
 	clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index d9aac0f..6ae2868 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -239,7 +239,7 @@ int __init mx27_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-	clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
 	clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
 	clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
 	clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 76e6462..729d1a9 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -127,7 +127,7 @@ int __init mx31_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
 	clk_register_clkdev(clk[epit1_gate], "epit", NULL);
 	clk_register_clkdev(clk[epit2_gate], "epit", NULL);
-	clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
 	clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index ee25812..fec48e6 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -256,7 +256,7 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
 	clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
 
 	clk_prepare_enable(clk[spba_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index c8ee7d2..22afd5f 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -272,7 +272,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
-	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
+	clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index b0f4747..d9717b3 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -239,6 +239,7 @@ struct platform_device *__init imx_add_mxc_mmc(
 
 #include <linux/platform_data/mtd-mxc_nand.h>
 struct imx_mxc_nand_data {
+	const char *devid;
 	/*
 	 * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
 	 * machines but don't change existing devices as the nand device usually
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index eb73b82..cec6961 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -10,15 +10,17 @@
 #include <mach/hardware.h>
 #include "devices-common.h"
 
-#define imx_mxc_nand_data_entry_single(soc, _size)			\
+#define imx_mxc_nand_data_entry_single(soc, _devid, _size)		\
 	{								\
+		.devid = _devid,					\
 		.iobase = soc ## _NFC_BASE_ADDR,			\
 		.iosize = _size,					\
 		.irq = soc ## _INT_NFC					\
 	}
 
-#define imx_mxc_nandv3_data_entry_single(soc, _size)			\
+#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size)		\
 	{								\
+		.devid = _devid,					\
 		.id = -1,						\
 		.iobase = soc ## _NFC_BASE_ADDR,			\
 		.iosize = _size,					\
@@ -28,32 +30,32 @@
 
 #ifdef CONFIG_SOC_IMX21
 const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX21, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
 #ifdef CONFIG_SOC_IMX25
 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX25, SZ_8K);
+	imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
 #endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX27, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
 #ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX31, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K);
 #endif
 
 #ifdef CONFIG_SOC_IMX35
 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX35, SZ_8K);
+	imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
 #endif
 
 #ifdef CONFIG_SOC_IMX51
 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-	imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
+	imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
 #endif
 
 struct platform_device *__init imx_add_mxc_nand(
@@ -76,7 +78,7 @@ struct platform_device *__init imx_add_mxc_nand(
 			.flags = IORESOURCE_IRQ,
 		},
 	};
-	return imx_add_platform_device("mxc_nand", data->id,
+	return imx_add_platform_device(data->devid, data->id,
 			res + !data->axibase,
 			ARRAY_SIZE(res) - !data->axibase,
 			pdata, sizeof(*pdata));
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 43fbf86..a6c288e 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -29,7 +29,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
 	OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
 	OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
-	OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "mxc_nand.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 5683604..d5f8f01 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -37,15 +37,9 @@
 
 #include <asm/mach/flash.h>
 #include <linux/platform_data/mtd-mxc_nand.h>
-#include <mach/hardware.h>
 
 #define DRIVER_NAME "mxc_nand"
 
-#define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
-#define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
-#define nfc_is_v3_2()		(cpu_is_mx51() || cpu_is_mx53())
-#define nfc_is_v3()		nfc_is_v3_2()
-
 /* Addresses for NFC registers */
 #define NFC_V1_V2_BUF_SIZE		(host->regs + 0x00)
 #define NFC_V1_V2_BUF_ADDR		(host->regs + 0x04)
@@ -1260,6 +1254,45 @@ static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
 	.eccsize = 0,
 };
 
+static inline int is_imx21_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx21_nand_devtype_data;
+}
+
+static inline int is_imx27_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx27_nand_devtype_data;
+}
+
+static inline int is_imx25_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx25_nand_devtype_data;
+}
+
+static inline int is_imx51_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx51_nand_devtype_data;
+}
+
+static struct platform_device_id mxcnd_devtype[] = {
+	{
+		.name = "imx21-nand",
+		.driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
+	}, {
+		.name = "imx27-nand",
+		.driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
+	}, {
+		.name = "imx25-nand",
+		.driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
+	}, {
+		.name = "imx51-nand",
+		.driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
+
 #ifdef CONFIG_OF_MTD
 static const struct of_device_id mxcnd_dt_ids[] = {
 	{
@@ -1311,30 +1344,6 @@ static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
 }
 #endif
 
-static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
-{
-	struct mxc_nand_platform_data *pdata = host->dev->platform_data;
-
-	if (!pdata)
-		return -ENODEV;
-
-	host->pdata = *pdata;
-
-	if (nfc_is_v1()) {
-		if (cpu_is_mx21())
-			host->devtype_data = &imx21_nand_devtype_data;
-		else
-			host->devtype_data = &imx27_nand_devtype_data;
-	} else if (nfc_is_v21()) {
-		host->devtype_data = &imx25_nand_devtype_data;
-	} else if (nfc_is_v3_2()) {
-		host->devtype_data = &imx51_nand_devtype_data;
-	} else
-		BUG();
-
-	return 0;
-}
-
 static int __init mxcnd_probe(struct platform_device *pdev)
 {
 	struct nand_chip *this;
@@ -1396,8 +1405,16 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	host->main_area0 = host->base;
 
 	err = mxcnd_probe_dt(host);
-	if (err > 0)
-		err = mxcnd_probe_pdata(host);
+	if (err > 0) {
+		struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
+		if (pdata) {
+			host->pdata = *pdata;
+			host->devtype_data = (struct mxc_nand_devtype_data *)
+						pdev->id_entry->driver_data;
+		} else {
+			err = -ENODEV;
+		}
+	}
 	if (err < 0)
 		goto eirq;
 
@@ -1473,7 +1490,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	}
 
 	/* first scan to find the device and get the page size */
-	if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
+	if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
 		err = -ENXIO;
 		goto escan;
 	}
@@ -1487,7 +1504,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 		this->ecc.layout = host->devtype_data->ecclayout_4k;
 
 	if (this->ecc.mode == NAND_ECC_HW) {
-		if (nfc_is_v1())
+		if (is_imx21_nfc(host) || is_imx27_nfc(host))
 			this->ecc.strength = 1;
 		else
 			this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
@@ -1549,6 +1566,7 @@ static struct platform_driver mxcnd_driver = {
 		   .owner = THIS_MODULE,
 		   .of_match_table = of_match_ptr(mxcnd_dt_ids),
 	},
+	.id_table = mxcnd_devtype,
 	.remove = __devexit_p(mxcnd_remove),
 };
 
-- 
1.7.9.5



From s.hauer at pengutronix.de  Mon Sep 17 03:51:38 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 17 Sep 2012 09:51:38 +0200
Subject: [PATCH 00/34] i.MX multi-platform support
In-Reply-To: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120917075138.GN6180@pengutronix.de>

Hi Shawn,

On Mon, Sep 17, 2012 at 01:34:29PM +0800, Shawn Guo wrote:
> The series enables multi-platform support for imx.  Since the required
> frameworks (clk, pwm) and spare_irq have already been adopted on imx,
> the series is all about cleaning up mach/* headers.  Along with the
> changes, arch/arm/plat-mxc gets merged into arch/arm/mach-imx.
> 
> It's based on a bunch of branches (works from others), Rob's initial
> multi-platform series, Arnd's platform-data and smp_ops (Marc's) and
> imx 3.7 material (Sascha and myself).
> 
> It's available on branch below.
> 
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform
> 
> It's been tested on imx5 and imx6, and only compile-tested on imx2 and
> imx3, so testing on imx2/3 are appreciated.

Great work! This really pushes the i.MX architecture one step closer to
a clean code base.

I gave it a test on i.MX1, i.MX27, i.MX31 and i.MX35. All run fine, but
the last patch breaks the imx_v4_v5_defconfig: Somehow it now defaults
to ARMv7 based machines. I haven't looked into it, just reenabled
ARMv4/ARMv5 and the boards again -> works. The config should be updated
with the last patch.

I'm fine with the changes to mx2-camera, but Javier should give his ok
to it, he has worked on it quite a lot recently.

One other issue related to imx-dma, see comment to that patch.

Otherwise:

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
Tested-by: Sascha Hauer <s.hauer at pengutronix.de>

Thanks
 Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From zajec5 at gmail.com  Mon Sep 17 05:50:49 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Mon, 17 Sep 2012 11:50:49 +0200
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
Message-ID: <1347875449-19318-1-git-send-email-zajec5@gmail.com>

This registers MTD driver for serial flash platform device. Right now it
supports reading only, writing still has to be implemented.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
V2: fix mem leak (add failure path in init)
    signed-off-by
V3: drop BROKEN
    drop useless check in bcm47xxsflash_remove
    marm flash memory as ROM (until we implement writing)
---
 drivers/mtd/devices/Kconfig                 |    8 ++
 drivers/mtd/devices/Makefile                |    1 +
 drivers/mtd/devices/bcm47xxsflash.c         |  131 +++++++++++++++++++++++++++
 include/linux/bcma/bcma_driver_chipcommon.h |    2 +
 4 files changed, 142 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/devices/bcm47xxsflash.c

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 6cc5a1a..ce6e3d4 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -120,6 +120,14 @@ config MTD_SST25L
 	  Set up your spi devices with the right board-specific platform data,
 	  if you want to specify device partitioning.
 
+config MTD_BCM47XXSFLASH
+	tristate "Support for serial flash on BCMA bus"
+	depends on BCMA_SFLASH
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  serial flash memories.
+
 config MTD_SLRAM
 	tristate "Uncached system RAM"
 	help
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index a4dd1d8..395733a 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_DATAFLASH)	+= mtd_dataflash.o
 obj-$(CONFIG_MTD_M25P80)	+= m25p80.o
 obj-$(CONFIG_MTD_SPEAR_SMI)	+= spear_smi.o
 obj-$(CONFIG_MTD_SST25L)	+= sst25l.o
+obj-$(CONFIG_MTD_BCM47XXSFLASH)	+= bcm47xxsflash.o
 
 CFLAGS_docg3.o			+= -I$(src)
\ No newline at end of file
diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
new file mode 100644
index 0000000..f711a51
--- /dev/null
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -0,0 +1,131 @@
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
+			      size_t *retlen, u_char *buf)
+{
+	struct bcma_sflash *sflash = mtd->priv;
+	size_t bytes_read = 0;
+	u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
+	int i;
+	size_t unaligned_before, unaligned_after;
+
+	/* Check address range */
+	if ((from + len) > mtd->size)
+		return -EINVAL;
+
+	unaligned_before = from & 0x3;
+	unaligned_after = (from + len) & 0x3;
+
+	for (i = 0; i < unaligned_before; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+	for (i = from - unaligned_before; i < from + len - unaligned_after;
+	     i += 4) {
+		*(u32 *)buf = readl((u32 *)src);
+		buf += 4;
+		src += 4;
+		bytes_read += 4;
+	}
+	for (i = 0; i < unaligned_after; i++) {
+		*buf = readb(src);
+		buf++;
+		src++;
+		bytes_read++;
+	}
+
+	*retlen = bytes_read;
+
+	return 0;
+}
+
+static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
+				   struct mtd_info *mtd)
+{
+	mtd->priv = sflash;
+	mtd->name = "bcm47xxsflash";
+	mtd->owner = THIS_MODULE;
+	mtd->type = MTD_ROM;
+	mtd->size = sflash->size;
+	mtd->_read = bcm47xxsflash_read;
+
+	/* TODO: implement writing support and verify/change following code */
+	mtd->flags = MTD_CAP_ROM;
+	mtd->writebufsize = mtd->writesize = 1;
+}
+
+static int bcm47xxsflash_probe(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+	int err;
+
+	sflash->mtd = kzalloc(sizeof(struct mtd_info), GFP_KERNEL);
+	if (!sflash->mtd) {
+		err = -ENOMEM;
+		goto out;
+	}
+	bcm47xxsflash_fill_mtd(sflash, sflash->mtd);
+
+	err = mtd_device_parse_register(sflash->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		goto err_dev_reg;
+	}
+
+	return 0;
+
+err_dev_reg:
+	kfree(sflash->mtd);
+out:
+	return err;
+}
+
+static int __devexit bcm47xxsflash_remove(struct platform_device *pdev)
+{
+	struct bcma_sflash *sflash = dev_get_platdata(&pdev->dev);
+
+	mtd_device_unregister(sflash->mtd);
+	kfree(sflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcma_sflash_driver = {
+	.remove = __devexit_p(bcm47xxsflash_remove),
+	.driver = {
+		.name = "bcma_sflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxsflash_init(void)
+{
+	int err;
+
+	err = platform_driver_probe(&bcma_sflash_driver, bcm47xxsflash_probe);
+	if (err)
+		pr_err("Failed to register BCMA serial flash driver: %d\n",
+		       err);
+
+	return err;
+}
+
+static void __exit bcm47xxsflash_exit(void)
+{
+	platform_driver_unregister(&bcma_sflash_driver);
+}
+
+module_init(bcm47xxsflash_init);
+module_exit(bcm47xxsflash_exit);
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 6ba45d2..1cf1749 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -522,6 +522,8 @@ struct bcma_sflash {
 	u32 blocksize;
 	u16 numblocks;
 	u32 size;
+
+	struct mtd_info *mtd;
 };
 #endif
 
-- 
1.7.7



From notasas at gmail.com  Mon Sep 17 06:52:12 2012
From: notasas at gmail.com (Grazvydas Ignotas)
Date: Mon, 17 Sep 2012 13:52:12 +0300
Subject: [PATCH] mtd: nand: omap2: Fix the nand-disk led trigger
In-Reply-To: <20120913150614.GC22993@renkinjitsu.usine.8d.com>
References: <20120913150614.GC22993@renkinjitsu.usine.8d.com>
Message-ID: <CANOLnOOfwe1EvG1VHAZbtaC2xAD7_Rc6PqCWrs2cwEqauun8KA@mail.gmail.com>

On Thu, Sep 13, 2012 at 6:06 PM, Raphael Assenat <raph at 8d.com> wrote:
> When the omap2 nand flash driver is used, the nand-disk led trigger does not
> work due to nand_wait_ready not being called.

I think better solution is just to delete omap_wait() function, which
is just a copy of nand_wait() without LED and oops handling. If
waitfunc is not set by the driver, default nand_wait is used by the
core.


> This patch exports the trigger from nand_base.c, letting specific drivers
> such omap2 control the led as appropriate.
>
> Signed-off-by: Raphael Assenat <raph at 8d.com>
>
> diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
> index a11253a..b967c45 100644
> --- a/drivers/mtd/nand/nand_base.c
> +++ b/drivers/mtd/nand/nand_base.c
> @@ -103,7 +103,7 @@ static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
>   * For devices which display every fart in the system on a separate LED. Is
>   * compiled away when LED support is disabled.
>   */
> -DEFINE_LED_TRIGGER(nand_led_trigger);
> +DEFINE_LED_TRIGGER_GLOBAL(nand_led_trigger);
>
>  static int check_offs_len(struct mtd_info *mtd,
>                                         loff_t ofs, uint64_t len)
> diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
> index ac4fd75..6aa683f 100644
> --- a/drivers/mtd/nand/omap2.c
> +++ b/drivers/mtd/nand/omap2.c
> @@ -19,6 +19,7 @@
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
> +#include <linux/leds.h>
>  #include <linux/omap-dma.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> @@ -254,6 +255,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
>         int ret = 0;
>         u32 *p = (u32 *)buf;
>
> +       led_trigger_event(nand_led_trigger, LED_FULL);
> +
>         /* take care of subpage reads */
>         if (len % 4) {
>                 if (info->nand.options & NAND_BUSWIDTH_16)
> @@ -284,6 +287,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
>                 /* disable and stop the PFPW engine */
>                 gpmc_prefetch_reset(info->gpmc_cs);
>         }
> +
> +       led_trigger_event(nand_led_trigger, LED_OFF);
>  }
>
>  /**
> @@ -302,6 +307,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
>         u16 *p = (u16 *)buf;
>         unsigned long tim, limit;
>
> +       led_trigger_event(nand_led_trigger, LED_FULL);
> +
>         /* take care of subpage writes */
>         if (len % 2 != 0) {
>                 writeb(*buf, info->nand.IO_ADDR_W);
> @@ -335,6 +342,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
>                 /* disable and stop the PFPW engine */
>                 gpmc_prefetch_reset(info->gpmc_cs);
>         }
> +
> +       led_trigger_event(nand_led_trigger, LED_OFF);
>  }
>
>  /*
> @@ -366,6 +375,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
>         unsigned n;
>         int ret;
>
> +       led_trigger_event(nand_led_trigger, LED_FULL);
> +
>         if (addr >= high_memory) {
>                 struct page *p1;
>
> @@ -417,6 +428,8 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
>         gpmc_prefetch_reset(info->gpmc_cs);
>
>         dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
> +
> +       led_trigger_event(nand_led_trigger, LED_OFF);
>         return 0;
>
>  out_copy_unmap:
> @@ -428,6 +441,9 @@ out_copy:
>         else
>                 is_write == 0 ? omap_read_buf8(mtd, (u_char *) addr, len)
>                         : omap_write_buf8(mtd, (u_char *) addr, len);
> +
> +       led_trigger_event(nand_led_trigger, LED_OFF);
> +
>         return 0;
>  }
>
> @@ -886,6 +902,8 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
>         else
>                 timeo += (HZ * 20) / 1000;
>
> +       led_trigger_event(nand_led_trigger, LED_FULL);
> +
>         gpmc_nand_write(info->gpmc_cs,
>                         GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
>         while (time_before(jiffies, timeo)) {
> @@ -894,6 +912,7 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
>                         break;
>                 cond_resched();
>         }
> +       led_trigger_event(nand_led_trigger, LED_OFF);
>
>         status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA);
>         return status;
> @@ -909,6 +928,8 @@ static int omap_dev_ready(struct mtd_info *mtd)
>         struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
>                                                         mtd);
>
> +       led_trigger_event(nand_led_trigger, LED_FULL);
> +
>         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
>         if ((val & 0x100) == 0x100) {
>                 /* Clear IRQ Interrupt */
> @@ -923,6 +944,8 @@ static int omap_dev_ready(struct mtd_info *mtd)
>                         val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
>                 }
>         }
> +
> +       led_trigger_event(nand_led_trigger, LED_OFF);
>
>         return 1;
>  }
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 57977c6..321b7ef 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -23,6 +23,7 @@
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/flashchip.h>
>  #include <linux/mtd/bbm.h>
> +#include <linux/leds.h>
>
>  struct mtd_info;
>  struct nand_flash_dev;
> @@ -48,6 +49,9 @@ extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>  /* unlocks specified locked blocks */
>  extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
>
> +/* LED trigger for NAND drivers not using nand_wait_ready. */
> +extern DEFINE_LED_TRIGGER_GLOBAL(nand_led_trigger);
> +
>  /* The maximum number of NAND chips in an array */
>  #define NAND_MAX_CHIPS         8
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Gra?vydas


From arnd at arndb.de  Mon Sep 17 07:38:13 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Mon, 17 Sep 2012 11:38:13 +0000
Subject: [PATCH 00/34] i.MX multi-platform support
In-Reply-To: <20120917075138.GN6180@pengutronix.de>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
 <20120917075138.GN6180@pengutronix.de>
Message-ID: <201209171138.13327.arnd@arndb.de>

On Monday 17 September 2012, Sascha Hauer wrote:
> On Mon, Sep 17, 2012 at 01:34:29PM +0800, Shawn Guo wrote:
> > The series enables multi-platform support for imx.  Since the required
> > frameworks (clk, pwm) and spare_irq have already been adopted on imx,
> > the series is all about cleaning up mach/* headers.  Along with the
> > changes, arch/arm/plat-mxc gets merged into arch/arm/mach-imx.
> > 
> > It's based on a bunch of branches (works from others), Rob's initial
> > multi-platform series, Arnd's platform-data and smp_ops (Marc's) and
> > imx 3.7 material (Sascha and myself).
> > 
> > It's available on branch below.
> > 
> >   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform
> > 
> > It's been tested on imx5 and imx6, and only compile-tested on imx2 and
> > imx3, so testing on imx2/3 are appreciated.
> 
> Great work! This really pushes the i.MX architecture one step closer to
> a clean code base.

I agree, this series is wonderful, I thought it would take much longer
to get this far.

Two small comments on the last two patches from me, but overall I really
love it.

Acked-by: Arnd Bergmann <arnd at arndb.de>


From motobud at gmail.com  Mon Sep 17 09:34:02 2012
From: motobud at gmail.com (Brent Taylor)
Date: Mon, 17 Sep 2012 08:34:02 -0500
Subject: UBIFS Recovery Issue: 'grab_empty_leb: could not find an empty
 LEB'
In-Reply-To: <CAP+RiCBRopbShAGf_fWCvK2R=uPPR1j4Pz12JfJxdEMUjwofNw@mail.gmail.com>
References: <CAP+RiCC1afVbKAZESMcZGd1G3+7aKuLTQGggOEFGZxQM6o+QQA@mail.gmail.com>
 <1346413469.9709.44.camel@sauron.fi.intel.com>
 <CAP+RiCBRopbShAGf_fWCvK2R=uPPR1j4Pz12JfJxdEMUjwofNw@mail.gmail.com>
Message-ID: <CAP+RiCAzOKvV00F8zppPxrL1CHKqR6eU2g08F+s_wm2R6jJ7Cg@mail.gmail.com>

On Fri, Aug 31, 2012 at 8:23 AM, Brent Taylor <motobud at gmail.com> wrote:
>
> I'm currently running the test again, and will know the results on wed, sept 5.  If I do see a failure, I can send you an image, the problem is that the image will be either 256MB, 1GB, or 15GB depending on which partition fails.  Will either of the larger sizes be an issue for you?  What would be the best way to get the image to you?
>
> Thanks for your time.
> Bud
>
> On Aug 31, 2012 7:39 AM, "Artem Bityutskiy" <dedekind1 at gmail.com> wrote:
>>
>> On Mon, 2012-07-16 at 13:22 -0500, Brent Taylor wrote:
>> > I'm developing on custom hardware using an at91sam9g45 processor with
>> > 64 MB of RAM and 64 MB of NOR flash running Linux 3.0.13.
>> >
>> > I'm doing some power-cycle testing and after several hours, UBIFS
>> > failed to mount the root partition and printed the message
>> > "grab_empty_leb: could not find an empty LEB".  The system boots and
>> > starts a script that will power cycle the board anytime between 10 and
>> > 20 seconds after the script has started.  Just before a power cycle
>> > occurs, syslog and our main process are the only processes that could
>> > be writing to disk.
>> >
>> I was trying to do power cut emulation testing with mtdram, and I see
>> there are some issues which do not seem to exist on NAND. But they are
>> different to yours. I remember I saw these -ENOSPC issues in the past,
>> but they were very difficult to reproduce.
>>
>> I will try to investigate why power-cut emulation testing fails on
>> mtdram, but I have limited amount of time and I do not know when I'll be
>> able to do this.
>>
>> --
>> Best Regards,
>> Artem Bityutskiy


Artem,
   I was finally able to capture the issue again with linux version
3.5.1, and I now have a 64MB mtd image for you to look at.  The issue
occurred in the root filesystem this time.  Let me know what's the
best way to get this image to you.  The image was retrieved from a NOR
flash chip instead of a NAND flash chip, but I've seen the error on
both which leads me to believe it's not a flash driver issue and it's
something in the UBIFS subsystem.  If there is more data you need from
me to help track this down, just let me know.

Thanks for your time,
Bud


From marex at denx.de  Mon Sep 17 10:09:56 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 17 Sep 2012 16:09:56 +0200
Subject: [PATCH] mtd: m25p80: Disable 4K erase for s25sl032p, s25sl064p
In-Reply-To: <1346729496-3303-1-git-send-email-marex@denx.de>
References: <1346729496-3303-1-git-send-email-marex@denx.de>
Message-ID: <201209171609.57109.marex@denx.de>

Bump, do you think this can be queued for 3.7 please?

> Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011,
> section 9.17:
> 
> A 64 kB sector erase (D8h) command issued on 4 kB or 8 kB erase
> sectors will erase all sectors in the specified 64 kB region.
> However, please note that a 4 kB sector erase (20h) or 8 kB
> sector erase (40h) command will not work on a 64 kB sector.
> 
> Refering further to Table 8.1 and Table 8.2, it is clearly seen
> that most of the sectors are 64kB, therefore disable this 4K
> erase support since it's valid only on first/last sectors.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Cc: David Woodhouse <david.woodhouse at intel.com>
> ---
>  drivers/mtd/devices/m25p80.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index c433051..9930e23 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -661,8 +661,8 @@ static const struct spi_device_id m25p_ids[] = {
>  	/* Spansion -- single (large) sector size only, at least
>  	 * for the chips listed here (without boot sectors).
>  	 */
> -	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, SECT_4K) },
> -	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, SECT_4K) },
> +	{ "s25sl032p",  INFO(0x010215, 0x4d00,  64 * 1024,  64, 0) },
> +	{ "s25sl064p",  INFO(0x010216, 0x4d00,  64 * 1024, 128, 0) },
>  	{ "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
>  	{ "s25fl256s1", INFO(0x010219, 0x4d01,  64 * 1024, 512, 0) },
>  	{ "s25fl512s",  INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },

Best regards,
Marek Vasut


From marex at denx.de  Mon Sep 17 10:10:28 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 17 Sep 2012 16:10:28 +0200
Subject: [PATCH V5] mtd: m25p80: Make fast read configurable via DT
In-Reply-To: <1345923416-9293-1-git-send-email-marex@denx.de>
References: <1345923416-9293-1-git-send-email-marex@denx.de>
Message-ID: <201209171610.28410.marex@denx.de>

Bump, do you think we can get this into 3.7 please?

> Add DT property "m25p,fast-read" that signalises the particular
> chip supports "fast read" opcode.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Cc: David Woodhouse <david.woodhouse at intel.com>
> ---
>  Documentation/devicetree/bindings/mtd/m25p80.txt |   29 ++++++++++++++++++
>  drivers/mtd/devices/m25p80.c                     |   34
> +++++++++++++--------- 2 files changed, 50 insertions(+), 13 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/mtd/m25p80.txt
> 
> V2: Add documentation for the DT property.
> V3: Use of_property_get_bool() instead of of_find_property().
> V4: Adjust the documentation's "compatible:" section, make it not
>     Linux-specific, but keep the reference to Linux's list of
>     supported devices. Also, use the default name, spansion,m25p80
>     in the example.
> V5: Enclose of_property_read_bool() into CONFIG_OF for systems that do not
>     use OF / Device Tree .
> 
> diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt
> b/Documentation/devicetree/bindings/mtd/m25p80.txt new file mode 100644
> index 0000000..701bb58
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/m25p80.txt
> @@ -0,0 +1,29 @@
> +* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
> +
> +Required properties:
> +- #address-cells, #size-cells : Must be present if the device has
> sub-nodes +  representing partitions.
> +- compatible : Should be the manufacturer and the name of the chip. Bear
> in mind +               the DT binding is not Linux-only, but in case of
> Linux, see the +               "m25p_ids" table in
> drivers/mtd/devices/m25p80.c for the list of +               supported
> chips.
> +- reg : Chip-Select number
> +- spi-max-frequency : Maximum frequency of the SPI bus the chip can
> operate at +
> +Optional properties:
> +- m25p,fast-read : Use the "fast read" opcode to read data from the chip
> instead +                   of the usual "read" opcode. This opcode isn
> not supported by +                   all chips and support for it can not
> be detected at runtime. +                   Refer to your chips' datasheet
> to check if this is supported +                   by your chip.
> +
> +Example:
> +
> +	flash: m25p80 at 0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "spansion,m25p80";
> +		reg = <0>;
> +		spi-max-frequency = <40000000>;
> +		m25p,fast-read;
> +	};
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index d16f75c..c433051 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -73,14 +73,6 @@
>  #define	MAX_READY_WAIT_JIFFIES	(40 * HZ)	/* M25P16 specs 40s max 
chip
> erase */ #define	MAX_CMD_SIZE		5
> 
> -#ifdef CONFIG_M25PXX_USE_FAST_READ
> -#define OPCODE_READ 	OPCODE_FAST_READ
> -#define FAST_READ_DUMMY_BYTE 1
> -#else
> -#define OPCODE_READ 	OPCODE_NORM_READ
> -#define FAST_READ_DUMMY_BYTE 0
> -#endif
> -
>  #define JEDEC_MFR(_jedec_id)	((_jedec_id) >> 16)
> 
>  /*************************************************************************
> ***/ @@ -93,6 +85,7 @@ struct m25p {
>  	u16			addr_width;
>  	u8			erase_opcode;
>  	u8			*command;
> +	bool			fast_read;
>  };
> 
>  static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
> @@ -342,6 +335,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t
> from, size_t len, struct m25p *flash = mtd_to_m25p(mtd);
>  	struct spi_transfer t[2];
>  	struct spi_message m;
> +	uint8_t opcode;
> 
>  	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
>  			__func__, (u32)from, len);
> @@ -354,7 +348,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t
> from, size_t len, * Should add 1 byte DUMMY_BYTE.
>  	 */
>  	t[0].tx_buf = flash->command;
> -	t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
> +	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
>  	spi_message_add_tail(&t[0], &m);
> 
>  	t[1].rx_buf = buf;
> @@ -376,12 +370,14 @@ static int m25p80_read(struct mtd_info *mtd, loff_t
> from, size_t len, */
> 
>  	/* Set up the write data buffer. */
> -	flash->command[0] = OPCODE_READ;
> +	opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
> +	flash->command[0] = opcode;
>  	m25p_addr2cmd(flash, from, flash->command);
> 
>  	spi_sync(flash->spi, &m);
> 
> -	*retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
> +	*retlen = m.actual_length - m25p_cmdsz(flash) -
> +			(flash->fast_read ? 1 : 0);
> 
>  	mutex_unlock(&flash->lock);
> 
> @@ -804,9 +800,10 @@ static int __devinit m25p_probe(struct spi_device
> *spi) struct flash_info		*info;
>  	unsigned			i;
>  	struct mtd_part_parser_data	ppdata;
> +	struct device_node		*np = spi->dev.of_node;
> 
>  #ifdef CONFIG_MTD_OF_PARTS
> -	if (!of_device_is_available(spi->dev.of_node))
> +	if (!of_device_is_available(np))
>  		return -ENODEV;
>  #endif
> 
> @@ -858,7 +855,8 @@ static int __devinit m25p_probe(struct spi_device *spi)
>  	flash = kzalloc(sizeof *flash, GFP_KERNEL);
>  	if (!flash)
>  		return -ENOMEM;
> -	flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE,
> GFP_KERNEL); +	flash->command = kmalloc(MAX_CMD_SIZE + (flash-
>fast_read ?
> 1 : 0), +					GFP_KERNEL);
>  	if (!flash->command) {
>  		kfree(flash);
>  		return -ENOMEM;
> @@ -915,6 +913,16 @@ static int __devinit m25p_probe(struct spi_device
> *spi) flash->page_size = info->page_size;
>  	flash->mtd.writebufsize = flash->page_size;
> 
> +	flash->fast_read = false;
> +#ifdef CONFIG_OF
> +	if (np && of_property_read_bool(np, "m25p,fast-read"))
> +		flash->fast_read = true;
> +#endif
> +
> +#ifdef CONFIG_M25PXX_USE_FAST_READ
> +	flash->fast_read = true;
> +#endif
> +
>  	if (info->addr_width)
>  		flash->addr_width = info->addr_width;
>  	else {


From computersforpeace at gmail.com  Mon Sep 17 14:42:18 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 17 Sep 2012 11:42:18 -0700
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <6871BC8982B258468985EE735D2C57524E269AFB89@ntcex01.corp.netcomm.com.au>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 <1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 <1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
 <CAN8TOE_ax=8inGyZxS+nTfcSkskyNvHEh9ipnOTVu-moB4FqjA@mail.gmail.com>
 <6871BC8982B258468985EE735D2C57524E269AFB89@ntcex01.corp.netcomm.com.au>
Message-ID: <CAN8TOE_fihvz0F3C9cRhXkKvePYfyRD0Qmiu1a6aDH8o4ntsOg@mail.gmail.com>

Hi Iwo,

On Wed, Sep 5, 2012 at 8:37 PM, Iwo Mergler
<Iwo.Mergler at netcommwireless.com> wrote:
> Please be aware that this test aims at MTD driver developers,
> so I expect the 'users' to know all about their flash geometries
> and not be surprised by whole block erases and such. :-)

Duly noted. I agree, but I also think we can do our best to make
things as easy to understand as possible.

> On Thu, 6 Sep 2012 04:19:57 +1000
> Brian Norris <computersforpeace at gmail.com> wrote:
>> On Thu, Aug 30, 2012 at 3:59 PM, Iwo Mergler
>> <Iwo.Mergler at netcommwireless.com> wrote:
>> > This tests ECC biterror recovery on a single NAND page. Mostly intended
>> > to test ECC hardware and low-level NAND driver.
>> >
>> > There are two test modes:
>>
>> Why does this test even need to be in the kernel? Can't it be done
>> easily in userspace? I think it could even be a simple script that
>> utilizes flash_erase + nandwrite / nanddump with the -n (no ECC)
>> option. And anything that's lacking in nandwrite for this
>> functionality could easily be added there (for instance, support
>> erasure in nandwrite, rather than having to use flash_erase).
>
> You are right. The same can be said about most of the other
> tests too.

Yeah, I suppose so. I don't know about all the tests, but one
exception I was thinking of: the oobtest doesn't just use user-visible
interfaces to test sanity, it tries to use the MTD interfaces
(mtd_read_oob / mtd_write_oob) to stress the driver in ways that might
not be exposed to the user normally.

> Personally, I appreciate these tests being where they are
> because they are most useful to driver developers and as
> such are more accessible in the kernel than in userspace.
>
> On new embedded systems, we often have to develop MTD drivers
> before we have a rootfs, since the rootfs is supposed to live in the MTD.
> MTD is often the first hardware driver to get ported / written for a new
> system.
>
> With the current test arrangement I can, with minimal edits,
> run any test from within the MTD driver under development.

Fair enough.

>> > +static unsigned page_offset;
>> > +module_param(page_offset, uint, S_IRUGO);
>> > +MODULE_PARM_DESC(page_offset, "Page number relative to dev start");
>>
>> Why use a page number? For erase, we'll be affecting many adjacent
>> pages, so this might be an unclear parameter to the user. Is there a
>> good reason not to use an entire eraseblock as the unit of test? Also,
>> is there a reason to use page number vs. eraseblock number vs. offset
>> as the input parameter?
>
> Mostly because loff_t isn't supported as a parameter type, so I can't
> specify offsets beyond 4G.
>
> Erase block number would work as well. There isn't much to be learned
> from applying the test to all pages of a block, but in rare circumstances
> I'd like to be able to control which page of the block to test anyway.
>
> It would of course be possible to specify the offset  as separate
> erase block numbers and page numbers. I don't have a strong
> preference either way.

I don't have a strong preference either. In the absence of a portable
module-parameter for "loff_t" address, then a page_offset or eb_offset
param is fine with me.

>> > +static loff_t   offset;     /* Offset of the page we're using. */
>> > +static unsigned eraseblock; /* Eraseblock number for our page. */
>> > +
>> > +/* We assume that the ECC can correct up to a certain number
>> > + * of biterrors per subpage. */
>> > +static unsigned subsize;  /* Size of subpages */
>> > +static unsigned subcount; /* Number of subpages per page */
>> > +
>> > +static struct mtd_info *mtd;   /* MTD device */
>> > +
>> > +static uint8_t *wbuffer; /* One page write / compare buffer */
>> > +static uint8_t *rbuffer; /* One page read buffer */
>>
>> Why are all of these globals? It seems like the read_page(),
>> write_page(), and rewrite_page() functions would be more sensible (and
>> safely extendible) if they had an extra parameter for the address. And
>> do you really need to represent the same value (offset) in three
>> different ways (offset, page offset, eraseblock)? In fact,
>
> I had to force myself ;-). My excuse is that I copied the style of
> the other tests, because of a probably misguided sense of consistency.

Yeah, I don't know if I can speak for anyone else, but I would
recommend focusing on writing clean, maintainable code and leave
consistency with other tests' style as a secondary objective. I think
it's useful for read_page(), etc., to have at least one parameter (not
global variable) for the offset (or similar; e.g., page number). The
other globals are up to you, I suppose. When a value really is a
global that won't change, it's fine to be global (e.g., the mtd_info
struct, subpage info).

Thanks for your efforts and for addressing my comments. For a v2, I
think there are some things to address in code (bad block checking,
function parameters vs. global decisions) while other issues just need
a little bit better explanation (e.g., usefulness of mtd_nandbiterrs
vs mtd_nandecctest, explaining how this can be used to generically
test real bit error correction on real MTDs).

Regards,
Brian


From computersforpeace at gmail.com  Mon Sep 17 21:06:54 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 17 Sep 2012 18:06:54 -0700
Subject: [RFC] nand_btt : use nand chip->block_bad
In-Reply-To: <CAN8TOE9fxLbYCc2MeLaqV2WA2ch9Dm9xnyPvY7LBOZ0guB-d0Q@mail.gmail.com>
References: <1340898442-1585-1-git-send-email-matthieu.castet@parrot.com>
 <20120628213146.7d929204@halley> <4FED6A2E.9010603@parrot.com>
 <20120630230252.58ca6bb4@halley> <4FF15BD1.9010109@parrot.com>
 <CAN8TOE8GMMn+sPu4trUH_iT3=5uh_Of=bsYzXX50E3dyPfKitg@mail.gmail.com>
 <20120725140233.7dc4ca8a@pixies.home.jungo.com>
 <CAN8TOE9fxLbYCc2MeLaqV2WA2ch9Dm9xnyPvY7LBOZ0guB-d0Q@mail.gmail.com>
Message-ID: <CAN8TOE9QCnq7AKT9t8VKc2iQE9VXT7USDQjJ7vR640FMweqJDQ@mail.gmail.com>

Hi Shmulik, Matthieu, and others,

On Mon, Aug 6, 2012 at 3:21 PM, Brian Norris
<computersforpeace at gmail.com> wrote:
> On Wed, Jul 25, 2012 at 4:02 AM, Shmulik Ladkani
>> I guess utilizing badblockbits may provide good coverage to that
>> condition.
>
> Yes, I agree that badblockbits is a good solution. I'm still not sure
> that any of the above arguments really suggest that we *can't* apply
> ECC, but for any important case, badblockbits would be more robust. I
> think I will look into fleshing out Matthieu's RFC at some point,
> unless he's already working on it.

I've done a little work at trying to flesh out this RFC, as I'm
thinking that we should more cleanly separate NAND BBT code and NAND
BBM code - i.e., bad block *table* vs. bad block *marker*. Markers
should be handled in a standard way in nand_base.c
(nand_default_block_markbad and nand_block_bad) and then nand_bbt.c
can be left the generic, focused job of handling the table. Now, that
all sounds nice, but I've run across at least one difficulty... This
approach should lead to the removal of nand_chip.badblock_pattern
entirely, as we would only be supporting the nand_base.c badblock
marker pattern, using nand_chip.badblockpos and a few
nand_chip.bbt_options flags. This leads me to analyzing all the
strange forms of badblock_pattern seen in various drivers. I'm not
sure all of them are even well thought out...

The following files use badblock_pattern to varying degrees. Some are
just duplicating some nand_base stuff, where we can replace the
badblock_pattern with something simple like "chip->badblockpos = 0" or
setting a few "chip->bbt_options |= NAND_BBT_SCAN*" options. But it's
not all so simple:

arch/arm/mach-pxa/corgi.c
arch/arm/mach-pxa/eseries.c
arch/arm/mach-pxa/poodle.c
arch/arm/mach-pxa/spitz.c
arch/arm/mach-pxa/tosa.c
drivers/mtd/nand/bcm_umi_nand.c
drivers/mtd/nand/docg4.c
drivers/mtd/nand/fsl_elbc_nand.c
drivers/mtd/nand/gpmi-nand/gpmi-nand.c
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/omap2.c
drivers/mtd/nand/sh_flctl.c
drivers/mtd/nand/sharpsl.c
drivers/mtd/nand/tmio_nand.c
drivers/mtd/onenand/onenand_bbt.c
include/linux/mfd/tmio.h
include/linux/mtd/sharpsl.h

Any thoughts on how to tackle this? Or is it even worth doing
properly? Is there a policy for dealing with old/unmaintained drivers
here, if I can't get a response from driver authors?

Thanks,
Brian


From scottwood at freescale.com  Mon Sep 17 21:28:17 2012
From: scottwood at freescale.com (Scott Wood)
Date: Mon, 17 Sep 2012 20:28:17 -0500
Subject: [RFC] nand_btt : use nand chip->block_bad
In-Reply-To: <CAN8TOE9QCnq7AKT9t8VKc2iQE9VXT7USDQjJ7vR640FMweqJDQ@mail.gmail.com>
 (from computersforpeace@gmail.com on Mon Sep 17 20:06:54 2012)
Message-ID: <1347931697.19543.24@snotra>

On 09/17/2012 08:06:54 PM, Brian Norris wrote:
> Hi Shmulik, Matthieu, and others,
> 
> On Mon, Aug 6, 2012 at 3:21 PM, Brian Norris
> <computersforpeace at gmail.com> wrote:
> > On Wed, Jul 25, 2012 at 4:02 AM, Shmulik Ladkani
> >> I guess utilizing badblockbits may provide good coverage to that
> >> condition.
> >
> > Yes, I agree that badblockbits is a good solution. I'm still not  
> sure
> > that any of the above arguments really suggest that we *can't* apply
> > ECC, but for any important case, badblockbits would be more robust.  
> I
> > think I will look into fleshing out Matthieu's RFC at some point,
> > unless he's already working on it.
> 
> I've done a little work at trying to flesh out this RFC, as I'm
> thinking that we should more cleanly separate NAND BBT code and NAND
> BBM code - i.e., bad block *table* vs. bad block *marker*. Markers
> should be handled in a standard way in nand_base.c
> (nand_default_block_markbad and nand_block_bad) and then nand_bbt.c
> can be left the generic, focused job of handling the table. Now, that
> all sounds nice, but I've run across at least one difficulty... This
> approach should lead to the removal of nand_chip.badblock_pattern
> entirely, as we would only be supporting the nand_base.c badblock
> marker pattern, using nand_chip.badblockpos and a few
> nand_chip.bbt_options flags. This leads me to analyzing all the
> strange forms of badblock_pattern seen in various drivers. I'm not
> sure all of them are even well thought out...
> 
> The following files use badblock_pattern to varying degrees. Some are
> just duplicating some nand_base stuff, where we can replace the
> badblock_pattern with something simple like "chip->badblockpos = 0" or
> setting a few "chip->bbt_options |= NAND_BBT_SCAN*" options. But it's
> not all so simple:
> 
> arch/arm/mach-pxa/corgi.c
> arch/arm/mach-pxa/eseries.c
> arch/arm/mach-pxa/poodle.c
> arch/arm/mach-pxa/spitz.c
> arch/arm/mach-pxa/tosa.c
> drivers/mtd/nand/bcm_umi_nand.c
> drivers/mtd/nand/docg4.c
> drivers/mtd/nand/fsl_elbc_nand.c
> drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> drivers/mtd/nand/nand_base.c
> drivers/mtd/nand/omap2.c
> drivers/mtd/nand/sh_flctl.c
> drivers/mtd/nand/sharpsl.c
> drivers/mtd/nand/tmio_nand.c
> drivers/mtd/onenand/onenand_bbt.c
> include/linux/mfd/tmio.h
> include/linux/mtd/sharpsl.h
> 
> Any thoughts on how to tackle this? Or is it even worth doing
> properly? Is there a policy for dealing with old/unmaintained drivers
> here, if I can't get a response from driver authors?

fsl_elbc_nand uses this for historical reasons, to retain compatibility  
with the original OOB layout which only reserved one byte for the bad  
block marker and let users write to the second byte.  This controller  
only supports 8-bit chips.

See commit 97ae023648e764f794ffb9c52da109d6caf09c47

-Scott


From s.hauer at pengutronix.de  Tue Sep 18 03:52:13 2012
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 18 Sep 2012 09:52:13 +0200
Subject: [PATCH 00/34] i.MX multi-platform support
In-Reply-To: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <20120918075213.GD24458@pengutronix.de>

Hi Shawn,

On Mon, Sep 17, 2012 at 01:34:29PM +0800, Shawn Guo wrote:
> The series enables multi-platform support for imx.  Since the required
> frameworks (clk, pwm) and spare_irq have already been adopted on imx,
> the series is all about cleaning up mach/* headers.  Along with the
> changes, arch/arm/plat-mxc gets merged into arch/arm/mach-imx.
> 
> It's based on a bunch of branches (works from others), Rob's initial
> multi-platform series, Arnd's platform-data and smp_ops (Marc's) and
> imx 3.7 material (Sascha and myself).
> 
> It's available on branch below.
> 
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform
> 
> It's been tested on imx5 and imx6, and only compile-tested on imx2 and
> imx3, so testing on imx2/3 are appreciated.
> 
> Subsystem maintainers,
> 
> I plan to send the whole series via arm-soc tree at the end of 3.7
> merge window when all dependant bits hit mainline.  Please have a
> look at the patches you get copied and provide ACKs if the changes
> are good.  Thanks.

I just had a look at the remaining initcalls in arch-imx. Most of them
are protected with a cpu_is_*, but this one should be fixed before i.MX
is enabled for multi platform:

arch/arm/mach-imx/devices/devices.c:48:core_initcall(mxc_device_init);

I think this won't harm others directly, but it will register i.MX
related devices on foreign platforms.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From shawn.guo at linaro.org  Tue Sep 18 04:05:43 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 18 Sep 2012 16:05:43 +0800
Subject: [alsa-devel] [PATCH 00/34] i.MX multi-platform support
In-Reply-To: <20120918075213.GD24458@pengutronix.de>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
 <20120918075213.GD24458@pengutronix.de>
Message-ID: <20120918080541.GA6377@S2101-09.ap.freescale.net>

On Tue, Sep 18, 2012 at 09:52:13AM +0200, Sascha Hauer wrote:
> I just had a look at the remaining initcalls in arch-imx. Most of them
> are protected with a cpu_is_*, but this one should be fixed before i.MX
> is enabled for multi platform:
> 
> arch/arm/mach-imx/devices/devices.c:48:core_initcall(mxc_device_init);
> 
Ah, I missed that.  Thanks for reminding, Sascha.

Shawn


From shawn.guo at linaro.org  Tue Sep 18 04:20:58 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Tue, 18 Sep 2012 16:20:58 +0800
Subject: [PATCH 00/34] i.MX multi-platform support
In-Reply-To: <20120917075138.GN6180@pengutronix.de>
References: <1347860103-4141-1-git-send-email-shawn.guo@linaro.org>
 <20120917075138.GN6180@pengutronix.de>
Message-ID: <20120918082055.GD6377@S2101-09.ap.freescale.net>

On Mon, Sep 17, 2012 at 09:51:38AM +0200, Sascha Hauer wrote:
> I gave it a test on i.MX1, i.MX27, i.MX31 and i.MX35. All run fine, but
> the last patch breaks the imx_v4_v5_defconfig: Somehow it now defaults
> to ARMv7 based machines. I haven't looked into it, just reenabled
> ARMv4/ARMv5 and the boards again -> works. The config should be updated
> with the last patch.
> 
Yes, I will rework the patch with all these and Arnd's comment on the
last patch taken into account.

> I'm fine with the changes to mx2-camera, but Javier should give his ok
> to it, he has worked on it quite a lot recently.
> 
> One other issue related to imx-dma, see comment to that patch.
> 
> Otherwise:
> 
> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
> Tested-by: Sascha Hauer <s.hauer at pengutronix.de>
> 
Thanks a lot.

Shawn


From richard.genoud at gmail.com  Tue Sep 18 04:27:44 2012
From: richard.genoud at gmail.com (Richard Genoud)
Date: Tue, 18 Sep 2012 10:27:44 +0200
Subject: [PATCH] MTD: nandsim: BUG: Fail if overridesize is too big
In-Reply-To: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>
References: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <CACQ1gAg7Kb7v1HZVdF1N2CtmUSGEYJwB+Un2GUJFDX+==6yO8g@mail.gmail.com>

2012/9/12 Richard Genoud <richard.genoud at gmail.com>:
> If override size is too big, the module was actually loaded instead of
> failing, because retval was not set.
>
> This lead to memory corruption with the use of the freed structs nandsim
> and nand_chip.
>
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>
> ---
>  drivers/mtd/nand/nandsim.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/nandsim.c b/drivers/mtd/nand/nandsim.c
> index cf0cd31..5d881180 100644
> --- a/drivers/mtd/nand/nandsim.c
> +++ b/drivers/mtd/nand/nandsim.c
> @@ -2333,6 +2333,7 @@ static int __init ns_init_module(void)
>                 uint64_t new_size = (uint64_t)nsmtd->erasesize << overridesize;
>                 if (new_size >> overridesize != nsmtd->erasesize) {
>                         NS_ERR("overridesize is too big\n");
> +                       retval = -EINVAL;
>                         goto err_exit;
>                 }
>                 /* N.B. This relies on nand_scan not doing anything with the size before we change it */
> --
> 1.7.2.5
>
Hi Artem, David.

As this is a bug fix, it should be pushed to 3.6-rc7, shouldn't it ?

Regards,
Richard.


From dedekind1 at gmail.com  Tue Sep 18 09:32:44 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 18 Sep 2012 16:32:44 +0300
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
Message-ID: <1347975164.7112.63.camel@sauron.fi.intel.com>

On Mon, 2012-09-17 at 11:50 +0200, Rafa? Mi?ecki wrote:
> This registers MTD driver for serial flash platform device. Right now it
> supports reading only, writing still has to be implemented.
> 
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> ---
> V2: fix mem leak (add failure path in init)
>     signed-off-by
> V3: drop BROKEN
>     drop useless check in bcm47xxsflash_remove
>     marm flash memory as ROM (until we implement writing)

Aiaiai complained:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/devices/bcm47xxsflash.c:30:30: warning: incorrect type in argument 1 (different address spaces) [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:30:30:    expected void const volatile [noderef] <asn:2>*mem [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:30:30:    got unsigned char [usertype] *src [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:37:38: warning: incorrect type in argument 1 (different address spaces) [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:37:38:    expected void const volatile [noderef] <asn:2>*mem [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:37:38:    got unsigned int [usertype] *<noident> [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:43:30: warning: incorrect type in argument 1 (different address spaces) [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:43:30:    expected void const volatile [noderef] <asn:2>*mem [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:43:30:    got unsigned char [usertype] *[assigned] src [sparse]

I pushed your patch to l2-mtd.git with these changes:

diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
index f711a51..a328872 100644
--- a/drivers/mtd/devices/bcm47xxsflash.c
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -15,7 +15,7 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
 {
        struct bcma_sflash *sflash = mtd->priv;
        size_t bytes_read = 0;
-       u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
+       __iomem u8 *src = (__iomem u8 *)KSEG0ADDR(sflash->window + from);
        int i;
        size_t unaligned_before, unaligned_after;
 
@@ -34,7 +34,7 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
        }
        for (i = from - unaligned_before; i < from + len - unaligned_after;
             i += 4) {
-               *(u32 *)buf = readl((u32 *)src);
+               *(u32 *)buf = readl(src);
                buf += 4;
                src += 4;
                bytes_read += 4;

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120918/ae862665/attachment.sig>

From jonas.gorski at gmail.com  Tue Sep 18 10:40:32 2012
From: jonas.gorski at gmail.com (Jonas Gorski)
Date: Tue, 18 Sep 2012 16:40:32 +0200
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
Message-ID: <CAOiHx==SFr7EUAm0vdrAbs8Ze7his8Bgx+g-Ri6j6Q-iqGDkXg@mail.gmail.com>

I know I'm a bit late, but ...

On 17 September 2012 11:50, Rafa? Mi?ecki <zajec5 at gmail.com> wrote:
> (...)
> diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
> index a4dd1d8..395733a 100644
> --- a/drivers/mtd/devices/Makefile
> +++ b/drivers/mtd/devices/Makefile
> @@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_DATAFLASH)   += mtd_dataflash.o
>  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
>  obj-$(CONFIG_MTD_SPEAR_SMI)    += spear_smi.o
>  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
> +obj-$(CONFIG_MTD_BCM47XXSFLASH)        += bcm47xxsflash.o
>
>  CFLAGS_docg3.o                 += -I$(src)
> \ No newline at end of file
> diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
> new file mode 100644
> index 0000000..f711a51
> --- /dev/null
> +++ b/drivers/mtd/devices/bcm47xxsflash.c
> @@ -0,0 +1,131 @@
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/slab.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/platform_device.h>
> +#include <linux/bcma/bcma.h>
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
> +
> +static const char *probes[] = { "bcm47xxpart", NULL };
> +
> +static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
> +                             size_t *retlen, u_char *buf)
> +{
> +       struct bcma_sflash *sflash = mtd->priv;
> +       size_t bytes_read = 0;
> +       u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
> +       int i;
> +       size_t unaligned_before, unaligned_after;
> +
> +       /* Check address range */
> +       if ((from + len) > mtd->size)
> +               return -EINVAL;
> +
> +       unaligned_before = from & 0x3;

I think this should be 4 - (from & 0x3), else you will read too much
in the unaligned_before loop, also being at an unaligned address then.

E.g. assuming I want to read four bytes from offset 3, you will read
three bytes from from, and will actually then read three bytes from 3,
landing at offset 6, and then reading another three in the
unaligned_after loop; overwriting memory with the last two.

> +       unaligned_after = (from + len) & 0x3;
> +
> +       for (i = 0; i < unaligned_before; i++) {
> +               *buf = readb(src);
> +               buf++;
> +               src++;
> +               bytes_read++;
> +       }
> +       for (i = from - unaligned_before; i < from + len - unaligned_after;

This one looks suspicious, aren't you assuming you have read
unaligned_before bytes, so shouldn't i be from /+/ unaligned_before?
Currently this will result in the example above that it will loop once
(since i = 3 - 3 = 0, and 0 < 3 + 4 - 3), resulting in additional 4
bytes read.

> +            i += 4) {
> +               *(u32 *)buf = readl((u32 *)src);
> +               buf += 4;
> +               src += 4;
> +               bytes_read += 4;
> +       }
> +       for (i = 0; i < unaligned_after; i++) {
> +               *buf = readb(src);
> +               buf++;
> +               src++;
> +               bytes_read++;
> +       }

It will also fail for unaligned reads within the same 4 byte block -
they will be read twice, once in _before, once in _after.

Also in the before and after loops, you are reading with native
endianess (since you don't swab the addresses), but in the aligned
case you are assuming little endianess. If you intend to do native
endianess reads (we only support little endian bcm47xx), you should be
fine by just replacing this whole logic with a memcpy(_fromio?), if
not you should probably swab the addresses when reading the unaligned
parts when big endian. Unfortunately I don't have any big endian
bcm47xx devices at hand to test ;-) (but I do know they exist - AFAICT
from netgear's gpl sources the bcm53xxx switch chips are big endian
bcm47xx).


Regards
Jonas


From dinguyen at altera.com  Tue Sep 18 19:31:35 2012
From: dinguyen at altera.com (Dinh Nguyen)
Date: Tue, 18 Sep 2012 17:31:35 -0600
Subject: nand/denali: Enable DT for Denali NAND controller
Message-ID: <1348011095.25236.15.camel@dinh-ubuntu>

Hi Jamie,

I saw that you posted a series of patches about a year ago to convert
the PCI Denali NAND controller over to a non-PCI based driver. It seems
that the best solution was to make it DT compatible, which at the time
the patch was posted, DT was not available on ARM.

http://thread.gmane.org/gmane.linux.drivers.mtd/35031/focus=35101

It appears that the denali NAND driver has not been enabled for DT yet.
Do you know if there is still an interest in doing that and if I can
help in anyway? I have a strong interest in converting the denali NAND
driver to be DT capable.

Thanks,

Dinh Nguyen




From sr at denx.de  Wed Sep 19 04:30:27 2012
From: sr at denx.de (Stefan Roese)
Date: Wed, 19 Sep 2012 10:30:27 +0200
Subject: [PATCH] mtd: cmdlineparts.c: Codingstyle cleanup
Message-ID: <1348043427-5165-1-git-send-email-sr@denx.de>

The codingstyle of cmdlineparts.c was really ugly. I've run this
file through Lindent and made some manual tweaks.

Signed-off-by: Stefan Roese <sr at denx.de>
---
 drivers/mtd/cmdlinepart.c | 178 +++++++++++++++++++++-------------------------
 1 file changed, 81 insertions(+), 97 deletions(-)

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index 4558e0f..0239c18 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -55,7 +55,6 @@
 #define dbg(x)
 #endif
 
-
 /* special size referring to all the remaining space in a partition */
 #define SIZE_REMAINING UINT_MAX
 #define OFFSET_CONTINUOUS UINT_MAX
@@ -82,12 +81,12 @@ static int cmdline_parsed = 0;
  * is allocated upon the last definition being found. At that point the
  * syntax has been verified ok.
  */
-static struct mtd_partition * newpart(char *s,
-                                      char **retptr,
-                                      int *num_parts,
-                                      int this_part,
-                                      unsigned char **extra_mem_ptr,
-                                      int extra_mem_size)
+static struct mtd_partition *newpart(char *s,
+				     char **retptr,
+				     int *num_parts,
+				     int this_part,
+				     unsigned char **extra_mem_ptr,
+				     int extra_mem_size)
 {
 	struct mtd_partition *parts;
 	unsigned long size;
@@ -99,79 +98,70 @@ static struct mtd_partition * newpart(char *s,
 	unsigned int mask_flags;
 
 	/* fetch the partition size */
-	if (*s == '-')
-	{	/* assign all remaining space to this partition */
+	if (*s == '-') {	/* assign all remaining space to this partition */
 		size = SIZE_REMAINING;
 		s++;
-	}
-	else
-	{
+	} else {
 		size = memparse(s, &s);
-		if (size < PAGE_SIZE)
-		{
-			printk(KERN_ERR ERRP "partition size too small (%lx)\n", size);
+		if (size < PAGE_SIZE) {
+			printk(KERN_ERR ERRP "partition size too small (%lx)\n",
+			       size);
 			return NULL;
 		}
 	}
 
 	/* fetch partition name and flags */
-	mask_flags = 0; /* this is going to be a regular partition */
+	mask_flags = 0;		/* this is going to be a regular partition */
 	delim = 0;
-        /* check for offset */
-        if (*s == '@')
-	{
-                s++;
-                offset = memparse(s, &s);
-        }
-        /* now look for name */
+
+	/* check for offset */
+	if (*s == '@') {
+		s++;
+		offset = memparse(s, &s);
+	}
+
+	/* now look for name */
 	if (*s == '(')
-	{
 		delim = ')';
-	}
 
-	if (delim)
-	{
+	if (delim) {
 		char *p;
 
-	    	name = ++s;
+		name = ++s;
 		p = strchr(name, delim);
-		if (!p)
-		{
-			printk(KERN_ERR ERRP "no closing %c found in partition name\n", delim);
+		if (!p) {
+			printk(KERN_ERR ERRP
+			       "no closing %c found in partition name\n",
+			       delim);
 			return NULL;
 		}
 		name_len = p - name;
 		s = p + 1;
-	}
-	else
-	{
-	    	name = NULL;
-		name_len = 13; /* Partition_000 */
+	} else {
+		name = NULL;
+		name_len = 13;	/* Partition_000 */
 	}
 
 	/* record name length for memory allocation later */
 	extra_mem_size += name_len + 1;
 
-        /* test for options */
-        if (strncmp(s, "ro", 2) == 0)
-	{
+	/* test for options */
+	if (strncmp(s, "ro", 2) == 0) {
 		mask_flags |= MTD_WRITEABLE;
 		s += 2;
-        }
+	}
 
-        /* if lk is found do NOT unlock the MTD partition*/
-        if (strncmp(s, "lk", 2) == 0)
-	{
+	/* if lk is found do NOT unlock the MTD partition */
+	if (strncmp(s, "lk", 2) == 0) {
 		mask_flags |= MTD_POWERUP_LOCK;
 		s += 2;
-        }
+	}
 
 	/* test if more partitions are following */
-	if (*s == ',')
-	{
-		if (size == SIZE_REMAINING)
-		{
-			printk(KERN_ERR ERRP "no partitions allowed after a fill-up partition\n");
+	if (*s == ',') {
+		if (size == SIZE_REMAINING) {
+			printk(KERN_ERR ERRP
+			       "no partitions allowed after a fill-up partition\n");
 			return NULL;
 		}
 		/* more partitions follow, parse them */
@@ -179,14 +169,12 @@ static struct mtd_partition * newpart(char *s,
 				&extra_mem, extra_mem_size);
 		if (!parts)
 			return NULL;
-	}
-	else
-	{	/* this is the last partition: allocate space for all */
+	} else {		/* this is the last partition: allocate space for all */
 		int alloc_size;
 
 		*num_parts = this_part + 1;
 		alloc_size = *num_parts * sizeof(struct mtd_partition) +
-			     extra_mem_size;
+		    extra_mem_size;
 		parts = kzalloc(alloc_size, GFP_KERNEL);
 		if (!parts)
 			return NULL;
@@ -196,27 +184,22 @@ static struct mtd_partition * newpart(char *s,
 	parts[this_part].size = size;
 	parts[this_part].offset = offset;
 	parts[this_part].mask_flags = mask_flags;
+
 	if (name)
-	{
 		strlcpy(extra_mem, name, name_len + 1);
-	}
 	else
-	{
 		sprintf(extra_mem, "Partition_%03d", this_part);
-	}
+
 	parts[this_part].name = extra_mem;
 	extra_mem += name_len + 1;
 
 	dbg(("partition %d: name <%s>, offset %llx, size %llx, mask flags %x\n",
-	     this_part,
-	     parts[this_part].name,
-	     parts[this_part].offset,
-	     parts[this_part].size,
-	     parts[this_part].mask_flags));
+	     this_part, parts[this_part].name, parts[this_part].offset,
+	     parts[this_part].size, parts[this_part].mask_flags));
 
 	/* return (updated) pointer to extra_mem memory */
 	if (extra_mem_ptr)
-	  *extra_mem_ptr = extra_mem;
+		*extra_mem_ptr = extra_mem;
 
 	/* return (updated) pointer command line string */
 	*retptr = s;
@@ -232,24 +215,22 @@ static int mtdpart_setup_real(char *s)
 {
 	cmdline_parsed = 1;
 
-	for( ; s != NULL; )
-	{
+	for (; s != NULL;) {
 		struct cmdline_mtd_partition *this_mtd;
 		struct mtd_partition *parts;
-	    	int mtd_id_len;
+		int mtd_id_len;
 		int num_parts;
 		char *p, *mtd_id;
 
-	    	mtd_id = s;
+		mtd_id = s;
 		/* fetch <mtd-id> */
-		if (!(p = strchr(s, ':')))
-		{
+		if (!(p = strchr(s, ':'))) {
 			printk(KERN_ERR ERRP "no mtd-id\n");
 			return 0;
 		}
 		mtd_id_len = p - mtd_id;
 
-		dbg(("parsing <%s>\n", p+1));
+		dbg(("parsing <%s>\n", p + 1));
 
 		/*
 		 * parse one mtd. have it reserve memory for the
@@ -259,11 +240,10 @@ static int mtdpart_setup_real(char *s)
 				&s,		/* out: updated cmdline ptr */
 				&num_parts,	/* out: number of parts */
 				0,		/* first partition */
-				(unsigned char**)&this_mtd, /* out: extra mem */
+				(unsigned char **)&this_mtd,	/* out: extra mem */
 				mtd_id_len + 1 + sizeof(*this_mtd) +
-				sizeof(void*)-1 /*alignment*/);
-		if(!parts)
-		{
+				sizeof(void *) - 1 /*alignment */ );
+		if (!parts) {
 			/*
 			 * An error occurred. We're either:
 			 * a) out of memory, or
@@ -271,16 +251,17 @@ static int mtdpart_setup_real(char *s)
 			 * Either way, this mtd is hosed and we're
 			 * unlikely to succeed in parsing any more
 			 */
-			 return 0;
-		 }
+			return 0;
+		}
 
 		/* align this_mtd */
 		this_mtd = (struct cmdline_mtd_partition *)
-			ALIGN((unsigned long)this_mtd, sizeof(void*));
+			ALIGN((unsigned long)this_mtd, sizeof(void *));
+
 		/* enter results */
 		this_mtd->parts = parts;
 		this_mtd->num_parts = num_parts;
-		this_mtd->mtd_id = (char*)(this_mtd + 1);
+		this_mtd->mtd_id = (char *)(this_mtd + 1);
 		strlcpy(this_mtd->mtd_id, mtd_id, mtd_id_len + 1);
 
 		/* link into chain */
@@ -290,19 +271,19 @@ static int mtdpart_setup_real(char *s)
 		dbg(("mtdid=<%s> num_parts=<%d>\n",
 		     this_mtd->mtd_id, this_mtd->num_parts));
 
-
 		/* EOS - we're done */
 		if (*s == 0)
 			break;
 
 		/* does another spec follow? */
-		if (*s != ';')
-		{
-			printk(KERN_ERR ERRP "bad character after partition (%c)\n", *s);
+		if (*s != ';') {
+			printk(KERN_ERR ERRP
+			       "bad character after partition (%c)\n", *s);
 			return 0;
 		}
 		s++;
 	}
+
 	return 1;
 }
 
@@ -326,40 +307,42 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 	if (!cmdline_parsed)
 		mtdpart_setup_real(cmdline);
 
-	for(part = partitions; part; part = part->next)
-	{
-		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id)))
-		{
-			for(i = 0, offset = 0; i < part->num_parts; i++)
-			{
+	for (part = partitions; part; part = part->next) {
+		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id))) {
+			for (i = 0, offset = 0; i < part->num_parts; i++) {
 				if (part->parts[i].offset == OFFSET_CONTINUOUS)
-				  part->parts[i].offset = offset;
+					part->parts[i].offset = offset;
 				else
-				  offset = part->parts[i].offset;
+					offset = part->parts[i].offset;
+
 				if (part->parts[i].size == SIZE_REMAINING)
-				  part->parts[i].size = master->size - offset;
-				if (offset + part->parts[i].size > master->size)
-				{
+					part->parts[i].size =
+						master->size - offset;
+
+				if (offset + part->parts[i].size > master->size) {
 					printk(KERN_WARNING ERRP
 					       "%s: partitioning exceeds flash size, truncating\n",
 					       part->mtd_id);
-					part->parts[i].size = master->size - offset;
+					part->parts[i].size =
+					    master->size - offset;
 					part->num_parts = i;
 				}
 				offset += part->parts[i].size;
 			}
+
 			*pparts = kmemdup(part->parts,
-					sizeof(*part->parts) * part->num_parts,
-					GFP_KERNEL);
+					  sizeof(*part->parts) *
+					  part->num_parts, GFP_KERNEL);
 			if (!*pparts)
 				return -ENOMEM;
+
 			return part->num_parts;
 		}
 	}
+
 	return 0;
 }
 
-
 /*
  * This is the handler for our kernel parameter, called from
  * main.c::checksetup(). Note that we can not yet kmalloc() anything,
@@ -370,6 +353,7 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 static int mtdpart_setup(char *s)
 {
 	cmdline = s;
+
 	return 1;
 }
 
-- 
1.7.12.1



From zajec5 at gmail.com  Wed Sep 19 06:46:09 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Wed, 19 Sep 2012 12:46:09 +0200
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <CAOiHx==SFr7EUAm0vdrAbs8Ze7his8Bgx+g-Ri6j6Q-iqGDkXg@mail.gmail.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
 <CAOiHx==SFr7EUAm0vdrAbs8Ze7his8Bgx+g-Ri6j6Q-iqGDkXg@mail.gmail.com>
Message-ID: <CACna6rxM9FRQTRmL9QRjciL3ZDkT_nQNwgifh__cK_HwSLf-GA@mail.gmail.com>

2012/9/18 Jonas Gorski <jonas.gorski at gmail.com>:
> I know I'm a bit late, but ...
>
> On 17 September 2012 11:50, Rafa? Mi?ecki <zajec5 at gmail.com> wrote:
>> (...)
>> diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
>> index a4dd1d8..395733a 100644
>> --- a/drivers/mtd/devices/Makefile
>> +++ b/drivers/mtd/devices/Makefile
>> @@ -19,5 +19,6 @@ obj-$(CONFIG_MTD_DATAFLASH)   += mtd_dataflash.o
>>  obj-$(CONFIG_MTD_M25P80)       += m25p80.o
>>  obj-$(CONFIG_MTD_SPEAR_SMI)    += spear_smi.o
>>  obj-$(CONFIG_MTD_SST25L)       += sst25l.o
>> +obj-$(CONFIG_MTD_BCM47XXSFLASH)        += bcm47xxsflash.o
>>
>>  CFLAGS_docg3.o                 += -I$(src)
>> \ No newline at end of file
>> diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
>> new file mode 100644
>> index 0000000..f711a51
>> --- /dev/null
>> +++ b/drivers/mtd/devices/bcm47xxsflash.c
>> @@ -0,0 +1,131 @@
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/slab.h>
>> +#include <linux/mtd/mtd.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/bcma/bcma.h>
>> +
>> +MODULE_LICENSE("GPL");
>> +MODULE_DESCRIPTION("Serial flash driver for BCMA bus");
>> +
>> +static const char *probes[] = { "bcm47xxpart", NULL };
>> +
>> +static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
>> +                             size_t *retlen, u_char *buf)
>> +{
>> +       struct bcma_sflash *sflash = mtd->priv;
>> +       size_t bytes_read = 0;
>> +       u8 *src = (u8 *)KSEG0ADDR(sflash->window + from);
>> +       int i;
>> +       size_t unaligned_before, unaligned_after;
>> +
>> +       /* Check address range */
>> +       if ((from + len) > mtd->size)
>> +               return -EINVAL;
>> +
>> +       unaligned_before = from & 0x3;
>
> I think this should be 4 - (from & 0x3), else you will read too much
> in the unaligned_before loop, also being at an unaligned address then.

Right, that's wrong.


>> +       unaligned_after = (from + len) & 0x3;
>> +
>> +       for (i = 0; i < unaligned_before; i++) {
>> +               *buf = readb(src);
>> +               buf++;
>> +               src++;
>> +               bytes_read++;
>> +       }
>> +       for (i = from - unaligned_before; i < from + len - unaligned_after;
>
> This one looks suspicious, aren't you assuming you have read
> unaligned_before bytes, so shouldn't i be from /+/ unaligned_before?

Right again. I could probably drom "from" too.


>> +            i += 4) {
>> +               *(u32 *)buf = readl((u32 *)src);
>> +               buf += 4;
>> +               src += 4;
>> +               bytes_read += 4;
>> +       }
>> +       for (i = 0; i < unaligned_after; i++) {
>> +               *buf = readb(src);
>> +               buf++;
>> +               src++;
>> +               bytes_read++;
>> +       }
>
> It will also fail for unaligned reads within the same 4 byte block -
> they will be read twice, once in _before, once in _after.

Hm, I don't understand that yet. It looks fine for me :| But I'll do
some test and it should become obvious to me then :)


> Also in the before and after loops, you are reading with native
> endianess (since you don't swab the addresses), but in the aligned
> case you are assuming little endianess. If you intend to do native
> endianess reads (we only support little endian bcm47xx), you should be
> fine by just replacing this whole logic with a memcpy(_fromio?), if
> not you should probably swab the addresses when reading the unaligned
> parts when big endian. Unfortunately I don't have any big endian
> bcm47xx devices at hand to test ;-) (but I do know they exist - AFAICT
> from netgear's gpl sources the bcm53xxx switch chips are big endian
> bcm47xx).

Whoops, I didn't know readl is LE access :| I though readb/readw/readl
are native endianess. Sorry for that.


I'm not sure about that endianess, what exactly we should implement. I
wanted to get some tip from simple map (see map_funcs.c and map.h) and
it seems it is using "inline_map_copy_from" indeed.

-- 
Rafa?


From zajec5 at gmail.com  Wed Sep 19 08:08:14 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Wed, 19 Sep 2012 14:08:14 +0200
Subject: [PATCH RFC] bcm47xxsflash: just use memcpy for reading
Message-ID: <1348056494-30019-1-git-send-email-zajec5@gmail.com>

---
Still have to check it with aiaiai
---
 drivers/mtd/devices/bcm47xxsflash.c |   31 ++-----------------------------
 1 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
index a328872..2f8dfd4 100644
--- a/drivers/mtd/devices/bcm47xxsflash.c
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -14,41 +14,14 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
 			      size_t *retlen, u_char *buf)
 {
 	struct bcma_sflash *sflash = mtd->priv;
-	size_t bytes_read = 0;
-	__iomem u8 *src = (__iomem u8 *)KSEG0ADDR(sflash->window + from);
-	int i;
-	size_t unaligned_before, unaligned_after;
 
 	/* Check address range */
 	if ((from + len) > mtd->size)
 		return -EINVAL;
 
-	unaligned_before = from & 0x3;
-	unaligned_after = (from + len) & 0x3;
+	memcpy(buf, (void *)KSEG0ADDR(sflash->window + from), len);
 
-	for (i = 0; i < unaligned_before; i++) {
-		*buf = readb(src);
-		buf++;
-		src++;
-		bytes_read++;
-	}
-	for (i = from - unaligned_before; i < from + len - unaligned_after;
-	     i += 4) {
-		*(u32 *)buf = readl(src);
-		buf += 4;
-		src += 4;
-		bytes_read += 4;
-	}
-	for (i = 0; i < unaligned_after; i++) {
-		*buf = readb(src);
-		buf++;
-		src++;
-		bytes_read++;
-	}
-
-	*retlen = bytes_read;
-
-	return 0;
+	return len;
 }
 
 static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
-- 
1.7.7



From mkl at pengutronix.de  Wed Sep 19 09:45:27 2012
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Wed, 19 Sep 2012 15:45:27 +0200
Subject: [PATCH RFC] bcm47xxsflash: just use memcpy for reading
In-Reply-To: <1348056494-30019-1-git-send-email-zajec5@gmail.com>
References: <1348056494-30019-1-git-send-email-zajec5@gmail.com>
Message-ID: <5059CC77.5060505@pengutronix.de>

On 09/19/2012 02:08 PM, Rafa? Mi?ecki wrote:
> ---
> Still have to check it with aiaiai
> ---
>  drivers/mtd/devices/bcm47xxsflash.c |   31 ++-----------------------------
>  1 files changed, 2 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
> index a328872..2f8dfd4 100644
> --- a/drivers/mtd/devices/bcm47xxsflash.c
> +++ b/drivers/mtd/devices/bcm47xxsflash.c
> @@ -14,41 +14,14 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
>  			      size_t *retlen, u_char *buf)
>  {
>  	struct bcma_sflash *sflash = mtd->priv;
> -	size_t bytes_read = 0;
> -	__iomem u8 *src = (__iomem u8 *)KSEG0ADDR(sflash->window + from);
> -	int i;
> -	size_t unaligned_before, unaligned_after;
>  
>  	/* Check address range */
>  	if ((from + len) > mtd->size)
>  		return -EINVAL;
>  
> -	unaligned_before = from & 0x3;
> -	unaligned_after = (from + len) & 0x3;
> +	memcpy(buf, (void *)KSEG0ADDR(sflash->window + from), len);

You should not access iomem with memcpy, there is a memcpy_fromio(), but
it's an unoptimized readb loop on arm.

Marc
>  
> -	for (i = 0; i < unaligned_before; i++) {
> -		*buf = readb(src);
> -		buf++;
> -		src++;
> -		bytes_read++;
> -	}
> -	for (i = from - unaligned_before; i < from + len - unaligned_after;
> -	     i += 4) {
> -		*(u32 *)buf = readl(src);
> -		buf += 4;
> -		src += 4;
> -		bytes_read += 4;
> -	}
> -	for (i = 0; i < unaligned_after; i++) {
> -		*buf = readb(src);
> -		buf++;
> -		src++;
> -		bytes_read++;
> -	}
> -
> -	*retlen = bytes_read;
> -
> -	return 0;
> +	return len;
>  }
>  
>  static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
> 


-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 259 bytes
Desc: OpenPGP digital signature
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120919/1abaa1c1/attachment-0001.sig>

From zajec5 at gmail.com  Wed Sep 19 10:07:47 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Wed, 19 Sep 2012 16:07:47 +0200
Subject: [PATCH RFC] bcm47xxsflash: just use memcpy for reading
In-Reply-To: <5059CC77.5060505@pengutronix.de>
References: <1348056494-30019-1-git-send-email-zajec5@gmail.com>
 <5059CC77.5060505@pengutronix.de>
Message-ID: <CACna6rzsF1gVCiGuhprfD3NPLd1N0bwi0eSuLCMrV23O8JvUWA@mail.gmail.com>

2012/9/19 Marc Kleine-Budde <mkl at pengutronix.de>:
> On 09/19/2012 02:08 PM, Rafa? Mi?ecki wrote:
>> ---
>> Still have to check it with aiaiai
>> ---
>>  drivers/mtd/devices/bcm47xxsflash.c |   31 ++-----------------------------
>>  1 files changed, 2 insertions(+), 29 deletions(-)
>>
>> diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
>> index a328872..2f8dfd4 100644
>> --- a/drivers/mtd/devices/bcm47xxsflash.c
>> +++ b/drivers/mtd/devices/bcm47xxsflash.c
>> @@ -14,41 +14,14 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
>>                             size_t *retlen, u_char *buf)
>>  {
>>       struct bcma_sflash *sflash = mtd->priv;
>> -     size_t bytes_read = 0;
>> -     __iomem u8 *src = (__iomem u8 *)KSEG0ADDR(sflash->window + from);
>> -     int i;
>> -     size_t unaligned_before, unaligned_after;
>>
>>       /* Check address range */
>>       if ((from + len) > mtd->size)
>>               return -EINVAL;
>>
>> -     unaligned_before = from & 0x3;
>> -     unaligned_after = (from + len) & 0x3;
>> +     memcpy(buf, (void *)KSEG0ADDR(sflash->window + from), len);
>
> You should not access iomem with memcpy, there is a memcpy_fromio(), but
> it's an unoptimized readb loop on arm.

Sure, I can replace that with _fromio, which AFAIK is the same for mips.

I'm afraid access to the serial flash can't be really optimal. Saving
is actually even worse, it requires some operations on BCMA core,
polling for ready, etc.

-- 
Rafa?


From jamie at jamieiles.com  Wed Sep 19 11:29:13 2012
From: jamie at jamieiles.com (Jamie Iles)
Date: Wed, 19 Sep 2012 16:29:13 +0100
Subject: nand/denali: Enable DT for Denali NAND controller
In-Reply-To: <1348011095.25236.15.camel@dinh-ubuntu>
References: <1348011095.25236.15.camel@dinh-ubuntu>
Message-ID: <20120919152913.GA19801@page>

Hi Dinh,

On Tue, Sep 18, 2012 at 05:31:35PM -0600, Dinh Nguyen wrote:
> It appears that the denali NAND driver has not been enabled for DT yet.
> Do you know if there is still an interest in doing that and if I can
> help in anyway? I have a strong interest in converting the denali NAND
> driver to be DT capable.

I no longer have access to a platform with the Denali controller so it's 
not something I'd work on personally, but I can imagine that this would 
still be the correct thing to do.

Thanks,

Jamie


From dinguyen at altera.com  Wed Sep 19 16:22:59 2012
From: dinguyen at altera.com (Dinh Nguyen)
Date: Wed, 19 Sep 2012 14:22:59 -0600
Subject: nand/denali: Enable DT for Denali NAND controller
In-Reply-To: <20120919152913.GA19801@page>
References: <1348011095.25236.15.camel@dinh-ubuntu>
 <20120919152913.GA19801@page>
Message-ID: <1348086179.12749.3.camel@dinh-ubuntu>

Hi Jamie,

On Wed, 2012-09-19 at 16:29 +0100, Jamie Iles wrote:
> Hi Dinh,
> 
> On Tue, Sep 18, 2012 at 05:31:35PM -0600, Dinh Nguyen wrote:
> > It appears that the denali NAND driver has not been enabled for DT yet.
> > Do you know if there is still an interest in doing that and if I can
> > help in anyway? I have a strong interest in converting the denali NAND
> > driver to be DT capable.
> 
> I no longer have access to a platform with the Denali controller so it's 
> not something I'd work on personally, but I can imagine that this would 
> still be the correct thing to do.

Ok, I'll take a crack at it since I have to enable it for mach-socfpga.
I guess the correct step is to make the whole driver DT only per David's
comment on the original patch.

Dinh
> 
> Thanks,
> 
> Jamie
> 





From tony at atomide.com  Wed Sep 19 17:05:43 2012
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 19 Sep 2012 14:05:43 -0700
Subject: [PATCH 04/29] ARM: OMAP1: Move board-ams-delta.h from plat to mach
In-Reply-To: <20120919205732.28074.43697.stgit@muffinssi>
References: <20120919205732.28074.43697.stgit@muffinssi>
Message-ID: <20120919210543.28074.10214.stgit@muffinssi>

This is only used by omap1.

And to fix things properly, this should not be included
from the drivers at all.

Cc: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
Cc: Tomi Valkeinen <tomi.valkeinen at ti.com>
Cc: linux-fbdev at vger.kernel.org
Cc: Artem Bityutskiy <Artem.Bityutskiy at linux.intel.com>
Cc: linux-mtd at lists.infradead.org
Cc: Dmitry Torokhov <dmitry.torokhov at gmail.com>
Cc: linux-input at vger.kernel.org
Cc: Peter Ujfalusi <peter.ujfalusi at ti.com>
Cc: Liam Girdwood <lrg at ti.com>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: alsa-devel at alsa-project.org
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/ams-delta-fiq-handler.S        |    2 +-
 arch/arm/mach-omap1/ams-delta-fiq.c                |    2 +-
 arch/arm/mach-omap1/board-ams-delta.c              |    2 +-
 arch/arm/mach-omap1/include/mach/board-ams-delta.h |    0 
 drivers/input/serio/ams_delta_serio.c              |    2 +-
 drivers/mtd/nand/ams-delta.c                       |    2 +-
 drivers/video/omap/lcd_ams_delta.c                 |    2 +-
 sound/soc/omap/ams-delta.c                         |    2 +-
 8 files changed, 7 insertions(+), 7 deletions(-)
 rename arch/arm/{plat-omap/include/plat/board-ams-delta.h => mach-omap1/include/mach/board-ams-delta.h} (100%)

diff --git a/arch/arm/mach-omap1/ams-delta-fiq-handler.S b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
index d2b6acc..3d1e1c2 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq-handler.S
+++ b/arch/arm/mach-omap1/ams-delta-fiq-handler.S
@@ -16,7 +16,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/irqs.h>
 #include <mach/ams-delta-fiq.h>
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index 68e8e56..f12a12a 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -19,7 +19,7 @@
 #include <linux/module.h>
 #include <linux/io.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <asm/fiq.h>
 
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index 05af063..b9929cb 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -35,7 +35,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <mach/mux.h>
 
diff --git a/arch/arm/plat-omap/include/plat/board-ams-delta.h b/arch/arm/mach-omap1/include/mach/board-ams-delta.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/board-ams-delta.h
rename to arch/arm/mach-omap1/include/mach/board-ams-delta.h
diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
index f5fbdf9..45887e3 100644
--- a/drivers/input/serio/ams_delta_serio.c
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -27,7 +27,7 @@
 #include <linux/module.h>
 
 #include <asm/mach-types.h>
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/ams-delta-fiq.h>
 
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index c28eec0..9e7723a 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -29,7 +29,7 @@
 #include <asm/io.h>
 #include <asm/sizes.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include <mach/hardware.h>
 
diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
index 5cca6b3..ed4cad8 100644
--- a/drivers/video/omap/lcd_ams_delta.c
+++ b/drivers/video/omap/lcd_ams_delta.c
@@ -27,7 +27,7 @@
 #include <linux/lcd.h>
 #include <linux/gpio.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 
 #include "omapfb.h"
 
diff --git a/sound/soc/omap/ams-delta.c b/sound/soc/omap/ams-delta.c
index 7b18b74..98e25d5 100644
--- a/sound/soc/omap/ams-delta.c
+++ b/sound/soc/omap/ams-delta.c
@@ -32,7 +32,7 @@
 
 #include <asm/mach-types.h>
 
-#include <plat/board-ams-delta.h>
+#include <mach/board-ams-delta.h>
 #include <plat/mcbsp.h>
 
 #include "omap-mcbsp.h"



From josh.wu at atmel.com  Wed Sep 19 22:03:32 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Thu, 20 Sep 2012 10:03:32 +0800
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
Message-ID: <505A7974.9060108@atmel.com>

Hi, Artem

Do you have any feedback since there is a long time about this patch?

Best Regards,
Josh Wu

On 9/11/2012 3:10 PM, Josh Wu wrote:
> Add err_ecc_ioremap label to fix following errors:
> ---8<---
>    CC      drivers/mtd/nand/atmel_nand.o
> drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
> drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
> make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
> make[2]: *** [drivers/mtd/nand] Error 2
> make[1]: *** [drivers/mtd] Error 2
> make: *** [drivers] Error 2
> --->8---
>
> This error was introduced in b654a9a46fc2100b318050483f8c5b5d0f187303 (mtd: atmel nand: fix gpio missing request)
>
> Signed-off-by: Josh Wu <josh.wu at atmel.com>
> ---
> change logs:
>    Add detail information for the commit message.
>
>   drivers/mtd/nand/atmel_nand.c |    3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 6a5a35b..9144557 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -1399,7 +1399,7 @@ static int __init atmel_nand_probe(struct platform_device *pdev)
>   	if (pdev->dev.of_node) {
>   		res = atmel_of_init_port(host, pdev->dev.of_node);
>   		if (res)
> -			goto err_nand_ioremap;
> +			goto err_ecc_ioremap;
>   	} else {
>   		memcpy(&host->board, pdev->dev.platform_data,
>   		       sizeof(struct atmel_nand_data));
> @@ -1560,6 +1560,7 @@ err_no_card:
>   	platform_set_drvdata(pdev, NULL);
>   	if (host->dma_chan)
>   		dma_release_channel(host->dma_chan);
> +err_ecc_ioremap:
>   	iounmap(host->io_base);
>   err_nand_ioremap:
>   	kfree(host);



From broonie at opensource.wolfsonmicro.com  Wed Sep 19 21:16:31 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 19 Sep 2012 21:16:31 -0400
Subject: [PATCH 04/29] ARM: OMAP1: Move board-ams-delta.h from plat to mach
In-Reply-To: <20120919210543.28074.10214.stgit@muffinssi>
References: <20120919205732.28074.43697.stgit@muffinssi>
 <20120919210543.28074.10214.stgit@muffinssi>
Message-ID: <20120920011630.GB17666@opensource.wolfsonmicro.com>

On Wed, Sep 19, 2012 at 02:05:43PM -0700, Tony Lindgren wrote:
> This is only used by omap1.
> 
> And to fix things properly, this should not be included
> from the drivers at all.

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

or I can apply it if that's easier.


From plagnioj at jcrosoft.com  Thu Sep 20 01:23:33 2012
From: plagnioj at jcrosoft.com (Jean-Christophe PLAGNIOL-VILLARD)
Date: Thu, 20 Sep 2012 07:23:33 +0200
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
Message-ID: <20120920052333.GC17667@game.jcrosoft.org>

On 15:10 Tue 11 Sep     , Josh Wu wrote:
> Add err_ecc_ioremap label to fix following errors:
> ---8<--- 
>   CC      drivers/mtd/nand/atmel_nand.o
> drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
> drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
> make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
> make[2]: *** [drivers/mtd/nand] Error 2
> make[1]: *** [drivers/mtd] Error 2
> make: *** [drivers] Error 2
> --->8---
switch to devm_xxx instead this will simplify the error patch and remove patch

Best Regards,
J.


From shawn.guo at linaro.org  Thu Sep 20 02:45:13 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 20 Sep 2012 14:45:13 +0800
Subject: [PATCH v2 00/34] i.MX multi-platform support
Message-ID: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>

Here is the second post, which should have addressed the comments that
reviewers put on v1.

It's available on branch below.

  git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform-v2

And it's based on the following branches.

  calxeda/multi-plat
  arm-soc/multiplatform/platform-data
  arm-soc/multiplatform/smp_ops
  arm-soc/imx/cleanup
  arm-soc/imx/dt
  sound/for-3.7

Subsystem maintainers,

I plan to send the whole series for 3.7 via arm-soc tree.  Please let
me know if you have problem with that.  Thanks.

Shawn

---

Shawn Guo (34):
  ARM: imx: include board headers in the same folder
  ARM: imx: move iomux drivers and headers into mach-imx
  ARM: imx: remove unnecessary inclusion from device-imx*.h
  ARM: imx: move platform device code into mach-imx
  ARM: imx: merge plat-mxc into mach-imx
  ARM: imx: include common.h rather than mach/common.h
  ARM: imx: ARM: imx: include cpuidle.h rather than mach/cpuidle.h
  ARM: imx: include iim.h rather than mach/iim.h
  ARM: imx: include iram.h rather than mach/iram.h
  ARM: imx: include ulpi.h rather than mach/ulpi.h
  media: mx1_camera: remove the driver
  ARM: imx: remove mach/dma-mx1-mx2.h
  dma: ipu: rename mach/ipu.h to include/linux/dma/ipu-dma.h
  dma: imx-sdma: remove unneeded mach/hardware.h inclusion
  ASoC: imx-ssi: remove unneeded mach/hardware.h inclusion
  usb: ehci-mxc: remove unneeded mach/hardware.h inclusion
  video: mx3fb: remove unneeded mach/hardware.h inclusion
  watchdog: imx2_wdt: remove unneeded mach/hardware.h inclusion
  i2c: imx: remove cpu_is_xxx by using platform_device_id
  mtd: mxc_nand: remove cpu_is_xxx by using platform_device_id
  rtc: mxc_rtc: remove cpu_is_xxx by using platform_device_id
  dma: imx-dma: use devm_kzalloc and devm_request_irq
  dma: imx-dma: retrieve MEM and IRQ from resources
  dma: imx-dma: remove cpu_is_xxx by using platform_device_id
  media: mx2_camera: remove dead code in mx2_camera_add_device
  media: mx2_camera: use managed functions to clean up code
  media: mx2_camera: remove cpu_is_xxx by using platform_device_id
  mmc: mxcmmc: remove cpu_is_xxx by using platform_device_id
  video: imxfb: remove cpu_is_xxx by using platform_device_id
  ARM: imx: move debug macros to include/debug
  ARM: imx: include hardware.h rather than mach/hardware.h
  ARM: imx: remove header file mach/irqs.h
  ARM: imx: call mxc_device_init() in soc specific function
  ARM: imx: enable multi-platform build

 .../devicetree/bindings/i2c/fsl-imx-i2c.txt        |    4 +-
 MAINTAINERS                                        |    1 -
 arch/arm/Kconfig                                   |   15 +-
 arch/arm/Kconfig.debug                             |    8 +
 arch/arm/Makefile                                  |    1 -
 arch/arm/boot/dts/imx27.dtsi                       |    4 +-
 arch/arm/boot/dts/imx51.dtsi                       |    4 +-
 arch/arm/boot/dts/imx53.dtsi                       |    6 +-
 arch/arm/boot/dts/imx6q.dtsi                       |    6 +-
 arch/arm/configs/imx_v4_v5_defconfig               |    5 +-
 arch/arm/configs/imx_v6_v7_defconfig               |    3 +-
 .../mach/debug-macro.S => include/debug/imx.S}     |   33 +-
 arch/arm/{plat-mxc => mach-imx}/3ds_debugboard.c   |    2 +-
 .../include/mach => mach-imx}/3ds_debugboard.h     |    0
 arch/arm/mach-imx/Kconfig                          |   89 +-
 arch/arm/mach-imx/Makefile                         |   23 +-
 arch/arm/{plat-mxc => mach-imx}/avic.c             |    5 +-
 .../include/mach => mach-imx}/board-mx31lilly.h    |    0
 .../include/mach => mach-imx}/board-mx31lite.h     |    0
 .../include/mach => mach-imx}/board-mx31moboard.h  |    0
 .../include/mach => mach-imx}/board-pcm038.h       |    0
 arch/arm/mach-imx/clk-imx1.c                       |   18 +-
 arch/arm/mach-imx/clk-imx21.c                      |   18 +-
 arch/arm/mach-imx/clk-imx25.c                      |   26 +-
 arch/arm/mach-imx/clk-imx27.c                      |   40 +-
 arch/arm/mach-imx/clk-imx31.c                      |   21 +-
 arch/arm/mach-imx/clk-imx35.c                      |   13 +-
 arch/arm/mach-imx/clk-imx51-imx53.c                |   15 +-
 arch/arm/mach-imx/clk-imx6q.c                      |    3 +-
 arch/arm/mach-imx/clk-pllv1.c                      |    4 +-
 .../{plat-mxc/include/mach => mach-imx}/common.h   |    1 +
 arch/arm/mach-imx/cpu-imx25.c                      |    5 +-
 arch/arm/mach-imx/cpu-imx27.c                      |    2 +-
 arch/arm/mach-imx/cpu-imx31.c                      |    7 +-
 arch/arm/mach-imx/cpu-imx35.c                      |    5 +-
 arch/arm/mach-imx/cpu-imx5.c                       |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpu.c              |    3 +-
 arch/arm/mach-imx/cpu_op-mx51.c                    |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpufreq.c          |    3 +-
 arch/arm/{plat-mxc => mach-imx}/cpuidle.c          |    0
 .../{plat-mxc/include/mach => mach-imx}/cpuidle.h  |    0
 arch/arm/mach-imx/devices-imx1.h                   |    3 +-
 arch/arm/mach-imx/devices-imx21.h                  |    3 +-
 arch/arm/mach-imx/devices-imx25.h                  |    3 +-
 arch/arm/mach-imx/devices-imx27.h                  |    3 +-
 arch/arm/mach-imx/devices-imx31.h                  |    3 +-
 arch/arm/mach-imx/devices-imx35.h                  |    3 +-
 arch/arm/mach-imx/devices-imx50.h                  |    3 +-
 arch/arm/mach-imx/devices-imx51.h                  |    3 +-
 arch/arm/{plat-mxc => mach-imx}/devices/Kconfig    |    3 -
 arch/arm/{plat-mxc => mach-imx}/devices/Makefile   |    3 +-
 .../mach => mach-imx/devices}/devices-common.h     |   19 +-
 arch/arm/{plat-mxc => mach-imx/devices}/devices.c  |    4 +-
 .../devices/platform-ahci-imx.c                    |    5 +-
 .../{plat-mxc => mach-imx}/devices/platform-fec.c  |    5 +-
 .../devices/platform-flexcan.c                     |    4 +-
 .../devices/platform-fsl-usb2-udc.c                |    5 +-
 .../devices/platform-gpio-mxc.c                    |    2 +-
 .../devices/platform-gpio_keys.c                   |    5 +-
 .../devices/platform-imx-dma.c                     |   23 +-
 .../devices/platform-imx-fb.c                      |   16 +-
 .../devices/platform-imx-i2c.c                     |   32 +-
 .../devices/platform-imx-keypad.c                  |    4 +-
 .../devices/platform-imx-ssi.c                     |    4 +-
 .../devices/platform-imx-uart.c                    |    4 +-
 .../devices/platform-imx2-wdt.c                    |    5 +-
 .../devices/platform-imx21-hcd.c                   |    4 +-
 .../devices/platform-imx_udc.c                     |    4 +-
 .../devices/platform-imxdi_rtc.c                   |    5 +-
 .../devices/platform-ipu-core.c                    |    5 +-
 .../devices/platform-mx2-camera.c                  |   16 +-
 .../devices/platform-mxc-ehci.c                    |    5 +-
 .../devices/platform-mxc-mmc.c                     |   20 +-
 .../devices/platform-mxc_nand.c                    |   25 +-
 .../devices/platform-mxc_pwm.c                     |    4 +-
 .../devices/platform-mxc_rnga.c                    |    4 +-
 .../devices/platform-mxc_rtc.c                     |   13 +-
 .../devices/platform-mxc_w1.c                      |    4 +-
 .../devices/platform-pata_imx.c                    |    4 +-
 .../devices/platform-sdhci-esdhc-imx.c             |    5 +-
 .../devices/platform-spi_imx.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx25.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx27.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx31.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx35.c                     |    4 +-
 arch/arm/mach-imx/ehci-imx5.c                      |    4 +-
 arch/arm/{plat-mxc => mach-imx}/epit.c             |    6 +-
 .../include/mach => mach-imx}/eukrea-baseboards.h  |    0
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c       |    7 +-
 arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c     |    8 +-
 arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c     |    7 +-
 arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c     |    7 +-
 .../{plat-mxc/include/mach => mach-imx}/hardware.h |   26 +-
 arch/arm/mach-imx/hotplug.c                        |    3 +-
 arch/arm/{plat-mxc/include/mach => mach-imx}/iim.h |    0
 arch/arm/mach-imx/imx27-dt.c                       |   11 +-
 arch/arm/mach-imx/imx31-dt.c                       |    5 +-
 arch/arm/mach-imx/imx51-dt.c                       |    9 +-
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h       |   10 -
 arch/arm/mach-imx/iomux-imx31.c                    |    5 +-
 .../include/mach => mach-imx}/iomux-mx1.h          |    2 +-
 .../include/mach => mach-imx}/iomux-mx21.h         |    4 +-
 .../include/mach => mach-imx}/iomux-mx25.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx27.h         |    4 +-
 .../include/mach => mach-imx}/iomux-mx2x.h         |    0
 .../include/mach => mach-imx}/iomux-mx3.h          |    0
 .../include/mach => mach-imx}/iomux-mx35.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx50.h         |    2 +-
 .../include/mach => mach-imx}/iomux-mx51.h         |    2 +-
 arch/arm/{plat-mxc => mach-imx}/iomux-v1.c         |    5 +-
 .../{plat-mxc/include/mach => mach-imx}/iomux-v1.h |    0
 arch/arm/{plat-mxc => mach-imx}/iomux-v3.c         |    5 +-
 .../{plat-mxc/include/mach => mach-imx}/iomux-v3.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/iram.h |    0
 arch/arm/{plat-mxc => mach-imx}/iram_alloc.c       |    3 +-
 arch/arm/{plat-mxc => mach-imx}/irq-common.c       |    0
 arch/arm/{plat-mxc => mach-imx}/irq-common.h       |    3 +
 arch/arm/mach-imx/lluart.c                         |    3 +-
 arch/arm/mach-imx/mach-apf9328.c                   |    7 +-
 arch/arm/mach-imx/mach-armadillo5x0.c              |    9 +-
 arch/arm/mach-imx/mach-bug.c                       |    7 +-
 arch/arm/mach-imx/mach-cpuimx27.c                  |   11 +-
 arch/arm/mach-imx/mach-cpuimx35.c                  |    9 +-
 arch/arm/mach-imx/mach-cpuimx51sd.c                |    9 +-
 arch/arm/mach-imx/mach-eukrea_cpuimx25.c           |   10 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c        |    6 +-
 arch/arm/mach-imx/mach-imx27ipcam.c                |    6 +-
 arch/arm/mach-imx/mach-imx27lite.c                 |    6 +-
 arch/arm/mach-imx/mach-imx53.c                     |   11 +-
 arch/arm/mach-imx/mach-imx6q.c                     |    6 +-
 arch/arm/mach-imx/mach-kzm_arm11_01.c              |    7 +-
 arch/arm/mach-imx/mach-mx1ads.c                    |    7 +-
 arch/arm/mach-imx/mach-mx21ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx25_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx27_3ds.c                  |   10 +-
 arch/arm/mach-imx/mach-mx27ads.c                   |    6 +-
 arch/arm/mach-imx/mach-mx31_3ds.c                  |   12 +-
 arch/arm/mach-imx/mach-mx31ads.c                   |    5 +-
 arch/arm/mach-imx/mach-mx31lilly.c                 |   11 +-
 arch/arm/mach-imx/mach-mx31lite.c                  |   11 +-
 arch/arm/mach-imx/mach-mx31moboard.c               |   14 +-
 arch/arm/mach-imx/mach-mx35_3ds.c                  |    8 +-
 arch/arm/mach-imx/mach-mx50_rdp.c                  |    7 +-
 arch/arm/mach-imx/mach-mx51_3ds.c                  |    9 +-
 arch/arm/mach-imx/mach-mx51_babbage.c              |    7 +-
 arch/arm/mach-imx/mach-mxt_td60.c                  |    6 +-
 arch/arm/mach-imx/mach-pca100.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037.c                    |    8 +-
 arch/arm/mach-imx/mach-pcm037_eet.c                |    5 +-
 arch/arm/mach-imx/mach-pcm038.c                    |   13 +-
 arch/arm/mach-imx/mach-pcm043.c                    |    9 +-
 arch/arm/mach-imx/mach-qong.c                      |    6 +-
 arch/arm/mach-imx/mach-scb9328.c                   |    7 +-
 arch/arm/mach-imx/mach-vpr200.c                    |    7 +-
 arch/arm/mach-imx/mm-imx1.c                        |    9 +-
 arch/arm/mach-imx/mm-imx21.c                       |   14 +-
 arch/arm/mach-imx/mm-imx25.c                       |   12 +-
 arch/arm/mach-imx/mm-imx27.c                       |   14 +-
 arch/arm/mach-imx/mm-imx3.c                        |   13 +-
 arch/arm/mach-imx/mm-imx5.c                        |   12 +-
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c            |   18 -
 arch/arm/mach-imx/mx1-camera-fiq.S                 |   35 -
 arch/arm/{plat-mxc/include/mach => mach-imx}/mx1.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx21.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx25.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx27.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx2x.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx31.h |    0
 arch/arm/mach-imx/mx31lilly-db.c                   |    9 +-
 arch/arm/mach-imx/mx31lite-db.c                    |    9 +-
 arch/arm/mach-imx/mx31moboard-devboard.c           |    9 +-
 arch/arm/mach-imx/mx31moboard-marxbot.c            |    9 +-
 arch/arm/mach-imx/mx31moboard-smartbot.c           |   11 +-
 .../arm/{plat-mxc/include/mach => mach-imx}/mx35.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx3x.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx50.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx51.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx53.h |    0
 .../arm/{plat-mxc/include/mach => mach-imx}/mx6q.h |    0
 arch/arm/{plat-mxc/include/mach => mach-imx}/mxc.h |    0
 arch/arm/mach-imx/pcm970-baseboard.c               |    7 +-
 arch/arm/mach-imx/platsmp.c                        |    5 +-
 arch/arm/mach-imx/pm-imx27.c                       |    3 +-
 arch/arm/mach-imx/pm-imx3.c                        |    7 +-
 arch/arm/mach-imx/pm-imx5.c                        |    7 +-
 arch/arm/mach-imx/pm-imx6q.c                       |    5 +-
 arch/arm/{plat-mxc => mach-imx}/ssi-fiq-ksym.c     |    0
 arch/arm/{plat-mxc => mach-imx}/ssi-fiq.S          |    0
 arch/arm/{plat-mxc => mach-imx}/system.c           |    5 +-
 arch/arm/{plat-mxc => mach-imx}/time.c             |    5 +-
 arch/arm/{plat-mxc => mach-imx}/tzic.c             |    6 +-
 arch/arm/{plat-mxc => mach-imx}/ulpi.c             |    2 +-
 .../arm/{plat-mxc/include/mach => mach-imx}/ulpi.h |    0
 arch/arm/plat-mxc/Kconfig                          |   89 --
 arch/arm/plat-mxc/Makefile                         |   24 -
 arch/arm/plat-mxc/devices/platform-mx1-camera.c    |   42 -
 arch/arm/plat-mxc/include/mach/irqs.h              |   21 -
 arch/arm/plat-mxc/include/mach/timex.h             |   22 -
 arch/arm/plat-mxc/include/mach/uncompress.h        |  132 ---
 drivers/dma/imx-dma.c                              |  137 +--
 drivers/dma/imx-sdma.c                             |    1 -
 drivers/dma/ipu/ipu_idmac.c                        |    3 +-
 drivers/dma/ipu/ipu_irq.c                          |    3 +-
 drivers/i2c/busses/i2c-imx.c                       |   40 +-
 drivers/media/video/Kconfig                        |   12 -
 drivers/media/video/Makefile                       |    1 -
 drivers/media/video/mx1_camera.c                   |  889 --------------------
 drivers/media/video/mx2_camera.c                   |  246 +++---
 drivers/media/video/mx3_camera.c                   |    2 +-
 drivers/mmc/host/mxcmmc.c                          |   31 +-
 drivers/mtd/nand/mxc_nand.c                        |   86 +-
 drivers/rtc/rtc-mxc.c                              |   34 +-
 drivers/usb/host/ehci-mxc.c                        |    1 -
 drivers/video/imxfb.c                              |   38 +-
 drivers/video/mx3fb.c                              |    3 +-
 drivers/watchdog/imx2_wdt.c                        |    1 -
 .../mach/ipu.h => include/linux/dma/ipu-dma.h      |    6 +-
 include/linux/platform_data/asoc-imx-ssi.h         |    2 +
 include/linux/platform_data/camera-mx1.h           |   35 -
 include/linux/platform_data/dma-imx.h              |    4 +-
 sound/soc/fsl/imx-pcm-fiq.c                        |    1 -
 sound/soc/fsl/imx-ssi.c                            |    1 -
 222 files changed, 1115 insertions(+), 2161 deletions(-)
 rename arch/arm/{plat-mxc/include/mach/debug-macro.S => include/debug/imx.S} (59%)
 rename arch/arm/{plat-mxc => mach-imx}/3ds_debugboard.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/3ds_debugboard.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/avic.c (98%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31lilly.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31lite.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-mx31moboard.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/board-pcm038.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/common.h (99%)
 rename arch/arm/{plat-mxc => mach-imx}/cpu.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/cpufreq.c (99%)
 rename arch/arm/{plat-mxc => mach-imx}/cpuidle.c (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/cpuidle.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/Kconfig (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/Makefile (96%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx/devices}/devices-common.h (96%)
 rename arch/arm/{plat-mxc => mach-imx/devices}/devices.c (92%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-ahci-imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-fec.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-flexcan.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-fsl-usb2-udc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-gpio-mxc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-gpio_keys.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-dma.c (63%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-fb.c (79%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-i2c.c (76%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-keypad.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-ssi.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx-uart.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx2-wdt.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx21-hcd.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imx_udc.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-imxdi_rtc.c (94%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-ipu-core.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mx2-camera.c (83%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc-ehci.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc-mmc.c (76%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_nand.c (74%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_pwm.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_rnga.c (95%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_rtc.c (77%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-mxc_w1.c (95%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-pata_imx.c (96%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-sdhci-esdhc-imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/devices/platform-spi_imx.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/epit.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/eukrea-baseboards.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/hardware.h (94%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iim.h (100%)
 delete mode 100644 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx1.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx21.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx25.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx27.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx35.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx50.h (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-mx51.h (99%)
 rename arch/arm/{plat-mxc => mach-imx}/iomux-v1.c (98%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-v1.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/iomux-v3.c (97%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iomux-v3.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/iram.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/iram_alloc.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/irq-common.c (100%)
 rename arch/arm/{plat-mxc => mach-imx}/irq-common.h (94%)
 delete mode 100644 arch/arm/mach-imx/mx1-camera-fiq-ksym.c
 delete mode 100644 arch/arm/mach-imx/mx1-camera-fiq.S
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx1.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx21.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx25.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx27.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx2x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx31.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx35.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx3x.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx50.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx51.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx53.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mx6q.h (100%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/mxc.h (100%)
 rename arch/arm/{plat-mxc => mach-imx}/ssi-fiq-ksym.c (100%)
 rename arch/arm/{plat-mxc => mach-imx}/ssi-fiq.S (100%)
 rename arch/arm/{plat-mxc => mach-imx}/system.c (97%)
 rename arch/arm/{plat-mxc => mach-imx}/time.c (99%)
 rename arch/arm/{plat-mxc => mach-imx}/tzic.c (98%)
 rename arch/arm/{plat-mxc => mach-imx}/ulpi.c (99%)
 rename arch/arm/{plat-mxc/include/mach => mach-imx}/ulpi.h (100%)
 delete mode 100644 arch/arm/plat-mxc/Kconfig
 delete mode 100644 arch/arm/plat-mxc/Makefile
 delete mode 100644 arch/arm/plat-mxc/devices/platform-mx1-camera.c
 delete mode 100644 arch/arm/plat-mxc/include/mach/irqs.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/timex.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/uncompress.h
 delete mode 100644 drivers/media/video/mx1_camera.c
 rename arch/arm/plat-mxc/include/mach/ipu.h => include/linux/dma/ipu-dma.h (97%)
 delete mode 100644 include/linux/platform_data/camera-mx1.h

-- 
1.7.9.5



From shawn.guo at linaro.org  Thu Sep 20 02:45:33 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 20 Sep 2012 14:45:33 +0800
Subject: [PATCH v2 20/34] mtd: mxc_nand: remove cpu_is_xxx by using
 platform_device_id
In-Reply-To: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <1348123547-31082-21-git-send-email-shawn.guo@linaro.org>

It changes the driver to use platform_device_id rather than cpu_is_xxx
to determine the controller type, and updates the platform code
accordingly.

As the result, mach/hardware.h inclusion gets removed from the driver.

Signed-off-by: Shawn Guo <shawn.guo at linaro.org>
Acked-by: Sascha Hauer <s.hauer at pengutronix.de>
Acked-by: Arnd Bergmann <arnd at arndb.de>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: linux-mtd at lists.infradead.org
---
 arch/arm/mach-imx/clk-imx21.c                 |    2 +-
 arch/arm/mach-imx/clk-imx25.c                 |    2 +-
 arch/arm/mach-imx/clk-imx27.c                 |    2 +-
 arch/arm/mach-imx/clk-imx31.c                 |    2 +-
 arch/arm/mach-imx/clk-imx35.c                 |    2 +-
 arch/arm/mach-imx/clk-imx51-imx53.c           |    2 +-
 arch/arm/mach-imx/devices/devices-common.h    |    1 +
 arch/arm/mach-imx/devices/platform-mxc_nand.c |   20 +++---
 arch/arm/mach-imx/imx27-dt.c                  |    2 +-
 drivers/mtd/nand/mxc_nand.c                   |   86 +++++++++++++++----------
 10 files changed, 71 insertions(+), 50 deletions(-)

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index 09fc31c..96a4788 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -162,7 +162,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 	clk_register_clkdev(clk[lcdc_hclk_gate], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[usb_gate], "per", "imx21-hcd.0");
 	clk_register_clkdev(clk[usb_hclk_gate], "ahb", "imx21-hcd.0");
-	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_gate], NULL, "imx21-nand.0");
 	clk_register_clkdev(clk[dma_hclk_gate], "ahb", "imx-dma");
 	clk_register_clkdev(clk[dma_gate], "ipg", "imx-dma");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index 54edac0..1aea073 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -198,7 +198,7 @@ int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usbotg_ahb], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
-	clk_register_clkdev(clk[nfc_ipg_per], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_ipg_per], NULL, "imx25-nand.0");
 	/* i.mx25 has the i.mx35 type cspi */
 	clk_register_clkdev(clk[cspi1_ipg], NULL, "imx35-cspi.0");
 	clk_register_clkdev(clk[cspi2_ipg], NULL, "imx35-cspi.1");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index d9aac0f..6ae2868 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -239,7 +239,7 @@ int __init mx27_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-	clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
 	clk_register_clkdev(clk[vpu_baud_gate], "per", "imx-vpu");
 	clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "imx-vpu");
 	clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 76e6462..729d1a9 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -127,7 +127,7 @@ int __init mx31_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[rtc_gate], NULL, "mxc_rtc");
 	clk_register_clkdev(clk[epit1_gate], "epit", NULL);
 	clk_register_clkdev(clk[epit2_gate], "epit", NULL);
-	clk_register_clkdev(clk[nfc], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0");
 	clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
 	clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
 	clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index e411153..2f15c6d 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -252,7 +252,7 @@ int __init mx35_clocks_init()
 	clk_register_clkdev(clk[ipg], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+	clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0");
 
 	clk_prepare_enable(clk[spba_gate]);
 	clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 54303a8..5399682 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -270,7 +270,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_register_clkdev(clk[usboh3_per_gate], "per", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
-	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
+	clk_register_clkdev(clk[nfc_gate], NULL, "imx51-nand");
 	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
 	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
 	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index b0f4747..d9717b3 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -239,6 +239,7 @@ struct platform_device *__init imx_add_mxc_mmc(
 
 #include <linux/platform_data/mtd-mxc_nand.h>
 struct imx_mxc_nand_data {
+	const char *devid;
 	/*
 	 * id is traditionally 0, but -1 is more appropriate.  We use -1 for new
 	 * machines but don't change existing devices as the nand device usually
diff --git a/arch/arm/mach-imx/devices/platform-mxc_nand.c b/arch/arm/mach-imx/devices/platform-mxc_nand.c
index eb73b82..cec6961 100644
--- a/arch/arm/mach-imx/devices/platform-mxc_nand.c
+++ b/arch/arm/mach-imx/devices/platform-mxc_nand.c
@@ -10,15 +10,17 @@
 #include <mach/hardware.h>
 #include "devices-common.h"
 
-#define imx_mxc_nand_data_entry_single(soc, _size)			\
+#define imx_mxc_nand_data_entry_single(soc, _devid, _size)		\
 	{								\
+		.devid = _devid,					\
 		.iobase = soc ## _NFC_BASE_ADDR,			\
 		.iosize = _size,					\
 		.irq = soc ## _INT_NFC					\
 	}
 
-#define imx_mxc_nandv3_data_entry_single(soc, _size)			\
+#define imx_mxc_nandv3_data_entry_single(soc, _devid, _size)		\
 	{								\
+		.devid = _devid,					\
 		.id = -1,						\
 		.iobase = soc ## _NFC_BASE_ADDR,			\
 		.iosize = _size,					\
@@ -28,32 +30,32 @@
 
 #ifdef CONFIG_SOC_IMX21
 const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX21, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX21, "imx21-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX21 */
 
 #ifdef CONFIG_SOC_IMX25
 const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX25, SZ_8K);
+	imx_mxc_nand_data_entry_single(MX25, "imx25-nand", SZ_8K);
 #endif /* ifdef CONFIG_SOC_IMX25 */
 
 #ifdef CONFIG_SOC_IMX27
 const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX27, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX27, "imx27-nand", SZ_4K);
 #endif /* ifdef CONFIG_SOC_IMX27 */
 
 #ifdef CONFIG_SOC_IMX31
 const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX31, SZ_4K);
+	imx_mxc_nand_data_entry_single(MX31, "imx27-nand", SZ_4K);
 #endif
 
 #ifdef CONFIG_SOC_IMX35
 const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
-	imx_mxc_nand_data_entry_single(MX35, SZ_8K);
+	imx_mxc_nand_data_entry_single(MX35, "imx25-nand", SZ_8K);
 #endif
 
 #ifdef CONFIG_SOC_IMX51
 const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
-	imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
+	imx_mxc_nandv3_data_entry_single(MX51, "imx51-nand", SZ_16K);
 #endif
 
 struct platform_device *__init imx_add_mxc_nand(
@@ -76,7 +78,7 @@ struct platform_device *__init imx_add_mxc_nand(
 			.flags = IORESOURCE_IRQ,
 		},
 	};
-	return imx_add_platform_device("mxc_nand", data->id,
+	return imx_add_platform_device(data->devid, data->id,
 			res + !data->axibase,
 			ARRAY_SIZE(res) - !data->axibase,
 			pdata, sizeof(*pdata));
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 43fbf86..a6c288e 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -29,7 +29,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI2_BASE_ADDR, "imx27-cspi.1", NULL),
 	OF_DEV_AUXDATA("fsl,imx27-cspi", MX27_CSPI3_BASE_ADDR, "imx27-cspi.2", NULL),
 	OF_DEV_AUXDATA("fsl,imx27-wdt", MX27_WDOG_BASE_ADDR, "imx2-wdt.0", NULL),
-	OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "mxc_nand.0", NULL),
+	OF_DEV_AUXDATA("fsl,imx27-nand", MX27_NFC_BASE_ADDR, "imx27-nand.0", NULL),
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 5683604..d5f8f01 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -37,15 +37,9 @@
 
 #include <asm/mach/flash.h>
 #include <linux/platform_data/mtd-mxc_nand.h>
-#include <mach/hardware.h>
 
 #define DRIVER_NAME "mxc_nand"
 
-#define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
-#define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
-#define nfc_is_v3_2()		(cpu_is_mx51() || cpu_is_mx53())
-#define nfc_is_v3()		nfc_is_v3_2()
-
 /* Addresses for NFC registers */
 #define NFC_V1_V2_BUF_SIZE		(host->regs + 0x00)
 #define NFC_V1_V2_BUF_ADDR		(host->regs + 0x04)
@@ -1260,6 +1254,45 @@ static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
 	.eccsize = 0,
 };
 
+static inline int is_imx21_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx21_nand_devtype_data;
+}
+
+static inline int is_imx27_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx27_nand_devtype_data;
+}
+
+static inline int is_imx25_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx25_nand_devtype_data;
+}
+
+static inline int is_imx51_nfc(struct mxc_nand_host *host)
+{
+	return host->devtype_data == &imx51_nand_devtype_data;
+}
+
+static struct platform_device_id mxcnd_devtype[] = {
+	{
+		.name = "imx21-nand",
+		.driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
+	}, {
+		.name = "imx27-nand",
+		.driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
+	}, {
+		.name = "imx25-nand",
+		.driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
+	}, {
+		.name = "imx51-nand",
+		.driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
+	}, {
+		/* sentinel */
+	}
+};
+MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
+
 #ifdef CONFIG_OF_MTD
 static const struct of_device_id mxcnd_dt_ids[] = {
 	{
@@ -1311,30 +1344,6 @@ static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
 }
 #endif
 
-static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
-{
-	struct mxc_nand_platform_data *pdata = host->dev->platform_data;
-
-	if (!pdata)
-		return -ENODEV;
-
-	host->pdata = *pdata;
-
-	if (nfc_is_v1()) {
-		if (cpu_is_mx21())
-			host->devtype_data = &imx21_nand_devtype_data;
-		else
-			host->devtype_data = &imx27_nand_devtype_data;
-	} else if (nfc_is_v21()) {
-		host->devtype_data = &imx25_nand_devtype_data;
-	} else if (nfc_is_v3_2()) {
-		host->devtype_data = &imx51_nand_devtype_data;
-	} else
-		BUG();
-
-	return 0;
-}
-
 static int __init mxcnd_probe(struct platform_device *pdev)
 {
 	struct nand_chip *this;
@@ -1396,8 +1405,16 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	host->main_area0 = host->base;
 
 	err = mxcnd_probe_dt(host);
-	if (err > 0)
-		err = mxcnd_probe_pdata(host);
+	if (err > 0) {
+		struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
+		if (pdata) {
+			host->pdata = *pdata;
+			host->devtype_data = (struct mxc_nand_devtype_data *)
+						pdev->id_entry->driver_data;
+		} else {
+			err = -ENODEV;
+		}
+	}
 	if (err < 0)
 		goto eirq;
 
@@ -1473,7 +1490,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 	}
 
 	/* first scan to find the device and get the page size */
-	if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
+	if (nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL)) {
 		err = -ENXIO;
 		goto escan;
 	}
@@ -1487,7 +1504,7 @@ static int __init mxcnd_probe(struct platform_device *pdev)
 		this->ecc.layout = host->devtype_data->ecclayout_4k;
 
 	if (this->ecc.mode == NAND_ECC_HW) {
-		if (nfc_is_v1())
+		if (is_imx21_nfc(host) || is_imx27_nfc(host))
 			this->ecc.strength = 1;
 		else
 			this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
@@ -1549,6 +1566,7 @@ static struct platform_driver mxcnd_driver = {
 		   .owner = THIS_MODULE,
 		   .of_match_table = of_match_ptr(mxcnd_dt_ids),
 	},
+	.id_table = mxcnd_devtype,
 	.remove = __devexit_p(mxcnd_remove),
 };
 
-- 
1.7.9.5



From arnd at arndb.de  Thu Sep 20 03:39:34 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 20 Sep 2012 07:39:34 +0000
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
Message-ID: <201209200739.34899.arnd@arndb.de>

On Thursday 20 September 2012, Shawn Guo wrote:
> 
> Here is the second post, which should have addressed the comments that
> reviewers put on v1.
> 
> It's available on branch below.
> 
>   git://git.linaro.org/people/shawnguo/linux-2.6.git imx/multi-platform-v2
> 
> And it's based on the following branches.
> 
>   calxeda/multi-plat
>   arm-soc/multiplatform/platform-data
>   arm-soc/multiplatform/smp_ops
>   arm-soc/imx/cleanup
>   arm-soc/imx/dt
>   sound/for-3.7
> 
> Subsystem maintainers,
> 
> I plan to send the whole series for 3.7 via arm-soc tree.  Please let
> me know if you have problem with that.  Thanks.

The first five branches are scheduled to go through the arm-soc tree, so
I'm fine with that. For the sound/for-3.7 branch, I'd like to know when
to expect that hitting mainline. If it always gets in very early during the
merge window, it's probably ok to put the imx/multi-platform patches into
the same branch as the other ones in arm-soc and wait for the sound stuff
to hit mainline first, otherwise I'd suggest we start a second
next/multiplatform-2 branch for imx and send the first part early on
but then wait with the second batch before sound gets in.

	Arnd


From nicolas.ferre at atmel.com  Thu Sep 20 04:20:48 2012
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Thu, 20 Sep 2012 10:20:48 +0200
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <20120920052333.GC17667@game.jcrosoft.org>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
 <20120920052333.GC17667@game.jcrosoft.org>
Message-ID: <505AD1E0.2040607@atmel.com>

On 09/20/2012 07:23 AM, Jean-Christophe PLAGNIOL-VILLARD :
> On 15:10 Tue 11 Sep     , Josh Wu wrote:
>> Add err_ecc_ioremap label to fix following errors:
>> ---8<--- 
>>   CC      drivers/mtd/nand/atmel_nand.o
>> drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
>> drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
>> make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
>> make[2]: *** [drivers/mtd/nand] Error 2
>> make[1]: *** [drivers/mtd] Error 2
>> make: *** [drivers] Error 2
>> --->8---
> switch to devm_xxx instead this will simplify the error patch and remove patch

As far as I understand, it is a correction patch: so my advice would be
to take this patch for fixing the current code (for 3.7 if I recall well).
If we want to move to the new devm_xxx API, we can do it once the
current code is fixed.

Bye,
-- 
Nicolas Ferre


From dpn at switchfin.org  Thu Sep 20 04:44:11 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Thu, 20 Sep 2012 11:44:11 +0300
Subject: ubiattach  issue
Message-ID: <006c01cd970c$1b9cb930$2901a8c0@dpn>

Hi Gents,

I am facing an issue with ubiattach on Linux kernel 3.0.8
On our target we have nand flash with mtd layer on top.
The logs attached below.

Can you please give me a pointer?


/bin # ubinfo -a
UBI version:                    1
Count of UBI devices:           0
UBI control device major/minor: 10:62

/bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904 eraseblocks 
of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
libscan: scanning eraseblock 3903 -- 100 % complete
ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
ubiformat: formatting eraseblock 3903 -- 100 % complete

/bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
ubiattach: error!: cannot attach mtd5
           error 25 (Inappropriate ioctl for device)


Best Regards
Dimitar 



From zajec5 at gmail.com  Thu Sep 20 05:00:25 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 20 Sep 2012 11:00:25 +0200
Subject: [PATCH] mtd: bcm47xxsflash: just use memcpy_fromio for reading
Message-ID: <1348131625-24349-1-git-send-email-zajec5@gmail.com>

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
It doesn't generate any errors on normal compilation, but I wasn't able
to test it with "verify". This tool defeated me ;/

First I cloned dedekind/maintaining.git but it didn't run because or
lacking aiaiai.

So I've cloned dedekind/aiaiai.git.

Then I had to move aiaiai to ~/git/aiaiai to let "verify" find it.

So I was able to use verify:
time ./verify ../l2-mtd/ mips-bcm47xx_defconfig < ../l2-mtd/0001-mtd-bcm47xxsflash-just-use-memcpy-for-reading.patch
but it didn't work because patch was already applied. My bad, but... it
took 2m17.277s to verify to realize that. And that magic commit/message
wasn't helpful:
Failed to apply patch(es) with git am on top of:
0f1afc8 Quick fixes - applied by aiaiai

So I've removed patch from my tree, and tried again. This time it took
3m14.398s just to display:
[2012-09-20 10:39:10] aiaiai-make-kernel: Program "aiaiai-locker" is required but not found in PATH

I just wanted to add ~/git/aiaiai to my $PATH, but noticed it doesn't contain
aiaiai-locker anyway... I gave up :|

I appreciate your work on additional quality tools, but apart from good
code it also need to be easy-usable to make ppl use it :|
---
 drivers/mtd/devices/bcm47xxsflash.c |   31 ++-----------------------------
 1 files changed, 2 insertions(+), 29 deletions(-)

diff --git a/drivers/mtd/devices/bcm47xxsflash.c b/drivers/mtd/devices/bcm47xxsflash.c
index a328872..dd650db 100644
--- a/drivers/mtd/devices/bcm47xxsflash.c
+++ b/drivers/mtd/devices/bcm47xxsflash.c
@@ -14,41 +14,14 @@ static int bcm47xxsflash_read(struct mtd_info *mtd, loff_t from, size_t len,
 			      size_t *retlen, u_char *buf)
 {
 	struct bcma_sflash *sflash = mtd->priv;
-	size_t bytes_read = 0;
-	__iomem u8 *src = (__iomem u8 *)KSEG0ADDR(sflash->window + from);
-	int i;
-	size_t unaligned_before, unaligned_after;
 
 	/* Check address range */
 	if ((from + len) > mtd->size)
 		return -EINVAL;
 
-	unaligned_before = from & 0x3;
-	unaligned_after = (from + len) & 0x3;
+	memcpy_fromio(buf, (void *)KSEG0ADDR(sflash->window + from), len);
 
-	for (i = 0; i < unaligned_before; i++) {
-		*buf = readb(src);
-		buf++;
-		src++;
-		bytes_read++;
-	}
-	for (i = from - unaligned_before; i < from + len - unaligned_after;
-	     i += 4) {
-		*(u32 *)buf = readl(src);
-		buf += 4;
-		src += 4;
-		bytes_read += 4;
-	}
-	for (i = 0; i < unaligned_after; i++) {
-		*buf = readb(src);
-		buf++;
-		src++;
-		bytes_read++;
-	}
-
-	*retlen = bytes_read;
-
-	return 0;
+	return len;
 }
 
 static void bcm47xxsflash_fill_mtd(struct bcma_sflash *sflash,
-- 
1.7.7



From dpn at switchfin.org  Thu Sep 20 06:18:19 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Thu, 20 Sep 2012 13:18:19 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn>
Message-ID: <00d401cd9719$41e314b0$2901a8c0@dpn>

Hi again,

Bellow the results of few mtd test tools I've tried.

==========================================================
mtd_speedtest: MTD device: 5
mtd_speedtest: MTD device size 511705088, eraseblock size 131072, page size 
2048, count of eraseblocks 3904, pages per eraseblock 64, OOB size 64
mtd_speedtest: scanning for bad eraseblocks
mtd_speedtest: scanned 3904 eraseblocks, 0 are bad
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 4552 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 2722 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 4517 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 2712 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 4533 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 2715 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 153662 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 292571 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 293258 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 293258 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 294641 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 292571 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 294641 KiB/s
mtd_speedtest: finished
=================================================

=================================================
mtd_pagetest: MTD device: 5
mtd_pagetest: MTD device size 511705088, eraseblock size 131072, page size 
2048, count of eraseblocks 3904, pages per eraseblock 64, OOB size 64
mtd_pagetest: scanning for bad eraseblocks
mtd_pagetest: scanned 3904 eraseblocks, 0 are bad
mtd_pagetest: erasing whole device
mtd_pagetest: erased 3904 eraseblocks
mtd_pagetest: writing whole device
mtd_pagetest: written up to eraseblock 0
mtd_pagetest: written up to eraseblock 256
mtd_pagetest: written up to eraseblock 512
mtd_pagetest: written up to eraseblock 768
mtd_pagetest: written up to eraseblock 1024
mtd_pagetest: written up to eraseblock 1280
mtd_pagetest: written up to eraseblock 1536
mtd_pagetest: written up to eraseblock 1792
mtd_pagetest: written up to eraseblock 2048
mtd_pagetest: written up to eraseblock 2304
mtd_pagetest: written up to eraseblock 2560
mtd_pagetest: written up to eraseblock 2816
mtd_pagetest: written up to eraseblock 3072
mtd_pagetest: written up to eraseblock 3328
mtd_pagetest: written up to eraseblock 3584
mtd_pagetest: written up to eraseblock 3840
mtd_pagetest: written 3904 eraseblocks
mtd_pagetest: verifying all eraseblocks
mtd_pagetest: verified up to eraseblock 0
mtd_pagetest: verified up to eraseblock 256
mtd_pagetest: verified up to eraseblock 512
mtd_pagetest: verified up to eraseblock 768
mtd_pagetest: verified up to eraseblock 1024
mtd_pagetest: verified up to eraseblock 1280
mtd_pagetest: verified up to eraseblock 1536
mtd_pagetest: verified up to eraseblock 1792
mtd_pagetest: verified up to eraseblock 2048
mtd_pagetest: verified up to eraseblock 2304
mtd_pagetest: verified up to eraseblock 2560
mtd_pagetest: verified up to eraseblock 2816
mtd_pagetest: verified up to eraseblock 3072
mtd_pagetest: verified up to eraseblock 3328
mtd_pagetest: verified up to eraseblock 3584
mtd_pagetest: verified up to eraseblock 3840
uncorrectable error :
mtd_pagetest: error: read failed at 0x1e7fd800
uncorrectable error :
mtd_pagetest: error: read failed at 0x1e7fd800
mtd_pagetest: error -74 occurred
=================================================
modprobe: can't load module mtd_pagetest 
(kernel/drivers/mtd/tests/mtd_pagetest.ko): Bad message

Thanks
Dimitar

----- Original Message ----- 
From: "Dimitar Penev" <dpn at switchfin.org>
To: <linux-mtd at lists.infradead.org>
Sent: Thursday, September 20, 2012 11:44 AM
Subject: ubiattach issue


> Hi Gents,
>
> I am facing an issue with ubiattach on Linux kernel 3.0.8
> On our target we have nand flash with mtd layer on top.
> The logs attached below.
>
> Can you please give me a pointer?
>
>
> /bin # ubinfo -a
> UBI version:                    1
> Count of UBI devices:           0
> UBI control device major/minor: 10:62
>
> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904 eraseblocks 
> of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
> libscan: scanning eraseblock 3903 -- 100 % complete
> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
> ubiformat: formatting eraseblock 3903 -- 100 % complete
>
> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
> ubiattach: error!: cannot attach mtd5
>           error 25 (Inappropriate ioctl for device)
>
>
> Best Regards
> Dimitar
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From broonie at opensource.wolfsonmicro.com  Thu Sep 20 07:41:50 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 20 Sep 2012 07:41:50 -0400
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <201209200739.34899.arnd@arndb.de>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
Message-ID: <20120920114148.GH17666@opensource.wolfsonmicro.com>

On Thu, Sep 20, 2012 at 07:39:34AM +0000, Arnd Bergmann wrote:

> The first five branches are scheduled to go through the arm-soc tree, so
> I'm fine with that. For the sound/for-3.7 branch, I'd like to know when
> to expect that hitting mainline. If it always gets in very early during the
> merge window, it's probably ok to put the imx/multi-platform patches into
> the same branch as the other ones in arm-soc and wait for the sound stuff
> to hit mainline first, otherwise I'd suggest we start a second
> next/multiplatform-2 branch for imx and send the first part early on
> but then wait with the second batch before sound gets in.

It's usually pretty early but Takashi will be on holiday this time so
I'm not sure if things might be different (he was going to send the pull
request from holiday).  I also didn't guarantee that it'll be stable
yet, can someone please tell me what the depenency is here?


From shawn.guo at linaro.org  Thu Sep 20 07:52:15 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 20 Sep 2012 19:52:15 +0800
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120920114148.GH17666@opensource.wolfsonmicro.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920114148.GH17666@opensource.wolfsonmicro.com>
Message-ID: <20120920115213.GF2450@S2101-09.ap.freescale.net>

On Thu, Sep 20, 2012 at 07:41:50AM -0400, Mark Brown wrote:
> It's usually pretty early but Takashi will be on holiday this time so
> I'm not sure if things might be different (he was going to send the pull
> request from holiday).  I also didn't guarantee that it'll be stable
> yet, can someone please tell me what the depenency is here?

We need the patch to have all imx drivers mach/* inclusion free,
so that we can enable multi-platform support for imx, which is the
whole point of the series.

If your for-3.7 is not stable anyway, I guess the easiest the way
to do it might be you drop the patch "ASoC: mx27vis: retrieve gpio
numbers from platform_data" from your tree and I have it be part of
the series to go via arm-soc tree as a whole.  (This is the original
plan that I mentioned in v1 cover letter)

Shawn


From dedekind1 at gmail.com  Thu Sep 20 08:22:31 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 20 Sep 2012 15:22:31 +0300
Subject: [PATCH] mtd: bcm47xxsflash: just use memcpy_fromio for reading
In-Reply-To: <1348131625-24349-1-git-send-email-zajec5@gmail.com>
References: <1348131625-24349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348143751.2388.16.camel@sauron.fi.intel.com>

On Thu, 2012-09-20 at 11:00 +0200, Rafa? Mi?ecki wrote:
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> ---
> It doesn't generate any errors on normal compilation, but I wasn't able
> to test it with "verify". This tool defeated me ;/
> 
> First I cloned dedekind/maintaining.git but it didn't run because or
> lacking aiaiai.
> 
> So I've cloned dedekind/aiaiai.git.
> 
> Then I had to move aiaiai to ~/git/aiaiai to let "verify" find it.
> 
> So I was able to use verify:
> time ./verify ../l2-mtd/ mips-bcm47xx_defconfig < ../l2-mtd/0001-mtd-bcm47xxsflash-just-use-memcpy-for-reading.patch
> but it didn't work because patch was already applied. My bad, but... it
> took 2m17.277s to verify to realize that. And that magic commit/message
> wasn't helpful:

Well, before doing anything with your tree, we clone it to a temporary
location (in the workdir, which can specify), that probably took 2
minutes in your machine.

> Failed to apply patch(es) with git am on top of:
> 0f1afc8 Quick fixes - applied by aiaiai

After this there should have been the right commit. But I agree this is
confusing, I'll look how I can improve this.

> So I've removed patch from my tree, and tried again. This time it took
> 3m14.398s just to display:
> [2012-09-20 10:39:10] aiaiai-make-kernel: Program "aiaiai-locker" is required but not found in PATH
> 
> I just wanted to add ~/git/aiaiai to my $PATH, but noticed it doesn't contain
> aiaiai-locker anyway... I gave up :|

Because you need to type "make". This is written in the docs. Dunno, how
would I make sure users do not forget to type make before running? I can
improve the error message though, and put a hint there.

> I appreciate your work on additional quality tools, but apart from good
> code it also need to be easy-usable to make ppl use it :|

Thanks for feed-back, appreciated!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120920/48e7ab56/attachment.sig>

From dedekind1 at gmail.com  Thu Sep 20 08:45:07 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 20 Sep 2012 15:45:07 +0300
Subject: [PATCH] mtd: bcm47xxsflash: just use memcpy_fromio for reading
In-Reply-To: <1348131625-24349-1-git-send-email-zajec5@gmail.com>
References: <1348131625-24349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348145107.2388.17.camel@sauron.fi.intel.com>

On Thu, 2012-09-20 at 11:00 +0200, Rafa? Mi?ecki wrote:
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>

Squashed this one to the previous one. Fixed up the following aiaiai
complaint:

Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/devices/bcm47xxsflash.c:22:29: warning: incorrect type in argument 2 (different address spaces) [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:22:29:    expected void const volatile [noderef] <asn:2>*src [sparse]
+drivers/mtd/devices/bcm47xxsflash.c:22:29:    got void *<noident> [sparse]

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120920/7db423df/attachment.sig>

From broonie at opensource.wolfsonmicro.com  Thu Sep 20 08:47:10 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 20 Sep 2012 08:47:10 -0400
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120920115213.GF2450@S2101-09.ap.freescale.net>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920114148.GH17666@opensource.wolfsonmicro.com>
 <20120920115213.GF2450@S2101-09.ap.freescale.net>
Message-ID: <20120920124709.GN17666@opensource.wolfsonmicro.com>

On Thu, Sep 20, 2012 at 07:52:15PM +0800, Shawn Guo wrote:
> On Thu, Sep 20, 2012 at 07:41:50AM -0400, Mark Brown wrote:

> > It's usually pretty early but Takashi will be on holiday this time so
> > I'm not sure if things might be different (he was going to send the pull
> > request from holiday).  I also didn't guarantee that it'll be stable
> > yet, can someone please tell me what the depenency is here?

> We need the patch to have all imx drivers mach/* inclusion free,
> so that we can enable multi-platform support for imx, which is the
> whole point of the series.

That doesn't answer the question.  What is the dependency - what is it
about this patch that something else depends on?  Your cover letters
just say you'd like to do this but don't mention dependencies at all and
when I asked the question last night you said the same thing.  I've not
seen the rest of the series...

> If your for-3.7 is not stable anyway, I guess the easiest the way

It probably *is* stable but I'm not enthused about people pulling
unsigned tags.  I might rebase, though - I'm going to finalise the tree
in the next few days.

> to do it might be you drop the patch "ASoC: mx27vis: retrieve gpio
> numbers from platform_data" from your tree and I have it be part of
> the series to go via arm-soc tree as a whole.  (This is the original
> plan that I mentioned in v1 cover letter)

You just mentioned it as a preference (you said it's something you'd
like to do), please if you're doing this sort of cross tree thing be
explicit about what the inter-tree relationships are.  If things need to
go in via the same tree say so explicitly (and ideally say way this is).

The main reason I applied it straight away was that Javier mentioned
that it was a bug fix and it's near the merge window and these random
ARM cleanup serieses never seem to go in quickly.


From zajec5 at gmail.com  Thu Sep 20 09:23:50 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Thu, 20 Sep 2012 15:23:50 +0200
Subject: [PATCH] mtd: bcm47xxsflash: just use memcpy_fromio for reading
In-Reply-To: <1348145107.2388.17.camel@sauron.fi.intel.com>
References: <1348131625-24349-1-git-send-email-zajec5@gmail.com>
 <1348145107.2388.17.camel@sauron.fi.intel.com>
Message-ID: <CACna6rz2XYu4LHq9y34m_Asm6Vmxt-9MvwTnWTsZ+SZscXc6ww@mail.gmail.com>

2012/9/20 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Thu, 2012-09-20 at 11:00 +0200, Rafa? Mi?ecki wrote:
>> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>
> Squashed this one to the previous one. Fixed up the following aiaiai
> complaint:
>
> Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", results:

Thanks!

I hope to learn using "verify + aiaiai" and send clean NAND driver soon :)

-- 
Rafa?


From shawn.guo at linaro.org  Thu Sep 20 09:36:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 20 Sep 2012 21:36:32 +0800
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120920124709.GN17666@opensource.wolfsonmicro.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920114148.GH17666@opensource.wolfsonmicro.com>
 <20120920115213.GF2450@S2101-09.ap.freescale.net>
 <20120920124709.GN17666@opensource.wolfsonmicro.com>
Message-ID: <20120920133630.GG2450@S2101-09.ap.freescale.net>

On Thu, Sep 20, 2012 at 08:47:10AM -0400, Mark Brown wrote:
> On Thu, Sep 20, 2012 at 07:52:15PM +0800, Shawn Guo wrote:
> > On Thu, Sep 20, 2012 at 07:41:50AM -0400, Mark Brown wrote:
> 
> > > It's usually pretty early but Takashi will be on holiday this time so
> > > I'm not sure if things might be different (he was going to send the pull
> > > request from holiday).  I also didn't guarantee that it'll be stable
> > > yet, can someone please tell me what the depenency is here?
> 
> > We need the patch to have all imx drivers mach/* inclusion free,
> > so that we can enable multi-platform support for imx, which is the
> > whole point of the series.
> 
> That doesn't answer the question.  What is the dependency - what is it
> about this patch that something else depends on?  Your cover letters
> just say you'd like to do this but don't mention dependencies at all and
> when I asked the question last night you said the same thing.  I've not
> seen the rest of the series...
> 
Ah, right.  You did get copied on the whole series.  So the whole point
of patch "ASoC: mx27vis: retrieve gpio numbers from platform_data" is
to get rid of inclusion mach/iomux-mx27.h.  This has to be done before
we enable multi-platform support for imx, since mach/* has to be removed
completely for multi-platform build.

> > If your for-3.7 is not stable anyway, I guess the easiest the way
> 
> It probably *is* stable but I'm not enthused about people pulling
> unsigned tags.  I might rebase, though - I'm going to finalise the tree
> in the next few days.
> 
> > to do it might be you drop the patch "ASoC: mx27vis: retrieve gpio
> > numbers from platform_data" from your tree and I have it be part of
> > the series to go via arm-soc tree as a whole.  (This is the original
> > plan that I mentioned in v1 cover letter)
> 
> You just mentioned it as a preference (you said it's something you'd
> like to do), please if you're doing this sort of cross tree thing be
> explicit about what the inter-tree relationships are.  If things need to
> go in via the same tree say so explicitly (and ideally say way this is).
> 
Ok, my bad.

> The main reason I applied it straight away was that Javier mentioned
> that it was a bug fix and it's near the merge window and these random
> ARM cleanup serieses never seem to go in quickly.

The series is planned for 3.7 merge window.  Is it still possible for
you to drop the patch from your tree to ease the process?  Or I will
hold my pull-request to arm-soc until you tell me you have your tree
finalized.

Shawn


From jkrzyszt at tis.icnet.pl  Thu Sep 20 09:41:45 2012
From: jkrzyszt at tis.icnet.pl (Janusz Krzysztofik)
Date: Thu, 20 Sep 2012 15:41:45 +0200
Subject: [PATCH 04/29] ARM: OMAP1: Move board-ams-delta.h from plat to mach
In-Reply-To: <20120919210543.28074.10214.stgit@muffinssi>
References: <20120919205732.28074.43697.stgit@muffinssi>
 <20120919210543.28074.10214.stgit@muffinssi>
Message-ID: <6194989.y5R5mbkCAc@acer>

On Wed, 19 Sep 2012 14:05:43 Tony Lindgren wrote:
> This is only used by omap1.
> 
> And to fix things properly, this should not be included
> from the drivers at all.

Akced-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>

I'll take care of updating the drivers when I have some spare time.

Thanks,
Janusz


From engycz at gmail.com  Thu Sep 20 10:49:50 2012
From: engycz at gmail.com (Jiri Engelthaler)
Date: Thu, 20 Sep 2012 16:49:50 +0200
Subject: [PATCH] [MTD] slram: Invalid checking of absolute end address
In-Reply-To: <CAHODtZT6UP4BCHuugpSr6q2=KoTDiGuW_hG_fqjWG7cXcTE35A@mail.gmail.com>
References: <CAHODtZT6UP4BCHuugpSr6q2=KoTDiGuW_hG_fqjWG7cXcTE35A@mail.gmail.com>
Message-ID: <CAHODtZQEbc8d-U+MWY=dkZUfAJ-z0xOXMUXSWgg8Zotmicz0Ww@mail.gmail.com>

Fixed parsing end absolute address
Signed-off-by: Jiri Engelthaler <engycz at gmail.com>
---
--- linux-3.2.28/drivers/mtd/devices/slram.c	2012-08-19 19:15:38.000000000 +0200
+++ linux-3.2.28.mod/drivers/mtd/devices/slram.c	2012-09-19
18:29:28.012740703 +0200
@@ -266,7 +266,7 @@ static int parse_cmdline(char *devname,

 	if (*(szlength) != '+') {
 		devlength = simple_strtoul(szlength, &buffer, 0);
-		devlength = handle_unit(devlength, buffer) - devstart;
+		devlength = handle_unit(devlength, buffer);
 		if (devlength < devstart)
 			goto err_out;


From shawn.guo at linaro.org  Thu Sep 20 10:53:44 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Thu, 20 Sep 2012 22:53:44 +0800
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <201209200739.34899.arnd@arndb.de>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
Message-ID: <20120920145342.GI2450@S2101-09.ap.freescale.net>

On Thu, Sep 20, 2012 at 07:39:34AM +0000, Arnd Bergmann wrote:
> The first five branches are scheduled to go through the arm-soc tree, so
> I'm fine with that. For the sound/for-3.7 branch, I'd like to know when
> to expect that hitting mainline. If it always gets in very early during the
> merge window, it's probably ok to put the imx/multi-platform patches into
> the same branch as the other ones in arm-soc and wait for the sound stuff
> to hit mainline first, otherwise I'd suggest we start a second
> next/multiplatform-2 branch for imx and send the first part early on
> but then wait with the second batch before sound gets in.
> 
It seems that we will have to go with next/multiplatform-2.  I just
tried to merge the series with linux-next together, and got some
non-trivial conflicts with media and mtd tree.  I might have to rebase
my series on top of these trees to sort out those conflicts.  That said,
I will have several dependencies outside arm-soc tree, and have to pend
my series until all those trees get merged into mainline.

Shawn


From arnout at mind.be  Thu Sep 20 11:44:10 2012
From: arnout at mind.be (Arnout Vandecappelle (Essensium/Mind))
Date: Thu, 20 Sep 2012 17:44:10 +0200
Subject: [PATCH] mtd: omap2-nand: avoid unaligned DMA accesses,
 fall back on prefetch method
Message-ID: <1348155850-26174-1-git-send-email-arnout@mind.be>

From: "Arnout Vandecappelle (Essensium/Mind)" <arnout at mind.be>

The buffers given to the read_buf and write_buf methods are not
necessarily u32-aligned, while the DMA engine is configured with
32-bit accesses.  As a consequence, the DMA engine gives an error
which appears in the log as follows:

DMA misaligned error with device 4

After this, no accesses to the NAND are possible anymore because the
access never completes.  This usually means the system hangs if the
rootfs is in NAND.

To avoid this, use the prefetch method if the buffer is not aligned.

It's difficult to reproduce the error, because the buffers are
aligned most of the time.

This bug and a patch was originally reported by Sven Krauss in
http://article.gmane.org/gmane.linux.drivers.mtd/34548

Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout at mind.be>
Cc: Sven Krauss <sven.krauss at web.de>
---
Perhaps a better method is to fetch the first few unaligned bytes
with the prefetch method, and then continue with DMA.  However,
since it's hard to force an unaligned buffer, it's also hard to
test that this method works.
---
 drivers/mtd/nand/omap2.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index c719b86..a313e83 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -441,7 +441,7 @@ out_copy:
  */
 static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 {
-	if (len <= mtd->oobsize)
+	if (len <= mtd->oobsize || !IS_ALIGNED((unsigned long)buf, 4))
 		omap_read_buf_pref(mtd, buf, len);
 	else
 		/* start transfer in DMA mode */
@@ -457,7 +457,7 @@ static void omap_read_buf_dma_pref(struct mtd_info *mtd, u_char *buf, int len)
 static void omap_write_buf_dma_pref(struct mtd_info *mtd,
 					const u_char *buf, int len)
 {
-	if (len <= mtd->oobsize)
+	if (len <= mtd->oobsize || !IS_ALIGNED((unsigned long)buf, 4))
 		omap_write_buf_pref(mtd, buf, len);
 	else
 		/* start transfer in DMA mode */
-- 
1.7.10.4



From arnd at arndb.de  Thu Sep 20 11:56:56 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Thu, 20 Sep 2012 15:56:56 +0000
Subject: [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120920145342.GI2450@S2101-09.ap.freescale.net>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
Message-ID: <201209201556.57171.arnd@arndb.de>

On Thursday 20 September 2012, Shawn Guo wrote:
> 
> On Thu, Sep 20, 2012 at 07:39:34AM +0000, Arnd Bergmann wrote:
> > The first five branches are scheduled to go through the arm-soc tree, so
> > I'm fine with that. For the sound/for-3.7 branch, I'd like to know when
> > to expect that hitting mainline. If it always gets in very early during the
> > merge window, it's probably ok to put the imx/multi-platform patches into
> > the same branch as the other ones in arm-soc and wait for the sound stuff
> > to hit mainline first, otherwise I'd suggest we start a second
> > next/multiplatform-2 branch for imx and send the first part early on
> > but then wait with the second batch before sound gets in.
> > 
> It seems that we will have to go with next/multiplatform-2.  I just
> tried to merge the series with linux-next together, and got some
> non-trivial conflicts with media and mtd tree.  I might have to rebase
> my series on top of these trees to sort out those conflicts.  That said,
> I will have several dependencies outside arm-soc tree, and have to pend
> my series until all those trees get merged into mainline.

Ok, fair enough. I think we can put it in arm-soc/for-next as a staging
branch anyway to give it some exposure to linux-next, and then we can
decide whether a rebase is necessary before sending it to Linus.

	Arnd


From tony at atomide.com  Thu Sep 20 13:10:54 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 20 Sep 2012 10:10:54 -0700
Subject: [PATCH 04/29] ARM: OMAP1: Move board-ams-delta.h from plat to mach
In-Reply-To: <6194989.y5R5mbkCAc@acer>
References: <20120919205732.28074.43697.stgit@muffinssi>
 <20120919210543.28074.10214.stgit@muffinssi>
 <6194989.y5R5mbkCAc@acer>
Message-ID: <20120920171054.GA28835@atomide.com>

* Janusz Krzysztofik <jkrzyszt at tis.icnet.pl> [120920 06:48]:
> On Wed, 19 Sep 2012 14:05:43 Tony Lindgren wrote:
> > This is only used by omap1.
> > 
> > And to fix things properly, this should not be included
> > from the drivers at all.
> 
> Akced-by: Janusz Krzysztofik <jkrzyszt at tis.icnet.pl>
> 
> I'll take care of updating the drivers when I have some spare time.

Thanks those can be fixed by passing them in the platform data.

Regards,

Tony


From tony at atomide.com  Thu Sep 20 13:12:41 2012
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 20 Sep 2012 10:12:41 -0700
Subject: [PATCH 04/29] ARM: OMAP1: Move board-ams-delta.h from plat to mach
In-Reply-To: <20120920011630.GB17666@opensource.wolfsonmicro.com>
References: <20120919205732.28074.43697.stgit@muffinssi>
 <20120919210543.28074.10214.stgit@muffinssi>
 <20120920011630.GB17666@opensource.wolfsonmicro.com>
Message-ID: <20120920171134.GB28835@atomide.com>

* Mark Brown <broonie at opensource.wolfsonmicro.com> [120919 19:05]:
> On Wed, Sep 19, 2012 at 02:05:43PM -0700, Tony Lindgren wrote:
> > This is only used by omap1.
> > 
> > And to fix things properly, this should not be included
> > from the drivers at all.
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
> or I can apply it if that's easier.

Thanks I'll do a series for Arnd on top of the multiplatform
changes to avoid more merge conflicts.

Regards,

Tony


From vikram186 at gmail.com  Thu Sep 20 14:25:07 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Thu, 20 Sep 2012 23:55:07 +0530
Subject: ubiattach  issue
In-Reply-To: <006c01cd970c$1b9cb930$2901a8c0@dpn>
References: <006c01cd970c$1b9cb930$2901a8c0@dpn>
Message-ID: <505B5F83.6070408@gmail.com>

On 9/20/2012 2:14 PM, Dimitar Penev wrote:
> Hi Gents,
>
> I am facing an issue with ubiattach on Linux kernel 3.0.8
> On our target we have nand flash with mtd layer on top.
> The logs attached below.
>
> Can you please give me a pointer?
>
>
> /bin # ubinfo -a
> UBI version: 1
> Count of UBI devices: 0
> UBI control device major/minor: 10:62
>
> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
> libscan: scanning eraseblock 3903 -- 100 % complete
> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
> ubiformat: formatting eraseblock 3903 -- 100 % complete
>
> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
> ubiattach: error!: cannot attach mtd5
> error 25 (Inappropriate ioctl for device)

Before any pointers, which version of mtd-utils are you using?
How to:
(http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)

~Vikram


From dpn at switchfin.org  Thu Sep 20 15:22:05 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Thu, 20 Sep 2012 22:22:05 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
Message-ID: <016601cd9765$38f20a90$2901a8c0@dpn>

Hi Vikram,

Thank you for your response.

It is a check out from http://git.infradead.org/?p=mtd-utils.git
Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6

If you expect version in a different format please let me know what to 
check.

Best Regards
Dimitar

----- Original Message ----- 
From: "Vikram Narayanan" <vikram186 at gmail.com>
To: "Dimitar Penev" <dpn at switchfin.org>
Cc: <linux-mtd at lists.infradead.org>
Sent: Thursday, September 20, 2012 9:25 PM
Subject: Re: ubiattach issue


> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>> Hi Gents,
>>
>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>> On our target we have nand flash with mtd layer on top.
>> The logs attached below.
>>
>> Can you please give me a pointer?
>>
>>
>> /bin # ubinfo -a
>> UBI version: 1
>> Count of UBI devices: 0
>> UBI control device major/minor: 10:62
>>
>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>> libscan: scanning eraseblock 3903 -- 100 % complete
>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>
>> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>> ubiattach: error!: cannot attach mtd5
>> error 25 (Inappropriate ioctl for device)
>
> Before any pointers, which version of mtd-utils are you using?
> How to:
> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>
> ~Vikram
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From dpn at switchfin.org  Thu Sep 20 15:40:59 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Thu, 20 Sep 2012 22:40:59 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
 <016601cd9765$38f20a90$2901a8c0@dpn>
Message-ID: <018301cd9767$dc466900$2901a8c0@dpn>

Hello,

My  nanddump reports
nanddump 1.4.6

Best Regards
Dimitar

----- Original Message ----- 
From: "Dimitar Penev" <dpn at switchfin.org>
To: "Vikram Narayanan" <vikram186 at gmail.com>
Cc: <linux-mtd at lists.infradead.org>
Sent: Thursday, September 20, 2012 10:22 PM
Subject: Re: ubiattach issue


> Hi Vikram,
>
> Thank you for your response.
>
> It is a check out from http://git.infradead.org/?p=mtd-utils.git
> Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6
>
> If you expect version in a different format please let me know what to 
> check.
>
> Best Regards
> Dimitar
>
> ----- Original Message ----- 
> From: "Vikram Narayanan" <vikram186 at gmail.com>
> To: "Dimitar Penev" <dpn at switchfin.org>
> Cc: <linux-mtd at lists.infradead.org>
> Sent: Thursday, September 20, 2012 9:25 PM
> Subject: Re: ubiattach issue
>
>
>> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>>> Hi Gents,
>>>
>>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>>> On our target we have nand flash with mtd layer on top.
>>> The logs attached below.
>>>
>>> Can you please give me a pointer?
>>>
>>>
>>> /bin # ubinfo -a
>>> UBI version: 1
>>> Count of UBI devices: 0
>>> UBI control device major/minor: 10:62
>>>
>>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>>> libscan: scanning eraseblock 3903 -- 100 % complete
>>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>>
>>> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>> ubiattach: error!: cannot attach mtd5
>>> error 25 (Inappropriate ioctl for device)
>>
>> Before any pointers, which version of mtd-utils are you using?
>> How to:
>> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>>
>> ~Vikram
>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From vikram186 at gmail.com  Thu Sep 20 16:37:14 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Fri, 21 Sep 2012 02:07:14 +0530
Subject: ubiattach  issue
In-Reply-To: <016601cd9765$38f20a90$2901a8c0@dpn>
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
 <016601cd9765$38f20a90$2901a8c0@dpn>
Message-ID: <505B7E7A.6070200@gmail.com>

Hello Dimitar,

Cc-ing Artem

On 9/21/2012 12:52 AM, Dimitar Penev wrote:
> Hi Vikram,
>
> Thank you for your response.
>
> It is a check out from http://git.infradead.org/?p=mtd-utils.git
> Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6

I tested with this checkout in my nandsim under x86. But couldn't 
reproduce the issue. (But I was on 2.6.38.8 kernel).

Could you also post the corresponding kernel logs when you issued the 
ubiattach command? That should give more hints.

~Vikram

>
> ----- Original Message ----- From: "Vikram Narayanan" <vikram186 at gmail.com>
> To: "Dimitar Penev" <dpn at switchfin.org>
> Cc: <linux-mtd at lists.infradead.org>
> Sent: Thursday, September 20, 2012 9:25 PM
> Subject: Re: ubiattach issue
>
>
>> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>>> Hi Gents,
>>>
>>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>>> On our target we have nand flash with mtd layer on top.
>>> The logs attached below.
>>>
>>> Can you please give me a pointer?
>>>
>>>
>>> /bin # ubinfo -a
>>> UBI version: 1
>>> Count of UBI devices: 0
>>> UBI control device major/minor: 10:62
>>>
>>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>>> libscan: scanning eraseblock 3903 -- 100 % complete
>>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>>
>>> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>> ubiattach: error!: cannot attach mtd5
>>> error 25 (Inappropriate ioctl for device)
>>
>> Before any pointers, which version of mtd-utils are you using?
>> How to:
>> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>>
>> ~Vikram
>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
>



From dpn at switchfin.org  Fri Sep 21 02:40:01 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Fri, 21 Sep 2012 09:40:01 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
 <016601cd9765$38f20a90$2901a8c0@dpn> <505B7E7A.6070200@gmail.com>
Message-ID: <002701cd97c3$ed7495b0$2901a8c0@dpn>

Hello Vikram,

Let me explain some more in details on my issue:

We have custom Blackfin based board running uClinux (using kernel 3.0.8)
and using mtd-utils (nanddump 1.4.6).
On this board we are using the Blackfin  platform nand driver.
UBIFS is working OK on this board.

Now we have another custom board also based on Blackfin CPU but this CPU has 
a hardware
nand controller which we have used to connect to our nand chip.
Under u-boot this driver seems to work fine and we can read/write on the 
nand flash without issues.
On Linux we are using the same  uClinux (using kernel 3.0.8) and mtd-utils 
(nanddump 1.4.6).
This time we get:
/bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
ubiattach: error!: cannot attach mtd5
                 error 25 (Inappropriate ioctl for device)

The difference between the two boards seems to be the fact that the second 
board is using the hardware nand controler
and the corresponding Blackfin Linux driver.

I don't see anything in my system logs related with ubiattach so I guess I 
have to enable some debugging in the kernel.
Let me recompile and try again.
If you want me to test something specific I will appreciate your advices.

Thank you.
Dimitar





----- Original Message ----- 
From: "Vikram Narayanan" <vikram186 at gmail.com>
To: "Dimitar Penev" <dpn at switchfin.org>
Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
Sent: Thursday, September 20, 2012 11:37 PM
Subject: Re: ubiattach issue


> Hello Dimitar,
>
> Cc-ing Artem
>
> On 9/21/2012 12:52 AM, Dimitar Penev wrote:
>> Hi Vikram,
>>
>> Thank you for your response.
>>
>> It is a check out from http://git.infradead.org/?p=mtd-utils.git
>> Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6
>
> I tested with this checkout in my nandsim under x86. But couldn't 
> reproduce the issue. (But I was on 2.6.38.8 kernel).
>
> Could you also post the corresponding kernel logs when you issued the 
> ubiattach command? That should give more hints.
>
> ~Vikram
>
>>
>> ----- Original Message ----- From: "Vikram Narayanan" 
>> <vikram186 at gmail.com>
>> To: "Dimitar Penev" <dpn at switchfin.org>
>> Cc: <linux-mtd at lists.infradead.org>
>> Sent: Thursday, September 20, 2012 9:25 PM
>> Subject: Re: ubiattach issue
>>
>>
>>> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>>>> Hi Gents,
>>>>
>>>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>>>> On our target we have nand flash with mtd layer on top.
>>>> The logs attached below.
>>>>
>>>> Can you please give me a pointer?
>>>>
>>>>
>>>> /bin # ubinfo -a
>>>> UBI version: 1
>>>> Count of UBI devices: 0
>>>> UBI control device major/minor: 10:62
>>>>
>>>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>>>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>>>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>>>> libscan: scanning eraseblock 3903 -- 100 % complete
>>>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>>>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>>>
>>>> /bin # ubiattach 
>>>> /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>>> ubiattach: error!: cannot attach mtd5
>>>> error 25 (Inappropriate ioctl for device)
>>>
>>> Before any pointers, which version of mtd-utils are you using?
>>> How to:
>>> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>>>
>>> ~Vikram
>>>
>>> ______________________________________________________
>>> Linux MTD discussion mailing list
>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>>
>>
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From shawn.guo at linaro.org  Fri Sep 21 04:01:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Fri, 21 Sep 2012 16:01:26 +0800
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <201209201556.57171.arnd@arndb.de>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
Message-ID: <20120921080123.GM2450@S2101-09.ap.freescale.net>

On Thu, Sep 20, 2012 at 03:56:56PM +0000, Arnd Bergmann wrote:
> Ok, fair enough. I think we can put it in arm-soc/for-next as a staging
> branch anyway to give it some exposure to linux-next, and then we can
> decide whether a rebase is necessary before sending it to Linus.
> 
I just saw the announcement from Olof - no more major merge for 3.7
will be accepted from now on.  Can this be an exception or should I
plan this for 3.8?

Shawn


From olof at lixom.net  Fri Sep 21 04:26:43 2012
From: olof at lixom.net (Olof Johansson)
Date: Fri, 21 Sep 2012 01:26:43 -0700
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120921080123.GM2450@S2101-09.ap.freescale.net>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
Message-ID: <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>

On Fri, Sep 21, 2012 at 1:01 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Thu, Sep 20, 2012 at 03:56:56PM +0000, Arnd Bergmann wrote:
>> Ok, fair enough. I think we can put it in arm-soc/for-next as a staging
>> branch anyway to give it some exposure to linux-next, and then we can
>> decide whether a rebase is necessary before sending it to Linus.
>>
> I just saw the announcement from Olof - no more major merge for 3.7
> will be accepted from now on.  Can this be an exception or should I
> plan this for 3.8?


I'll take a look at merging it tomorrow after I've dealt with smp_ops;
if it looks reasonably conflict-free I'll pull it in. We need the
sound dependency sorted out (or agreed upon) first though.


-Olof


From dpn at switchfin.org  Fri Sep 21 04:44:01 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Fri, 21 Sep 2012 11:44:01 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
 <016601cd9765$38f20a90$2901a8c0@dpn> <505B7E7A.6070200@gmail.com>
 <002701cd97c3$ed7495b0$2901a8c0@dpn>
Message-ID: <008d01cd97d5$3fb70680$2901a8c0@dpn>

Hi Gents,

I have enabled CONFIG_MTD_DEBUG, CONFIG_MTD_UBI_DEBUG, CONFIG_UBIFS_FS_DEBUG
And got some more messages during ubiformat however no additional info in my 
system log after ubiattach

The only information I get in the console is the old message

>/bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>ubiattach: error!: cannot attach mtd5
>                 error 25 (Inappropriate ioctl for device)


It seems it is failing in /mtd-utils/ubi-utils/libubi.c at

static int do_attach(const char *node, const struct ubi_attach_req *r)
...
ret = ioctl(fd, UBI_IOCATT, r);
...

I get ret == -1 here, it seems my node /dev/ubi_ctrl doesn't have UBI_IOCATT 
command hooked.

Note that the node /dev/ubi_ctrl I create manually like this:

mknod /dev/ubi_ctrl c 10 63

So my ubi character control device seems not hooked to the /dev/ubi_ctrl?
Any suggestions?

Thanks
Dimitar




----- Original Message ----- 
From: "Dimitar Penev" <dpn at switchfin.org>
To: "Vikram Narayanan" <vikram186 at gmail.com>
Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
Sent: Friday, September 21, 2012 9:40 AM
Subject: Re: ubiattach issue


> Hello Vikram,
>
> Let me explain some more in details on my issue:
>
> We have custom Blackfin based board running uClinux (using kernel 3.0.8)
> and using mtd-utils (nanddump 1.4.6).
> On this board we are using the Blackfin  platform nand driver.
> UBIFS is working OK on this board.
>
> Now we have another custom board also based on Blackfin CPU but this CPU 
> has a hardware
> nand controller which we have used to connect to our nand chip.
> Under u-boot this driver seems to work fine and we can read/write on the 
> nand flash without issues.
> On Linux we are using the same  uClinux (using kernel 3.0.8) and mtd-utils 
> (nanddump 1.4.6).
> This time we get:
> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
> ubiattach: error!: cannot attach mtd5
>                 error 25 (Inappropriate ioctl for device)
>
> The difference between the two boards seems to be the fact that the second 
> board is using the hardware nand controler
> and the corresponding Blackfin Linux driver.
>
> I don't see anything in my system logs related with ubiattach so I guess I 
> have to enable some debugging in the kernel.
> Let me recompile and try again.
> If you want me to test something specific I will appreciate your advices.
>
> Thank you.
> Dimitar
>
>
>
>
>
> ----- Original Message ----- 
> From: "Vikram Narayanan" <vikram186 at gmail.com>
> To: "Dimitar Penev" <dpn at switchfin.org>
> Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
> Sent: Thursday, September 20, 2012 11:37 PM
> Subject: Re: ubiattach issue
>
>
>> Hello Dimitar,
>>
>> Cc-ing Artem
>>
>> On 9/21/2012 12:52 AM, Dimitar Penev wrote:
>>> Hi Vikram,
>>>
>>> Thank you for your response.
>>>
>>> It is a check out from http://git.infradead.org/?p=mtd-utils.git
>>> Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6
>>
>> I tested with this checkout in my nandsim under x86. But couldn't 
>> reproduce the issue. (But I was on 2.6.38.8 kernel).
>>
>> Could you also post the corresponding kernel logs when you issued the 
>> ubiattach command? That should give more hints.
>>
>> ~Vikram
>>
>>>
>>> ----- Original Message ----- From: "Vikram Narayanan" 
>>> <vikram186 at gmail.com>
>>> To: "Dimitar Penev" <dpn at switchfin.org>
>>> Cc: <linux-mtd at lists.infradead.org>
>>> Sent: Thursday, September 20, 2012 9:25 PM
>>> Subject: Re: ubiattach issue
>>>
>>>
>>>> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>>>>> Hi Gents,
>>>>>
>>>>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>>>>> On our target we have nand flash with mtd layer on top.
>>>>> The logs attached below.
>>>>>
>>>>> Can you please give me a pointer?
>>>>>
>>>>>
>>>>> /bin # ubinfo -a
>>>>> UBI version: 1
>>>>> Count of UBI devices: 0
>>>>> UBI control device major/minor: 10:62
>>>>>
>>>>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>>>>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>>>>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>>>>> libscan: scanning eraseblock 3903 -- 100 % complete
>>>>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>>>>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>>>>
>>>>> /bin # ubiattach 
>>>>> /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>>>> ubiattach: error!: cannot attach mtd5
>>>>> error 25 (Inappropriate ioctl for device)
>>>>
>>>> Before any pointers, which version of mtd-utils are you using?
>>>> How to:
>>>> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>>>>
>>>> ~Vikram
>>>>
>>>> ______________________________________________________
>>>> Linux MTD discussion mailing list
>>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>>>
>>>
>>
>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From dpn at switchfin.org  Fri Sep 21 05:05:14 2012
From: dpn at switchfin.org (Dimitar Penev)
Date: Fri, 21 Sep 2012 12:05:14 +0300
Subject: ubiattach  issue
References: <006c01cd970c$1b9cb930$2901a8c0@dpn> <505B5F83.6070408@gmail.com>
 <016601cd9765$38f20a90$2901a8c0@dpn> <505B7E7A.6070200@gmail.com>
 <002701cd97c3$ed7495b0$2901a8c0@dpn> <008d01cd97d5$3fb70680$2901a8c0@dpn>
Message-ID: <00ab01cd97d8$36cc6f30$2901a8c0@dpn>

Hi Gents,

I had my UBI control at minor number 62 instead of 63 and thats why I got 
the error :)
I have never understood how those numbers gets assigned.

Now I have my ubifs working.

Thank you for the support and sorry for the noise.
Dimitar




----- Original Message ----- 
From: "Dimitar Penev" <dpn at switchfin.org>
To: "Vikram Narayanan" <vikram186 at gmail.com>
Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
Sent: Friday, September 21, 2012 11:44 AM
Subject: Re: ubiattach issue


> Hi Gents,
>
> I have enabled CONFIG_MTD_DEBUG, CONFIG_MTD_UBI_DEBUG, 
> CONFIG_UBIFS_FS_DEBUG
> And got some more messages during ubiformat however no additional info in 
> my system log after ubiattach
>
> The only information I get in the console is the old message
>
>>/bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>ubiattach: error!: cannot attach mtd5
>>                 error 25 (Inappropriate ioctl for device)
>
>
> It seems it is failing in /mtd-utils/ubi-utils/libubi.c at
>
> static int do_attach(const char *node, const struct ubi_attach_req *r)
> ...
> ret = ioctl(fd, UBI_IOCATT, r);
> ...
>
> I get ret == -1 here, it seems my node /dev/ubi_ctrl doesn't have 
> UBI_IOCATT command hooked.
>
> Note that the node /dev/ubi_ctrl I create manually like this:
>
> mknod /dev/ubi_ctrl c 10 63
>
> So my ubi character control device seems not hooked to the /dev/ubi_ctrl?
> Any suggestions?
>
> Thanks
> Dimitar
>
>
>
>
> ----- Original Message ----- 
> From: "Dimitar Penev" <dpn at switchfin.org>
> To: "Vikram Narayanan" <vikram186 at gmail.com>
> Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
> Sent: Friday, September 21, 2012 9:40 AM
> Subject: Re: ubiattach issue
>
>
>> Hello Vikram,
>>
>> Let me explain some more in details on my issue:
>>
>> We have custom Blackfin based board running uClinux (using kernel 3.0.8)
>> and using mtd-utils (nanddump 1.4.6).
>> On this board we are using the Blackfin  platform nand driver.
>> UBIFS is working OK on this board.
>>
>> Now we have another custom board also based on Blackfin CPU but this CPU 
>> has a hardware
>> nand controller which we have used to connect to our nand chip.
>> Under u-boot this driver seems to work fine and we can read/write on the 
>> nand flash without issues.
>> On Linux we are using the same  uClinux (using kernel 3.0.8) and 
>> mtd-utils (nanddump 1.4.6).
>> This time we get:
>> /bin # ubiattach /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>> ubiattach: error!: cannot attach mtd5
>>                 error 25 (Inappropriate ioctl for device)
>>
>> The difference between the two boards seems to be the fact that the 
>> second board is using the hardware nand controler
>> and the corresponding Blackfin Linux driver.
>>
>> I don't see anything in my system logs related with ubiattach so I guess 
>> I have to enable some debugging in the kernel.
>> Let me recompile and try again.
>> If you want me to test something specific I will appreciate your advices.
>>
>> Thank you.
>> Dimitar
>>
>>
>>
>>
>>
>> ----- Original Message ----- 
>> From: "Vikram Narayanan" <vikram186 at gmail.com>
>> To: "Dimitar Penev" <dpn at switchfin.org>
>> Cc: <linux-mtd at lists.infradead.org>; <dedekind1 at gmail.com>
>> Sent: Thursday, September 20, 2012 11:37 PM
>> Subject: Re: ubiattach issue
>>
>>
>>> Hello Dimitar,
>>>
>>> Cc-ing Artem
>>>
>>> On 9/21/2012 12:52 AM, Dimitar Penev wrote:
>>>> Hi Vikram,
>>>>
>>>> Thank you for your response.
>>>>
>>>> It is a check out from http://git.infradead.org/?p=mtd-utils.git
>>>> Git signature 36d8de81049c9c908740b690c664b5bd3703ccd6
>>>
>>> I tested with this checkout in my nandsim under x86. But couldn't 
>>> reproduce the issue. (But I was on 2.6.38.8 kernel).
>>>
>>> Could you also post the corresponding kernel logs when you issued the 
>>> ubiattach command? That should give more hints.
>>>
>>> ~Vikram
>>>
>>>>
>>>> ----- Original Message ----- From: "Vikram Narayanan" 
>>>> <vikram186 at gmail.com>
>>>> To: "Dimitar Penev" <dpn at switchfin.org>
>>>> Cc: <linux-mtd at lists.infradead.org>
>>>> Sent: Thursday, September 20, 2012 9:25 PM
>>>> Subject: Re: ubiattach issue
>>>>
>>>>
>>>>> On 9/20/2012 2:14 PM, Dimitar Penev wrote:
>>>>>> Hi Gents,
>>>>>>
>>>>>> I am facing an issue with ubiattach on Linux kernel 3.0.8
>>>>>> On our target we have nand flash with mtd layer on top.
>>>>>> The logs attached below.
>>>>>>
>>>>>> Can you please give me a pointer?
>>>>>>
>>>>>>
>>>>>> /bin # ubinfo -a
>>>>>> UBI version: 1
>>>>>> Count of UBI devices: 0
>>>>>> UBI control device major/minor: 10:62
>>>>>>
>>>>>> /bin # ubiformat /dev/mtd5 -y --vid-hdr-offset="2048"
>>>>>> ubiformat: mtd5 (nand), size 511705088 bytes (488.0 MiB), 3904
>>>>>> eraseblocks of 131072 bytes (128.0 KiB), min. I/O size 2048 bytes
>>>>>> libscan: scanning eraseblock 3903 -- 100 % complete
>>>>>> ubiformat: 3904 eraseblocks have valid erase counter, mean value is 3
>>>>>> ubiformat: formatting eraseblock 3903 -- 100 % complete
>>>>>>
>>>>>> /bin # ubiattach 
>>>>>> /dev/ubi_ctrl --mtdn=5 --devn=0 --vid-hdr-offset="2048"
>>>>>> ubiattach: error!: cannot attach mtd5
>>>>>> error 25 (Inappropriate ioctl for device)
>>>>>
>>>>> Before any pointers, which version of mtd-utils are you using?
>>>>> How to:
>>>>> (http://linux-mtd.infradead.org/faq/general.html#L_compile_mtd)
>>>>>
>>>>> ~Vikram
>>>>>
>>>>> ______________________________________________________
>>>>> Linux MTD discussion mailing list
>>>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>>>>
>>>>
>>>
>>>
>>> ______________________________________________________
>>> Linux MTD discussion mailing list
>>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>>
>>
>>
>> ______________________________________________________
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>>
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
> 



From josh.wu at atmel.com  Fri Sep 21 06:16:12 2012
From: josh.wu at atmel.com (Josh Wu)
Date: Fri, 21 Sep 2012 18:16:12 +0800
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <20120920052333.GC17667@game.jcrosoft.org>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
 <20120920052333.GC17667@game.jcrosoft.org>
Message-ID: <505C3E6C.70309@atmel.com>

Hi, J.C

On 9/20/2012 1:23 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
> On 15:10 Tue 11 Sep     , Josh Wu wrote:
>> Add err_ecc_ioremap label to fix following errors:
>> ---8<---
>>    CC      drivers/mtd/nand/atmel_nand.o
>> drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
>> drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
>> make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
>> make[2]: *** [drivers/mtd/nand] Error 2
>> make[1]: *** [drivers/mtd] Error 2
>> make: *** [drivers] Error 2
>> --->8---
> switch to devm_xxx instead this will simplify the error patch and remove patch

understood. I will push a patch  which use devm_xxx. That should remove 
many code of the error handling. Thanks

Best Regards,
Josh Wu

>
> Best Regards,
> J.



From dedekind1 at gmail.com  Fri Sep 21 07:44:16 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 21 Sep 2012 14:44:16 +0300
Subject: [PATCH 2/2] drivers/mtd/devices/m25p80.c: Fix whole device erase
In-Reply-To: <5044D88F.2060003@ic.fr>
References: <5044D88F.2060003@ic.fr>
Message-ID: <1348227856.1890.6.camel@sauron.fi.intel.com>

On Mon, 2012-09-03 at 18:19 +0200, C?dric Cano wrote:
> From: C?dric Cano <ccano at interfaceconcept.com>
> 
> There are two ways to erase SPI Flash devices: sector per sector or the 
> entire Flash (used when MTD partition is the whole Flash).
> 
> When the whole Flash is erased, the SPI command is sent to the device 
> and the erase function ends. Then, when another access (read, write or 
> erase) is done, a  wait of busy is performed that fails because of Flash 
> erase time (can be more than 30s in case of whole erase).
> 
> This patch removes chip erase and use only sector per sector erase to 
> erase the chip. When erase is performed, Flash accesses can be done.

Please, re-send the patch with a better commit message which not only
explains _what_ you do, but also _why_ you do this, which problem you
solve, and what is the impact of the patch.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120921/5e0fa192/attachment-0001.sig>

From festevam at gmail.com  Fri Sep 21 08:19:33 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Fri, 21 Sep 2012 09:19:33 -0300
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <1346855725-31726-1-git-send-email-festevam@gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
Message-ID: <CAOMZO5DC8xuQ_0949ivyRDubWMv3=buEO+tm2yzdBApB7uT=Xg@mail.gmail.com>

Hi Artem.

On Wed, Sep 5, 2012 at 11:35 AM, Fabio Estevam <festevam at gmail.com> wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
>
> Using module_platform_driver() makes the code smaller and cleaner.
>
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> ---
> This patch depends on: "mtd: gpmi-nand: Improve logging style"

Any comments, please?

Regards,

Fabio Estevam


From dedekind1 at gmail.com  Fri Sep 21 08:25:13 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 21 Sep 2012 15:25:13 +0300
Subject: [MTD website] UBI: now we reserve 20/1024 PEB for bad block
 handling
In-Reply-To: <1346766969-13490-1-git-send-email-richard.genoud@gmail.com>
References: <1346766969-13490-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348230313.1890.7.camel@sauron.fi.intel.com>

On Tue, 2012-09-04 at 15:56 +0200, Richard Genoud wrote:
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Pushed to mtd-www, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120921/5aa396df/attachment.sig>

From ccano at interfaceconcept.com  Fri Sep 21 08:39:51 2012
From: ccano at interfaceconcept.com (=?ISO-8859-1?Q?C=E9dric_Cano?=)
Date: Fri, 21 Sep 2012 14:39:51 +0200
Subject: Fwd: [PATCH 1/1] drivers/mtd/devices/m25p80.c: Fix whole device erase
In-Reply-To: <5045BCA9.5040401@ic.fr>
References: <5045BCA9.5040401@ic.fr>
Message-ID: <505C6017.8060607@ic.fr>

From: C?dric Cano<ccano at interfaceconcept.com>

When the whole SPI Flash is erased, the chip erase command is sent to the
device without waiting for end of erase. So next read/write accesses are
in failure.

This patch removes chip erase to use only sector per sector erase for
whole Flash too. When chip erase is done, Flash can be accessed without
error.

C. Cano

Signed-off-by: C?dric Cano<ccano at interfaceconcept.com>
---
  drivers/mtd/devices/m25p80.c |   50 +++++-------------------------------------
  1 file changed, 5 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 5257345..b8956df 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -202,31 +202,6 @@ static int wait_till_ready(struct m25p *flash)
  	return 1;
  }
  
-/*
- * Erase the whole flash memory
- *
- * Returns 0 if successful, non-zero otherwise.
- */
-static int erase_chip(struct m25p *flash)
-{
-	pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
-			(long long)(flash->mtd.size >> 10));
-
-	/* Wait until finished previous write command. */
-	if (wait_till_ready(flash))
-		return 1;
-
-	/* Send write enable, then erase commands. */
-	write_enable(flash);
-
-	/* Set up command buffer. */
-	flash->command[0] = OPCODE_CHIP_ERASE;
-
-	spi_write(flash->spi, flash->command, 1);
-
-	return 0;
-}
-
  static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
  {
  	/* opcode is in cmd[0] */
@@ -297,31 +272,16 @@ static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
  
  	mutex_lock(&flash->lock);
  
-	/* whole-chip erase? */
-	if (len == flash->mtd.size) {
-		if (erase_chip(flash)) {
+	/* "sector"-at-a-time erase */
+	while (len) {
+		if (erase_sector(flash, addr)) {
  			instr->state = MTD_ERASE_FAILED;
  			mutex_unlock(&flash->lock);
  			return -EIO;
  		}
  
-	/* REVISIT in some cases we could speed up erasing large regions
-	 * by using OPCODE_SE instead of OPCODE_BE_4K.  We may have set up
-	 * to use "small sector erase", but that's not always optimal.
-	 */
-
-	/* "sector"-at-a-time erase */
-	} else {
-		while (len) {
-			if (erase_sector(flash, addr)) {
-				instr->state = MTD_ERASE_FAILED;
-				mutex_unlock(&flash->lock);
-				return -EIO;
-			}
-
-			addr += mtd->erasesize;
-			len -= mtd->erasesize;
-		}
+		addr += mtd->erasesize;
+		len -= mtd->erasesize;
  	}
  
  	mutex_unlock(&flash->lock);
-- 






From marex at denx.de  Fri Sep 21 08:53:42 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 21 Sep 2012 14:53:42 +0200
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <CAOMZO5DC8xuQ_0949ivyRDubWMv3=buEO+tm2yzdBApB7uT=Xg@mail.gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
 <CAOMZO5DC8xuQ_0949ivyRDubWMv3=buEO+tm2yzdBApB7uT=Xg@mail.gmail.com>
Message-ID: <201209211453.42528.marex@denx.de>

Dear Fabio Estevam,

> Hi Artem.
> 
> On Wed, Sep 5, 2012 at 11:35 AM, Fabio Estevam <festevam at gmail.com> wrote:
> > From: Fabio Estevam <fabio.estevam at freescale.com>
> > 
> > Using module_platform_driver() makes the code smaller and cleaner.
> > 
> > Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
> > ---
> > This patch depends on: "mtd: gpmi-nand: Improve logging style"
> 
> Any comments, please?

WFM

Reviewed-by: Marek Vasut <marex at denx.de>

> Regards,
> 
> Fabio Estevam

Best regards,
Marek Vasut


From artem.bityutskiy at linux.intel.com  Fri Sep 21 09:12:31 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Fri, 21 Sep 2012 16:12:31 +0300
Subject: [PATCH] mtd: m25p80: Disable 4K erase for s25sl032p, s25sl064p
In-Reply-To: <1346729496-3303-1-git-send-email-marex@denx.de>
References: <1346729496-3303-1-git-send-email-marex@denx.de>
Message-ID: <1348233151.7550.0.camel@sauron.fi.intel.com>

On Tue, 2012-09-04 at 05:31 +0200, Marek Vasut wrote:
> Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011,
> section 9.17:
> 
> A 64 kB sector erase (D8h) command issued on 4 kB or 8 kB erase
> sectors will erase all sectors in the specified 64 kB region.
> However, please note that a 4 kB sector erase (20h) or 8 kB
> sector erase (40h) command will not work on a 64 kB sector.
> 
> Refering further to Table 8.1 and Table 8.2, it is clearly seen
> that most of the sectors are 64kB, therefore disable this 4K
> erase support since it's valid only on first/last sectors.

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120921/6baa5c40/attachment.sig>

From dedekind1 at gmail.com  Fri Sep 21 09:19:10 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 21 Sep 2012 16:19:10 +0300
Subject: [PATCH V5] mtd: m25p80: Make fast read configurable via DT
In-Reply-To: <201209171610.28410.marex@denx.de>
References: <1345923416-9293-1-git-send-email-marex@denx.de>
 <201209171610.28410.marex@denx.de>
Message-ID: <1348233550.7550.2.camel@sauron.fi.intel.com>

On Mon, 2012-09-17 at 16:10 +0200, Marek Vasut wrote:
> Bump, do you think we can get this into 3.7 please?

Aiaiai!

--------------------------------------------------------------------------------

Successfully built configuration "i386_defconfig,i386,", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/devices/m25p80.c: In function ?m25p_probe?:
+drivers/mtd/devices/m25p80.c:808:23: warning: unused variable ?np? [-Wunused-variable]

--------------------------------------------------------------------------------


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120921/d7874f00/attachment.sig>

From marex at denx.de  Fri Sep 21 09:39:08 2012
From: marex at denx.de (Marek Vasut)
Date: Fri, 21 Sep 2012 15:39:08 +0200
Subject: [PATCH] mtd: m25p80: Disable 4K erase for s25sl032p, s25sl064p
In-Reply-To: <1348233151.7550.0.camel@sauron.fi.intel.com>
References: <1346729496-3303-1-git-send-email-marex@denx.de>
 <1348233151.7550.0.camel@sauron.fi.intel.com>
Message-ID: <201209211539.08938.marex@denx.de>

Dear Artem Bityutskiy,

> On Tue, 2012-09-04 at 05:31 +0200, Marek Vasut wrote:
> > Quoting from the datasheet for S25FL064P, rev. 05, Nov 18 2011,
> > section 9.17:
> > 
> > A 64 kB sector erase (D8h) command issued on 4 kB or 8 kB erase
> > sectors will erase all sectors in the specified 64 kB region.
> > However, please note that a 4 kB sector erase (20h) or 8 kB
> > sector erase (40h) command will not work on a 64 kB sector.
> > 
> > Refering further to Table 8.1 and Table 8.2, it is clearly seen
> > that most of the sectors are 64kB, therefore disable this 4K
> > erase support since it's valid only on first/last sectors.
> 
> Pushed to l2-mtd.git, thanks!

Thank you!

Best regards,
Marek Vasut


From dedekind1 at gmail.com  Fri Sep 21 09:42:18 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 21 Sep 2012 16:42:18 +0300
Subject: Fwd: [PATCH 1/1] drivers/mtd/devices/m25p80.c: Fix whole device
 erase
In-Reply-To: <505C6017.8060607@ic.fr>
References: <5045BCA9.5040401@ic.fr> <505C6017.8060607@ic.fr>
Message-ID: <1348234938.7964.1.camel@sauron.fi.intel.com>

On Fri, 2012-09-21 at 14:39 +0200, C?dric Cano wrote:
> From: C?dric Cano<ccano at interfaceconcept.com>
> 
> When the whole SPI Flash is erased, the chip erase command is sent to the
> device without waiting for end of erase. So next read/write accesses are
> in failure.

Can you wait while the chip erase to finish?

> This patch removes chip erase to use only sector per sector erase for
> whole Flash too. When chip erase is done, Flash can be accessed without
> error.

How much slower is this method?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120921/066be6f2/attachment-0001.sig>

From marcus.prebble at axis.com  Fri Sep 21 11:41:58 2012
From: marcus.prebble at axis.com (Marcus Prebble)
Date: Fri, 21 Sep 2012 17:41:58 +0200
Subject: mkfs.ubifs problem when output file really isn't in the UBIFS root
 directory
Message-ID: <1348242118.2552.1460.camel@lnxprebble2.se.axis.com>

Hi,

We are working on a project using UBI/UBIFS and I have run into a
problem with mkfs.ubifs which I am hoping someone can advise on.
Apologies if I have already missed the answer to this in the archives
somewhere.

A requirement of the project is to take an image of the root filesystem
(/) which is implemented as a static UBI read only volume. Obviously its
not possible to unmount /, but it seems to be possible to re-mount the
UBI volume, read only, onto another location e.g. /tmp/mnt/new_rootfs.

The problem arises when running mkfs.ubifs is that it fails saying that
the output file cannot be in the UBIFS root directory.
This sounds like a reasonable constraint if the output file really was
in the root, but this is not the case for us seeing root is mounted
somewhere belowtmp. To give a concrete example of the command we are
running:

mkfs.ubifs --output=/tmp/rootfs.img  --leb-size=129024
--root=/tmp/rootfs_mnt --min-io-size=2048 --max-leb-cnt=147 

Where /dev/ubi0_11 is mounted read-only on both / and /tmp/rootfs_mnt/.

Having a look at the source for mkfs.ubifs it seems that the function
in_path(..) is the problem - it works up the directory tree using ../
until it either reaches the top_dir (/) or the inode number/dev match in
which case it fails. It doesn't seem that this section of code has
changed in the latest version of mtd-utils (we are running 1.4.3-2) and
I wonder if this is a bug in in_path(..) or a genuine safeguard against
screwing something up? I suspect the former for when I disabled this
check in mkfs.ubifs.c the resulting image was completely OK.

Kind regards,

Marcus Prebble
Axis Communications AB



From shawn.guo at linaro.org  Fri Sep 21 12:46:26 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 22 Sep 2012 00:46:26 +0800
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
Message-ID: <20120921164622.GA5394@S2101-09.ap.freescale.net>

Hi Olof,

On Fri, Sep 21, 2012 at 01:26:43AM -0700, Olof Johansson wrote:
> I'll take a look at merging it tomorrow after I've dealt with smp_ops;
> if it looks reasonably conflict-free I'll pull it in. We need the
> sound dependency sorted out (or agreed upon) first though.
> 
I just published the branch below with this series rebased on top of
the necessary dependant branches.

  git://git.linaro.org/people/shawnguo/linux-2.6.git staging/imx-multiplatform

The dependant branches include:

* arm-soc/multiplatform/platform-data

* arm-soc/multiplatform/smp_ops

* git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-3.7

  It contains dependant patch "ASoC: mx27vis: retrieve gpio numbers
  from platform_data"

* git://git.infradead.org/mtd-2.6.git master

  The series is based on this tree to solve some non-trivial conflicts
  on mxc_nand driver.  Because mtd tree completely missed 3.6 merge
  window, having the series base on 3.6-rc actually means 3.5 code base
  in term of mtd support.  There are currently two cycles changes
  accumulated on mtd, and we need to base the series on it to sort out
  the conflicts.

* git://linuxtv.org/mchehab/media-next.git master

  The media tree renames mx2/mx3 camera drivers twice.  I'm not sure
  if git merge can detect them, so I just rebased the series on media
  tree to solve that.  The bonus point is that a number of trivial
  conflicts with imx27-coda support on media tree gets solved as well.

I'm not requesting you to pull the branch into arm-soc as a stable
branch but staging one, because the external dependencies which might
not be stable.  I attempt to use it for exposing the series on
linux-next, so that we can send it to Linus for 3.7 if there is chance
for us to (e.g. all the dependant branches hit mainline early during
3.7 merge window).

Shawn


From shawn.guo at linaro.org  Fri Sep 21 12:53:08 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 22 Sep 2012 00:53:08 +0800
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120921164622.GA5394@S2101-09.ap.freescale.net>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
 <20120921164622.GA5394@S2101-09.ap.freescale.net>
Message-ID: <20120921165305.GB5394@S2101-09.ap.freescale.net>

On Sat, Sep 22, 2012 at 12:46:26AM +0800, Shawn Guo wrote:
> I just published the branch below with this series rebased on top of
> the necessary dependant branches.
> 
>   git://git.linaro.org/people/shawnguo/linux-2.6.git staging/imx-multiplatform
> 
> The dependant branches include:
> 

Forgot the base:

  * arm-soc/next/multiplatform

Shawn

> * arm-soc/multiplatform/platform-data
> 
> * arm-soc/multiplatform/smp_ops
> 
> * git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-3.7
> 
>   It contains dependant patch "ASoC: mx27vis: retrieve gpio numbers
>   from platform_data"
> 
> * git://git.infradead.org/mtd-2.6.git master
> 
>   The series is based on this tree to solve some non-trivial conflicts
>   on mxc_nand driver.  Because mtd tree completely missed 3.6 merge
>   window, having the series base on 3.6-rc actually means 3.5 code base
>   in term of mtd support.  There are currently two cycles changes
>   accumulated on mtd, and we need to base the series on it to sort out
>   the conflicts.
> 
> * git://linuxtv.org/mchehab/media-next.git master
> 
>   The media tree renames mx2/mx3 camera drivers twice.  I'm not sure
>   if git merge can detect them, so I just rebased the series on media
>   tree to solve that.  The bonus point is that a number of trivial
>   conflicts with imx27-coda support on media tree gets solved as well.
> 
> I'm not requesting you to pull the branch into arm-soc as a stable
> branch but staging one, because the external dependencies which might
> not be stable.  I attempt to use it for exposing the series on
> linux-next, so that we can send it to Linus for 3.7 if there is chance
> for us to (e.g. all the dependant branches hit mainline early during
> 3.7 merge window).


From vikram186 at gmail.com  Fri Sep 21 14:29:01 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Fri, 21 Sep 2012 23:59:01 +0530
Subject: i.MX6S/GPMI-NAND issue on 3.5.4
Message-ID: <505CB1ED.8010909@gmail.com>

Hello,

I'm facing some issue with GPMI-NAND driver on i.MX6 solo.
I've a TOSHIBA 4KiB page NAND connected to the GPMI.
(4KiB + 128 bytes OOB)

I tested it using the following,

1) U-boot v2012.04
2) Freescale's U-boot for i.MX6
3) Freescale's Kernel 3.0.15
	Result: 0x98 0xAC 0x90 0x26 (Correct)

4) Linux v3.5.4 stable
	Result: 0x98 0xA8 0x90 0x20 (Incorrect)

When I issue a READID command, 1, 2 & 3 gives me correct results, 
whereas the 3.5.4 version gives me some different result.

Any help would be very much appreciated.

Regards,
Vikram


From csd at broadcom.com  Fri Sep 21 17:40:24 2012
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 21 Sep 2012 14:40:24 -0700
Subject: [PATCH v3 0/2] ARM: Removal of bcmring
Message-ID: <1348263626-3087-1-git-send-email-csd@broadcom.com>


Remove mach-bcmring as this is no longer maintained or used.

Updated the removal with:
 - drop the edit to mach-types requested by Russell King
 - eliminate defconfig mod from patch 1 requested Olof Johansson

Also switched to using git send-email to avoid word-wrapping 
problems


Christian Daudt (2):
  ARM: Remove bcmring NAND driver
  ARM: Remove mach-bcmring

 MAINTAINERS                                        |   16 -
 arch/arm/Kconfig                                   |   14 -
 arch/arm/Makefile                                  |    1 -
 arch/arm/configs/bcmring_defconfig                 |   79 -
 arch/arm/mach-bcmring/Kconfig                      |   19 -
 arch/arm/mach-bcmring/Makefile                     |    8 -
 arch/arm/mach-bcmring/Makefile.boot                |    6 -
 arch/arm/mach-bcmring/arch.c                       |  199 ---
 arch/arm/mach-bcmring/clock.c                      |  223 ---
 arch/arm/mach-bcmring/clock.h                      |   33 -
 arch/arm/mach-bcmring/core.c                       |  228 ---
 arch/arm/mach-bcmring/core.h                       |   31 -
 arch/arm/mach-bcmring/csp/Makefile                 |    3 -
 arch/arm/mach-bcmring/csp/chipc/Makefile           |    1 -
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |  776 ---------
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |  293 ----
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |  124 --
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |   64 -
 arch/arm/mach-bcmring/csp/dmac/Makefile            |    1 -
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |  917 -----------
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      | 1017 ------------
 arch/arm/mach-bcmring/csp/tmr/Makefile             |    1 -
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |  576 -------
 arch/arm/mach-bcmring/dma.c                        | 1518 ------------------
 arch/arm/mach-bcmring/dma_device.c                 |  593 -------
 arch/arm/mach-bcmring/include/cfg_global.h         |   13 -
 arch/arm/mach-bcmring/include/cfg_global_defines.h |   40 -
 arch/arm/mach-bcmring/include/csp/cache.h          |   35 -
 arch/arm/mach-bcmring/include/csp/delay.h          |   36 -
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |  596 -------
 arch/arm/mach-bcmring/include/csp/errno.h          |   32 -
 arch/arm/mach-bcmring/include/csp/intcHw.h         |   40 -
 arch/arm/mach-bcmring/include/csp/module.h         |   32 -
 arch/arm/mach-bcmring/include/csp/reg.h            |  114 --
 arch/arm/mach-bcmring/include/csp/secHw.h          |   65 -
 arch/arm/mach-bcmring/include/csp/stdint.h         |   30 -
 arch/arm/mach-bcmring/include/csp/string.h         |   34 -
 arch/arm/mach-bcmring/include/csp/tmrHw.h          |  263 ---
 arch/arm/mach-bcmring/include/mach/csp/cap.h       |   63 -
 .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
 .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
 .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 --------------------
 .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
 .../mach-bcmring/include/mach/csp/dmacHw_priv.h    |  145 --
 .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
 .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h   |  101 --
 arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
 .../mach-bcmring/include/mach/csp/secHw_inline.h   |   79 -
 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
 arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
 arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
 arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
 arch/arm/mach-bcmring/include/mach/irqs.h          |  132 --
 .../mach-bcmring/include/mach/memory_settings.h    |   67 -
 arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
 arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
 arch/arm/mach-bcmring/include/mach/timer.h         |   77 -
 arch/arm/mach-bcmring/include/mach/timex.h         |   25 -
 arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
 arch/arm/mach-bcmring/irq.c                        |  126 --
 arch/arm/mach-bcmring/mm.c                         |   60 -
 arch/arm/mach-bcmring/timer.c                      |   61 -
 drivers/mtd/nand/Kconfig                           |   16 -
 drivers/mtd/nand/Makefile                          |    1 -
 drivers/mtd/nand/bcm_umi_bch.c                     |  217 ---
 drivers/mtd/nand/bcm_umi_nand.c                    |  555 -------
 drivers/mtd/nand/nand_bcm_umi.c                    |  149 --
 drivers/mtd/nand/nand_bcm_umi.h                    |  337 ----
 72 files changed, 17052 deletions(-)
 delete mode 100644 arch/arm/configs/bcmring_defconfig
 delete mode 100644 arch/arm/mach-bcmring/Kconfig
 delete mode 100644 arch/arm/mach-bcmring/Makefile
 delete mode 100644 arch/arm/mach-bcmring/Makefile.boot
 delete mode 100644 arch/arm/mach-bcmring/arch.c
 delete mode 100644 arch/arm/mach-bcmring/clock.c
 delete mode 100644 arch/arm/mach-bcmring/clock.h
 delete mode 100644 arch/arm/mach-bcmring/core.c
 delete mode 100644 arch/arm/mach-bcmring/core.h
 delete mode 100644 arch/arm/mach-bcmring/csp/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw.c
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
 delete mode 100644 arch/arm/mach-bcmring/csp/tmr/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/tmr/tmrHw.c
 delete mode 100644 arch/arm/mach-bcmring/dma.c
 delete mode 100644 arch/arm/mach-bcmring/dma_device.c
 delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h
 delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/memory_settings.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/timer.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/timex.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-bcmring/irq.c
 delete mode 100644 arch/arm/mach-bcmring/mm.c
 delete mode 100644 arch/arm/mach-bcmring/timer.c
 delete mode 100644 drivers/mtd/nand/bcm_umi_bch.c
 delete mode 100644 drivers/mtd/nand/bcm_umi_nand.c
 delete mode 100644 drivers/mtd/nand/nand_bcm_umi.c
 delete mode 100644 drivers/mtd/nand/nand_bcm_umi.h

-- 
1.7.9.5




From csd at broadcom.com  Fri Sep 21 17:40:25 2012
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 21 Sep 2012 14:40:25 -0700
Subject: [PATCH v3 1/2] ARM: Remove bcmring NAND driver
In-Reply-To: <1348263626-3087-1-git-send-email-csd@broadcom.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
Message-ID: <1348263626-3087-2-git-send-email-csd@broadcom.com>

This driver is being removed as part of the cleanup of the bcmring
SoC from mainline as it is no longer maintained.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
Acked-by: Will Deacon <will.deacon at arm.com>
---
 MAINTAINERS                     |    9 -
 drivers/mtd/nand/Kconfig        |   16 --
 drivers/mtd/nand/Makefile       |    1 -
 drivers/mtd/nand/bcm_umi_bch.c  |  217 ---------------
 drivers/mtd/nand/bcm_umi_nand.c |  555 ---------------------------------------
 drivers/mtd/nand/nand_bcm_umi.c |  149 -----------
 drivers/mtd/nand/nand_bcm_umi.h |  337 ------------------------
 7 files changed, 1284 deletions(-)
 delete mode 100644 drivers/mtd/nand/bcm_umi_bch.c
 delete mode 100644 drivers/mtd/nand/bcm_umi_nand.c
 delete mode 100644 drivers/mtd/nand/nand_bcm_umi.c
 delete mode 100644 drivers/mtd/nand/nand_bcm_umi.h

diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..36da5f9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -665,15 +665,6 @@ L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-bcmring
 
-ARM/BCMRING MTD NAND DRIVER
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-mtd at lists.infradead.org
-S:	Maintained
-F:	drivers/mtd/nand/bcm_umi_nand.c
-F:	drivers/mtd/nand/bcm_umi_bch.c
-F:	drivers/mtd/nand/nand_bcm_umi.h
-
 ARM/CALXEDA HIGHBANK ARCHITECTURE
 M:	Rob Herring <rob.herring at calxeda.com>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..5c60a44 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -267,22 +267,6 @@ config MTD_NAND_S3C2410_CLKSTOP
 	  when the is NAND chip selected or released, but will save
 	  approximately 5mA of power when there is nothing happening.
 
-config MTD_NAND_BCM_UMI
-	tristate "NAND Flash support for BCM Reference Boards"
-	depends on ARCH_BCMRING
-	help
-	  This enables the NAND flash controller on the BCM UMI block.
-
-	  No board specific support is done by this driver, each board
-	  must advertise a platform_device for the driver to attach.
-
-config MTD_NAND_BCM_UMI_HWCS
-	bool "BCM UMI NAND Hardware CS"
-	depends on MTD_NAND_BCM_UMI
-	help
-	  Enable the use of the BCM UMI block's internal CS using NAND.
-	  This should only be used if you know the external NAND CS can toggle.
-
 config MTD_NAND_DISKONCHIP
 	tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)"
 	depends on EXPERIMENTAL
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..8b2825a 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -46,7 +46,6 @@ obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
 obj-$(CONFIG_MTD_NAND_NUC900)		+= nuc900_nand.o
 obj-$(CONFIG_MTD_NAND_NOMADIK)		+= nomadik_nand.o
-obj-$(CONFIG_MTD_NAND_BCM_UMI)		+= bcm_umi_nand.o nand_bcm_umi.o
 obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
 obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
diff --git a/drivers/mtd/nand/bcm_umi_bch.c b/drivers/mtd/nand/bcm_umi_bch.c
deleted file mode 100644
index 5914bb3..0000000
--- a/drivers/mtd/nand/bcm_umi_bch.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include "nand_bcm_umi.h"
-
-/* ---- External Variable Declarations ----------------------------------- */
-/* ---- External Function Prototypes ------------------------------------- */
-/* ---- Public Variables ------------------------------------------------- */
-/* ---- Private Constants and Types -------------------------------------- */
-
-/* ---- Private Function Prototypes -------------------------------------- */
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required);
-
-/* ---- Private Variables ------------------------------------------------ */
-
-/*
-** nand_hw_eccoob
-** New oob placement block for use with hardware ecc generation.
-*/
-static struct nand_ecclayout nand_hw_eccoob_512 = {
-	/* Reserve 5 for BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 3)
-		    {.offset = 0, .length = 2}
-#else
-		    {.offset = 0, .length = 5},
-		    {.offset = 6, .length = 7}
-#endif
-		    }
-};
-
-/*
-** We treat the OOB for a 2K page as if it were 4 512 byte oobs,
-** except the BI is at byte 0.
-*/
-static struct nand_ecclayout nand_hw_eccoob_2048 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-#elif (NAND_ECC_NUM_BYTES > 7)
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6}
-#else
-		    {.offset = 1, .length = 8},
-		    {.offset = 16, .length = 9},
-		    {.offset = 32, .length = 9},
-		    {.offset = 48, .length = 9}
-#endif
-		    }
-};
-
-/* We treat the OOB for a 4K page as if it were 8 512 byte oobs,
- * except the BI is at byte 0. */
-static struct nand_ecclayout nand_hw_eccoob_4096 = {
-	/* Reserve 0 as BI indicator */
-	.oobfree = {
-#if (NAND_ECC_NUM_BYTES > 10)
-		    {.offset = 1, .length = 2},
-		    {.offset = 16, .length = 3},
-		    {.offset = 32, .length = 3},
-		    {.offset = 48, .length = 3},
-		    {.offset = 64, .length = 3},
-		    {.offset = 80, .length = 3},
-		    {.offset = 96, .length = 3},
-		    {.offset = 112, .length = 3}
-#else
-		    {.offset = 1, .length = 5},
-		    {.offset = 16, .length = 6},
-		    {.offset = 32, .length = 6},
-		    {.offset = 48, .length = 6},
-		    {.offset = 64, .length = 6},
-		    {.offset = 80, .length = 6},
-		    {.offset = 96, .length = 6},
-		    {.offset = 112, .length = 6}
-#endif
-		    }
-};
-
-/* ---- Private Functions ------------------------------------------------ */
-/* ==== Public Functions ================================================= */
-
-/****************************************************************************
-*
-*  bcm_umi_bch_read_page_hwecc - hardware ecc based page read function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	buffer to store read data
-*  @oob_required:	caller expects OOB data read to chip->oob_poi
-*
-***************************************************************************/
-static int bcm_umi_bch_read_page_hwecc(struct mtd_info *mtd,
-				       struct nand_chip *chip, uint8_t * buf,
-				       int oob_required, int page)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	uint8_t *datap = buf;
-	uint8_t eccCalc[NAND_ECC_NUM_BYTES];
-	int sectorOobSize = mtd->oobsize / eccsteps;
-	int stat;
-	unsigned int max_bitflips = 0;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-			sectorIdx++, datap += eccsize) {
-		if (sectorIdx > 0) {
-			/* Seek to page location within sector */
-			chip->cmdfunc(mtd, NAND_CMD_RNDOUT, sectorIdx * eccsize,
-				      -1);
-		}
-
-		/* Enable hardware ECC before reading the buf */
-		nand_bcm_umi_bch_enable_read_hwecc();
-
-		/* Read in data */
-		bcm_umi_nand_read_buf(mtd, datap, eccsize);
-
-		/* Pause hardware ECC after reading the buf */
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		/* Read the OOB ECC */
-		chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
-			      mtd->writesize + sectorIdx * sectorOobSize, -1);
-		nand_bcm_umi_bch_read_oobEcc(mtd->writesize, eccCalc,
-					     NAND_ECC_NUM_BYTES,
-					     chip->oob_poi +
-					     sectorIdx * sectorOobSize);
-
-		/* Correct any ECC detected errors */
-		stat =
-		    nand_bcm_umi_bch_correct_page(datap, eccCalc,
-						  NAND_ECC_NUM_BYTES);
-
-		/* Update Stats */
-		if (stat < 0) {
-#if defined(NAND_BCM_UMI_DEBUG)
-			printk(KERN_WARNING "%s uncorr_err sectorIdx=%d\n",
-			       __func__, sectorIdx);
-			printk(KERN_WARNING
-			       "%s data %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x\n",
-			       __func__, datap[0], datap[1], datap[2], datap[3],
-			       datap[4], datap[5], datap[6], datap[7]);
-			printk(KERN_WARNING
-			       "%s ecc  %02x %02x %02x %02x "
-					 "%02x %02x %02x %02x %02x %02x "
-					 "%02x %02x %02x\n",
-			       __func__, eccCalc[0], eccCalc[1], eccCalc[2],
-			       eccCalc[3], eccCalc[4], eccCalc[5], eccCalc[6],
-			       eccCalc[7], eccCalc[8], eccCalc[9], eccCalc[10],
-			       eccCalc[11], eccCalc[12]);
-			BUG();
-#endif
-			mtd->ecc_stats.failed++;
-		} else {
-#if defined(NAND_BCM_UMI_DEBUG)
-			if (stat > 0) {
-				printk(KERN_INFO
-				       "%s %d correctable_errors detected\n",
-				       __func__, stat);
-			}
-#endif
-			mtd->ecc_stats.corrected += stat;
-			max_bitflips = max_t(unsigned int, max_bitflips, stat);
-		}
-	}
-	return max_bitflips;
-}
-
-/****************************************************************************
-*
-*  bcm_umi_bch_write_page_hwecc - hardware ecc based page write function
-*  @mtd:	mtd info structure
-*  @chip:	nand chip info structure
-*  @buf:	data buffer
-*  @oob_required:	must write chip->oob_poi to OOB
-*
-***************************************************************************/
-static void bcm_umi_bch_write_page_hwecc(struct mtd_info *mtd,
-	struct nand_chip *chip, const uint8_t *buf, int oob_required)
-{
-	int sectorIdx = 0;
-	int eccsize = chip->ecc.size;
-	int eccsteps = chip->ecc.steps;
-	const uint8_t *datap = buf;
-	uint8_t *oobp = chip->oob_poi;
-	int sectorOobSize = mtd->oobsize / eccsteps;
-
-	for (sectorIdx = 0; sectorIdx < eccsteps;
-	     sectorIdx++, datap += eccsize, oobp += sectorOobSize) {
-		/* Enable hardware ECC before writing the buf */
-		nand_bcm_umi_bch_enable_write_hwecc();
-		bcm_umi_nand_write_buf(mtd, datap, eccsize);
-		nand_bcm_umi_bch_write_oobEcc(mtd->writesize, oobp,
-					      NAND_ECC_NUM_BYTES);
-	}
-
-	bcm_umi_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
-}
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
deleted file mode 100644
index c855e7c..0000000
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ /dev/null
@@ -1,555 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/reg_nand.h>
-#include <mach/reg_umi.h>
-
-#include "nand_bcm_umi.h"
-
-#include <mach/memory_settings.h>
-
-#define USE_DMA 1
-#include <mach/dma.h>
-#include <linux/dma-mapping.h>
-#include <linux/completion.h>
-
-/* ---- External Variable Declarations ----------------------------------- */
-/* ---- External Function Prototypes ------------------------------------- */
-/* ---- Public Variables ------------------------------------------------- */
-/* ---- Private Constants and Types -------------------------------------- */
-static const __devinitconst char gBanner[] = KERN_INFO \
-	"BCM UMI MTD NAND Driver: 1.00\n";
-
-#if NAND_ECC_BCH
-static uint8_t scan_ff_pattern[] = { 0xff };
-
-static struct nand_bbt_descr largepage_bbt = {
-	.options = 0,
-	.offs = 0,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-#endif
-
-/*
-** Preallocate a buffer to avoid having to do this every dma operation.
-** This is the size of the preallocated coherent DMA buffer.
-*/
-#if USE_DMA
-#define DMA_MIN_BUFLEN	512
-#define DMA_MAX_BUFLEN	PAGE_SIZE
-#define USE_DIRECT_IO(len)	(((len) < DMA_MIN_BUFLEN) || \
-	((len) > DMA_MAX_BUFLEN))
-
-/*
- * The current NAND data space goes from 0x80001900 to 0x80001FFF,
- * which is only 0x700 = 1792 bytes long. This is too small for 2K, 4K page
- * size NAND flash. Need to break the DMA down to multiple 1Ks.
- *
- * Need to make sure REG_NAND_DATA_PADDR + DMA_MAX_LEN < 0x80002000
- */
-#define DMA_MAX_LEN             1024
-
-#else /* !USE_DMA */
-#define DMA_MIN_BUFLEN          0
-#define DMA_MAX_BUFLEN          0
-#define USE_DIRECT_IO(len)      1
-#endif
-/* ---- Private Function Prototypes -------------------------------------- */
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len);
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
-				   int len);
-
-/* ---- Private Variables ------------------------------------------------ */
-static struct mtd_info *board_mtd;
-static void __iomem *bcm_umi_io_base;
-static void *virtPtr;
-static dma_addr_t physPtr;
-static struct completion nand_comp;
-
-/* ---- Private Functions ------------------------------------------------ */
-#if NAND_ECC_BCH
-#include "bcm_umi_bch.c"
-#else
-#include "bcm_umi_hamming.c"
-#endif
-
-#if USE_DMA
-
-/* Handler called when the DMA finishes. */
-static void nand_dma_handler(DMA_Device_t dev, int reason, void *userData)
-{
-	complete(&nand_comp);
-}
-
-static int nand_dma_init(void)
-{
-	int rc;
-
-	rc = dma_set_device_handler(DMA_DEVICE_NAND_MEM_TO_MEM,
-		nand_dma_handler, NULL);
-	if (rc != 0) {
-		printk(KERN_ERR "dma_set_device_handler failed: %d\n", rc);
-		return rc;
-	}
-
-	virtPtr =
-	    dma_alloc_coherent(NULL, DMA_MAX_BUFLEN, &physPtr, GFP_KERNEL);
-	if (virtPtr == NULL) {
-		printk(KERN_ERR "NAND - Failed to allocate memory for DMA buffer\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static void nand_dma_term(void)
-{
-	if (virtPtr != NULL)
-		dma_free_coherent(NULL, DMA_MAX_BUFLEN, virtPtr, physPtr);
-}
-
-static void nand_dma_read(void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (virtPtr == NULL)
-		panic("nand_dma_read: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_read: physPtr == NULL\n");
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_read: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, REG_NAND_DATA_PADDR,
-					physPtr + offset, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-
-	if (buf != NULL)
-		memcpy(buf, virtPtr, len);
-}
-
-static void nand_dma_write(const void *buf, int len)
-{
-	int offset = 0;
-	int tmp_len = 0;
-	int len_left = len;
-	DMA_Handle_t hndl;
-
-	if (buf == NULL)
-		panic("nand_dma_write: buf == NULL\n");
-
-	if (virtPtr == NULL)
-		panic("nand_dma_write: virtPtr == NULL\n");
-
-	if ((void *)physPtr == NULL)
-		panic("nand_dma_write: physPtr == NULL\n");
-
-	memcpy(virtPtr, buf, len);
-
-
-	hndl = dma_request_channel(DMA_DEVICE_NAND_MEM_TO_MEM);
-	if (hndl < 0) {
-		printk(KERN_ERR
-		       "nand_dma_write: unable to allocate dma channel: %d\n",
-		       (int)hndl);
-		panic("\n");
-	}
-
-	while (len_left > 0) {
-		if (len_left > DMA_MAX_LEN) {
-			tmp_len = DMA_MAX_LEN;
-			len_left -= DMA_MAX_LEN;
-		} else {
-			tmp_len = len_left;
-			len_left = 0;
-		}
-
-		init_completion(&nand_comp);
-		dma_transfer_mem_to_mem(hndl, physPtr + offset,
-					REG_NAND_DATA_PADDR, tmp_len);
-		wait_for_completion(&nand_comp);
-
-		offset += tmp_len;
-	}
-
-	dma_free_channel(hndl);
-}
-
-#endif
-
-static int nand_dev_ready(struct mtd_info *mtd)
-{
-	return nand_bcm_umi_dev_ready();
-}
-
-/****************************************************************************
-*
-*  bcm_umi_nand_inithw
-*
-*   This routine does the necessary hardware (board-specific)
-*   initializations.  This includes setting up the timings, etc.
-*
-***************************************************************************/
-int bcm_umi_nand_inithw(void)
-{
-	/* Configure nand timing parameters */
-	REG_UMI_NAND_TCR &= ~0x7ffff;
-	REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
-
-#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
-	/* enable software control of CS */
-	REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
-#endif
-
-	/* keep NAND chip select asserted */
-	REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
-
-	REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
-	/* enable writes to flash */
-	REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
-
-	writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
-	nand_bcm_umi_wait_till_ready();
-
-#if NAND_ECC_BCH
-	nand_bcm_umi_bch_config_ecc(NAND_ECC_NUM_BYTES);
-#endif
-
-	return 0;
-}
-
-/* Used to turn latch the proper register for access. */
-static void bcm_umi_nand_hwcontrol(struct mtd_info *mtd, int cmd,
-				   unsigned int ctrl)
-{
-	/* send command to hardware */
-	struct nand_chip *chip = mtd->priv;
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if (ctrl & NAND_CLE) {
-			chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_CMD_OFFSET;
-			goto CMD;
-		}
-		if (ctrl & NAND_ALE) {
-			chip->IO_ADDR_W =
-			    bcm_umi_io_base + REG_NAND_ADDR_OFFSET;
-			goto CMD;
-		}
-		chip->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	}
-
-CMD:
-	/* Send command to chip directly */
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, chip->IO_ADDR_W);
-}
-
-static void bcm_umi_nand_write_buf(struct mtd_info *mtd, const u_char * buf,
-				   int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		/* Do it the old way if the buffer is small or too large.
-		 * Probably quicker than starting and checking dma. */
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			writeb(buf[i], this->IO_ADDR_W);
-	}
-#if USE_DMA
-	else
-		nand_dma_write(buf, len);
-#endif
-}
-
-static void bcm_umi_nand_read_buf(struct mtd_info *mtd, u_char * buf, int len)
-{
-	if (USE_DIRECT_IO(len)) {
-		int i;
-		struct nand_chip *this = mtd->priv;
-
-		for (i = 0; i < len; i++)
-			buf[i] = readb(this->IO_ADDR_R);
-	}
-#if USE_DMA
-	else
-		nand_dma_read(buf, len);
-#endif
-}
-
-static uint8_t readbackbuf[NAND_MAX_PAGESIZE];
-static int bcm_umi_nand_verify_buf(struct mtd_info *mtd, const u_char * buf,
-				   int len)
-{
-	/*
-	 * Try to readback page with ECC correction. This is necessary
-	 * for MLC parts which may have permanently stuck bits.
-	 */
-	struct nand_chip *chip = mtd->priv;
-	int ret = chip->ecc.read_page(mtd, chip, readbackbuf, 0, 0);
-	if (ret < 0)
-		return -EFAULT;
-	else {
-		if (memcmp(readbackbuf, buf, len) == 0)
-			return 0;
-
-		return -EFAULT;
-	}
-	return 0;
-}
-
-static int __devinit bcm_umi_nand_probe(struct platform_device *pdev)
-{
-	struct nand_chip *this;
-	struct resource *r;
-	int err = 0;
-
-	printk(gBanner);
-
-	/* Allocate memory for MTD device structure and private data */
-	board_mtd =
-	    kmalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip),
-		    GFP_KERNEL);
-	if (!board_mtd) {
-		printk(KERN_WARNING
-		       "Unable to allocate NAND MTD device structure.\n");
-		return -ENOMEM;
-	}
-
-	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	if (!r) {
-		err = -ENXIO;
-		goto out_free;
-	}
-
-	/* map physical address */
-	bcm_umi_io_base = ioremap(r->start, resource_size(r));
-
-	if (!bcm_umi_io_base) {
-		printk(KERN_ERR "ioremap to access BCM UMI NAND chip failed\n");
-		err = -EIO;
-		goto out_free;
-	}
-
-	/* Get pointer to private data */
-	this = (struct nand_chip *)(&board_mtd[1]);
-
-	/* Initialize structures */
-	memset((char *)board_mtd, 0, sizeof(struct mtd_info));
-	memset((char *)this, 0, sizeof(struct nand_chip));
-
-	/* Link the private data with the MTD structure */
-	board_mtd->priv = this;
-
-	/* Initialize the NAND hardware.  */
-	if (bcm_umi_nand_inithw() < 0) {
-		printk(KERN_ERR "BCM UMI NAND chip could not be initialized\n");
-		err = -EIO;
-		goto out_unmap;
-	}
-
-	/* Set address of NAND IO lines */
-	this->IO_ADDR_W = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-	this->IO_ADDR_R = bcm_umi_io_base + REG_NAND_DATA8_OFFSET;
-
-	/* Set command delay time, see datasheet for correct value */
-	this->chip_delay = 0;
-	/* Assign the device ready function, if available */
-	this->dev_ready = nand_dev_ready;
-	this->options = 0;
-
-	this->write_buf = bcm_umi_nand_write_buf;
-	this->read_buf = bcm_umi_nand_read_buf;
-	this->verify_buf = bcm_umi_nand_verify_buf;
-
-	this->cmd_ctrl = bcm_umi_nand_hwcontrol;
-	this->ecc.mode = NAND_ECC_HW;
-	this->ecc.size = 512;
-	this->ecc.bytes = NAND_ECC_NUM_BYTES;
-#if NAND_ECC_BCH
-	this->ecc.read_page = bcm_umi_bch_read_page_hwecc;
-	this->ecc.write_page = bcm_umi_bch_write_page_hwecc;
-#else
-	this->ecc.correct = nand_correct_data512;
-	this->ecc.calculate = bcm_umi_hamming_get_hw_ecc;
-	this->ecc.hwctl = bcm_umi_hamming_enable_hwecc;
-#endif
-
-#if USE_DMA
-	err = nand_dma_init();
-	if (err != 0)
-		goto out_unmap;
-#endif
-
-	/* Figure out the size of the device that we have.
-	 * We need to do this to figure out which ECC
-	 * layout we'll be using.
-	 */
-
-	err = nand_scan_ident(board_mtd, 1, NULL);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Now that we know the nand size, we can setup the ECC layout */
-
-	switch (board_mtd->writesize) {	/* writesize is the pagesize */
-	case 4096:
-		this->ecc.layout = &nand_hw_eccoob_4096;
-		break;
-	case 2048:
-		this->ecc.layout = &nand_hw_eccoob_2048;
-		break;
-	case 512:
-		this->ecc.layout = &nand_hw_eccoob_512;
-		break;
-	default:
-		{
-			printk(KERN_ERR "NAND - Unrecognized pagesize: %d\n",
-					 board_mtd->writesize);
-			err = -EINVAL;
-			goto out_unmap;
-		}
-	}
-
-#if NAND_ECC_BCH
-	if (board_mtd->writesize > 512) {
-		if (this->bbt_options & NAND_BBT_USE_FLASH)
-			largepage_bbt.options = NAND_BBT_SCAN2NDPAGE;
-		this->badblock_pattern = &largepage_bbt;
-	}
-
-	this->ecc.strength = 8;
-
-#endif
-
-	/* Now finish off the scan, now that ecc.layout has been initialized. */
-
-	err = nand_scan_tail(board_mtd);
-	if (err) {
-		printk(KERN_ERR "nand_scan failed: %d\n", err);
-		goto out_unmap;
-	}
-
-	/* Register the partitions */
-	board_mtd->name = "bcm_umi-nand";
-	mtd_device_parse_register(board_mtd, NULL, NULL, NULL, 0);
-
-	/* Return happy */
-	return 0;
-out_unmap:
-	iounmap(bcm_umi_io_base);
-out_free:
-	kfree(board_mtd);
-	return err;
-}
-
-static int bcm_umi_nand_remove(struct platform_device *pdev)
-{
-#if USE_DMA
-	nand_dma_term();
-#endif
-
-	/* Release resources, unregister device */
-	nand_release(board_mtd);
-
-	/* unmap physical address */
-	iounmap(bcm_umi_io_base);
-
-	/* Free the MTD device structure */
-	kfree(board_mtd);
-
-	return 0;
-}
-
-#ifdef CONFIG_PM
-static int bcm_umi_nand_suspend(struct platform_device *pdev,
-				pm_message_t state)
-{
-	printk(KERN_ERR "MTD NAND suspend is being called\n");
-	return 0;
-}
-
-static int bcm_umi_nand_resume(struct platform_device *pdev)
-{
-	printk(KERN_ERR "MTD NAND resume is being called\n");
-	return 0;
-}
-#else
-#define bcm_umi_nand_suspend   NULL
-#define bcm_umi_nand_resume    NULL
-#endif
-
-static struct platform_driver nand_driver = {
-	.driver = {
-		   .name = "bcm-nand",
-		   .owner = THIS_MODULE,
-		   },
-	.probe = bcm_umi_nand_probe,
-	.remove = bcm_umi_nand_remove,
-	.suspend = bcm_umi_nand_suspend,
-	.resume = bcm_umi_nand_resume,
-};
-
-module_platform_driver(nand_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Broadcom");
-MODULE_DESCRIPTION("BCM UMI MTD NAND driver");
diff --git a/drivers/mtd/nand/nand_bcm_umi.c b/drivers/mtd/nand/nand_bcm_umi.c
deleted file mode 100644
index 46a6bc9..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include "nand_bcm_umi.h"
-#ifdef BOOT0_BUILD
-#include <uart.h>
-#endif
-
-/* ---- External Variable Declarations ----------------------------------- */
-/* ---- External Function Prototypes ------------------------------------- */
-/* ---- Public Variables ------------------------------------------------- */
-/* ---- Private Constants and Types -------------------------------------- */
-/* ---- Private Function Prototypes -------------------------------------- */
-/* ---- Private Variables ------------------------------------------------ */
-/* ---- Private Functions ------------------------------------------------ */
-
-#if NAND_ECC_BCH
-/****************************************************************************
-*  nand_bch_ecc_flip_bit - Routine to flip an errored bit
-*
-*  PURPOSE:
-*     This is a helper routine that flips the bit (0 -> 1 or 1 -> 0) of the
-*     errored bit specified
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*     errorLocation - Location of the bit that needs to be flipped
-*
-*  RETURNS:
-*     None
-****************************************************************************/
-static void nand_bcm_umi_bch_ecc_flip_bit(uint8_t *datap, int errorLocation)
-{
-	int locWithinAByte = (errorLocation & REG_UMI_BCH_ERR_LOC_BYTE) >> 0;
-	int locWithinAWord = (errorLocation & REG_UMI_BCH_ERR_LOC_WORD) >> 3;
-	int locWithinAPage = (errorLocation & REG_UMI_BCH_ERR_LOC_PAGE) >> 5;
-
-	uint8_t errorByte = 0;
-	uint8_t byteMask = 1 << locWithinAByte;
-
-	/* BCH uses big endian, need to change the location
-	 * bits to little endian */
-	locWithinAWord = 3 - locWithinAWord;
-
-	errorByte = datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord];
-
-#ifdef BOOT0_BUILD
-	puthexs("\nECC Correct Offset: ",
-		locWithinAPage * sizeof(uint32_t) + locWithinAWord);
-	puthexs(" errorByte:", errorByte);
-	puthex8(" Bit: ", locWithinAByte);
-#endif
-
-	if (errorByte & byteMask) {
-		/* bit needs to be cleared */
-		errorByte &= ~byteMask;
-	} else {
-		/* bit needs to be set */
-		errorByte |= byteMask;
-	}
-
-	/* write back the value with the fixed bit */
-	datap[locWithinAPage * sizeof(uint32_t) + locWithinAWord] = errorByte;
-}
-
-/****************************************************************************
-*  nand_correct_page_bch - Routine to correct bit errors when reading NAND
-*
-*  PURPOSE:
-*     This routine reads the BCH registers to determine if there are any bit
-*     errors during the read of the last 512 bytes of data + ECC bytes.  If
-*     errors exists, the routine fixes it.
-*
-*  PARAMETERS:
-*     datap - Container that holds the 512 byte data
-*
-*  RETURNS:
-*     0 or greater = Number of errors corrected
-*                    (No errors are found or errors have been fixed)
-*    -1 = Error(s) cannot be fixed
-****************************************************************************/
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes)
-{
-	int numErrors;
-	int errorLocation;
-	int idx;
-	uint32_t regValue;
-
-	/* wait for read ECC to be valid */
-	regValue = nand_bcm_umi_bch_poll_read_ecc_calc();
-
-	/*
-	 * read the control status register to determine if there
-	 * are error'ed bits
-	 * see if errors are correctible
-	 */
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR) > 0) {
-		int i;
-
-		for (i = 0; i < numEccBytes; i++) {
-			if (readEccData[i] != 0xff) {
-				/* errors cannot be fixed, return -1 */
-				return -1;
-			}
-		}
-		/* If ECC is unprogrammed then we can't correct,
-		 * assume everything OK */
-		return 0;
-	}
-
-	if ((regValue & REG_UMI_BCH_CTRL_STATUS_CORR_ERR) == 0) {
-		/* no errors */
-		return 0;
-	}
-
-	/*
-	 * Fix errored bits by doing the following:
-	 * 1. Read the number of errors in the control and status register
-	 * 2. Read the error location registers that corresponds to the number
-	 *    of errors reported
-	 * 3. Invert the bit in the data
-	 */
-	numErrors = (regValue & REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR) >> 20;
-
-	for (idx = 0; idx < numErrors; idx++) {
-		errorLocation =
-		    REG_UMI_BCH_ERR_LOC_ADDR(idx) & REG_UMI_BCH_ERR_LOC_MASK;
-
-		/* Flip bit */
-		nand_bcm_umi_bch_ecc_flip_bit(datap, errorLocation);
-	}
-	/* Errors corrected */
-	return numErrors;
-}
-#endif
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
deleted file mode 100644
index 198b304..0000000
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ /dev/null
@@ -1,337 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#ifndef NAND_BCM_UMI_H
-#define NAND_BCM_UMI_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/reg_umi.h>
-#include <mach/reg_nand.h>
-#include <cfg_global.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
-#define NAND_ECC_BCH (CFG_GLOBAL_CHIP_REV > 0xA0)
-#else
-#define NAND_ECC_BCH 0
-#endif
-
-#define CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES	13
-
-#if NAND_ECC_BCH
-#ifdef BOOT0_BUILD
-#define NAND_ECC_NUM_BYTES 13
-#else
-#define NAND_ECC_NUM_BYTES CFG_GLOBAL_NAND_ECC_BCH_NUM_BYTES
-#endif
-#else
-#define NAND_ECC_NUM_BYTES 3
-#endif
-
-#define NAND_DATA_ACCESS_SIZE 512
-
-/* ---- Variable Externs ------------------------------------------ */
-/* ---- Function Prototypes --------------------------------------- */
-int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
-				  int numEccBytes);
-
-/* Check in device is ready */
-static inline int nand_bcm_umi_dev_ready(void)
-{
-	return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
-}
-
-/* Wait until device is ready */
-static inline void nand_bcm_umi_wait_till_ready(void)
-{
-	while (nand_bcm_umi_dev_ready() == 0)
-		;
-}
-
-/* Enable Hamming ECC */
-static inline void nand_bcm_umi_hamming_enable_hwecc(void)
-{
-	/* disable and reset ECC, 512 byte page */
-	REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
-		REG_UMI_NAND_ECC_CSR_256BYTE);
-	/* enable ECC */
-	REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
-}
-
-#if NAND_ECC_BCH
-/* BCH ECC specifics */
-#define ECC_BITS_PER_CORRECTABLE_BIT 13
-
-/* Enable BCH Read ECC */
-static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Enable BCH Write ECC */
-static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
-{
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
-	/* Turn on ECC */
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
-}
-
-/* Config number of BCH ECC bytes */
-static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
-{
-	uint32_t nValue;
-	uint32_t tValue;
-	uint32_t kValue;
-	uint32_t numBits = numEccBytes * 8;
-
-	/* disable and reset ECC */
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
-	    REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
-
-	/* Every correctible bit requires 13 ECC bits */
-	tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Total data in number of bits for generating and computing BCH ECC */
-	nValue = (NAND_DATA_ACCESS_SIZE + numEccBytes) * 8;
-
-	/* K parameter is used internally.  K = N - (T * 13) */
-	kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
-
-	/* Write the settings */
-	REG_UMI_BCH_N = nValue;
-	REG_UMI_BCH_T = tValue;
-	REG_UMI_BCH_K = kValue;
-}
-
-/* Pause during ECC read calculation to skip bytes in OOB */
-static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS =
-	    REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
-	    REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
-}
-
-/* Resume during ECC read calculation after skipping bytes in OOB */
-static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
-{
-	REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
-}
-
-/* Poll read ECC calc to check when hardware completes */
-static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
-{
-	uint32_t regVal;
-
-	do {
-		/* wait for ECC to be valid */
-		regVal = REG_UMI_BCH_CTRL_STATUS;
-	} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
-
-	return regVal;
-}
-
-/* Poll write ECC calc to check when hardware completes */
-static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
-{
-	/* wait for ECC to be valid */
-	while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
-	       == 0)
-		;
-}
-
-/* Read the OOB and ECC, for kernel write OOB to a buffer */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes, uint8_t *oobp)
-#else
-static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
-	uint8_t *eccCalc, int numEccBytes)
-#endif
-{
-	int eccPos = 0;
-	int numToRead = 16;	/* There are 16 bytes per sector in the OOB */
-
-	/* ECC is already paused when this function is called */
-	if (pageSize != NAND_DATA_ACCESS_SIZE) {
-		/* skip BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	while (numToRead > numEccBytes) {
-		/* skip free oob region */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp++ = REG_NAND_DATA8;
-#else
-		REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* read ECC bytes before BI */
-		nand_bcm_umi_bch_resume_read_ecc_calc();
-
-		while (numToRead > 11) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp = REG_NAND_DATA8;
-			eccCalc[eccPos++] = *oobp;
-			oobp++;
-#else
-			eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-		nand_bcm_umi_bch_pause_read_ecc_calc();
-
-		if (numToRead == 11) {
-			/* read BI */
-#if defined(__KERNEL__) && !defined(STANDALONE)
-			*oobp++ = REG_NAND_DATA8;
-#else
-			REG_NAND_DATA8;
-#endif
-			numToRead--;
-		}
-
-	}
-	/* read ECC bytes */
-	nand_bcm_umi_bch_resume_read_ecc_calc();
-	while (numToRead) {
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		*oobp = REG_NAND_DATA8;
-		eccCalc[eccPos++] = *oobp;
-		oobp++;
-#else
-		eccCalc[eccPos++] = REG_NAND_DATA8;
-#endif
-		numToRead--;
-	}
-}
-
-/* Helper function to write ECC */
-static inline void NAND_BCM_UMI_ECC_WRITE(int numEccBytes, int eccBytePos,
-					  uint8_t *oobp, uint8_t eccVal)
-{
-	if (eccBytePos <= numEccBytes)
-		*oobp = eccVal;
-}
-
-/* Write OOB with ECC */
-static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
-						 uint8_t *oobp, int numEccBytes)
-{
-	uint32_t eccVal = 0xffffffff;
-
-	/* wait for write ECC to be valid */
-	nand_bcm_umi_bch_poll_write_ecc_calc();
-
-	/*
-	 ** Get the hardware ecc from the 32-bit result registers.
-	 ** Read after 512 byte accesses. Format B3B2B1B0
-	 ** where B3 = ecc3, etc.
-	 */
-
-	if (pageSize == NAND_DATA_ACCESS_SIZE) {
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually we skip CM in oob[0,1] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[1],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[2,3,4] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[2],
-			eccVal & 0xff);	/* ECC 12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[4],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-
-		/* Always Skip BI in oob[5] */
-	} else {
-		/* Always Skip BI in oob[0] */
-
-		/* Now fill in the ECC bytes */
-		if (numEccBytes >= 13)
-			eccVal = REG_UMI_BCH_WR_ECC_3;
-
-		/* Usually skip CM in oob[1,2] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
-			(eccVal >> 16) & 0xff);
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 14, &oobp[2],
-			(eccVal >> 8) & 0xff);
-
-		/* Write ECC in oob[3-15] */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 13, &oobp[3],
-			eccVal & 0xff);	/* ECC12 */
-
-		if (numEccBytes >= 9)
-			eccVal = REG_UMI_BCH_WR_ECC_2;
-
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
-			(eccVal >> 24) & 0xff);	/* ECC11 */
-		NAND_BCM_UMI_ECC_WRITE(numEccBytes, 11, &oobp[5],
-			(eccVal >> 16) & 0xff);	/* ECC10 */
-	}
-
-	/* Fill in the remainder of ECC locations */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 10, &oobp[6],
-		(eccVal >> 8) & 0xff);	/* ECC9 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 9, &oobp[7],
-		eccVal & 0xff);	/* ECC8 */
-
-	if (numEccBytes >= 5)
-		eccVal = REG_UMI_BCH_WR_ECC_1;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
-		(eccVal >> 24) & 0xff);	/* ECC7 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 7, &oobp[9],
-		(eccVal >> 16) & 0xff);	/* ECC6 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 6, &oobp[10],
-		(eccVal >> 8) & 0xff);	/* ECC5 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 5, &oobp[11],
-		eccVal & 0xff);	/* ECC4 */
-
-	if (numEccBytes >= 1)
-		eccVal = REG_UMI_BCH_WR_ECC_0;
-
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
-		(eccVal >> 24) & 0xff);	/* ECC3 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 3, &oobp[13],
-		(eccVal >> 16) & 0xff);	/* ECC2 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 2, &oobp[14],
-		(eccVal >> 8) & 0xff);	/* ECC1 */
-	NAND_BCM_UMI_ECC_WRITE(numEccBytes, 1, &oobp[15],
-		eccVal & 0xff);	/* ECC0 */
-}
-#endif
-
-#endif /* NAND_BCM_UMI_H */
-- 
1.7.9.5




From csd at broadcom.com  Fri Sep 21 17:40:26 2012
From: csd at broadcom.com (Christian Daudt)
Date: Fri, 21 Sep 2012 14:40:26 -0700
Subject: [PATCH v3 2/2] ARM: Remove mach-bcmring
In-Reply-To: <1348263626-3087-1-git-send-email-csd@broadcom.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
Message-ID: <1348263626-3087-3-git-send-email-csd@broadcom.com>

Remove mach-bcmring as this is no longer maintained or used.

Signed-off-by: Christian Daudt <csd at broadcom.com>
Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
---
 MAINTAINERS                                        |    7 -
 arch/arm/Kconfig                                   |   14 -
 arch/arm/Makefile                                  |    1 -
 arch/arm/configs/bcmring_defconfig                 |   79 -
 arch/arm/mach-bcmring/Kconfig                      |   19 -
 arch/arm/mach-bcmring/Makefile                     |    8 -
 arch/arm/mach-bcmring/Makefile.boot                |    6 -
 arch/arm/mach-bcmring/arch.c                       |  199 ---
 arch/arm/mach-bcmring/clock.c                      |  223 ---
 arch/arm/mach-bcmring/clock.h                      |   33 -
 arch/arm/mach-bcmring/core.c                       |  228 ---
 arch/arm/mach-bcmring/core.h                       |   31 -
 arch/arm/mach-bcmring/csp/Makefile                 |    3 -
 arch/arm/mach-bcmring/csp/chipc/Makefile           |    1 -
 arch/arm/mach-bcmring/csp/chipc/chipcHw.c          |  776 ---------
 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c     |  293 ----
 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c    |  124 --
 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c      |   64 -
 arch/arm/mach-bcmring/csp/dmac/Makefile            |    1 -
 arch/arm/mach-bcmring/csp/dmac/dmacHw.c            |  917 -----------
 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c      | 1017 ------------
 arch/arm/mach-bcmring/csp/tmr/Makefile             |    1 -
 arch/arm/mach-bcmring/csp/tmr/tmrHw.c              |  576 -------
 arch/arm/mach-bcmring/dma.c                        | 1518 ------------------
 arch/arm/mach-bcmring/dma_device.c                 |  593 -------
 arch/arm/mach-bcmring/include/cfg_global.h         |   13 -
 arch/arm/mach-bcmring/include/cfg_global_defines.h |   40 -
 arch/arm/mach-bcmring/include/csp/cache.h          |   35 -
 arch/arm/mach-bcmring/include/csp/delay.h          |   36 -
 arch/arm/mach-bcmring/include/csp/dmacHw.h         |  596 -------
 arch/arm/mach-bcmring/include/csp/errno.h          |   32 -
 arch/arm/mach-bcmring/include/csp/intcHw.h         |   40 -
 arch/arm/mach-bcmring/include/csp/module.h         |   32 -
 arch/arm/mach-bcmring/include/csp/reg.h            |  114 --
 arch/arm/mach-bcmring/include/csp/secHw.h          |   65 -
 arch/arm/mach-bcmring/include/csp/stdint.h         |   30 -
 arch/arm/mach-bcmring/include/csp/string.h         |   34 -
 arch/arm/mach-bcmring/include/csp/tmrHw.h          |  263 ---
 arch/arm/mach-bcmring/include/mach/csp/cap.h       |   63 -
 .../arm/mach-bcmring/include/mach/csp/cap_inline.h |  409 -----
 .../mach-bcmring/include/mach/csp/chipcHw_def.h    | 1123 -------------
 .../mach-bcmring/include/mach/csp/chipcHw_inline.h | 1673 --------------------
 .../mach-bcmring/include/mach/csp/chipcHw_reg.h    |  530 -------
 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h   |  872 ----------
 .../mach-bcmring/include/mach/csp/dmacHw_priv.h    |  145 --
 .../arm/mach-bcmring/include/mach/csp/dmacHw_reg.h |  406 -----
 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h    |   73 -
 .../arm/mach-bcmring/include/mach/csp/intcHw_reg.h |  246 ---
 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h   |  101 --
 arch/arm/mach-bcmring/include/mach/csp/mm_io.h     |  147 --
 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h |  100 --
 .../mach-bcmring/include/mach/csp/secHw_inline.h   |   79 -
 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h |   82 -
 arch/arm/mach-bcmring/include/mach/dma.h           |  630 --------
 arch/arm/mach-bcmring/include/mach/entry-macro.S   |   76 -
 arch/arm/mach-bcmring/include/mach/hardware.h      |   57 -
 arch/arm/mach-bcmring/include/mach/irqs.h          |  132 --
 .../mach-bcmring/include/mach/memory_settings.h    |   67 -
 arch/arm/mach-bcmring/include/mach/reg_nand.h      |   66 -
 arch/arm/mach-bcmring/include/mach/reg_umi.h       |  237 ---
 arch/arm/mach-bcmring/include/mach/timer.h         |   77 -
 arch/arm/mach-bcmring/include/mach/timex.h         |   25 -
 arch/arm/mach-bcmring/include/mach/uncompress.h    |   43 -
 arch/arm/mach-bcmring/irq.c                        |  126 --
 arch/arm/mach-bcmring/mm.c                         |   60 -
 arch/arm/mach-bcmring/timer.c                      |   61 -
 66 files changed, 15768 deletions(-)
 delete mode 100644 arch/arm/configs/bcmring_defconfig
 delete mode 100644 arch/arm/mach-bcmring/Kconfig
 delete mode 100644 arch/arm/mach-bcmring/Makefile
 delete mode 100644 arch/arm/mach-bcmring/Makefile.boot
 delete mode 100644 arch/arm/mach-bcmring/arch.c
 delete mode 100644 arch/arm/mach-bcmring/clock.c
 delete mode 100644 arch/arm/mach-bcmring/clock.h
 delete mode 100644 arch/arm/mach-bcmring/core.c
 delete mode 100644 arch/arm/mach-bcmring/core.h
 delete mode 100644 arch/arm/mach-bcmring/csp/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
 delete mode 100644 arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw.c
 delete mode 100644 arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
 delete mode 100644 arch/arm/mach-bcmring/csp/tmr/Makefile
 delete mode 100644 arch/arm/mach-bcmring/csp/tmr/tmrHw.c
 delete mode 100644 arch/arm/mach-bcmring/dma.c
 delete mode 100644 arch/arm/mach-bcmring/dma_device.c
 delete mode 100644 arch/arm/mach-bcmring/include/cfg_global.h
 delete mode 100644 arch/arm/mach-bcmring/include/cfg_global_defines.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/cache.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/delay.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/dmacHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/errno.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/intcHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/module.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/secHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/stdint.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/string.h
 delete mode 100644 arch/arm/mach-bcmring/include/csp/tmrHw.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/mm_io.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/dma.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/entry-macro.S
 delete mode 100644 arch/arm/mach-bcmring/include/mach/hardware.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/irqs.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/memory_settings.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_nand.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/reg_umi.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/timer.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/timex.h
 delete mode 100644 arch/arm/mach-bcmring/include/mach/uncompress.h
 delete mode 100644 arch/arm/mach-bcmring/irq.c
 delete mode 100644 arch/arm/mach-bcmring/mm.c
 delete mode 100644 arch/arm/mach-bcmring/timer.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 36da5f9..a4b166c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -658,13 +658,6 @@ W:	http://www.linux4sam.org
 S:	Supported
 F:	arch/arm/mach-at91/
 
-ARM/BCMRING ARM ARCHITECTURE
-M:	Jiandong Zheng <jdzheng at broadcom.com>
-M:	Scott Branden <sbranden at broadcom.com>
-L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
-S:	Maintained
-F:	arch/arm/mach-bcmring
-
 ARM/CALXEDA HIGHBANK ARCHITECTURE
 M:	Rob Herring <rob.herring at calxeda.com>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c5f9ae5..e99177a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -350,18 +350,6 @@ config ARCH_AT91
 	  This enables support for systems based on Atmel
 	  AT91RM9200 and AT91SAM9* processors.
 
-config ARCH_BCMRING
-	bool "Broadcom BCMRING"
-	depends on MMU
-	select CPU_V6
-	select ARM_AMBA
-	select ARM_TIMER_SP804
-	select CLKDEV_LOOKUP
-	select GENERIC_CLOCKEVENTS
-	select ARCH_WANT_OPTIONAL_GPIOLIB
-	help
-	  Support for Broadcom's BCMRing platform.
-
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank-based"
 	select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -1031,8 +1019,6 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
 
-source "arch/arm/mach-bcmring/Kconfig"
-
 source "arch/arm/mach-clps711x/Kconfig"
 
 source "arch/arm/mach-cns3xxx/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..8383e2e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -136,7 +136,6 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)		:= at91
-machine-$(CONFIG_ARCH_BCMRING)		:= bcmring
 machine-$(CONFIG_ARCH_CLPS711X)		:= clps711x
 machine-$(CONFIG_ARCH_CNS3XXX)		:= cns3xxx
 machine-$(CONFIG_ARCH_DAVINCI)		:= davinci
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
deleted file mode 100644
index 9e6a8fe..0000000
--- a/arch/arm/configs/bcmring_defconfig
+++ /dev/null
@@ -1,79 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_EXPERT=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-# CONFIG_HOTPLUG is not set
-# CONFIG_ELF_CORE is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_TIMERFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_PERF_EVENTS=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_BCMRING=y
-CONFIG_BCM_ZRELADDR=0x8000
-CONFIG_CPU_32v6K=y
-CONFIG_NO_HZ=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_ZBOOT_ROM_TEXT=0x0e000000
-CONFIG_ZBOOT_ROM_BSS=0x0ea00000
-CONFIG_ZBOOT_ROM=y
-CONFIG_NET=y
-# CONFIG_WIRELESS is not set
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_CFI_I2 is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_BCM_UMI=y
-CONFIG_MTD_NAND_BCM_UMI_HWCS=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_LEGACY_PTY_COUNT=64
-# CONFIG_HW_RANDOM is not set
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-# CONFIG_JFFS2_FS_SECURITY is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_HEADERS_CHECK=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
deleted file mode 100644
index 9170d16..0000000
--- a/arch/arm/mach-bcmring/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-choice
-	prompt "Processor selection in BCMRING family of devices"
-	depends on ARCH_BCMRING
-	default ARCH_BCM11107
-
-config ARCH_FPGA11107
-	bool "FPGA11107"
-
-config ARCH_BCM11107
-	bool "BCM11107"
-endchoice
-
-menu "BCMRING Options"
-	depends on ARCH_BCMRING
-
-config BCM_ZRELADDR
-	hex "Compressed ZREL ADDR"
-
-endmenu
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
deleted file mode 100644
index f8d9fce..0000000
--- a/arch/arm/mach-bcmring/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
-obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
deleted file mode 100644
index aef2467..0000000
--- a/arch/arm/mach-bcmring/Makefile.boot
+++ /dev/null
@@ -1,6 +0,0 @@
-# Address where decompressor will be written and eventually executed.
-#
-# default to SDRAM
-zreladdr-y      += $(CONFIG_BCM_ZRELADDR)
-params_phys-y   := 0x00000800
-
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
deleted file mode 100644
index 45c97b1..0000000
--- a/arch/arm/mach-bcmring/arch.c
+++ /dev/null
@@ -1,199 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-
-#include <asm/irq.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/pmu.h>
-
-#include <asm/mach/arch.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <cfg_global.h>
-
-#include "core.h"
-
-HW_DECLARE_SPINLOCK(arch)
-HW_DECLARE_SPINLOCK(gpio)
-#if defined(CONFIG_DEBUG_SPINLOCK)
-    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
-#endif
-
-/* sysctl */
-static int bcmring_arch_warm_reboot;	/* do a warm reboot on hard reset */
-
-static void bcmring_restart(char mode, const char *cmd)
-{
-	printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
-
-	if (mode == 'h') {
-		/* Reboot configured in proc entry */
-		if (bcmring_arch_warm_reboot) {
-			printk("warm reset\n");
-			/* Issue Warm reset (do not reset ethernet switch, keep alive) */
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
-		} else {
-			/* Force reset of everything */
-			printk("force reset\n");
-			chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-	} else {
-		/* Force reset of everything */
-		printk("force reset\n");
-		chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-	}
-}
-
-static struct ctl_table_header *bcmring_sysctl_header;
-
-static struct ctl_table bcmring_sysctl_warm_reboot[] = {
-	{
-	 .procname = "warm",
-	 .data = &bcmring_arch_warm_reboot,
-	 .maxlen = sizeof(int),
-	 .mode = 0644,
-	 .proc_handler = proc_dointvec},
-	{}
-};
-
-static struct ctl_table bcmring_sysctl_reboot[] = {
-	{
-	 .procname = "reboot",
-	 .mode = 0555,
-	 .child = bcmring_sysctl_warm_reboot},
-	{}
-};
-
-static struct resource nand_resource[] = {
-	[0] = {
-		.start = MM_ADDR_IO_NAND,
-		.end = MM_ADDR_IO_NAND + 0x1000 - 1,
-		.flags = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device nand_device = {
-	.name = "bcm-nand",
-	.id = -1,
-	.resource = nand_resource,
-	.num_resources	= ARRAY_SIZE(nand_resource),
-};
-
-static struct resource pmu_resource = {
-	.start	= IRQ_PMUIRQ,
-	.end	= IRQ_PMUIRQ,
-	.flags	= IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
-	.resource	= &pmu_resource,
-	.num_resources	= 1,
-};
-
-
-static struct platform_device *devices[] __initdata = {
-	&nand_device,
-	&pmu_device,
-};
-
-/****************************************************************************
-*
-*   Called from the customize_machine function in arch/arm/kernel/setup.c
-*
-*   The customize_machine function is tagged as an arch_initcall
-*   (see include/linux/init.h for the order that the various init sections
-*   are called in.
-*
-*****************************************************************************/
-static void __init bcmring_init_machine(void)
-{
-
-	bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
-
-	/* Enable spread spectrum */
-	chipcHw_enableSpreadSpectrum();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	bcmring_amba_init();
-
-	dma_init();
-}
-
-/****************************************************************************
-*
-*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
-*   passed in by the boot loader.
-*
-*****************************************************************************/
-
-static void __init bcmring_fixup(struct tag *t, char **cmdline,
-	struct meminfo *mi) {
-#ifdef CONFIG_BLK_DEV_INITRD
-	printk(KERN_NOTICE "bcmring_fixup\n");
-	t->hdr.tag = ATAG_CORE;
-	t->hdr.size = tag_size(tag_core);
-	t->u.core.flags = 0;
-	t->u.core.pagesize = PAGE_SIZE;
-	t->u.core.rootdev = 31 << 8 | 0;
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_MEM;
-	t->hdr.size = tag_size(tag_mem32);
-	t->u.mem.start = CFG_GLOBAL_RAM_BASE;
-	t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
-
-	t = tag_next(t);
-
-	t->hdr.tag = ATAG_NONE;
-	t->hdr.size = 0;
-#endif
-}
-
-/****************************************************************************
-*
-*   Machine Description
-*
-*****************************************************************************/
-
-MACHINE_START(BCMRING, "BCMRING")
-	/* Maintainer: Broadcom Corporation */
-	.fixup = bcmring_fixup,
-	.map_io = bcmring_map_io,
-	.init_early = bcmring_init_early,
-	.init_irq = bcmring_init_irq,
-	.timer = &bcmring_timer,
-	.init_machine = bcmring_init_machine,
-	.restart = bcmring_restart,
-MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
deleted file mode 100644
index ad237a4..0000000
--- a/arch/arm/mach-bcmring/clock.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/clkdev.h>
-#include <mach/csp/hw_cfg.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include "clock.h"
-
-#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
-#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
-#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
-#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
-#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
-
-#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
-
-static DEFINE_SPINLOCK(clk_lock);
-
-static void __clk_enable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	/* enable parent clock first */
-	if (clk->parent)
-		__clk_enable(clk->parent);
-
-	if (clk->use_cnt++ == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Enable(clk->rate_hz, 0);
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Enable(clk->rate_hz);
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockEnable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockEnable(clk->csp_id);
-		}
-	}
-}
-
-int clk_enable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return -EINVAL;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_enable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
-	if (!clk)
-		return;
-
-	BUG_ON(clk->use_cnt == 0);
-
-	if (--clk->use_cnt == 0) {
-		if (clk_is_pll1(clk)) {	/* PLL1 */
-			chipcHw_pll1Disable();
-		} else if (clk_is_pll2(clk)) {	/* PLL2 */
-			chipcHw_pll2Disable();
-		} else if (clk_is_using_xtal(clk)) {	/* source is crystal */
-			if (!clk_is_primary(clk))
-				chipcHw_bypassClockDisable(clk->csp_id);
-		} else {	/* source is PLL */
-			chipcHw_setClockDisable(clk->csp_id);
-		}
-	}
-
-	if (clk->parent)
-		__clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
-	unsigned long flags;
-
-	if (!clk)
-		return;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	__clk_disable(clk);
-	spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
-	if (!clk)
-		return 0;
-
-	return clk->rate_hz;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return rate_hz;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned long flags;
-	unsigned long actual;
-	unsigned long rate_hz;
-
-	if (!clk)
-		return -EINVAL;
-
-	if (!clk_is_programmable(clk))
-		return -EINVAL;
-
-	if (clk->use_cnt)
-		return -EBUSY;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	actual = clk->parent->rate_hz;
-	rate_hz = min(actual, rate);
-	rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
-	clk->rate_hz = rate_hz;
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
-	if (!clk)
-		return NULL;
-
-	return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	unsigned long flags;
-	struct clk *old_parent;
-
-	if (!clk || !parent)
-		return -EINVAL;
-
-	if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
-		return -EINVAL;
-
-	/* if more than one user, parent is not allowed */
-	if (clk->use_cnt > 1)
-		return -EBUSY;
-
-	if (clk->parent == parent)
-		return 0;
-
-	spin_lock_irqsave(&clk_lock, flags);
-	old_parent = clk->parent;
-	clk->parent = parent;
-	if (clk_is_using_xtal(parent))
-		clk->mode |= CLK_MODE_XTAL;
-	else
-		clk->mode &= (~CLK_MODE_XTAL);
-
-	/* if clock is active */
-	if (clk->use_cnt != 0) {
-		clk->use_cnt--;
-		/* enable clock with the new parent */
-		__clk_enable(clk);
-		/* disable the old parent */
-		__clk_disable(old_parent);
-	}
-	spin_unlock_irqrestore(&clk_lock, flags);
-
-	return 0;
-}
-EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
deleted file mode 100644
index 5e0b981..0000000
--- a/arch/arm/mach-bcmring/clock.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/chipcHw_def.h>
-
-#define CLK_TYPE_PRIMARY         1	/* primary clock must NOT have a parent */
-#define CLK_TYPE_PLL1            2	/* PPL1 */
-#define CLK_TYPE_PLL2            4	/* PPL2 */
-#define CLK_TYPE_PROGRAMMABLE    8	/* programmable clock rate */
-#define CLK_TYPE_BYPASSABLE      16	/* parent can be changed */
-
-#define CLK_MODE_XTAL            1	/* clock source is from crystal */
-
-struct clk {
-	const char *name;	/* clock name */
-	unsigned int type;	/* clock type */
-	unsigned int mode;	/* current mode */
-	volatile int use_bypass;	/* indicate if it's in bypass mode */
-	chipcHw_CLOCK_e csp_id;	/* clock ID for CSP CHIPC */
-	unsigned long rate_hz;	/* clock rate in Hz */
-	unsigned int use_cnt;	/* usage count */
-	struct clk *parent;	/* parent clock */
-};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
deleted file mode 100644
index adbfb19..0000000
--- a/arch/arm/mach-bcmring/core.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- *  derived from linux/arch/arm/mach-versatile/core.c
- *  linux/arch/arm/mach-bcmring/core.c
- *
- *  Copyright (C) 1999 - 2003 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/amba/bus.h>
-#include <linux/clkdev.h>
-
-#include <mach/csp/mm_addr.h>
-#include <mach/hardware.h>
-#include <linux/io.h>
-#include <asm/irq.h>
-#include <asm/hardware/arm_timer.h>
-#include <asm/hardware/timer-sp.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <cfg_global.h>
-
-#include "clock.h"
-
-#include <csp/secHw.h>
-#include <mach/csp/secHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <mach/csp/tmrHw_reg.h>
-
-static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
-static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
-
-static struct clk pll1_clk = {
-	.name = "PLL1",
-	.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
-	.rate_hz = 2000000000,
-	.use_cnt = 7,
-};
-
-static struct clk uart_clk = {
-	.name = "UART",
-	.type = CLK_TYPE_PROGRAMMABLE,
-	.csp_id = chipcHw_CLOCK_UART,
-	.rate_hz = HW_CFG_UART_CLK_HZ,
-	.parent = &pll1_clk,
-};
-
-static struct clk dummy_apb_pclk = {
-	.name = "BUSCLK",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-};
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-static struct clk sp804_timer012_clk = {
-	.name = "sp804-timer-0,1,2",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
-};
-
-static struct clk sp804_timer3_clk = {
-	.name = "sp804-timer-3",
-	.type = CLK_TYPE_PRIMARY,
-	.mode = CLK_MODE_XTAL,
-	.rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
-};
-
-static struct clk_lookup lookups[] = {
-	{			/* Bus clock */
-		.con_id = "apb_pclk",
-		.clk = &dummy_apb_pclk,
-	}, {			/* UART0 */
-		.dev_id = "uarta",
-		.clk = &uart_clk,
-	}, {			/* UART1 */
-		.dev_id = "uartb",
-		.clk = &uart_clk,
-	}, {			/* SP804 timer 0 */
-		.dev_id = "sp804",
-		.con_id = "timer0",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 1 */
-		.dev_id = "sp804",
-		.con_id = "timer1",
-		.clk = &sp804_timer012_clk,
-	}, {			/* SP804 timer 3 */
-		.dev_id = "sp804",
-		.con_id = "timer3",
-		.clk = &sp804_timer3_clk,
-	}
-};
-
-static struct amba_device *amba_devs[] __initdata = {
-	&uartA_device,
-	&uartB_device,
-};
-
-void __init bcmring_amba_init(void)
-{
-	int i;
-	u32 bus_clock;
-
-/* Linux is run initially in non-secure mode. Secure peripherals */
-/* generate FIQ, and must be handled in secure mode. Until we have */
-/* a linux security monitor implementation, keep everything in */
-/* non-secure mode. */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
-	secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
-			  secHw_BLK_MASK_KEY_SCAN |
-			  secHw_BLK_MASK_TOUCH_SCREEN |
-			  secHw_BLK_MASK_UART0 |
-			  secHw_BLK_MASK_UART1 |
-			  secHw_BLK_MASK_WATCHDOG |
-			  secHw_BLK_MASK_SPUM |
-			  secHw_BLK_MASK_DDR2 |
-			  secHw_BLK_MASK_SPU |
-			  secHw_BLK_MASK_PKA |
-			  secHw_BLK_MASK_RNG |
-			  secHw_BLK_MASK_RTC |
-			  secHw_BLK_MASK_OTP |
-			  secHw_BLK_MASK_BOOT |
-			  secHw_BLK_MASK_MPU |
-			  secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
-
-	/* Only the devices attached to the AMBA bus are enabled just before the bus is */
-	/* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
-	/* driver to access these blocks. The bus is probed, and the drivers are loaded. */
-	/* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
-	bus_clock = chipcHw_REG_BUS_CLOCK_GE
-	    | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
-
-	chipcHw_busInterfaceClockEnable(bus_clock);
-
-	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
-		struct amba_device *d = amba_devs[i];
-		amba_device_register(d, &iomem_resource);
-	}
-}
-
-/*
- * Where is the timer (VA)?
- */
-#define TIMER0_VA_BASE		((void __iomem *)MM_IO_BASE_TMR)
-#define TIMER1_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x20))
-#define TIMER2_VA_BASE		((void __iomem *)(MM_IO_BASE_TMR + 0x40))
-#define TIMER3_VA_BASE          ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
-
-static int __init bcmring_clocksource_init(void)
-{
-	/* setup timer1 as free-running clocksource */
-	sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
-
-	/* setup timer3 as free-running clocksource */
-	sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
-
-	return 0;
-}
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-void __init bcmring_init_timer(void)
-{
-	printk(KERN_INFO "bcmring_init_timer\n");
-	/*
-	 * Initialise to a known state (all timers off)
-	 */
-	writel(0, TIMER0_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER1_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER2_VA_BASE + TIMER_CTRL);
-	writel(0, TIMER3_VA_BASE + TIMER_CTRL);
-
-	/*
-	 * Make irqs happen for the system timer
-	 */
-	bcmring_clocksource_init();
-
-	sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
-}
-
-struct sys_timer bcmring_timer = {
-	.init = bcmring_init_timer,
-};
-
-void __init bcmring_init_early(void)
-{
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
deleted file mode 100644
index e0e02c4..0000000
--- a/arch/arm/mach-bcmring/core.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- *  linux/arch/arm/mach-versatile/core.h
- *
- *  Copyright (C) 2004 ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Portions copyright Broadcom 2008 */
-#ifndef __ASM_ARCH_BCMRING_H
-#define __ASM_ARCH_BCMRING_H
-
-void __init bcmring_amba_init(void);
-void __init bcmring_map_io(void);
-void __init bcmring_init_irq(void);
-void __init bcmring_init_early(void);
-
-extern struct sys_timer bcmring_timer;
-#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
deleted file mode 100644
index 648c037..0000000
--- a/arch/arm/mach-bcmring/csp/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += dmac/
-obj-y += tmr/
-obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
deleted file mode 100644
index 6739527..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
deleted file mode 100644
index 96273ff..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw.c
-*
-*  @brief   Low level Various CHIP clock controlling routines
-*
-*  @note
-*
-*   These routines provide basic clock controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-
-/* VPM alignment algorithm uses this */
-#define MAX_PHASE_ADJUST_COUNT         0xFFFF	/* Max number of times allowed to adjust the phase */
-#define MAX_PHASE_ALIGN_ATTEMPTS       10	/* Max number of attempt to align the phase */
-
-/* Local definition of clock type */
-#define PLL_CLOCK                      1	/* PLL Clock */
-#define NON_PLL_CLOCK                  2	/* Divider clock */
-
-static int chipcHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in hertz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-	} else {
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz =
-	    chipcHw_XTAL_FREQ_Hz *
-		 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Obtain PLL clock frequency */
-		if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (clock == chipcHw_CLOCK_DDR) {
-			/* DDR frequency is configured in PLLDivider register */
-			return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				vcoHz >>= 1;
-			}
-			/* Obtain PLL clock frequency using VCO dividers */
-			return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-	} else if (pClockCtrl) {
-		/* Obtain divider clock frequency */
-		uint32_t div;
-		uint32_t freq = 0;
-
-		if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-			/* Return crystal clock frequency when bypassed */
-			return chipcHw_XTAL_FREQ_Hz;
-		} else if (pDependentClock) {
-			/* Identify the dependent clock frequency */
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
-					/* Use crystal clock frequency when dependent PLL clock is bypassed */
-					freq = chipcHw_XTAL_FREQ_Hz;
-				} else {
-					/* Obtain PLL clock frequency using VCO dividers */
-					div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
-					freq = div ? chipcHw_divide(vcoHz, div) : 0;
-				}
-				break;
-			case NON_PLL_CLOCK:
-				if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-					freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-				} else {
-					if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
-						/* Use crystal clock frequency when dependent divider clock is bypassed */
-						freq = chipcHw_XTAL_FREQ_Hz;
-					} else {
-						/* Obtain divider clock frequency using XTAL dividers */
-						div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
-					}
-				}
-				break;
-			}
-		} else {
-			/* Dependent on crystal clock */
-			freq = chipcHw_XTAL_FREQ_Hz;
-		}
-
-		div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-		return chipcHw_divide(freq, (div ? div : 256));
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) {
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-	volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
-	uint32_t vcoFreqPll1Hz = 0;	/* Effective VCO frequency for PLL1 in Hz */
-	uint32_t desVcoFreqPll1Hz = 0;	/* Desired VCO frequency for PLL1 in Hz */
-	uint32_t vcoFreqPll2Hz = 0;	/* Effective VCO frequency for PLL2 in Hz */
-	uint32_t dependentClockType = 0;
-	uint32_t vcoHz = 0;
-	uint32_t desVcoHz = 0;
-
-	/* Get VCO frequencies */
-	if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		uint64_t adjustFreq = 0;
-
-		vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-		/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
-		adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
-			(uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
-			chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
-		vcoFreqPll1Hz += (uint32_t) adjustFreq;
-
-		/* Desired VCO frequency */
-		desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
-	} else {
-		vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
-		    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-		    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-	}
-	vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
-	    ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
-	     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		/* Configure the DDR_ctrl:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
-			pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->DDRClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_VPM:
-		/* Configure the VPM:BUS ratio settings */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
-				<< chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-		pPLLReg = &pChipcHw->VPMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		pDependentClock = &pChipcHw->ARMClock;
-		vcoHz = vcoFreqPll1Hz;
-		desVcoHz = desVcoFreqPll1Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		pDependentClock = &pChipcHw->ACLKClock;
-		dependentClockType = NON_PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		pDependentClock = &pChipcHw->APMClock;
-		vcoHz = vcoFreqPll2Hz;
-		desVcoHz = vcoFreqPll2Hz;
-		dependentClockType = PLL_CLOCK;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		/* Select XTAL as bypass source */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
-		reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* For DDR settings use only the PLL divider clock */
-		if (pPLLReg == &pChipcHw->DDRClock) {
-			/* Set M1DIV for PLL1, which controls the DDR clock */
-			reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
-		} else {
-			/* From chip revision number B0, LCD clock is internally divided by 2 */
-			if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
-				desVcoHz >>= 1;
-				vcoHz >>= 1;
-			}
-			/* Set MDIV to change the frequency */
-			reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
-			reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
-			/* Calculate expected frequency */
-			freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
-		}
-		/* Wait for for atleast 200ns as per the protocol to change frequency */
-		udelay(1);
-		/* Do not bypass */
-		reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-		/* Return the configured frequency */
-		return freq;
-	} else if (pClockCtrl) {
-		uint32_t divider = 0;
-
-		/* Divider clock should not be bypassed  */
-		reg32_modify_and(pClockCtrl,
-				 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-
-		/* Identify the clock source */
-		if (pDependentClock) {
-			switch (dependentClockType) {
-			case PLL_CLOCK:
-				divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
-				break;
-			case NON_PLL_CLOCK:
-				{
-					uint32_t sourceClock = 0;
-
-					if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
-						sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
-					} else {
-						uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
-						sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
-					}
-					divider = chipcHw_divide(sourceClock, freq);
-				}
-				break;
-			}
-		} else {
-			divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
-		}
-
-		if (divider) {
-			REG_LOCAL_IRQ_SAVE;
-			/* Set the divider to obtain the required frequency */
-			*pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
-			REG_LOCAL_IRQ_RESTORE;
-			return freq;
-		}
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(chipcHw_setClockFrequency);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-static int vpmPhaseAlignA0(void)
-{
-	uint32_t phaseControl;
-	uint32_t phaseValue;
-	uint32_t prevPhaseComp;
-	int iter = 0;
-	int adjustCount = 0;
-	int count = 0;
-
-	for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
-		phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
-		phaseValue = 0;
-		prevPhaseComp = 0;
-
-		/* Step 1: Look for falling PH_COMP transition */
-
-		/* Read the contents of VPM Clock resgister */
-		phaseValue = pChipcHw->VPMClock;
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) ||	/* Look for a transition */
-			  ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&	/* Look for a falling edge */
-			 (adjustCount < MAX_PHASE_ADJUST_COUNT)	/* Do not exceed the limit while trying */
-		    );
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		/* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
-
-		for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl + 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 5) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
-
-		for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if (count != 3) {
-			/* Detected noisy transition */
-			continue;
-		}
-
-		/* Step 4: Keep moving backward before the original transition took place. */
-
-		for (count = 0; (count < 5); count++) {
-			phaseControl = (0x3F & (phaseControl - 1));
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			phaseValue = pChipcHw->VPMClock;
-			/* Count number of adjustment made */
-			adjustCount++;
-		}
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
-			return -1;
-		}
-
-		if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
-			/* Detected false transition */
-			continue;
-		}
-
-		/* Step 5: Re discover the valid transition */
-
-		do {
-			/* Store previous value of phase comparator */
-			prevPhaseComp = phaseValue;
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^=
-			    chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Read the contents of  VPM Clock resgister. */
-			phaseValue = pChipcHw->VPMClock;
-
-			if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
-				phaseControl = (0x3F & (phaseControl - 1));
-			} else {
-				/* Increment to the Phase count value for next write, if Phase is not stable. */
-				phaseControl = (0x3F & (phaseControl + 1));
-			}
-
-			/* Count number of adjustment made */
-			adjustCount++;
-		} while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
-
-		if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
-			/* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
-			return -1;
-		} else {
-			/* Valid phase must have detected */
-			break;
-		}
-	}
-
-	/* For VPM Phase should be perfectly aligned. */
-	phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
-		/* Load new phase value */
-		pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-	/* Return the status */
-	return (int)adjustCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success (# of adjustment required)
-*            -1 : On failure
-*
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void)
-{
-
-	if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
-		return vpmPhaseAlignA0();
-	} else {
-		uint32_t phaseControl = chipcHw_getVpmPhaseControl();
-		uint32_t phaseValue = 0;
-		int adjustCount = 0;
-
-		/* Disable VPM access */
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-		/* Disable HW VPM phase alignment  */
-		chipcHw_vpmHwPhaseAlignDisable();
-		/* Enable SW VPM phase alignment  */
-		chipcHw_vpmSwPhaseAlignEnable();
-		/* Adjust VPM phase */
-		while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
-			phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
-
-			/* Adjust phase control value */
-			if (phaseValue > 0xF) {
-				/* Increment phase control value */
-				phaseControl++;
-			} else if (phaseValue < 0xF) {
-				/* Decrement phase control value */
-				phaseControl--;
-			} else {
-				/* Enable VPM access */
-				pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-				/* Return adjust count */
-				return adjustCount;
-			}
-			/* Change the value of PH_CTRL. */
-			reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
-			/* Wait atleast 20 ns */
-			udelay(1);
-			/* Toggle the LOAD_CH after phase control is written. */
-			pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
-			/* Count adjustment */
-			adjustCount++;
-		}
-	}
-
-	/* Disable VPM access */
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
-	return -1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int chipcHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
deleted file mode 100644
index 367df75..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_init.c
-*
-*  @brief   Low level CHIPC PLL configuration functions
-*
-*  @note
-*
-*   These routines provide basic PLL controlling functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
-
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-
-#include <csp/reg.h>
-#include <csp/delay.h>
-/* ---- Private Constants and Types --------------------------------------- */
-
-/*
-    Calculation for NDIV_i to obtain VCO frequency
-    -----------------------------------------------
-
-	Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
-	for Freq_vco = VCO_FREQ_MHz
-		Freq_ref = chipcHw_XTAL_FREQ_Hz
-		PLL_P1 = PLL_P2 = 1
-		and
-		PLL_NDIV_f = 0
-
-	We get:
-		PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
-
-    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
-    -----------------------------------------------------------------
-		Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
-
-		PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
-*/
-
-/* ---- Private Variables ------------------------------------------------- */
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL2
-*
-*  This function initializes the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz)
-{
-	uint32_t pllPreDivider2 = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		pChipcHw->PLLConfig2 =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-
-		pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-		    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-		    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-		     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-		    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-		     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider2 = pllPreDivider2;
-		/* Set NDIV Frac */
-		pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
-
-		/* This has to be removed once the default values are fixed for PLL2. */
-		pChipcHw->PLLControl12 = 0x38000700;
-		pChipcHw->PLLControl22 = 0x00000015;
-
-		/* Reset PLL2 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-		REG_LOCAL_IRQ_RESTORE;
-	}
-
-	/* Insert certain amount of delay before deasserting ARESET. */
-	udelay(1);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove analog reset and Power on the PLL */
-		pChipcHw->PLLConfig2 &=
-		    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-		      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-
-		REG_LOCAL_IRQ_RESTORE;
-
-	}
-
-	/* Wait until PLL is locked */
-	while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-		;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		/* Remove digital reset */
-		pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll2Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the PLL1
-*
-*  This function initializes the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
-{
-	uint32_t pllPreDivider = 0;
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->PLLConfig =
-		    chipcHw_REG_PLL_CONFIG_D_RESET |
-		    chipcHw_REG_PLL_CONFIG_A_RESET;
-		/* Setting VCO frequency */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pllPreDivider =
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
-			    ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
-			      1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		} else {
-			pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
-			    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
-			    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
-			     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
-			    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
-			     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
-		}
-
-		/* Enable CHIPC registers to control the PLL */
-		pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
-
-		/* Set pre divider to get desired VCO frequency */
-		pChipcHw->PLLPreDivider = pllPreDivider;
-		/* Set NDIV Frac */
-		if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
-		} else {
-			pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
-			    chipcHw_REG_PLL_DIVIDER_NDIV_f;
-		}
-
-		/* Reset PLL1 */
-		if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		} else {
-			pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
-			    chipcHw_REG_PLL_CONFIG_A_RESET |
-			    chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
-			    chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-		}
-
-		REG_LOCAL_IRQ_RESTORE;
-
-		/* Insert certain amount of delay before deasserting ARESET. */
-		udelay(1);
-
-		{
-			REG_LOCAL_IRQ_SAVE;
-			/* Remove analog reset and Power on the PLL */
-			pChipcHw->PLLConfig &=
-			    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
-			      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
-			REG_LOCAL_IRQ_RESTORE;
-		}
-
-		/* Wait until PLL is locked */
-		while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
-		       || !(pChipcHw->
-			    PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
-			;
-
-		/* Remove digital reset */
-		{
-			REG_LOCAL_IRQ_SAVE;
-			pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
-			REG_LOCAL_IRQ_RESTORE;
-		}
-	}
-}
-
-EXPORT_SYMBOL(chipcHw_pll1Enable);
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the chipc module
-*
-*  This function initializes the PLLs and core system clocks
-*
-*/
-/****************************************************************************/
-
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip initialization parameter */
-    ) {
-#if !(defined(__KERNEL__) && !defined(STANDALONE))
-	delay_init();
-#endif
-
-	/* Do not program PLL, when warm reset */
-	if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
-		chipcHw_pll1Enable(initParam->pllVcoFreqHz,
-				   initParam->ssSupport);
-		chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
-	} else {
-		/* Clear sticky bits */
-		chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
-	}
-	/* Clear sticky bits */
-	chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
-
-	/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
-	pChipcHw->ACLKClock =
-	    (pChipcHw->
-	     ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
-								 armBusRatio &
-								 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
-
-	/* Set various core component frequencies. The order in which this is done is important for some. */
-	/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
-	/* frequency to find its ratio with the BUS.  Hence we must set the ARM first, followed by the BUS,  */
-	/* then VPM and RTBUS. */
-
-	chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
-				  initParam->busClockFreqHz *
-				  initParam->armBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
-				  initParam->busClockFreqHz *
-				  initParam->vpmBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
-				  initParam->busClockFreqHz *
-				  initParam->ddrBusRatio);
-	chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
-				  initParam->busClockFreqHz / 2);
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
deleted file mode 100644
index 2671d88..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <mach/csp/chipcHw_def.h>
-#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-/* ---- Private Variables ------------------------------------------------- */
-void chipcHw_reset_run_from_aram(void);
-
-typedef void (*RUNFUNC) (void);
-
-/****************************************************************************/
-/**
-*  @brief   warmReset
-*
-*  @note warmReset configures the clocks which are not reset back to the state
-*   required to execute on reset.  To do so we need to copy the code into internal
-*   memory to change the ARM clock while we are not executing from DDR.
-*/
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask)
-{
-	int i = 0;
-	RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
-
-	/* Disable all interrupts */
-	intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
-	intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
-	intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-		if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
-			chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
-		}
-		/* Bypass the PLL clocks before reboot */
-		pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-		pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
-
-		/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
-		do {
-			((uint32_t *) MM_IO_BASE_ARAM)[i] =
-			    ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
-			i++;
-		} while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);	/* 0xe1a0f00f == asm ("mov r15, r15"); */
-
-		CSP_CACHE_FLUSH_ALL;
-
-		/* run the function from ARAM */
-		runFunc();
-
-		/* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/* This function must run from internal memory */
-void chipcHw_reset_run_from_aram(void)
-{
-/* Make sure, pipeline is filled with instructions coming from ARAM */
-__asm (" nop                                                            \n\t"
-		" nop                                                            \n\t"
-#if defined(__KERNEL__) && !defined(STANDALONE)
-		" MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" BIC      r0,r0,#0xd                                            \n\t"
-		" MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-#endif
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Bypass the ARM clock and switch to XTAL clock */
-		" MOV      r2,#0x80000000                                        \n\t"
-		" LDR      r3,[r2,#8]                                            \n\t"
-		" ORR      r3,r3,#0x20000                                        \n\t"
-		" STR      r3,[r2,#8]                                            \n\t"
-
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-		" nop                                                            \n\t"
-/* Issue reset */
-		" MOV      r3,#0x2                                               \n\t"
-		" STR      r3,[r2,#0x80]                                         \n\t"
-/* End here */
-		" MOV      pc,pc                                                 \n\t");
-/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
-}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
deleted file mode 100644
index 54ad964..0000000
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*****************************************************************************
-* Copyright 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-/****************************************************************************/
-/**
-*  @file    chipcHw_str.c
-*
-*  @brief   Contains strings which are useful to linux and csp
-*
-*  @note
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-
-static const char *gMuxStr[] = {
-	"GPIO",			/* 0 */
-	"KeyPad",		/* 1 */
-	"I2C-Host",		/* 2 */
-	"SPI",			/* 3 */
-	"Uart",			/* 4 */
-	"LED-Mtx-P",		/* 5 */
-	"LED-Mtx-S",		/* 6 */
-	"SDIO-0",		/* 7 */
-	"SDIO-1",		/* 8 */
-	"PCM",			/* 9 */
-	"I2S",			/* 10 */
-	"ETM",			/* 11 */
-	"Debug",		/* 12 */
-	"Misc",			/* 13 */
-	"0xE",			/* 14 */
-	"0xF",			/* 15 */
-};
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin)
-{
-	if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
-		return "";
-	}
-
-	return gMuxStr[chipcHw_getGpioPinFunction(pin)];
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
deleted file mode 100644
index fb1104f..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += dmacHw.o dmacHw_extra.o
\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
deleted file mode 100644
index 6b9be2e..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ /dev/null
@@ -1,917 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.c
-*
-*  @brief   Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-#include <mach/csp/chipcHw_inline.h>
-
-/* ---- External Function Prototypes ------------------------------------- */
-
-/* Allocate DMA control blocks */
-dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
-
-uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
-uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
-
-/****************************************************************************/
-/**
-*  @brief   Get maximum FIFO for a DMA channel
-*
-*  @return  Maximum allowable FIFO size
-*
-*
-*/
-/****************************************************************************/
-static uint32_t GetFifoSize(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	uint32_t val = 0;
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_MISC_t *pMiscReg =
-	    (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
-
-	switch (pCblk->channel) {
-	case 0:
-		val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
-		break;
-	case 1:
-		val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
-		break;
-	case 2:
-		val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
-		break;
-	case 3:
-		val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
-		break;
-	case 4:
-		val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
-		break;
-	case 5:
-		val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
-		break;
-	case 6:
-		val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
-		break;
-	case 7:
-		val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
-		break;
-	}
-
-	if (val <= 0x4) {
-		return 8 << val;
-	} else {
-		dmacHw_ASSERT(0);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pProg;
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Not safe yet to program the channel */
-		return;
-	}
-
-	if (pCblk->varDataStarted) {
-		if (pCblk->descUpdated) {
-			pCblk->descUpdated = 0;
-			pProg =
-			    (dmacHw_DESC_t *) ((uint32_t)
-					       dmacHw_REG_LLP(pCblk->module,
-							      pCblk->channel) +
-					       pRing->virt2PhyOffset);
-
-			/* Load descriptor if not loaded */
-			if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
-				dmacHw_SET_SAR(pCblk->module, pCblk->channel,
-					       pProg->sar);
-				dmacHw_SET_DAR(pCblk->module, pCblk->channel,
-					       pProg->dar);
-				dmacHw_REG_CTL_LO(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.lo;
-				dmacHw_REG_CTL_HI(pCblk->module,
-						  pCblk->channel) =
-				    pProg->ctl.hi;
-			} else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
-				/* Return as end descriptor is processed */
-				return;
-			} else {
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			return;
-		}
-	} else {
-		if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
-			/* Do not make a single chain, rather process one descriptor at a time */
-			pProg = pRing->pHead;
-			/* Point to the next descriptor for next iteration */
-			dmacHw_NEXT_DESC(pRing, pHead);
-		} else {
-			/* Return if no more pending descriptor */
-			if (pRing->pEnd == NULL) {
-				return;
-			}
-
-			pProg = pRing->pProg;
-			if (pConfig->transferMode ==
-			    dmacHw_TRANSFER_MODE_CONTINUOUS) {
-				/* Make sure a complete ring can be formed */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
-					      llp == pRing->pProg);
-				/* Make sure pProg pointing to the pHead */
-				dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
-					      pRing->pHead);
-				/* Make a complete ring */
-				do {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				} while (pRing->pProg != pRing->pHead);
-			} else {
-				/* Make a single long chain */
-				while (pRing->pProg != pRing->pEnd) {
-					pRing->pProg->ctl.lo |=
-					    (dmacHw_REG_CTL_LLP_DST_EN |
-					     dmacHw_REG_CTL_LLP_SRC_EN);
-					pRing->pProg =
-					    (dmacHw_DESC_t *) pRing->pProg->llp;
-				}
-			}
-		}
-
-		/* Program the channel registers */
-		dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
-		dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
-		    pProg->ctl.lo;
-		dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
-		    pProg->ctl.hi;
-		if (pRing->pEnd) {
-			/* Remember the descriptor to use next */
-			pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
-		}
-		/* Indicate no more pending descriptor  */
-		pRing->pEnd = (dmacHw_DESC_t *) NULL;
-	}
-	/* Start DMA operation */
-	dmacHw_DMA_START(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void)
-{
-
-	uint32_t i = 0;
-
-	dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
-	dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
-
-	/* Enable access to the DMA block */
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
-
-	if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
-		dmacHw_ASSERT(0);
-	}
-
-	memset((void *)dmacHw_gCblk, 0,
-	       sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
-	for (i = 0; i < dmaChannelCount_0; i++) {
-		dmacHw_gCblk[i].module = 0;
-		dmacHw_gCblk[i].channel = i;
-	}
-	for (i = 0; i < dmaChannelCount_1; i++) {
-		dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
-		dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void)
-{
-	/* Disable access to the DMA block */
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
-	chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] DMA Channel Id */
-    ) {
-	int idx;
-
-	switch ((channelId >> 8)) {
-	case 0:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
-		idx = (channelId & 0xff);
-		break;
-	case 1:
-		dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
-		idx = dmaChannelCount_0 + (channelId & 0xff);
-		break;
-	default:
-		dmacHw_ASSERT(0);
-		return (dmacHw_HANDLE_t) -1;
-	}
-
-	return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	int module = pCblk->module;
-	int channel = pCblk->channel;
-
-	/* Reinitialize the control block */
-	memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
-	pCblk->module = module;
-	pCblk->channel = channel;
-
-	/* Enable DMA controller */
-	dmacHw_DMA_ENABLE(pCblk->module);
-	/* Reset DMA channel */
-	dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
-	dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Mask event specific interrupts */
-	dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/* [ IN ] Number of descriptor in the ring */
-    ) {
-	/* Need extra 4 byte to ensure 32 bit alignment  */
-	return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
-		sizeof(uint32_t);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
-*       accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    ) {
-	uint32_t i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	/* Check the alignment of the descriptor */
-	if ((uint32_t) pDescriptorVirt & 0x00000003) {
-		dmacHw_ASSERT(0);
-		return -1;
-	}
-
-	/* Check if enough space has been allocated for descriptor ring */
-	if (len < dmacHw_descriptorLen(num)) {
-		return -1;
-	}
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
-	pRing->pHead =
-	    (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-	/* Initialize link item chain, starting from the head */
-	pDesc = pRing->pHead;
-	/* Find the offset between virtual to physical address */
-	pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
-
-	/* Form the descriptor ring */
-	for (i = 0; i < num - 1; i++) {
-		/* Clear link list item */
-		memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-		/* Point to the next item in the physical address */
-		pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
-		/* Point to the next item in the virtual address */
-		pDesc->llp = (uint32_t) (pDesc + 1);
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-
-	/* Clear last link list item */
-	memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
-	/* Last item pointing to the first item in the
-	   physical address to complete the ring */
-	pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
-	/* Last item pointing to the first item in the
-	   virtual address to complete the ring
-	 */
-	pDesc->llp = (uint32_t) pRing->pHead;
-	/* Mark descriptor is ready to use */
-	pDesc->ctl.hi = dmacHw_DESC_FREE;
-	/* Set the number of descriptors in the ring */
-	pRing->num = num;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	uint32_t cfgHigh = 0;
-	int srcTrSize;
-	int dstTrSize;
-
-	pCblk->varDataStarted = 0;
-	pCblk->userData = NULL;
-
-	/* Configure
-	   - Burst transaction when enough data in available in FIFO
-	   - AHB Access protection 1
-	   - Source and destination peripheral ports
-	 */
-	cfgHigh =
-	    dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
-	    dmacHw_SRC_PERI_INTF(pConfig->
-				 srcPeripheralPort) |
-	    dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
-	/* Set priority */
-	dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
-				    pConfig->channelPriority);
-
-	if (pConfig->dstStatusRegisterAddress != 0) {
-		/* Destination status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
-		/* Configure status registers */
-		dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->dstStatusRegisterAddress);
-	}
-
-	if (pConfig->srcStatusRegisterAddress != 0) {
-		/* Source status update enable */
-		cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
-		/* Source status update enable */
-		dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
-				   pConfig->srcStatusRegisterAddress);
-	}
-	/* Configure the config high register */
-	dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
-
-	/* Clear all raw interrupt status */
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-
-	/* Configure block interrupt */
-	if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure complete transfer interrupt */
-	if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure error interrupt */
-	if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
-		dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
-	} else {
-		dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
-	}
-	/* Configure gather register */
-	if (pConfig->srcGatherWidth) {
-		srcTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-		if (!
-		    ((pConfig->srcGatherWidth % srcTrSize)
-		     && (pConfig->srcGatherJump % srcTrSize))) {
-			dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->srcGatherWidth /
-			      srcTrSize) << 20) | (pConfig->srcGatherJump /
-						   srcTrSize);
-		} else {
-			return -1;
-		}
-	}
-	/* Configure scatter register */
-	if (pConfig->dstScatterWidth) {
-		dstTrSize =
-		    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-		if (!
-		    ((pConfig->dstScatterWidth % dstTrSize)
-		     && (pConfig->dstScatterJump % dstTrSize))) {
-			dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
-			    ((pConfig->dstScatterWidth /
-			      dstTrSize) << 20) | (pConfig->dstScatterJump /
-						   dstTrSize);
-		} else {
-			return -1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_BUSY;
-	} else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
-		   (0x00000001 << pCblk->channel)) {
-		return dmacHw_TRANSFER_STATUS_ERROR;
-	}
-
-	return dmacHw_TRANSFER_STATUS_DONE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			     void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) address */
-			     size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-	dmacHw_DESC_t *pProg;
-	int srcTs = 0;
-	int blkTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int count = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if ((pConfig->srcGatherWidth % srcTrSize)
-	    || (pConfig->dstScatterWidth % dstTrSize)) {
-		return -2;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination addresses are
-	   not properly aligned with the channel's transaction width. So, for successful
-	   DMA transfer, transaction width must be set according to the alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	/* Check the availability of "descCount" discriptors in the ring */
-	pProg = pRing->pHead;
-	for (count = 0; (descCount <= pRing->num) && (count < descCount);
-	     count++) {
-		if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
-			/* Sufficient descriptors are not available */
-			return -3;
-		}
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	}
-
-	/* Remember the link list item to program the channel registers */
-	pStart = pProg = pRing->pHead;
-	/* Make a link list with "descCount(=count)" number of descriptors */
-	while (count) {
-		/* Reset channel control information */
-		pProg->ctl.lo = 0;
-		/* Enable source gather if configured */
-		if (pConfig->srcGatherWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
-		}
-		/* Enable destination scatter if configured */
-		if (pConfig->dstScatterWidth) {
-			pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
-		}
-		/* Set source and destination address */
-		pProg->sar = (uint32_t) pSrcAddr;
-		pProg->dar = (uint32_t) pDstAddr;
-		/* Use "devCtl" to mark that user memory need to be freed later if needed */
-		if (pProg == pRing->pHead) {
-			pProg->devCtl = dmacHw_FREE_USER_MEMORY;
-		} else {
-			pProg->devCtl = 0;
-		}
-
-		blkTs = srcTs;
-
-		/* Special treatmeant for last descriptor */
-		if (count == 1) {
-			/* Mark the last descriptor */
-			pProg->ctl.lo &=
-			    ~(dmacHw_REG_CTL_LLP_DST_EN |
-			      dmacHw_REG_CTL_LLP_SRC_EN);
-			/* Treatment for odd data bytes */
-			if (oddSize) {
-				/* Adjust for single byte transaction width */
-				switch (pConfig->transferType) {
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs =
-					    (oddSize / srcTrSize) +
-					    ((oddSize % srcTrSize) ? 1 : 0);
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-					srcTrWidth =
-					    dmacHw_SRC_TRANSACTION_WIDTH_8;
-					dstTrWidth =
-					    dmacHw_DST_TRANSACTION_WIDTH_8;
-					blkTs = oddSize;
-					break;
-				case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-					/* Do not adjust the transaction width  */
-					break;
-				}
-			} else {
-				srcTs -= blkTs;
-			}
-		} else {
-			if (srcTs / maxBlockSize) {
-				blkTs = maxBlockSize;
-			}
-			/* Remaining source transactions for next iteration */
-			srcTs -= blkTs;
-		}
-		/* Must have a valid source transactions */
-		dmacHw_ASSERT(blkTs > 0);
-		/* Set control information */
-		if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-			pProg->ctl.lo |= pConfig->transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		} else {
-			uint32_t transferType = 0;
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-			pProg->ctl.lo |= transferType |
-			    pConfig->srcUpdate |
-			    pConfig->dstUpdate |
-			    srcTrWidth |
-			    dstTrWidth |
-			    pConfig->srcMaxBurstWidth |
-			    pConfig->dstMaxBurstWidth |
-			    pConfig->srcMasterInterface |
-			    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-		}
-
-		/* Set block transaction size */
-		pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		/* Look for next descriptor */
-		if (count > 1) {
-			/* Point to the next descriptor */
-			pProg = (dmacHw_DESC_t *) pProg->llp;
-
-			/* Update source and destination address for next iteration */
-			switch (pConfig->transferType) {
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
-				if (pConfig->dstScatterWidth) {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->dstScatterWidth) *
-					     pConfig->dstScatterJump);
-				} else {
-					pDstAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize;
-				}
-
-				if (pConfig->srcGatherWidth) {
-					pSrcAddr =
-					    (char *)pDstAddr +
-					    blkTs * srcTrSize +
-					    (((blkTs * srcTrSize) /
-					      pConfig->srcGatherWidth) *
-					     pConfig->srcGatherJump);
-				} else {
-					pSrcAddr =
-					    (char *)pSrcAddr +
-					    blkTs * srcTrSize;
-				}
-				break;
-			case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
-				/* Do not adjust the address */
-				break;
-			default:
-				dmacHw_ASSERT(0);
-			}
-		} else {
-			/* At the end of transfer "srcTs" must be zero */
-			dmacHw_ASSERT(srcTs == 0);
-		}
-		count--;
-	}
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pStart;
-	}
-	/* Indicate that the descriptor is updated */
-	pRing->pEnd = pProg;
-	/* Head pointing to the next descriptor */
-	pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
-	/* Update Tail pointer if destination is a peripheral,
-	   because no one is going to read from the pTail
-	 */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ IN ]  DMA Channel handle */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	switch (attr) {
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
-		return dmacHw_GET_NUM_CHANNEL(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
-		return (1 <<
-			 (dmacHw_GET_MAX_BLOCK_SIZE
-			  (pCblk->module, pCblk->module) + 2)) - 8;
-	case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
-		return dmacHw_GET_NUM_INTERFACE(pCblk->module);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
-		return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
-							   pCblk->channel);
-	case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
-		return GetFifoSize(handle);
-	}
-	dmacHw_ASSERT(0);
-	return 0;
-}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
deleted file mode 100644
index a1f3283..0000000
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ /dev/null
@@ -1,1017 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_extra.c
-*
-*  @brief   Extra Low level DMA controller driver routines
-*
-*  @note
-*
-*   These routines provide basic DMA functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <stddef.h>
-
-#include <csp/dmacHw.h>
-#include <mach/csp/dmacHw_reg.h>
-#include <mach/csp/dmacHw_priv.h>
-
-extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];	/* Declared in dmacHw.c */
-
-/* ---- External Function Prototypes ------------------------------------- */
-
-/* ---- Internal Use Function Prototypes --------------------------------- */
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display DMA registers
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayRegisterContents(int module,	/*   [ IN ] DMA Controller unit  (0-1) */
-				    int channel,	/*   [ IN ] DMA Channel          (0-7) / -1(all) */
-				    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the print function */
-    ) {
-	int chan;
-
-	(*fpPrint) ("Displaying register content \n\n");
-	(*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
-	(*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
-	(*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: SW source req                       0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest req                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
-	(*fpPrint) ("Module %d: SW source signal                    0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
-	(*fpPrint) ("Module %d: SW source last                      0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
-	(*fpPrint) ("Module %d: SW dest last                        0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
-	(*fpPrint) ("--------------------------------------------------\n");
-	(*fpPrint) ("Module %d: misc config                         0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
-	(*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
-	(*fpPrint) ("Module %d: misc ID                             0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
-	(*fpPrint) ("Module %d: misc test                           0x%X\n",
-		    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
-
-	if (channel == -1) {
-		for (chan = 0; chan < 8; chan++) {
-			(*fpPrint)
-			    ("--------------------------------------------------\n");
-			(*fpPrint)
-			    ("Module %d: Channel %d Source                   0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Destination              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d LLP                      0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_LLP(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (LO)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Control (HI)             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats             0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats               0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (LO)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-			(*fpPrint)
-			    ("Module %d: Channel %d Config (HI)              0x%X\n",
-			     module, chan,
-			     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-		}
-	} else {
-		chan = channel;
-		(*fpPrint)
-		    ("--------------------------------------------------\n");
-		(*fpPrint)
-		    ("Module %d: Channel %d Source                   0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Destination              0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d LLP                      0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (LO)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Control (HI)             0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats             0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats               0x%X\n",
-		     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (LO)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
-		(*fpPrint)
-		    ("Module %d: Channel %d Config (HI)              0x%X\n",
-		     module, chan,
-		     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Helper function to display descriptor ring
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static void DisplayDescRing(void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			    int (*fpPrint) (const char *, ...)	/*   [ IN ] Callback to the print function */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	dmacHw_DESC_t *pStart;
-
-	if (pRing->pHead == NULL) {
-		return;
-	}
-
-	pStart = pRing->pHead;
-
-	while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
-		if (pStart == pRing->pHead) {
-			(*fpPrint) ("Head\n");
-		}
-		if (pStart == pRing->pTail) {
-			(*fpPrint) ("Tail\n");
-		}
-		if (pStart == pRing->pProg) {
-			(*fpPrint) ("Prog\n");
-		}
-		if (pStart == pRing->pEnd) {
-			(*fpPrint) ("End\n");
-		}
-		if (pStart == pRing->pFree) {
-			(*fpPrint) ("Free\n");
-		}
-		(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-		(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-		(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-		(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-		(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-		(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-		(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-		(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-		(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-
-		pStart = (dmacHw_DESC_t *) pStart->llp;
-	}
-	if (pStart == pRing->pHead) {
-		(*fpPrint) ("Head\n");
-	}
-	if (pStart == pRing->pTail) {
-		(*fpPrint) ("Tail\n");
-	}
-	if (pStart == pRing->pProg) {
-		(*fpPrint) ("Prog\n");
-	}
-	if (pStart == pRing->pEnd) {
-		(*fpPrint) ("End\n");
-	}
-	if (pStart == pRing->pFree) {
-		(*fpPrint) ("Free\n");
-	}
-	(*fpPrint) ("0x%X:\n", (uint32_t) pStart);
-	(*fpPrint) ("sar    0x%0X\n", pStart->sar);
-	(*fpPrint) ("dar    0x%0X\n", pStart->dar);
-	(*fpPrint) ("llp    0x%0X\n", pStart->llp);
-	(*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
-	(*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
-	(*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
-	(*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
-	(*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check if DMA channel is the flow controller
-*
-*  @return  1 : If DMA is a flow controller
-*           0 : Peripheral is the flow controller
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int DmaIsFlowController(void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	uint32_t ttfc =
-	    (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
-	    lo & dmacHw_REG_CTL_TTFC_MASK;
-
-	switch (ttfc) {
-	case dmacHw_REG_CTL_TTFC_MM_DMAC:
-	case dmacHw_REG_CTL_TTFC_MP_DMAC:
-	case dmacHw_REG_CTL_TTFC_PM_DMAC:
-	case dmacHw_REG_CTL_TTFC_PP_DMAC:
-		return 1;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Overwrites data length in the descriptor
-*
-*  This function overwrites data length in the descriptor
-*
-*
-*  @return   void
-*
-*  @note
-*          This is only used for PCM channel
-*/
-/****************************************************************************/
-void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			  void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			  size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	dmacHw_DESC_t *pProg;
-	dmacHw_DESC_t *pHead;
-	int srcTs = 0;
-	int srcTrSize = 0;
-
-	pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
-	pProg = pHead;
-
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-	srcTs = dataLen / srcTrSize;
-	do {
-		pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
-		pProg = (dmacHw_DESC_t *) pProg->llp;
-	} while (pProg != pHead);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*
-*  @return   void
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/* [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
-	dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*
-*  @note
-*     Should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle	/* [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
-
-	if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_TRANS;
-	}
-	if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_BLOCK;
-	}
-	if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
-	    ((0x00000001 << pCblk->channel))) {
-		status |= dmacHw_INTERRUPT_STATUS_ERROR;
-	}
-
-	return status;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
-{
-	uint32_t i;
-
-	for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
-		if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
-		     ((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
-			((0x00000001 << dmacHw_gCblk[i].channel)))
-		    ) {
-			return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
-		}
-	}
-	return dmacHw_CBLK_TO_HANDLE(NULL);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    ) {
-	int srcTs = 0;
-	int oddSize = 0;
-	int descCount = 0;
-	int dstTrSize = 0;
-	int srcTrSize = 0;
-	uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
-	dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
-	dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
-
-	dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
-	srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
-
-	/* Skip Tx if buffer is NULL  or length is unknown */
-	if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
-		/* Do not initiate transfer */
-		return -1;
-	}
-
-	/* Ensure scatter and gather are transaction aligned */
-	if (pConfig->srcGatherWidth % srcTrSize
-	    || pConfig->dstScatterWidth % dstTrSize) {
-		return -1;
-	}
-
-	/*
-	   Background 1: DMAC can not perform DMA if source and destination addresses are
-	   not properly aligned with the channel's transaction width. So, for successful
-	   DMA transfer, transaction width must be set according to the alignment of the
-	   source and destination address.
-	 */
-
-	/* Adjust destination transaction width if destination address is not aligned properly */
-	dstTrWidth = pConfig->dstMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
-		dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
-		dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
-	}
-
-	/* Adjust source transaction width if source address is not aligned properly */
-	srcTrWidth = pConfig->srcMaxTransactionWidth;
-	while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
-		srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
-		srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
-	}
-
-	/* Find the maximum transaction per descriptor */
-	if (pConfig->maxDataPerBlock
-	    && ((pConfig->maxDataPerBlock / srcTrSize) <
-		dmacHw_MAX_BLOCKSIZE)) {
-		maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
-	}
-
-	/* Find number of source transactions needed to complete the DMA transfer */
-	srcTs = dataLen / srcTrSize;
-	/* Find the odd number of bytes that need to be transferred as single byte transaction width */
-	if (srcTs && (dstTrSize > srcTrSize)) {
-		oddSize = dataLen % dstTrSize;
-		/* Adjust source transaction count due to "oddSize" */
-		srcTs = srcTs - (oddSize / srcTrSize);
-	} else {
-		oddSize = dataLen % srcTrSize;
-	}
-	/* Adjust "descCount" due to "oddSize" */
-	if (oddSize) {
-		descCount++;
-	}
-
-	/* Find the number of descriptor needed for total "srcTs" */
-	if (srcTs) {
-		descCount += ((srcTs - 1) / maxBlockSize) + 1;
-	}
-
-	return descCount;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	/* Make sure channel is not busy */
-	if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
-		/* Check if pEnd is not processed */
-		if (pRing->pEnd) {
-			/* Something left for processing */
-			return 1;
-		}
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk;
-
-	pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	/* Stop the channel */
-	dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  On failure : -1
-*           On success : Number of buffer freed
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-		   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-		   void (*fpFree) (void *)	/*   [ IN ] Function pointer to free data memory */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t count = 0;
-
-	if (fpFree == NULL) {
-		return -1;
-	}
-
-	while ((pRing->pFree != pRing->pTail)
-	       && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
-		if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
-			/* Identify, which memory to free */
-			if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-				(*fpFree) ((void *)pRing->pFree->dar);
-			} else {
-				/* Destination was a peripheral */
-				(*fpFree) ((void *)pRing->pFree->sar);
-			}
-			/* Unmark user memory to indicate it is freed */
-			pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
-		}
-		dmacHw_NEXT_DESC(pRing, pFree);
-
-		count++;
-	}
-
-	return count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will update the discriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor updated
-*
-*
-*  @note
-*     Channel must be configured for peripheral to memory transfer
-*
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-				     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				     void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				     uint32_t srcAddr,	/*   [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*   [ IN ] Function pointer  that provides destination memory */
-				     int len,	/*   [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-				     int num	/*   [ IN ] Number of descriptor to set */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-	dmacHw_DESC_t *pProg = NULL;
-	dmacHw_DESC_t *pLast = NULL;
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	uint32_t dstAddr;
-	uint32_t controlParam;
-	int i;
-
-	dmacHw_ASSERT(pConfig->transferType ==
-		      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
-
-	if (num > pRing->num) {
-		return -1;
-	}
-
-	pLast = pRing->pEnd;	/* Last descriptor updated */
-	pProg = pRing->pHead;	/* First descriptor in the new list */
-
-	controlParam = pConfig->srcUpdate |
-	    pConfig->dstUpdate |
-	    pConfig->srcMaxTransactionWidth |
-	    pConfig->dstMaxTransactionWidth |
-	    pConfig->srcMasterInterface |
-	    pConfig->dstMasterInterface |
-	    pConfig->srcMaxBurstWidth |
-	    pConfig->dstMaxBurstWidth |
-	    dmacHw_REG_CTL_TTFC_PM_PERI |
-	    dmacHw_REG_CTL_LLP_DST_EN |
-	    dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
-
-	for (i = 0; i < num; i++) {
-		/* Allocate Rx buffer only for idle descriptor */
-		if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
-		    ) {
-			/* Rx descriptor is not idle */
-			break;
-		}
-		/* Set source address */
-		pRing->pHead->sar = srcAddr;
-		if (fpAlloc) {
-			/* Allocate memory for buffer in descriptor */
-			dstAddr = (uint32_t) (*fpAlloc) (len);
-			/* Check the destination address */
-			if (dstAddr == 0) {
-				if (i == 0) {
-					/* Not a single descriptor is available */
-					return -1;
-				}
-				break;
-			}
-			/* Set destination address */
-			pRing->pHead->dar = dstAddr;
-		}
-		/* Set control information */
-		pRing->pHead->ctl.lo = controlParam;
-		/* Use "devCtl" to mark the memory that need to be freed later */
-		pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
-		/* Descriptor is now owned by the channel */
-		pRing->pHead->ctl.hi = 0;
-		/* Remember the descriptor last updated */
-		pRing->pEnd = pRing->pHead;
-		/* Update next descriptor */
-		dmacHw_NEXT_DESC(pRing, pHead);
-	}
-
-	/* Mark the end of the list */
-	pRing->pEnd->ctl.lo &=
-	    ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
-	/* Connect the list */
-	if (pLast != pProg) {
-		pLast->ctl.lo |=
-		    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
-	}
-	/* Mark the descriptors are updated */
-	pCblk->descUpdated = 1;
-	if (!pCblk->varDataStarted) {
-		/* LLP must be pointing to the first descriptor */
-		dmacHw_SET_LLP(pCblk->module, pCblk->channel,
-			       (uint32_t) pProg - pRing->virt2PhyOffset);
-		/* Channel, handling variable data started */
-		pCblk->varDataStarted = 1;
-	}
-
-	return i;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMAed to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @param    handle     -
-*  @param    ppBbuf     -
-*  @param    pLen       -
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle */
-			       dmacHw_CONFIG_t *pConfig,	/*   [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			       void **ppBbuf,	/*   [ OUT ] Data received */
-			       size_t *pLlen	/*   [ OUT ] Length of the data received */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	(void)handle;
-
-	if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
-		if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
-		    (pRing->pTail == pRing->pHead)
-		    ) {
-			/* No receive data available */
-			*ppBbuf = (char *)NULL;
-			*pLlen = 0;
-
-			return 0;
-		}
-	}
-
-	/* Return read buffer and length */
-	*ppBbuf = (char *)pRing->pTail->dar;
-
-	/* Extract length of the received data */
-	if (DmaIsFlowController(pDescriptor)) {
-		uint32_t srcTrSize = 0;
-
-		switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
-			srcTrSize = 1;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
-			srcTrSize = 2;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
-			srcTrSize = 4;
-			break;
-		case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
-			srcTrSize = 8;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		/* Calculate length from the block size */
-		*pLlen =
-		    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
-		    srcTrSize;
-	} else {
-		/* Extract length from the source peripheral */
-		*pLlen = pRing->pTail->sstat;
-	}
-
-	/* Advance tail to next descriptor */
-	dmacHw_NEXT_DESC(pRing, pTail);
-
-	return 1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-				uint32_t ctlAddress,	/*   [ IN ] Address of the device control register */
-				uint32_t control	/*   [ IN ] Device control information */
-    ) {
-	dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
-
-	if (ctlAddress == 0) {
-		return -1;
-	}
-
-	/* Check the availability of descriptors in the ring */
-	if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
-		return -1;
-	}
-	/* Set control information */
-	pRing->pHead->devCtl = control;
-	/* Set source and destination address */
-	pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
-	pRing->pHead->dar = ctlAddress;
-	/* Set control parameters */
-	if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
-		pRing->pHead->ctl.lo = pConfig->transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
-	} else {
-		uint32_t transferType = 0;
-		switch (pConfig->transferType) {
-		case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
-			transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
-			break;
-		case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
-			transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
-			break;
-		default:
-			dmacHw_ASSERT(0);
-		}
-		pRing->pHead->ctl.lo = transferType |
-		    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
-		    dmacHw_SRC_TRANSACTION_WIDTH_32 |
-		    pConfig->dstMaxTransactionWidth |
-		    dmacHw_SRC_BURST_WIDTH_0 |
-		    dmacHw_DST_BURST_WIDTH_0 |
-		    pConfig->srcMasterInterface |
-		    pConfig->dstMasterInterface |
-		    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
-	}
-
-	/* Set block transaction size to one 32 bit transaction */
-	pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
-
-	/* Remember the descriptor to initialize the registers */
-	if (pRing->pProg == dmacHw_DESC_INIT) {
-		pRing->pProg = pRing->pHead;
-	}
-	pRing->pEnd = pRing->pHead;
-
-	/* Advance the descriptor */
-	dmacHw_NEXT_DESC(pRing, pHead);
-
-	/* Update Tail pointer if destination is a peripheral */
-	if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
-		pRing->pTail = pRing->pHead;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle */
-			       void *userData	/*  [ IN ] User data */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	pCblk->userData = userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel handle */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	return pCblk->userData;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    ) {
-	int i;
-	dmacHw_DESC_RING_t *pRing;
-	dmacHw_DESC_t *pDesc;
-
-	pRing = dmacHw_GET_DESC_RING(pDescriptor);
-	pDesc = pRing->pHead;
-
-	for (i = 0; i < pRing->num; i++) {
-		/* Mark descriptor is ready to use */
-		pDesc->ctl.hi = dmacHw_DESC_FREE;
-		/* Look into next link list item */
-		pDesc++;
-	}
-	pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
-	pRing->pProg = dmacHw_DESC_INIT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*  @return  void
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle */
-			   void *pDescriptor,	/*   [ IN ] Descriptor buffer */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback function */
-    ) {
-	dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
-
-	DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
-	DisplayDescRing(pDescriptor, fpPrint);
-}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
deleted file mode 100644
index 244a61a..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
deleted file mode 100644
index 16225e4..0000000
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.c
-*
-*  @brief   Low level Timer driver routines
-*
-*  @note
-*
-*   These routines provide basic timer functionality only.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/stdint.h>
-
-#include <csp/tmrHw.h>
-#include <mach/csp/tmrHw_reg.h>
-
-#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
-#define tmrHw_MILLISEC_PER_SEC              (1000)
-
-#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
-#define tmrHw_LOW_16_RESOLUTION_COUNT       (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
-#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
-#define tmrHw_LOW_256_RESOLUTION_COUNT      (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
-#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
-
-#define tmrHw_HIGH_1_RESOLUTION_COUNT       (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
-#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
-#define tmrHw_HIGH_16_RESOLUTION_COUNT      (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
-#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
-#define tmrHw_HIGH_256_RESOLUTION_COUNT     (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
-#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
-
-static void ResetTimer(tmrHw_ID_t timerId)
-    __attribute__ ((section(".aramtext")));
-static int tmrHw_divide(int num, int denom)
-    __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-) {
-	switch (capability) {
-	case tmrHw_CAPABILITY_CLOCK:
-		return (timerId <=
-			1) ? tmrHw_LOW_RESOLUTION_CLOCK :
-		    tmrHw_HIGH_RESOLUTION_CLOCK;
-	case tmrHw_CAPABILITY_RESOLUTION:
-		return 32;
-	default:
-		return 0;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Resets a timer
-*
-*  This function initializes  timer
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-static void ResetTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer Id */
-) {
-	/* Reset timer */
-	pTmrHw[timerId].LoadValue = 0;
-	pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
-	pTmrHw[timerId].Control = 0;
-	pTmrHw[timerId].BackgroundLoad = 0;
-	/* Always configure as a 32 bit timer */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
-	/* Clear interrupt only if raw status interrupt is set */
-	if (pTmrHw[timerId].RawInterruptStatus) {
-		pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Sets counter value for an interval in ms
-*
-*  @return   On success: Effective counter value set
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-				       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	uint32_t scale = 0;
-	uint32_t count = 0;
-
-	if (timerId == 0 || timerId == 1) {
-		if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_LOW_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_LOW_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_LOW_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-
-	} else if (timerId == 2 || timerId == 3) {
-		if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-			scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-			scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
-		} else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
-			pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-			scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
-		} else {
-			return 0;
-		}
-
-		count = msec * scale;
-		/* Set counter value */
-		pTmrHw[timerId].LoadValue = count;
-		pTmrHw[timerId].BackgroundLoad = count;
-	}
-	return count / scale;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-) {
-	uint32_t resolution = 0;
-	uint32_t count = 0;
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-	/* Set timer in highest resolution */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-
-	if (rate && (timerId == 0 || timerId == 1)) {
-		if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
-			return 0;
-		}
-		resolution = tmrHw_LOW_RESOLUTION_CLOCK;
-	} else if (rate && (timerId == 2 || timerId == 3)) {
-		if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
-			return 0;
-		} else {
-			resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
-		}
-	} else {
-		return 0;
-	}
-	/* Find the counter value */
-	count = resolution / rate;
-	/* Set counter value */
-	pTmrHw[timerId].LoadValue = count;
-	pTmrHw[timerId].BackgroundLoad = count;
-
-	return resolution / count;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode periodic */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in milli-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in milli-second */
-) {
-	ResetTimer(timerId);
-
-	/* Set timer mode oneshot */
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
-
-	return SetTimerPeriod(timerId, msec);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) {
-	uint32_t scale = 0;
-
-	ResetTimer(timerId);
-	/* Set timer as free running mode */
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
-
-	if (divider >= 64) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
-		scale = 256;
-	} else if (divider >= 8) {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
-		scale = 16;
-	} else {
-		pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
-		scale = 1;
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
-	} else if (timerId == 2 || timerId == 3) {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	/* return 32 bit timer value */
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
-	case tmrHw_CONTROL_FREE_RUNNING:
-		if (pTmrHw[timerId].CurrentValue) {
-			return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
-		}
-		break;
-	case tmrHw_CONTROL_PERIODIC:
-	case tmrHw_CONTROL_ONESHOT:
-		return pTmrHw[timerId].BackgroundLoad -
-		    pTmrHw[timerId].CurrentValue;
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	uint32_t divider = 0;
-
-	switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
-	case tmrHw_CONTROL_PRESCALE_1:
-		divider = 1;
-		break;
-	case tmrHw_CONTROL_PRESCALE_16:
-		divider = 16;
-		break;
-	case tmrHw_CONTROL_PRESCALE_256:
-		divider = 256;
-		break;
-	default:
-		tmrHw_ASSERT(0);
-	}
-
-	if (timerId == 0 || timerId == 1) {
-		return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
-	} else {
-		return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
-	}
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	pTmrHw[timerId].InterruptClear = 0x1;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) {
-	if (pTmrHw[timerId].InterruptStatus) {
-		return tmrHw_INTERRUPT_STATUS_SET;
-	} else {
-		return tmrHw_INTERRUPT_STATUS_UNSET;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void	/*  void */
-) {
-	int i;
-
-	for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
-		if (pTmrHw[i].InterruptStatus) {
-			return i;
-		}
-	}
-
-	return 0xFFFFFFFF;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback function */
-) {
-	(*fpPrint) ("Displaying register contents \n\n");
-	(*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
-		    pTmrHw[timerId].LoadValue);
-	(*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
-		    pTmrHw[timerId].BackgroundLoad);
-	(*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
-		    pTmrHw[timerId].Control);
-	(*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptClear);
-	(*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
-		    pTmrHw[timerId].RawInterruptStatus);
-	(*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
-		    pTmrHw[timerId].InterruptStatus);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs /*  [ IN ] usec to delay */
-) {
-	tmrHw_RATE_t usec_tick_rate;
-	tmrHw_COUNT_t start_time;
-	tmrHw_COUNT_t delta_time;
-
-	start_time = tmrHw_GetCurrentCount(timerId);
-	usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
-	delta_time = usecs * usec_tick_rate;
-
-	/* Busy wait */
-	while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
-		;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Local Divide function
-*
-*  This function does the divide
-*
-*  @return divide value
-*
-*/
-/****************************************************************************/
-static int tmrHw_divide(int num, int denom)
-{
-	int r;
-	int t = 1;
-
-	/* Shift denom and t up to the largest value to optimize algorithm */
-	/* t contains the units of each divide */
-	while ((denom & 0x40000000) == 0) {	/* fails if denom=0 */
-		denom = denom << 1;
-		t = t << 1;
-	}
-
-	/* Initialize the result */
-	r = 0;
-
-	do {
-		/* Determine if there exists a positive remainder */
-		if ((num - denom) >= 0) {
-			/* Accumlate t to the result and calculate a new remainder */
-			num = num - denom;
-			r = r + t;
-		}
-		/* Continue to shift denom and shift t down to 0 */
-		denom = denom >> 1;
-		t = t >> 1;
-	} while (t != 0);
-	return r;
-}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
deleted file mode 100644
index e5fd241..0000000
--- a/arch/arm/mach-bcmring/dma.c
+++ /dev/null
@@ -1,1518 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.c
-*
-*   @brief  Implements the DMA interface.
-*/
-/****************************************************************************/
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/module.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/irqreturn.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-
-#include <mach/timer.h>
-
-#include <linux/pfn.h>
-#include <linux/atomic.h>
-#include <mach/dma.h>
-
-/* ---- Public Variables ------------------------------------------------- */
-
-/* ---- Private Constants and Types -------------------------------------- */
-
-#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 4) | (channelIdx))
-
-#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
-#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
-
-
-/* ---- Private Variables ------------------------------------------------ */
-
-static DMA_Global_t gDMA;
-static struct proc_dir_entry *gDmaDir;
-
-#include "dma_device.c"
-
-/* ---- Private Function Prototypes -------------------------------------- */
-
-/* ---- Functions  ------------------------------------------------------- */
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/channels
-*/
-/****************************************************************************/
-
-static int dma_proc_read_channels(char *buf, char **start, off_t offset,
-				  int count, int *eof, void *data)
-{
-	int controllerIdx;
-	int channelIdx;
-	int limit = count - 200;
-	int len = 0;
-	DMA_Channel_t *channel;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			if (len >= limit) {
-				break;
-			}
-
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			len +=
-			    sprintf(buf + len, "%d:%d ", controllerIdx,
-				    channelIdx);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				len +=
-				    sprintf(buf + len, "Dedicated for %s ",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-			} else {
-				len += sprintf(buf + len, "Shared ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
-				len += sprintf(buf + len, "No ISR ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
-				len += sprintf(buf + len, "Fifo: 128 ");
-			} else {
-				len += sprintf(buf + len, "Fifo: 64  ");
-			}
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-				len +=
-				    sprintf(buf + len, "InUse by %s",
-					    DMA_gDeviceAttribute[channel->
-								 devType].name);
-#if (DMA_DEBUG_TRACK_RESERVATION)
-				len +=
-				    sprintf(buf + len, " (%s:%d)",
-					    channel->fileName,
-					    channel->lineNum);
-#endif
-			} else {
-				len += sprintf(buf + len, "Avail ");
-			}
-
-			if (channel->lastDevType != DMA_DEVICE_NONE) {
-				len +=
-				    sprintf(buf + len, "Last use: %s ",
-					    DMA_gDeviceAttribute[channel->
-								 lastDevType].
-					    name);
-			}
-
-			len += sprintf(buf + len, "\n");
-		}
-	}
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Displays information for /proc/dma/devices
-*/
-/****************************************************************************/
-
-static int dma_proc_read_devices(char *buf, char **start, off_t offset,
-				 int count, int *eof, void *data)
-{
-	int limit = count - 200;
-	int len = 0;
-	int devIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (devAttr->name == NULL) {
-			continue;
-		}
-
-		if (len >= limit) {
-			break;
-		}
-
-		len += sprintf(buf + len, "%-12s ", devAttr->name);
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			len +=
-			    sprintf(buf + len, "Dedicated %d:%d ",
-				    devAttr->dedicatedController,
-				    devAttr->dedicatedChannel);
-		} else {
-			len += sprintf(buf + len, "Shared DMA:");
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
-				len += sprintf(buf + len, "0");
-			}
-			if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
-				len += sprintf(buf + len, "1");
-			}
-			len += sprintf(buf + len, " ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
-			len += sprintf(buf + len, "NoISR ");
-		}
-		if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
-			len += sprintf(buf + len, "Allow-128 ");
-		}
-
-		len +=
-		    sprintf(buf + len,
-			    "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
-			    devAttr->numTransfers, devAttr->transferTicks,
-			    devAttr->transferBytes,
-			    devAttr->ring.bytesAllocated);
-
-	}
-
-	up(&gDMA.lock);
-	*eof = 1;
-
-	return len;
-}
-
-/****************************************************************************/
-/**
-*   Determines if a DMA_Device_t is "valid".
-*
-*   @return
-*       TRUE        - dma device is valid
-*       FALSE       - dma device isn't valid
-*/
-/****************************************************************************/
-
-static inline int IsDeviceValid(DMA_Device_t device)
-{
-	return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
-}
-
-/****************************************************************************/
-/**
-*   Translates a DMA handle into a pointer to a channel.
-*
-*   @return
-*       non-NULL    - pointer to DMA_Channel_t
-*       NULL        - DMA Handle was invalid
-*/
-/****************************************************************************/
-
-static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
-{
-	int controllerIdx;
-	int channelIdx;
-
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-	channelIdx = CHANNEL_FROM_HANDLE(handle);
-
-	if ((controllerIdx > DMA_NUM_CONTROLLERS)
-	    || (channelIdx > DMA_NUM_CHANNELS)) {
-		return NULL;
-	}
-	return &gDMA.controller[controllerIdx].channel[channelIdx];
-}
-
-/****************************************************************************/
-/**
-*   Interrupt handler which is called to process DMA interrupts.
-*/
-/****************************************************************************/
-
-static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int irqStatus;
-
-	channel = (DMA_Channel_t *) dev_id;
-
-	/* Figure out why we were called, and knock down the interrupt */
-
-	irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
-	dmacHw_clearInterrupt(channel->dmacHwHandle);
-
-	if ((channel->devType < 0)
-	    || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
-		printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
-		       channel->devType);
-		return IRQ_NONE;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Update stats */
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
-		devAttr->transferTicks +=
-		    (timer_get_tick_count() - devAttr->transferStartTime);
-	}
-
-	if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
-		printk(KERN_ERR
-		       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
-		       channel->devType, devAttr->name);
-	} else {
-		devAttr->numTransfers++;
-		devAttr->transferBytes += devAttr->numBytes;
-	}
-
-	/* Call any installed handler */
-
-	if (devAttr->devHandler != NULL) {
-		devAttr->devHandler(channel->devType, irqStatus,
-				    devAttr->userData);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -EINVAL     Invalid parameters passed in
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be allocated. */
-    ) {
-	size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
-
-	if ((ring == NULL) || (numDescriptors <= 0)) {
-		return -EINVAL;
-	}
-
-	ring->physAddr = 0;
-	ring->descriptorsAllocated = 0;
-	ring->bytesAllocated = 0;
-
-	ring->virtAddr = dma_alloc_writecombine(NULL,
-						     bytesToAlloc,
-						     &ring->physAddr,
-						     GFP_KERNEL);
-	if (ring->virtAddr == NULL) {
-		return -ENOMEM;
-	}
-
-	ring->bytesAllocated = bytesToAlloc;
-	ring->descriptorsAllocated = numDescriptors;
-
-	return dma_init_descriptor_ring(ring, numDescriptors);
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor to release */
-    ) {
-	if (ring->virtAddr != NULL) {
-		dma_free_writecombine(NULL,
-				      ring->bytesAllocated,
-				      ring->virtAddr, ring->physAddr);
-	}
-
-	ring->bytesAllocated = 0;
-	ring->descriptorsAllocated = 0;
-	ring->virtAddr = NULL;
-	ring->physAddr = 0;
-}
-
-EXPORT_SYMBOL(dma_free_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    ) {
-	if (ring->virtAddr == NULL) {
-		return -EINVAL;
-	}
-	if (dmacHw_initDescriptor(ring->virtAddr,
-				  ring->physAddr,
-				  ring->bytesAllocated, numDescriptors) < 0) {
-		printk(KERN_ERR
-		       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_init_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -ENODEV - Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int numDescriptors;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR
-		       "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
-		return -EINVAL;
-	}
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_calculate_descriptor_count);
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*       -EINVAL Invalid parameters
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	int rc;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	rc = dmacHw_setDataDescriptor(&devAttr->config,
-				      ring->virtAddr,
-				      (void *)srcData,
-				      (void *)dstData, numBytes);
-	if (rc < 0) {
-		printk(KERN_ERR
-		       "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
-		       rc);
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_add_descriptors);
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors to */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	/* Free the previously allocated descriptor ring */
-
-	dma_free_descriptor_ring(&devAttr->ring);
-
-	if (ring != NULL) {
-		/* Copy in the new one */
-
-		devAttr->ring = *ring;
-	}
-
-	/* Set things up so that if dma_transfer is called then this descriptor */
-	/* ring will get freed. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -ENODEV Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	memset(ring, 0, sizeof(*ring));
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	*ring = devAttr->ring;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_get_device_descriptor_ring);
-
-/****************************************************************************/
-/**
-*   Configures a DMA channel.
-*
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-static int ConfigChannel(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int controllerIdx;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-	controllerIdx = CONTROLLER_FROM_HANDLE(handle);
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
-		if (devAttr->config.transferType ==
-		    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
-			devAttr->config.dstPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		} else if (devAttr->config.transferType ==
-			   dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
-			devAttr->config.srcPeripheralPort =
-			    devAttr->dmacPort[controllerIdx];
-		}
-	}
-
-	if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
-		printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
-		return -EIO;
-	}
-
-	return 0;
-}
-
-/****************************************************************************/
-/**
-*   Initializes all of the data structures associated with the DMA.
-*   @return
-*       >= 0    - Initialization was successful.
-*
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_init(void)
-{
-	int rc = 0;
-	int controllerIdx;
-	int channelIdx;
-	DMA_Device_t devIdx;
-	DMA_Channel_t *channel;
-	DMA_Handle_t dedicatedHandle;
-
-	memset(&gDMA, 0, sizeof(gDMA));
-
-	sema_init(&gDMA.lock, 0);
-	init_waitqueue_head(&gDMA.freeChannelQ);
-
-	/* Initialize the Hardware */
-
-	dmacHw_initDma();
-
-	/* Start off by marking all of the DMA channels as shared. */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			channel->flags = 0;
-			channel->devType = DMA_DEVICE_NONE;
-			channel->lastDevType = DMA_DEVICE_NONE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-			channel->fileName = "";
-			channel->lineNum = 0;
-#endif
-
-			channel->dmacHwHandle =
-			    dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
-						    (controllerIdx,
-						     channelIdx));
-			dmacHw_initChannel(channel->dmacHwHandle);
-		}
-	}
-
-	/* Record any special attributes that channels may have */
-
-	gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-	gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
-
-	/* Now walk through and record the dedicated channels. */
-
-	for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
-		DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
-
-		if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
-		    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
-			printk(KERN_ERR
-			       "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
-			       devAttr->name);
-			rc = -EINVAL;
-			goto out;
-		}
-
-		if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-			/* This is a dedicated device. Mark the channel as being reserved. */
-
-			if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Controller %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedController);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
-				printk(KERN_ERR
-				       "DMA Device: %s DMA Channel %d is out of range\n",
-				       devAttr->name,
-				       devAttr->dedicatedChannel);
-				rc = -EINVAL;
-				goto out;
-			}
-
-			dedicatedHandle =
-			    MAKE_HANDLE(devAttr->dedicatedController,
-					devAttr->dedicatedChannel);
-			channel = HandleToChannel(dedicatedHandle);
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
-			    0) {
-				printk
-				    ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
-				     devAttr->name,
-				     devAttr->dedicatedController,
-				     devAttr->dedicatedChannel,
-				     DMA_gDeviceAttribute[channel->devType].
-				     name);
-				rc = -EBUSY;
-				goto out;
-			}
-
-			channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
-			channel->devType = devIdx;
-
-			if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
-				channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
-			}
-
-			/* For dedicated channels, we can go ahead and configure the DMA channel now */
-			/* as well. */
-
-			ConfigChannel(dedicatedHandle);
-		}
-	}
-
-	/* Go through and register the interrupt handlers */
-
-	for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
-	     controllerIdx++) {
-		for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
-		     channelIdx++) {
-			channel =
-			    &gDMA.controller[controllerIdx].channel[channelIdx];
-
-			if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
-				snprintf(channel->name, sizeof(channel->name),
-					 "dma %d:%d %s", controllerIdx,
-					 channelIdx,
-					 channel->devType ==
-					 DMA_DEVICE_NONE ? "" :
-					 DMA_gDeviceAttribute[channel->devType].
-					 name);
-
-				rc =
-				     request_irq(IRQ_DMA0C0 +
-						 (controllerIdx *
-						  DMA_NUM_CHANNELS) +
-						 channelIdx,
-						 dma_interrupt_handler,
-						 IRQF_DISABLED, channel->name,
-						 channel);
-				if (rc != 0) {
-					printk(KERN_ERR
-					       "request_irq for IRQ_DMA%dC%d failed\n",
-					       controllerIdx, channelIdx);
-				}
-			}
-		}
-	}
-
-	/* Create /proc/dma/channels and /proc/dma/devices */
-
-	gDmaDir = proc_mkdir("dma", NULL);
-
-	if (gDmaDir == NULL) {
-		printk(KERN_ERR "Unable to create /proc/dma\n");
-	} else {
-		create_proc_read_entry("channels", 0, gDmaDir,
-				       dma_proc_read_channels, NULL);
-		create_proc_read_entry("devices", 0, gDmaDir,
-				       dma_proc_read_devices, NULL);
-	}
-
-out:
-
-	up(&gDMA.lock);
-
-	return rc;
-}
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg
-    (DMA_Device_t dev, const char *fileName, int lineNum)
-#else
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-#endif
-{
-	DMA_Handle_t handle;
-	DMA_DeviceAttribute_t *devAttr;
-	DMA_Channel_t *channel;
-	int controllerIdx;
-	int controllerIdx2;
-	int channelIdx;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
-		handle = -ENODEV;
-		goto out;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	{
-		char *s;
-
-		s = strrchr(fileName, '/');
-		if (s != NULL) {
-			fileName = s + 1;
-		}
-	}
-#endif
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
-		/* This device has already been requested and not been freed */
-
-		printk(KERN_ERR "%s: device %s is already requested\n",
-		       __func__, devAttr->name);
-		handle = -EBUSY;
-		goto out;
-	}
-
-	if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
-		/* This device has a dedicated channel. */
-
-		channel =
-		    &gDMA.controller[devAttr->dedicatedController].
-		    channel[devAttr->dedicatedChannel];
-		if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
-			handle = -EBUSY;
-			goto out;
-		}
-
-		channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
-		devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-		channel->fileName = fileName;
-		channel->lineNum = lineNum;
-#endif
-		handle =
-		    MAKE_HANDLE(devAttr->dedicatedController,
-				devAttr->dedicatedChannel);
-		goto out;
-	}
-
-	/* This device needs to use one of the shared channels. */
-
-	handle = DMA_INVALID_HANDLE;
-	while (handle == DMA_INVALID_HANDLE) {
-		/* Scan through the shared channels and see if one is available */
-
-		for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
-		     controllerIdx2++) {
-			/* Check to see if we should try on controller 1 first. */
-
-			controllerIdx = controllerIdx2;
-			if ((devAttr->
-			     flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
-				controllerIdx = 1 - controllerIdx;
-			}
-
-			/* See if the device is available on the controller being tested */
-
-			if ((devAttr->
-			     flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
-			    != 0) {
-				for (channelIdx = 0;
-				     channelIdx < DMA_NUM_CHANNELS;
-				     channelIdx++) {
-					channel =
-					    &gDMA.controller[controllerIdx].
-					    channel[channelIdx];
-
-					if (((channel->
-					      flags &
-					      DMA_CHANNEL_FLAG_IS_DEDICATED) ==
-					     0)
-					    &&
-					    ((channel->
-					      flags & DMA_CHANNEL_FLAG_IN_USE)
-					     == 0)) {
-						if (((channel->
-						      flags &
-						      DMA_CHANNEL_FLAG_LARGE_FIFO)
-						     != 0)
-						    &&
-						    ((devAttr->
-						      flags &
-						      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
-						     == 0)) {
-							/* This channel is a large fifo - don't tie it up */
-							/* with devices that we don't want using it. */
-
-							continue;
-						}
-
-						channel->flags |=
-						    DMA_CHANNEL_FLAG_IN_USE;
-						channel->devType = dev;
-						devAttr->flags |=
-						    DMA_DEVICE_FLAG_IN_USE;
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-						channel->fileName = fileName;
-						channel->lineNum = lineNum;
-#endif
-						handle =
-						    MAKE_HANDLE(controllerIdx,
-								channelIdx);
-
-						/* Now that we've reserved the channel - we can go ahead and configure it */
-
-						if (ConfigChannel(handle) != 0) {
-							handle = -EIO;
-							printk(KERN_ERR
-							       "dma_request_channel: ConfigChannel failed\n");
-						}
-						goto out;
-					}
-				}
-			}
-		}
-
-		/* No channels are currently available. Let's wait for one to free up. */
-
-		{
-			DEFINE_WAIT(wait);
-
-			prepare_to_wait(&gDMA.freeChannelQ, &wait,
-					TASK_INTERRUPTIBLE);
-			up(&gDMA.lock);
-			schedule();
-			finish_wait(&gDMA.freeChannelQ, &wait);
-
-			if (signal_pending(current)) {
-				/* We don't currently hold gDMA.lock, so we return directly */
-
-				return -ERESTARTSYS;
-			}
-		}
-
-		if (down_interruptible(&gDMA.lock)) {
-			return -ERESTARTSYS;
-		}
-	}
-
-out:
-	up(&gDMA.lock);
-
-	return handle;
-}
-
-/* Create both _dbg and non _dbg functions for modules. */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-#undef dma_request_channel
-DMA_Handle_t dma_request_channel(DMA_Device_t dev)
-{
-	return dma_request_channel_dbg(dev, __FILE__, __LINE__);
-}
-
-EXPORT_SYMBOL(dma_request_channel_dbg);
-#endif
-EXPORT_SYMBOL(dma_request_channel);
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t handle	/* DMA handle. */
-    ) {
-	int rc = 0;
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (down_interruptible(&gDMA.lock) < 0) {
-		return -ERESTARTSYS;
-	}
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		rc = -EINVAL;
-		goto out;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
-		channel->lastDevType = channel->devType;
-		channel->devType = DMA_DEVICE_NONE;
-	}
-	channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
-	devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
-
-out:
-	up(&gDMA.lock);
-
-	wake_up_interruptible(&gDMA.freeChannelQ);
-
-	return rc;
-}
-
-EXPORT_SYMBOL(dma_free_channel);
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return
-*       0           Device uses a dedicated channel
-*       > zero      Device uses a shared channel
-*       < zero      Error code
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t device	/* Device to check. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-
-	if (!IsDeviceValid(device)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[device];
-
-	return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
-}
-
-EXPORT_SYMBOL(dma_device_is_channel_shared);
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
-							      (void *)srcData,
-							      (void *)dstData,
-							      numBytes);
-	if (numDescriptors < 0) {
-		printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, numDescriptors);
-			return rc;
-		}
-		/* Setup the descriptor for this transfer */
-
-		if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-					  devAttr->ring.physAddr,
-					  devAttr->ring.bytesAllocated,
-					  numDescriptors) < 0) {
-			printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
-			       __func__);
-			return -EINVAL;
-		}
-	} else {
-		/* We've already got enough ring buffer allocated. All we need to do is reset */
-		/* any control information, just in case the previous DMA was stopped. */
-
-		dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* Remember the critical information for this transfer so that we can eliminate */
-	/* another call to dma_alloc_descriptors if the caller reuses the same buffers */
-
-	devAttr->prevSrcData = srcData;
-	devAttr->prevDstData = dstData;
-	devAttr->prevNumBytes = numBytes;
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_alloc_descriptors);
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int numDst1Descriptors;
-	int numDst2Descriptors;
-	int numDescriptors;
-	size_t ringBytesRequired;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	/* Figure out how many descriptors we need. */
-
-	/* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
-	/*        srcData, dstData, numBytes); */
-
-	numDst1Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData1, numBytes);
-	if (numDst1Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDst2Descriptors =
-	     dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
-					     (void *)dstData2, numBytes);
-	if (numDst2Descriptors < 0) {
-		return -EINVAL;
-	}
-	numDescriptors = numDst1Descriptors + numDst2Descriptors;
-	/* printk("numDescriptors: %d\n", numDescriptors); */
-
-	/* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
-	/* a new one. */
-
-	ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
-
-	/* printk("ringBytesRequired: %d\n", ringBytesRequired); */
-
-	if (ringBytesRequired > devAttr->ring.bytesAllocated) {
-		/* Make sure that this code path is never taken from interrupt context. */
-		/* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
-		/* allocation needs to have already been done. */
-
-		might_sleep();
-
-		/* Free the old descriptor ring and allocate a new one. */
-
-		dma_free_descriptor_ring(&devAttr->ring);
-
-		/* And allocate a new one. */
-
-		rc =
-		     dma_alloc_descriptor_ring(&devAttr->ring,
-					       numDescriptors);
-		if (rc < 0) {
-			printk(KERN_ERR
-			       "%s: dma_alloc_descriptor_ring(%d) failed\n",
-			       __func__, ringBytesRequired);
-			return rc;
-		}
-	}
-
-	/* Setup the descriptor for this transfer. Since this function is used with */
-	/* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
-	/* setDataDescriptor will keep trying to append onto the end. */
-
-	if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
-				  devAttr->ring.physAddr,
-				  devAttr->ring.bytesAllocated,
-				  numDescriptors) < 0) {
-		printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
-		return -EINVAL;
-	}
-
-	/* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
-	/* as last time, then we don't need to call setDataDescriptor again. */
-
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData1, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-	if (dmacHw_setDataDescriptor(&devAttr->config,
-				     devAttr->ring.virtAddr,
-				     (void *)srcData,
-				     (void *)dstData2, numBytes) < 0) {
-		printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
-		       __func__);
-		return -EINVAL;
-	}
-
-	/* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
-	/* try to make the 'prev' variables right. */
-
-	devAttr->prevSrcData = 0;
-	devAttr->prevDstData = 0;
-	devAttr->prevNumBytes = 0;
-
-	return numDescriptors;
-}
-
-EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_start_transfer);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	dmacHw_stopTransfer(channel->dmacHwHandle);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_stop_transfer);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle)
-{
-	DMA_Channel_t *channel;
-	dmacHw_TRANSFER_STATUS_e status;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	while ((status =
-		dmacHw_transferCompleted(channel->dmacHwHandle)) ==
-	       dmacHw_TRANSFER_STATUS_BUSY) {
-		;
-	}
-
-	if (status == dmacHw_TRANSFER_STATUS_ERROR) {
-		printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
-		return -EIO;
-	}
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_wait_transfer_done);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA, allocating the descriptors as required.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	DMA_Channel_t *channel;
-	DMA_DeviceAttribute_t *devAttr;
-	int rc = 0;
-
-	channel = HandleToChannel(handle);
-	if (channel == NULL) {
-		return -ENODEV;
-	}
-
-	devAttr = &DMA_gDeviceAttribute[channel->devType];
-
-	if (devAttr->config.transferType != transferType) {
-		return -EINVAL;
-	}
-
-	/* We keep track of the information about the previous request for this */
-	/* device, and if the attributes match, then we can use the descriptors we setup */
-	/* the last time, and not have to reinitialize everything. */
-
-	{
-		rc =
-		     dma_alloc_descriptors(handle, transferType, srcData,
-					   dstData, numBytes);
-		if (rc != 0) {
-			return rc;
-		}
-	}
-
-	/* And kick off the transfer */
-
-	devAttr->numBytes = numBytes;
-	devAttr->transferStartTime = timer_get_tick_count();
-
-	dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
-				devAttr->ring.virtAddr);
-
-	/* Since we got this far, everything went successfully */
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_transfer);
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    ) {
-	DMA_DeviceAttribute_t *devAttr;
-	unsigned long flags;
-
-	if (!IsDeviceValid(dev)) {
-		return -ENODEV;
-	}
-	devAttr = &DMA_gDeviceAttribute[dev];
-
-	local_irq_save(flags);
-
-	devAttr->userData = userData;
-	devAttr->devHandler = devHandler;
-
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-EXPORT_SYMBOL(dma_set_device_handler);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
deleted file mode 100644
index ca0ad73..0000000
--- a/arch/arm/mach-bcmring/dma_device.c
+++ /dev/null
@@ -1,593 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma_device.c
-*
-*   @brief  private array of DMA_DeviceAttribute_t
-*/
-/****************************************************************************/
-
-DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
-	[DMA_DEVICE_MEM_TO_MEM] =	/* MEM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-mem",
-	 .config = {
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-
-		    },
-	 },
-	[DMA_DEVICE_VPM_MEM_TO_MEM] =	/* VPM */
-	{
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
-	 .name = "vpm",
-	 .dedicatedController = 0,
-	 .dedicatedChannel = 0,
-	 /* reserve DMA0:0 for VPM */
-	 },
-	[DMA_DEVICE_NAND_MEM_TO_MEM] =	/* NAND */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "nand",
-	 .config = {
-		    .srcPeripheralPort = 0,
-		    .dstPeripheralPort = 0,
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
-		    },
-	 },
-	[DMA_DEVICE_PIF_MEM_TO_DEV] =	/* PIF TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_tx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    /* dstPeripheralPort          = 5 or 14 */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_PIF_DEV_TO_MEM] =	/* PIF RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
-	 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
-	 /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
-	 | DMA_DEVICE_FLAG_PORT_PER_DMAC,
-	 .name = "pif_rx",
-	 .dmacPort = {14, 5},
-	 .config = {
-		    /* srcPeripheralPort          = 5 or 14 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .maxDataPerBlock = 16256,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_DEV_TO_MEM] =	/* I2S RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_rx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: I2S0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S0_MEM_TO_DEV] =	/* I2S TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "i2s0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: I2S0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_DEV_TO_MEM] =	/* I2S1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: I2S1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_I2S1_MEM_TO_DEV] =	/* I2S1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "i2s1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: I2S1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_ESW_MEM_TO_DEV] =	/* ESW TX */
-	{
-	 .name = "esw_tx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 3,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 1,	/* DST: ESW (MTP) */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x30490010,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_ESW_DEV_TO_MEM] =	/* ESW RX */
-	{
-	 .name = "esw_rx",
-	 .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
-	 .dedicatedController = 1,
-	 .dedicatedChannel = 2,
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: ESW (PTM) */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    /* DMAx_AHB_SSTATARy */
-		    .srcStatusRegisterAddress = 0x30480010,
-		    /* DMAx_AHB_DSTATARy */
-		    .dstStatusRegisterAddress = 0x00000000,
-		    /* DMAx_AHB_CFGy */
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    /* DMAx_AHB_CTLy */
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =	/* APM Codec A Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_rx",
-	 .config = {
-		    .srcPeripheralPort = 2,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =	/* APM Codec A Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_a_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 3,	/* DST: Codec A Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =	/* APM Codec B Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec B Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =	/* APM Codec B Egress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "apm_b_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 5,	/* DST: Codec B Egress FIFO */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =	/* APM Codec C Ingress */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "apm_c_rx",
-	 .config = {
-		    .srcPeripheralPort = 4,	/* SRC: Codec C Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =	/* PCM0 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_rx",
-	 .config = {
-		    .srcPeripheralPort = 12,	/* SRC: PCM0 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =	/* PCM0 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0,
-	 .name = "pcm0_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 13,	/* DST: PCM0 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =	/* PCM1 RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_rx",
-	 .config = {
-		    .srcPeripheralPort = 14,	/* SRC: PCM1 */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
-		    },
-	 },
-	[DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =	/* PCM1 TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "pcm1_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 15,	/* DST: PCM1 */
-		    .srcStatusRegisterAddress = 0,
-		    .dstStatusRegisterAddress = 0,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_DEV_TO_MEM] =	/* SPUM RX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_rx",
-	 .config = {
-		    .srcPeripheralPort = 6,	/* SRC: Codec A Ingress FIFO */
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    /* on the RX side, SPU needs to be the flow controller */
-		    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
-		    },
-	 },
-	[DMA_DEVICE_SPUM_MEM_TO_DEV] =	/* SPUM TX */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "spum_tx",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .dstPeripheralPort = 7,	/* DST: SPUM */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
-		    /* Busrt size **MUST** be 16 for SPUM to work */
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
-		    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
-		    },
-	 },
-	[DMA_DEVICE_MEM_TO_VRAM] =	/* MEM 2 VRAM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "mem-to-vram",
-	 .config = {
-		    .srcPeripheralPort = 0,	/* SRC: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-	[DMA_DEVICE_VRAM_TO_MEM] =	/* VRAM 2 MEM */
-	{
-	 .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
-	 .name = "vram-to-mem",
-	 .config = {
-		    .dstPeripheralPort = 0,	/* DST: memory */
-		    .srcStatusRegisterAddress = 0x00000000,
-		    .dstStatusRegisterAddress = 0x00000000,
-		    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
-		    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
-		    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-		    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
-		    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
-		    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
-		    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
-		    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
-		    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
-		    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
-		    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
-		    },
-	 },
-};
-EXPORT_SYMBOL(DMA_gDeviceAttribute);	/* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da87..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP                         BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV                     0xB0
-#define CFG_GLOBAL_RAM_SIZE                     0x10000000
-#define CFG_GLOBAL_RAM_BASE                     0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h
deleted file mode 100644
index b5beb0b..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CFG_GLOBAL_DEFINES_H
-#define CFG_GLOBAL_DEFINES_H
-
-/* CHIP */
-#define BCM1103 1
-
-#define BCM1191 4
-#define BCM2153 5
-#define BCM2820 6
-
-#define BCM2826 8
-#define FPGA11107 9
-#define BCM11107   10
-#define BCM11109   11
-#define BCM11170   12
-#define BCM11110   13
-#define BCM11211   14
-
-/* CFG_GLOBAL_CHIP_FAMILY types */
-#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
-#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
-#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
-#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
-
-#define IMAGE_HEADER_SIZE_CHECKSUM    4
-#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e5..0000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d803..0000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-   #include <linux/delay.h>
-#else
-   #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
deleted file mode 100644
index e6a1dc4..0000000
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw.h
-*
-*  @brief   API definitions for low level DMA controller driver
-*
-*/
-/****************************************************************************/
-#ifndef _DMACHW_H
-#define _DMACHW_H
-
-#include <stddef.h>
-
-#include <csp/stdint.h>
-#include <mach/csp/dmacHw_reg.h>
-
-/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
-
-   System specific channel ID should be defined as follows
-
-   For example:
-
-   #include <dmacHw.h>
-   ...
-   #define systemHw_LCD_CHANNEL_ID                dmacHw_MAKE_CHANNEL_ID(0,5)
-   #define systemHw_SWITCH_RX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,0)
-   #define systemHw_SWITCH_TX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,1)
-   #define systemHw_APM_RX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,3)
-   #define systemHw_APM_TX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,4)
-   ...
-   #define systemHw_SHARED1_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,4)
-   #define systemHw_SHARED2_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,5)
-   #define systemHw_SHARED3_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(0,6)
-   ...
-*/
-#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
-
-typedef enum {
-	dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,	/* Channel priority 0. Lowest priority DMA channel */
-	dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,	/* Channel priority 1 */
-	dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,	/* Channel priority 2 */
-	dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,	/* Channel priority 3 */
-	dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,	/* Channel priority 4 */
-	dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,	/* Channel priority 5 */
-	dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,	/* Channel priority 6 */
-	dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7	/* Channel priority 7. Highest priority DMA channel */
-} dmacHw_CHANNEL_PRIORITY_e;
-
-/* Source destination master interface */
-typedef enum {
-	dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,	/* Source DMA master interface 1 */
-	dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,	/* Source DMA master interface 2 */
-	dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,	/* Destination DMA master interface 1 */
-	dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2	/* Destination DMA master interface 2 */
-} dmacHw_MASTER_INTERFACE_e;
-
-typedef enum {
-	dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8,	/* Source 8 bit  (1 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,	/* Source 16 bit (2 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,	/* Source 32 bit (4 byte) per transaction */
-	dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,	/* Source 64 bit (8 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8,	/* Destination 8 bit  (1 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,	/* Destination 16 bit (2 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,	/* Destination 32 bit (4 byte) per transaction */
-	dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64	/* Destination 64 bit (8 byte) per transaction */
-} dmacHw_TRANSACTION_WIDTH_e;
-
-typedef enum {
-	dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,	/* Source No burst */
-	dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,	/* Source 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,	/* Source 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,	/* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,	/* Destination No burst */
-	dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,	/* Destination 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,	/* Destination 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-	dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16	/* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
-} dmacHw_BURST_WIDTH_e;
-
-typedef enum {
-	dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,	/* Memory to memory transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC,	/* Peripheral to memory transfer */
-	dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC,	/* Memory to peripheral transfer */
-	dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC	/* Peripheral to peripheral transfer */
-} dmacHw_TRANSFER_TYPE_e;
-
-typedef enum {
-	dmacHw_TRANSFER_MODE_PERREQUEST,	/* Block transfer per DMA request */
-	dmacHw_TRANSFER_MODE_CONTINUOUS,	/* Continuous transfer of streaming data */
-	dmacHw_TRANSFER_MODE_PERIODIC	/* Periodic transfer of streaming data */
-} dmacHw_TRANSFER_MODE_e;
-
-typedef enum {
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,	/* Increment source address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,	/* Decrement source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,	/* Increment destination address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,	/* Decrement destination address after every transaction */
-	dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,	/* No change in source address after every transaction */
-	dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC	/* No change in destination address after every transaction */
-} dmacHw_ADDRESS_UPDATE_MODE_e;
-
-typedef enum {
-	dmacHw_FLOW_CONTROL_DMA,	/* DMA working as flow controller (default) */
-	dmacHw_FLOW_CONTROL_PERIPHERAL	/* Peripheral working as flow controller */
-} dmacHw_FLOW_CONTROL_e;
-
-typedef enum {
-	dmacHw_TRANSFER_STATUS_BUSY,	/* DMA Transfer ongoing */
-	dmacHw_TRANSFER_STATUS_DONE,	/* DMA Transfer completed */
-	dmacHw_TRANSFER_STATUS_ERROR	/* DMA Transfer error */
-} dmacHw_TRANSFER_STATUS_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_DISABLE,	/* Interrupt disable  */
-	dmacHw_INTERRUPT_ENABLE	/* Interrupt enable */
-} dmacHw_INTERRUPT_e;
-
-typedef enum {
-	dmacHw_INTERRUPT_STATUS_NONE = 0x0,	/* No DMA interrupt */
-	dmacHw_INTERRUPT_STATUS_TRANS = 0x1,	/* End of DMA transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,	/* End of block transfer interrupt */
-	dmacHw_INTERRUPT_STATUS_ERROR = 0x4	/* Error interrupt */
-} dmacHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,	/* Number of DMA channel */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,	/* Maximum channel burst size */
-	dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,	/* Number of DMA master interface */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,	/* Channel Data bus width */
-	dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE	/* Channel FIFO size */
-} dmacHw_CONTROLLER_ATTRIB_e;
-
-typedef unsigned long dmacHw_HANDLE_t;	/* DMA channel handle */
-typedef uint32_t dmacHw_ID_t;	/* DMA channel Id.  Must be created using
-				   "dmacHw_MAKE_CHANNEL_ID" macro
-				 */
-/* DMA channel configuration parameters */
-typedef struct {
-	uint32_t srcPeripheralPort;	/* Source peripheral port */
-	uint32_t dstPeripheralPort;	/* Destination peripheral port */
-	uint32_t srcStatusRegisterAddress;	/* Source status register address */
-	uint32_t dstStatusRegisterAddress;	/* Destination status register address of type  */
-
-	uint32_t srcGatherWidth;	/* Number of bytes gathered before successive gather opearation */
-	uint32_t srcGatherJump;	/* Number of bytes jumpped before successive gather opearation */
-	uint32_t dstScatterWidth;	/* Number of bytes sacattered before successive scatter opearation */
-	uint32_t dstScatterJump;	/* Number of bytes jumpped  before successive scatter opearation */
-	uint32_t maxDataPerBlock;	/* Maximum number of bytes to be transferred per block/descrptor.
-					   0 = Maximum possible.
-					 */
-
-	dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate;	/* Source address update mode */
-	dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate;	/* Destination address update mode */
-	dmacHw_TRANSFER_TYPE_e transferType;	/* DMA transfer type  */
-	dmacHw_TRANSFER_MODE_e transferMode;	/* DMA transfer mode */
-	dmacHw_MASTER_INTERFACE_e srcMasterInterface;	/* DMA source interface  */
-	dmacHw_MASTER_INTERFACE_e dstMasterInterface;	/* DMA destination interface */
-	dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;	/* Source transaction width   */
-	dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;	/* Destination transaction width */
-	dmacHw_BURST_WIDTH_e srcMaxBurstWidth;	/* Source burst width */
-	dmacHw_BURST_WIDTH_e dstMaxBurstWidth;	/* Destination burst width */
-	dmacHw_INTERRUPT_e blockTransferInterrupt;	/* Block trsnafer interrupt */
-	dmacHw_INTERRUPT_e completeTransferInterrupt;	/* Complete DMA trsnafer interrupt */
-	dmacHw_INTERRUPT_e errorInterrupt;	/* Error interrupt */
-	dmacHw_CHANNEL_PRIORITY_e channelPriority;	/* Channel priority */
-	dmacHw_FLOW_CONTROL_e flowControler;	/* Data flow controller */
-} dmacHw_CONFIG_t;
-
-/****************************************************************************/
-/**
-*  @brief   Initializes DMA
-*
-*  This function initializes DMA CSP driver
-*
-*  @note
-*     Must be called before using any DMA channel
-*/
-/****************************************************************************/
-void dmacHw_initDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Exit function for  DMA
-*
-*  This function isolates DMA from the system
-*
-*/
-/****************************************************************************/
-void dmacHw_exitDma(void);
-
-/****************************************************************************/
-/**
-*  @brief   Gets a handle to a DMA channel
-*
-*  This function returns a handle, representing a control block of a particular DMA channel
-*
-*  @return  -1       - On Failure
-*            handle  - On Success, representing a channel control block
-*
-*  @note
-*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId	/* [ IN ] DMA Channel Id */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes a DMA channel for use
-*
-*  This function initializes and resets a DMA channel for use
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_initChannel(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
-*
-*
-*  @return  On failure : -1
-*           On success : Number of descriptor count
-*
-*
-*/
-/****************************************************************************/
-int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-				    void *pSrcAddr,	/*   [ IN ] Source (Peripheral/Memory) address */
-				    void *pDstAddr,	/*   [ IN ] Destination (Peripheral/Memory) address */
-				    size_t dataLen	/*   [ IN ] Data length in bytes */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Initializes descriptor ring
-*
-*  This function will initializes the descriptor ring of a DMA channel
-*
-*
-*  @return   -1 - On failure
-*             0 - On success
-*  @note
-*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
-*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
-*       is accessed by ARM and DMA
-*/
-/****************************************************************************/
-int dmacHw_initDescriptor(void *pDescriptorVirt,	/*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
-			  uint32_t descriptorPhyAddr,	/*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
-			  uint32_t len,	/*  [ IN ] Size of the pBuf */
-			  uint32_t num	/*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Finds amount of memory required to form a descriptor ring
-*
-*
-*  @return   Number of bytes required to form a descriptor ring
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorLen(uint32_t descCnt	/*  [ IN ] Number of descriptor in the ring */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure DMA channel
-*
-*  @return  0  : On success
-*           -1 : On failure
-*/
-/****************************************************************************/
-int dmacHw_configChannel(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle  */
-			 dmacHw_CONFIG_t *pConfig	/*   [ IN ] Configuration settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptors for known data length
-*
-*  When DMA has to work as a flow controller, this function prepares the
-*  descriptor chain to transfer data
-*
-*  from:
-*          - Memory to memory
-*          - Peripheral to memory
-*          - Memory to Peripheral
-*          - Peripheral to Peripheral
-*
-*  @return   -1 - On failure
-*             0 - On success
-*
-*/
-/****************************************************************************/
-int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-			     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			     void *pSrcAddr,	/*  [ IN ] Source (Peripheral/Memory) address */
-			     void *pDstAddr,	/*  [ IN ] Destination (Peripheral/Memory) address */
-			     size_t dataLen	/*  [ IN ] Length in bytes   */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indicates whether DMA transfer is in progress or completed
-*
-*  @return   DMA transfer status
-*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
-*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
-*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
-*
-*/
-/****************************************************************************/
-dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set descriptor carrying control information
-*
-*  This function will be used to send specific control information to the device
-*  using the DMA channel
-*
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-				void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				uint32_t ctlAddress,	/*  [ IN ] Address of the device control register  */
-				uint32_t control	/*  [ IN ] Device control information */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Read data DMA transferred to memory
-*
-*  This function will read data that has been DMAed to memory while transferring from:
-*          - Memory to memory
-*          - Peripheral to memory
-*
-*  @return  0 - No more data is available to read
-*           1 - More data might be available to read
-*
-*/
-/****************************************************************************/
-int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle    */
-			       dmacHw_CONFIG_t *pConfig,	/*  [ IN ]  Configuration settings */
-			       void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			       void **ppBbuf,	/*  [ OUT ] Data received */
-			       size_t *pLlen	/*  [ OUT ] Length of the data received */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
-*
-*  This function will form the descriptor ring by allocating buffers, when source peripheral
-*  has to work as a flow controller to transfer data from:
-*           - Peripheral to memory.
-*
-*  @return  -1 - On failure
-*            0 - On success
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle   */
-				     dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-				     void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-				     uint32_t srcAddr,	/*  [ IN ] Source peripheral address */
-				     void *(*fpAlloc) (int len),	/*  [ IN ] Function pointer  that provides destination memory */
-				     int len,	/*  [ IN ] Number of bytes "fpAlloc" will allocate for destination */
-				     int num	/*  [ IN ] Number of descriptor to set */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to initiate transfer
-*
-*  @return  void
-*
-*
-*  @note
-*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
-*     - This function should also be called from ISR to program the channel with
-*       pending descriptors
-*/
-/****************************************************************************/
-void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-			     dmacHw_CONFIG_t *pConfig,	/*   [ IN ] Configuration settings */
-			     void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Resets descriptor control information
-*
-*  @return  void
-*/
-/****************************************************************************/
-void dmacHw_resetDescriptorControl(void *pDescriptor	/*   [ IN ] Descriptor buffer  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Program channel register to stop transfer
-*
-*  Ensures the channel is not doing any transfer after calling this function
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void dmacHw_stopTransfer(dmacHw_HANDLE_t handle	/*   [ IN ] DMA Channel handle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Check the existence of pending descriptor
-*
-*  This function confirmes if there is any pending descriptor in the chain
-*  to program the channel
-*
-*  @return  1 : Channel need to be programmed with pending descriptor
-*           0 : No more pending descriptor to programe the channel
-*
-*  @note
-*     - This function should be called from ISR in case there are pending
-*       descriptor to program the channel.
-*
-*     Example:
-*
-*     dmac_isr ()
-*     {
-*         ...
-*         if (dmacHw_descriptorPending (handle))
-*         {
-*            dmacHw_initiateTransfer (handle);
-*         }
-*     }
-*
-*/
-/****************************************************************************/
-uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,	/*   [ IN ] DMA Channel handle */
-				  void *pDescriptor	/*   [ IN ] Descriptor buffer */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Deallocates source or destination memory, allocated
-*
-*  This function can be called to deallocate data memory that was DMAed successfully
-*
-*  @return  -1  - On failure
-*            0  - On success
-*
-*  @note
-*     This function will be called ONLY, when source OR destination address is pointing
-*     to dynamic memory
-*/
-/****************************************************************************/
-int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,	/*  [ IN ] Configuration settings */
-		   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-		   void (*fpFree) (void *)	/*  [ IN ] Function pointer to free data memory */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the DMA channel specific interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Returns the cause of channel specific DMA interrupt
-*
-*  This function returns the cause of interrupt
-*
-*  @return  Interrupt status, each bit representing a specific type of interrupt
-*           of type dmacHw_INTERRUPT_STATUS_e
-*  @note
-*           This function should be called under the context of ISR
-*/
-/****************************************************************************/
-dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a DMA channel causing interrupt
-*
-*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
-*
-*  @return  NULL   : No channel causing DMA interrupt
-*           ! NULL : Handle to a channel causing DMA interrupt
-*  @note
-*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
-*/
-/****************************************************************************/
-dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Sets channel specific user data
-*
-*  This function associates user data to a specific DMA channel
-*
-*/
-/****************************************************************************/
-void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle  */
-			       void *userData	/*  [ IN ] User data  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Gets channel specific user data
-*
-*  This function returns user data specific to a DMA channel
-*
-*  @return   user data
-*/
-/****************************************************************************/
-void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle	/*  [ IN ] DMA Channel handle  */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Displays channel specific registers and other control parameters
-*
-*
-*  @return  void
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,	/*  [ IN ] DMA Channel handle  */
-			   void *pDescriptor,	/*  [ IN ] Descriptor buffer  */
-			   int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Provides DMA controller attributes
-*
-*
-*  @return  DMA controller attributes
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,	/*  [ IN ]  DMA Channel handle  */
-					  dmacHw_CONTROLLER_ATTRIB_e attr	/*  [ IN ]  DMA Controller attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
-    );
-
-#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd..0000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if   defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8..0000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-*  @file    intcHw.h
-*
-*  @brief   generic interrupt controller API
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5..0000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-    #include <linux/module.h>
-#else
-    #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
deleted file mode 100644
index 56654d2..0000000
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    reg.h
-*
-*  @brief   Generic register definitions used in CSP
-*/
-/****************************************************************************/
-
-#ifndef CSP_REG_H
-#define CSP_REG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-
-/* Macros used to define a sequence of reserved registers. The start / end */
-/* are byte offsets in the particular register definition, with the "end" */
-/* being the offset of the next un-reserved register. E.g. if offsets */
-/* 0x10 through to 0x1f are reserved, then this reserved area could be */
-/* specified as follows. */
-/*  typedef struct */
-/*  { */
-/*      uint32_t reg1;           offset 0x00 */
-/*      uint32_t reg2;           offset 0x04 */
-/*      uint32_t reg3;           offset 0x08 */
-/*      uint32_t reg4;           offset 0x0c */
-/*      REG32_RSVD(0x10, 0x20); */
-/*      uint32_t reg5;           offset 0x20 */
-/*      ... */
-/*  } EXAMPLE_REG_t; */
-#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
-#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
-#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
-/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
-/* flags variable to be declared locally. */
-/* e.g. */
-/*    statement1; */
-/*    { */
-/*       REG_LOCAL_IRQ_SAVE; */
-/*       <multiple statements here> */
-/*       REG_LOCAL_IRQ_RESTORE; */
-/*    } */
-/*    statement2; */
-/*  */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <mach/hardware.h>
-#include <linux/interrupt.h>
-
-#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
-	unsigned long flags; HW_IRQ_SAVE(reg32, flags)
-
-#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
-
-#else
-
-#define REG_LOCAL_IRQ_SAVE
-#define REG_LOCAL_IRQ_RESTORE
-
-#endif
-
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg &= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg |= value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
-				     uint32_t value)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*reg = (*reg & mask) | value;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-	*reg = value;
-}
-
-#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e07..0000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw.h
-*
-*  @brief   Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
-	secHw_MODE_SECURE = 0x0,	/* Switches processor into secure mode */
-	secHw_MODE_NONSECURE = 0x1	/* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-*  @brief   Requesting to execute the function in secure mode
-*
-*  This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t	/* Function to run in secure mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Sets the  mode
-*
-*  his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE	/* Processor mode */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get the current mode
-*
-*  This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718b..0000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e400..0000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-   #include <linux/string.h>
-#else
-   #include <string.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h
deleted file mode 100644
index 2cbb530..0000000
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw.h
-*
-*  @brief   API definitions for low level Timer driver
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_H
-#define _TMRHW_H
-
-#include <csp/stdint.h>
-
-typedef uint32_t tmrHw_ID_t;	/* Timer ID */
-typedef uint32_t tmrHw_COUNT_t;	/* Timer count */
-typedef uint32_t tmrHw_INTERVAL_t;	/* Timer interval */
-typedef uint32_t tmrHw_RATE_t;	/* Timer event (count/interrupt) rate */
-
-typedef enum {
-	tmrHw_INTERRUPT_STATUS_SET,	/* Interrupted  */
-	tmrHw_INTERRUPT_STATUS_UNSET	/* No Interrupt */
-} tmrHw_INTERRUPT_STATUS_e;
-
-typedef enum {
-	tmrHw_CAPABILITY_CLOCK,	/* Clock speed in HHz */
-	tmrHw_CAPABILITY_RESOLUTION	/* Timer resolution in bits */
-} tmrHw_CAPABILITY_e;
-
-/****************************************************************************/
-/**
-*  @brief   Get timer capability
-*
-*  This function returns various capabilities/attributes of a timer
-*
-*  @return  Numeric capability
-*
-*/
-/****************************************************************************/
-uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-				  tmrHw_CAPABILITY_e capability	/*  [ IN ] Timer capability */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer in terms of timer interrupt rate
-*
-*  This function initializes a periodic timer to generate specific number of
-*  timer interrupt per second
-*
-*  @return   On success: Effective timer frequency
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-					tmrHw_RATE_t rate	/*  [ IN ] Number of timer interrupt per second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt after
-*           certain time interval
-*
-*  This function initializes a periodic timer to generate timer interrupt
-*  after every time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-						tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a periodic timer to generate timer interrupt just once
-*           after certain time interval
-*
-*  This function initializes a periodic timer to generate a single ticks after
-*  certain time interval in millisecond
-*
-*  @return   On success: Effective interval set in mili-second
-*            On failure: 0
-*
-*/
-/****************************************************************************/
-tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-					       tmrHw_INTERVAL_t msec	/*  [ IN ] Interval in mili-second */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Configures a timer to run as a free running timer
-*
-*  This function initializes a timer to run as a free running timer
-*
-*  @return   Timer resolution (count / sec)
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,	/*  [ IN ] Timer Id */
-				       uint32_t divider	/*  [ IN ] Dividing the clock frequency */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Starts a timer
-*
-*  This function starts a preconfigured timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_startTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Stops a timer
-*
-*  This function stops a running timer
-*
-*  @return  -1     - On Failure
-*            0     - On Success
-*/
-/****************************************************************************/
-int tmrHw_stopTimer(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets current timer count
-*
-*  This function returns the current timer value
-*
-*  @return  Current downcounting timer value
-*
-*/
-/****************************************************************************/
-tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Gets timer count rate
-*
-*  This function returns the number of counts per second
-*
-*  @return  Count rate
-*
-*/
-/****************************************************************************/
-tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Enables timer interrupt
-*
-*  This function enables the timer interrupt
-*
-*  @return   N/A
-*
-*/
-/****************************************************************************/
-void tmrHw_enableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Disables timer interrupt
-*
-*  This function disable the timer interrupt
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_disableInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Clears the interrupt
-*
-*  This function clears the timer interrupt
-*
-*  @return   N/A
-*
-*  @note
-*     Must be called under the context of ISR
-*/
-/****************************************************************************/
-void tmrHw_clearInterrupt(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Gets the interrupt status
-*
-*  This function returns timer interrupt status
-*
-*  @return   Interrupt status
-*/
-/****************************************************************************/
-tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId	/*  [ IN ] Timer id */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Indentifies a timer causing interrupt
-*
-*  This functions returns a timer causing interrupt
-*
-*  @return  0xFFFFFFFF   : No timer causing an interrupt
-*           ! 0xFFFFFFFF : timer causing an interrupt
-*  @note
-*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
-*/
-/****************************************************************************/
-tmrHw_ID_t tmrHw_getInterruptSource(void);
-
-/****************************************************************************/
-/**
-*  @brief   Displays specific timer registers
-*
-*
-*  @return  void
-*
-*/
-/****************************************************************************/
-void tmrHw_printDebugInfo(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-			  int (*fpPrint) (const char *, ...)	/*  [ IN ] Print callback function */
-);
-
-/****************************************************************************/
-/**
-*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
-*
-*  @return   N/A
-*/
-/****************************************************************************/
-void tmrHw_udelay(tmrHw_ID_t timerId,	/*  [ IN ] Timer id */
-		  unsigned long usecs	/*  [ IN ] usec to delay */
-) __attribute__ ((section(".aramtext")));
-
-#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
deleted file mode 100644
index 30fa2d5..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_H
-#define CAP_H
-
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Public Constants and Types --------------------------------------- */
-typedef enum {
-	CAP_NOT_PRESENT = 0,
-	CAP_PRESENT
-} CAP_RC_T;
-
-typedef enum {
-	CAP_VPM,
-	CAP_ETH_PHY,
-	CAP_ETH_GMII,
-	CAP_ETH_SGMII,
-	CAP_USB,
-	CAP_TSC,
-	CAP_EHSS,
-	CAP_SDIO,
-	CAP_UARTB,
-	CAP_KEYPAD,
-	CAP_CLCD,
-	CAP_GE,
-	CAP_LEDM,
-	CAP_BBL,
-	CAP_VDEC,
-	CAP_PIF,
-	CAP_APM,
-	CAP_SPU,
-	CAP_PKA,
-	CAP_RNG,
-} CAP_CAPABILITY_T;
-
-typedef enum {
-	CAP_LCD_WVGA = 0,
-	CAP_LCD_VGA = 0x1,
-	CAP_LCD_WQVGA = 0x2,
-	CAP_LCD_QVGA = 0x3
-} CAP_LCD_RES_T;
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
-static inline uint32_t cap_getMaxArmSpeedHz(void);
-static inline uint32_t cap_getMaxVpmSpeedHz(void);
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
deleted file mode 100644
index 933ce68..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*****************************************************************************
-* Copyright 2009 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CAP_INLINE_H
-#define CAP_INLINE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/cap.h>
-#include <cfg_global.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-#define CAP_CONFIG0_VPM_DIS          0x00000001
-#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
-#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
-#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
-#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
-#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
-#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
-#define CAP_CONFIG0_USB0_DIS         0x00000080
-#define CAP_CONFIG0_USB1_DIS         0x00000100
-#define CAP_CONFIG0_TSC_DIS          0x00000200
-#define CAP_CONFIG0_EHSS0_DIS        0x00000400
-#define CAP_CONFIG0_EHSS1_DIS        0x00000800
-#define CAP_CONFIG0_SDIO0_DIS        0x00001000
-#define CAP_CONFIG0_SDIO1_DIS        0x00002000
-#define CAP_CONFIG0_UARTB_DIS        0x00004000
-#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
-#define CAP_CONFIG0_CLCD_DIS         0x00010000
-#define CAP_CONFIG0_GE_DIS           0x00020000
-#define CAP_CONFIG0_LEDM_DIS         0x00040000
-#define CAP_CONFIG0_BBL_DIS          0x00080000
-#define CAP_CONFIG0_VDEC_DIS         0x00100000
-#define CAP_CONFIG0_PIF_DIS          0x00200000
-#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
-#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
-
-#define CAP_CONFIG1_APMA_DIS         0x00000001
-#define CAP_CONFIG1_APMB_DIS         0x00000002
-#define CAP_CONFIG1_APMC_DIS         0x00000004
-#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
-#define CAP_CONFIG1_CLCD_RES_SHIFT   9
-#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
-
-#define CAP_CONFIG2_SPU_DIS          0x00000010
-#define CAP_CONFIG2_PKA_DIS          0x00000020
-#define CAP_CONFIG2_RNG_DIS          0x00000080
-
-#if   (CFG_GLOBAL_CHIP == BCM11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == FPGA11107)
-#define capConfig0 0
-#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 3
-#elif (CFG_GLOBAL_CHIP == BCM11109)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11170)
-#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11110)
-#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
-#define CAP_APM_MAX_NUM_CHANS 2
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
-#define capConfig1 CAP_CONFIG1_APMC_DIS
-#define capConfig2 0
-#define CAP_APM_MAX_NUM_CHANS 2
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_ARM_CLK_HZ 500000000
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_ARM_CLK_HZ 300000000
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-#define CAP_HW_CFG_ARM_CLK_HZ 666666666
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-#define CAP_HW_CFG_VPM_CLK_HZ 333333333
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-#define CAP_HW_CFG_VPM_CLK_HZ 200000000
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************
-*  cap_isPresent -
-*
-*  PURPOSE:
-*     Determines if the chip has a certain capability present
-*
-*  PARAMETERS:
-*     capability - type of capability to determine if present
-*
-*  RETURNS:
-*     CAP_PRESENT or CAP_NOT_PRESENT
-****************************************************************************/
-static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
-{
-	CAP_RC_T returnVal = CAP_NOT_PRESENT;
-
-	switch (capability) {
-	case CAP_VPM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_PHY:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_GMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_ETH_SGMII:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_USB:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_TSC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_EHSS:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SDIO:
-		{
-			if ((index == 0)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_UARTB:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_KEYPAD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_CLCD:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_GE:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_LEDM:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_BBL:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_VDEC:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PIF:
-		{
-			if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_APM:
-		{
-			if ((index == 0)
-			    && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 1)
-			    && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-			if ((index == 2)
-			    && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_SPU:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_PKA:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	case CAP_RNG:
-		{
-			if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
-				returnVal = CAP_PRESENT;
-			}
-		}
-		break;
-
-	default:
-		{
-		}
-		break;
-	}
-	return returnVal;
-}
-
-/****************************************************************************
-*  cap_getMaxArmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the ARM CPU
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the ARM processor is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxArmSpeedHz(void)
-{
-#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
-	return 500000000;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-	return 300000000;
-#elif (CFG_GLOBAL_CHIP == BCM11211)
-	return 666666666;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxVpmSpeedHz -
-*
-*  PURPOSE:
-*     Determines the maximum speed of the VPM
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*     clock speed in Hz that the VPM is able to run at
-****************************************************************************/
-static inline uint32_t cap_getMaxVpmSpeedHz(void)
-{
-#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
-	return 333333333;
-#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
-	return 200000000;
-#else
-#error CFG_GLOBAL_CHIP type capabilities not defined
-#endif
-}
-
-/****************************************************************************
-*  cap_getMaxLcdRes -
-*
-*  PURPOSE:
-*     Determines the maximum LCD resolution capabilities
-*
-*  PARAMETERS:
-*     none
-*
-*  RETURNS:
-*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
-*
-****************************************************************************/
-static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
-{
-	return (CAP_LCD_RES_T)
-		((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
-		 CAP_CONFIG1_CLCD_RES_SHIFT);
-}
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
deleted file mode 100644
index 1619733..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ /dev/null
@@ -1,1123 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_DEF_H
-#define CHIPC_DEF_H
-
-/* ---- Include Files ----------------------------------------------------- */
-
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-
-/* ---- Public Constants and Types ---------------------------------------- */
-
-/* Set 1 to configure DDR/VPM phase alignment by HW */
-#define chipcHw_DDR_HW_PHASE_ALIGN    0
-#define chipcHw_VPM_HW_PHASE_ALIGN    0
-
-typedef uint32_t chipcHw_freq;
-
-/* Configurable miscellaneous clocks */
-typedef enum {
-	chipcHw_CLOCK_DDR,	/* DDR PHY Clock */
-	chipcHw_CLOCK_ARM,	/* ARM Clock */
-	chipcHw_CLOCK_ESW,	/* Ethernet Switch Clock */
-	chipcHw_CLOCK_VPM,	/* VPM Clock */
-	chipcHw_CLOCK_ESW125,	/* Ethernet MII Clock */
-	chipcHw_CLOCK_UART,	/* UART Clock */
-	chipcHw_CLOCK_SDIO0,	/* SDIO 0 Clock */
-	chipcHw_CLOCK_SDIO1,	/* SDIO 1 Clock */
-	chipcHw_CLOCK_SPI,	/* SPI Clock */
-	chipcHw_CLOCK_ETM,	/* ARM ETM Clock */
-
-	chipcHw_CLOCK_BUS,	/* BUS Clock */
-	chipcHw_CLOCK_OTP,	/* OTP Clock */
-	chipcHw_CLOCK_I2C,	/* I2C Host Clock */
-	chipcHw_CLOCK_I2S0,	/* I2S 0 Host Clock */
-	chipcHw_CLOCK_RTBUS,	/* DDR PHY Configuration Clock */
-	chipcHw_CLOCK_APM100,	/* APM100 Clock */
-	chipcHw_CLOCK_TSC,	/* Touch screen Clock */
-	chipcHw_CLOCK_LED,	/* LED Clock */
-
-	chipcHw_CLOCK_USB,	/* USB Clock */
-	chipcHw_CLOCK_LCD,	/* LCD CLock */
-	chipcHw_CLOCK_APM,	/* APM Clock */
-
-	chipcHw_CLOCK_I2S1,	/* I2S 1 Host Clock */
-} chipcHw_CLOCK_e;
-
-/* System booting strap options */
-typedef enum {
-	chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
-	chipcHw_BOOT_DEVICE_SERIAL_FLASH =
-	    chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
-	chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
-	chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
-	    chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
-} chipcHw_BOOT_DEVICE_e;
-
-/* System booting modes */
-typedef enum {
-	chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
-	chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
-	chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
-	chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
-} chipcHw_BOOT_MODE_e;
-
-/* NAND Flash page size strap options */
-typedef enum {
-	chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
-	chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
-	chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
-	chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
-} chipcHw_NAND_PAGESIZE_e;
-
-/* GPIO Pin function */
-typedef enum {
-	chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
-	chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
-	chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
-	chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
-	chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
-	chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
-	chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
-	chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
-	chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
-	chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
-	chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
-	chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
-	chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
-	chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
-} chipcHw_GPIO_FUNCTION_e;
-
-/* PIN Output slew rate */
-typedef enum {
-	chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
-	chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
-} chipcHw_PIN_SLEW_RATE_e;
-
-/* PIN Current drive strength */
-typedef enum {
-	chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
-	chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
-	chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
-	chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
-	chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
-	chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
-} chipcHw_PIN_CURRENT_STRENGTH_e;
-
-/* PIN Pull up register settings */
-typedef enum {
-	chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
-	chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
-	chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
-} chipcHw_PIN_PULL_e;
-
-/* PIN input type settings */
-typedef enum {
-	chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
-	chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
-} chipcHw_PIN_INPUTTYPE_e;
-
-/* Allow/Disalow the support of spread spectrum  */
-typedef enum {
-	chipcHw_SPREAD_SPECTRUM_DISALLOW,	/* Spread spectrum support is not allowed */
-	chipcHw_SPREAD_SPECTRUM_ALLOW	/* Spread spectrum support is allowed */
-} chipcHw_SPREAD_SPECTRUM_e;
-
-typedef struct {
-	chipcHw_SPREAD_SPECTRUM_e ssSupport;	/* Allow/Disalow to support spread spectrum.
-						   If supported, call chipcHw_enableSpreadSpectrum ()
-						   to activate the spread spectrum with desired spread. */
-	uint32_t pllVcoFreqHz;	/* PLL VCO frequency in Hz */
-	uint32_t pll2VcoFreqHz;	/* PLL2 VCO frequency in Hz */
-	uint32_t busClockFreqHz;	/* Bus clock frequency in Hz */
-	uint32_t armBusRatio;	/* ARM clock : Bus clock */
-	uint32_t vpmBusRatio;	/* VPM clock : Bus clock */
-	uint32_t ddrBusRatio;	/* DDR clock : Bus clock */
-} chipcHw_INIT_PARAM_t;
-
-/* CHIP revision number */
-typedef enum {
-	chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
-	chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
-} chipcHw_REV_NUMBER_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
-	chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
-	chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
-	chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
-} chipcHw_VPM_HW_PHASE_INTR_e;
-
-typedef enum {
-	chipcHw_DDR_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for DDR phase align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for DDR phase align condition */
-	chipcHw_DDR_HW_PHASE_MARGIN_WIDE	/*  Wider margin for DDR phase align condition */
-} chipcHw_DDR_HW_PHASE_MARGIN_e;
-
-typedef enum {
-	chipcHw_VPM_HW_PHASE_MARGIN_STRICT,	/*  Strict margin for VPM phase align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,	/*  Medium margin for VPM phase align condition */
-	chipcHw_VPM_HW_PHASE_MARGIN_WIDE	/*  Wider margin for VPM phase align condition */
-} chipcHw_VPM_HW_PHASE_MARGIN_e;
-
-#define chipcHw_XTAL_FREQ_Hz                    25000000	/* Reference clock frequency in Hz */
-
-/* Programmable pin defines */
-#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
-									     /* GPIO pin 0 - 60 */
-#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)	/* UART Transmit */
-#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)	/* NVI Interface */
-#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)	/* NVI Interface */
-#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)	/* NVI Interface */
-#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)	/* NVI Interface */
-#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)	/* NVI Interface */
-#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)	/* NVI Interface */
-#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)	/* NVI Interface */
-#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)	/* LCD Data 0 - 17 */
-#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)	/* LCD Data 18 - 20 */
-#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)	/* LCD Data 21 - 23 */
-#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)	/* LCD Power */
-#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)	/* LCD Ack */
-#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)	/* LCD FP */
-#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)	/* LCD LP */
-#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)	/* UART Receive */
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************/
-/**
-*  @brief  Initializes the clock module
-*
-*/
-/****************************************************************************/
-void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam	/*  [ IN ] Misc chip initialization parameter */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL1
-*
-*  This function enables the PLL1
-*
-*/
-/****************************************************************************/
-void chipcHw_pll1Enable(uint32_t vcoFreqHz,	/*  [ IN ] VCO frequency in Hz */
-			chipcHw_SPREAD_SPECTRUM_e ssSupport	/*  [ IN ] SS status */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Enables the PLL2
-*
-*  This function enables the PLL2
-*
-*/
-/****************************************************************************/
-void chipcHw_pll2Enable(uint32_t vcoFreqHz	/*  [ IN ] VCO frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in KHz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set clock fequency for miscellaneous configurable clocks
-*
-*  This function sets clock frequency
-*
-*  @return  Configured clock frequency in Hz
-*
-*/
-/****************************************************************************/
-chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,	/*  [ IN ] Configurable clock */
-				       uint32_t freq	/*  [ IN ] Clock frequency in Hz */
-    ) __attribute__ ((section(".aramtext")));
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM clock in sync with BUS clock
-*
-*  This function does the phase adjustment between VPM and BUS clock
-*
-*  @return >= 0 : On success ( # of adjustment required )
-*            -1 : On failure
-*/
-/****************************************************************************/
-int chipcHw_vpmPhaseAlign(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables core a clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @return  void
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock	/*  [ IN ] Configurable clock */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask	/*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask	/*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask	/*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask	/*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask	/*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetDisable(uint64_t mask	/*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-static inline void chipcHw_softResetEnable(uint64_t mask	/*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask	/*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlDisable(uint32_t mask	/*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-static inline void chipcHw_miscControlEnable(uint32_t mask	/*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask	/*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask	/*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask	/*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief    Get software override strap options
-*
-*  Retrieves software override strap options
-*
-*  @return   Software override strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
-
-/****************************************************************************/
-/**
-*  @brief    Get pin strap options
-*
-*  Retrieves pin strap options
-*
-*  @return   Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Get valid pin strap options
-*
-*  Retrieves valid pin strap options
-*
-*  @return   valid Pin strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE_e
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin	/* GPIO Pin number */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,	/* GPIO Pin number */
-					      chipcHw_GPIO_FUNCTION_e func	/* Configuration function */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,	/* Pin of type chipcHw_PIN_XXXXX */
-					  chipcHw_PIN_SLEW_RATE_e slewRate	/* Pin slew rate */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,	/* Pin of type chipcHw_PIN_XXXXX */
-					       chipcHw_PIN_CURRENT_STRENGTH_e curr	/* Pin current rating */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual  pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin,	/* Pin of type chipcHw_PIN_XXXXX */
-					chipcHw_PIN_PULL_e pullup	/* Pullup register settings */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual Pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,	/* Pin of type chipcHw_PIN_XXXXX */
-					   chipcHw_PIN_INPUTTYPE_e inputType	/* Pin input type */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Retrieves a string representation of the mux setting for a pin.
-*
-*  @return  Pointer to a character string.
-*/
-/****************************************************************************/
-
-const char *chipcHw_getGpioPinFunctionStr(int pin);
-
-/****************************************************************************/
-/**  @brief issue warmReset
- */
-/****************************************************************************/
-void chipcHw_reset(uint32_t mask);
-
-/****************************************************************************/
-/**  @brief clock reconfigure
- */
-/****************************************************************************/
-void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
-			   uint32_t ddrRatio);
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void);
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void);
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void);
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void);
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val);
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void);
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin	/* Margin alinging DDR  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin	/* Margin alinging VPM  phase */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle	/* Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle	/* Timeout in bus cycle */
-    );
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
-
-/* ---- Private Constants and Types -------------------------------------- */
-
-#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
deleted file mode 100644
index 03238c2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ /dev/null
@@ -1,1673 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CHIPC_INLINE_H
-#define CHIPC_INLINE_H
-
-/* ---- Include Files ----------------------------------------------------- */
-
-#include <csp/errno.h>
-#include <csp/reg.h>
-#include <mach/csp/chipcHw_reg.h>
-#include <mach/csp/chipcHw_def.h>
-
-/* ---- Private Constants and Types --------------------------------------- */
-typedef enum {
-	chipcHw_OPTYPE_BYPASS,	/* Bypass operation */
-	chipcHw_OPTYPE_OUTPUT	/* Output operation */
-} chipcHw_OPTYPE_e;
-
-/* ---- Public Constants and Types ---------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------- */
-/* ---- Public Function Prototypes ---------------------------------------- */
-/* ---- Private Function Prototypes --------------------------------------- */
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode);
-
-/****************************************************************************/
-/**
-*  @brief   Get Numeric Chip ID
-*
-*  This function returns Chip ID that includes the revison number
-*
-*  @return  Complete numeric Chip ID
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipId(void)
-{
-	return pChipcHw->ChipId;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable Spread Spectrum
-*
-*  @note chipcHw_Init() must be called earlier
-*/
-/****************************************************************************/
-static inline void chipcHw_enableSpreadSpectrum(void)
-{
-	if ((pChipcHw->
-	     PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
-	    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
-		    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
-		    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
-		     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
-		ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
-		    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable Spread Spectrum
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_disableSpreadSpectrum(void)
-{
-	ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Chip Product ID
-*
-*  This function returns Chip Product ID
-*
-*  @return  Chip Product ID
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getChipProductId(void)
-{
-	return (pChipcHw->
-		 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
-		chipcHw_REG_CHIPID_BASE_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get revision number
-*
-*  This function returns revision number of the chip
-*
-*  @return  Revision number
-*/
-/****************************************************************************/
-static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
-{
-	return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bus interface clock
-*
-*  Enables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->BusIntfClock, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables bus interface clock
-*
-*  Disables  bus interface clock of various device
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get status (enabled/disabled) of bus interface clock
-*
-*  This function returns the status of devices' bus interface clock
-*
-*  @return  Bus interface clock
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
-{
-	return pChipcHw->BusIntfClock;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables various audio channels
-*
-*  Enables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->AudioEnable, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables various audio channels
-*
-*  Disables audio channel
-*
-*  @return  void
-*
-*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_audioChannelDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Soft resets devices
-*
-*  Soft resets various devices
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
-*/
-/****************************************************************************/
-static inline void chipcHw_softReset(uint64_t mask)
-{
-	chipcHw_softResetEnable(mask);
-	chipcHw_softResetDisable(mask);
-}
-
-static inline void chipcHw_softResetDisable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	/* Deassert module soft reset */
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 ^= ctrl1;
-	pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-static inline void chipcHw_softResetEnable(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-	uint32_t unhold = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->SoftReset1 |= ctrl1;
-	/* Mask out unhold request bits */
-	pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
-
-	/* Process unhold requests */
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
-		unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
-	}
-
-	if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
-		unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
-	}
-
-	if (unhold) {
-		/* Make sure unhold request is effective */
-		pChipcHw->SoftReset1 &= ~unhold;
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Configures misc CHIP functionality
-*
-*  Configures CHIP functionality
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_miscControl(uint32_t mask)
-{
-	reg32_write(&pChipcHw->MiscCtrl, mask);
-}
-
-static inline void chipcHw_miscControlDisable(uint32_t mask)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
-}
-
-static inline void chipcHw_miscControlEnable(uint32_t mask)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, mask);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set OTP options
-*
-*  Set OTP options
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_OTP_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setOTPOption(uint64_t mask)
-{
-	uint32_t ctrl1 = (uint32_t) mask;
-	uint32_t ctrl2 = (uint32_t) (mask >> 32);
-
-	reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
-	reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get sticky bits
-*
-*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getStickyBits(void)
-{
-	return pChipcHw->Sticky;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_setStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask & chipcHw_REG_STICKY_POR_BROM) {
-		bits |= chipcHw_REG_STICKY_POR_BROM;
-	} else {
-		uint32_t sticky;
-		sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
-			bits |= chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Clear sticky bits
-*
-*  @return   void
-*
-*  @note     use chipcHw_REG_STICKY_XXXXXX
-*/
-/****************************************************************************/
-static inline void chipcHw_clearStickyBits(uint32_t mask)
-{
-	uint32_t bits = 0;
-
-	REG_LOCAL_IRQ_SAVE;
-	if (mask &
-	    (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
-	     chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
-	     chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
-		uint32_t sticky = pChipcHw->Sticky;
-
-		if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
-		    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
-			bits = chipcHw_REG_STICKY_BOOT_DONE;
-			mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_1)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_1;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_1;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_2)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_2;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_2;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_3)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_3;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_3;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_4)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_4;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_4;
-		}
-		if ((mask & chipcHw_REG_STICKY_GENERAL_5)
-		    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
-			bits |= chipcHw_REG_STICKY_GENERAL_5;
-			mask &= ~chipcHw_REG_STICKY_GENERAL_5;
-		}
-	}
-	pChipcHw->Sticky = bits | mask;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Get software strap value
-*
-*  Retrieves software strap value
-*
-*  @return   Software strap value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getSoftStraps(void)
-{
-	return pChipcHw->SoftStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Set software override strap options
-*
-*  set software override strap options
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
-{
-	reg32_write(&pChipcHw->SoftStraps, strapOptions);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Pin Strap Options
-*
-*  This function returns the raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getPinStraps(void)
-{
-	return pChipcHw->PinStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get Valid Strap Options
-*
-*  This function returns the valid raw boot strap options
-*
-*  @return  strap options
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getValidStraps(void)
-{
-	uint32_t softStraps;
-
-	/*
-	 ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
-	 ** which copies HW straps to soft straps if there is no override
-	 */
-	softStraps = chipcHw_getSoftStraps();
-
-	return softStraps;
-}
-
-/****************************************************************************/
-/**
-*  @brief    Initialize valid pin strap options
-*
-*  Retrieves valid pin strap options by copying HW strap options to soft register
-*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
-*
-*  @return   nothing
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_initValidStraps(void)
-{
-	uint32_t softStraps;
-
-	REG_LOCAL_IRQ_SAVE;
-	softStraps = chipcHw_getSoftStraps();
-
-	if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
-		/* Copy HW straps to software straps */
-		chipcHw_setSoftStraps(chipcHw_getPinStraps());
-	}
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot device
-*
-*  This function returns the device type used in booting the system
-*
-*  @return  Boot device of type chipcHw_BOOT_DEVICE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get boot mode
-*
-*  This function returns the way the system was booted
-*
-*  @return  Boot mode of type chipcHw_BOOT_MODE
-*
-*/
-/****************************************************************************/
-static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash page size
-*
-*  This function returns the NAND device page size
-*
-*  @return  Boot NAND device page size
-*
-*/
-/****************************************************************************/
-static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
-{
-	return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get NAND flash address cycle configuration
-*
-*  This function returns the NAND flash address cycle configuration
-*
-*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
-*
-*/
-/****************************************************************************/
-static inline int chipcHw_getNandExtraCycle(void)
-{
-	if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates PIF interface
-*
-*  This function activates PIF interface by taking control of LCD pins
-*
-*  @note
-*       When activated, LCD pins will be defined as follows for PIF operation
-*
-*       CLD[17:0]  = pif_data[17:0]
-*       CLD[23:18] = pif_address[5:0]
-*       CLPOWER    = pif_wr_str
-*       CLCP       = pif_rd_str
-*       CLAC       = pif_hat1
-*       CLFP       = pif_hrdy1
-*       CLLP       = pif_hat2
-*       GPIO[42]   = pif_hrdy2
-*
-*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_activatePifInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Activates LCD interface
-*
-*  This function activates LCD interface
-*
-*  @note
-*       When activated, LCD pins will be defined as follows
-*
-*       CLD[17:0]  = LCD data
-*       CLD[23:18] = LCD data
-*       CLPOWER    = LCD power
-*       CLCP       =
-*       CLAC       = LCD ack
-*       CLFP       =
-*       CLLP       =
-*/
-/****************************************************************************/
-static inline void chipcHw_activateLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Deactivates PIF/LCD interface
-*
-*  This function deactivates PIF/LCD interface
-*
-*  @note
-*       When deactivated LCD pins will be in rti-stated
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_deactivatePifLcdInterface(void)
-{
-	reg32_write(&pChipcHw->LcdPifMode, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE2
-*
-*  This function select GE2 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE2(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Select GE3
-*
-*  This function select GE3 as the graphic engine
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_selectGE3(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get to know the configuration of GPIO pin
-*
-*/
-/****************************************************************************/
-static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
-{
-	return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
-		(chipcHw_REG_GPIO_MUX_MASK <<
-		 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
-	    chipcHw_REG_GPIO_MUX_POSITION(pin);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Configure GPIO pin function
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setGpioPinFunction(int pin,
-					      chipcHw_GPIO_FUNCTION_e func)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
-	    ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
-	    func << chipcHw_REG_GPIO_MUX_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin slew rate
-*
-*  This function sets the slew of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinSlewRate(uint32_t pin,
-					  chipcHw_PIN_SLEW_RATE_e slewRate)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
-	    ~(chipcHw_REG_SLEW_RATE_MASK <<
-	      chipcHw_REG_SLEW_RATE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
-	    (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin output drive current
-*
-*  This function sets output drive current of individual pin
-*
-*  Note: Avoid the use of the word 'current' since linux headers define this
-*        to be the current task.
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
-					       chipcHw_PIN_CURRENT_STRENGTH_e
-					       curr)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
-	    ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
-	    (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin pullup register
-*
-*  This function sets pullup register of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
-	    ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
-	    (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set Pin input type
-*
-*  This function sets input type of individual pin
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setPinInputType(uint32_t pin,
-					   chipcHw_PIN_INPUTTYPE_e inputType)
-{
-	REG_LOCAL_IRQ_SAVE;
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
-	    ~(chipcHw_REG_INPUTTYPE_MASK <<
-	      chipcHw_REG_INPUTTYPE_POSITION(pin));
-	*((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
-	    (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power up the USB PHY
-*
-*  This function powers up the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerUpUsbPhy(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_POWERON);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Power down the USB PHY
-*
-*  This function powers down the USB PHY
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_powerDownUsbPhy(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_POWEROFF);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as host
-*
-*  This function sets the 2nd USB as host
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbHost(void)
-{
-	reg32_modify_or(&pChipcHw->MiscCtrl,
-			chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set the 2nd USB as device
-*
-*  This function sets the 2nd USB as device
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setUsbDevice(void)
-{
-	reg32_modify_and(&pChipcHw->MiscCtrl,
-			 chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Lower layer function to enable/disable a clock of a certain device
-*
-*  This function enables/disables a core clock
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
-				    chipcHw_OPTYPE_e type, int mode)
-{
-	volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
-	volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
-
-	switch (clock) {
-	case chipcHw_CLOCK_DDR:
-		pPLLReg = &pChipcHw->DDRClock;
-		break;
-	case chipcHw_CLOCK_ARM:
-		pPLLReg = &pChipcHw->ARMClock;
-		break;
-	case chipcHw_CLOCK_ESW:
-		pPLLReg = &pChipcHw->ESWClock;
-		break;
-	case chipcHw_CLOCK_VPM:
-		pPLLReg = &pChipcHw->VPMClock;
-		break;
-	case chipcHw_CLOCK_ESW125:
-		pPLLReg = &pChipcHw->ESW125Clock;
-		break;
-	case chipcHw_CLOCK_UART:
-		pPLLReg = &pChipcHw->UARTClock;
-		break;
-	case chipcHw_CLOCK_SDIO0:
-		pPLLReg = &pChipcHw->SDIO0Clock;
-		break;
-	case chipcHw_CLOCK_SDIO1:
-		pPLLReg = &pChipcHw->SDIO1Clock;
-		break;
-	case chipcHw_CLOCK_SPI:
-		pPLLReg = &pChipcHw->SPIClock;
-		break;
-	case chipcHw_CLOCK_ETM:
-		pPLLReg = &pChipcHw->ETMClock;
-		break;
-	case chipcHw_CLOCK_USB:
-		pPLLReg = &pChipcHw->USBClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_LCD:
-		pPLLReg = &pChipcHw->LCDClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_APM:
-		pPLLReg = &pChipcHw->APMClock;
-		if (type == chipcHw_OPTYPE_OUTPUT) {
-			if (mode) {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			} else {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_POWER_DOWN);
-			}
-		}
-		break;
-	case chipcHw_CLOCK_BUS:
-		pClockCtrl = &pChipcHw->ACLKClock;
-		break;
-	case chipcHw_CLOCK_OTP:
-		pClockCtrl = &pChipcHw->OTPClock;
-		break;
-	case chipcHw_CLOCK_I2C:
-		pClockCtrl = &pChipcHw->I2CClock;
-		break;
-	case chipcHw_CLOCK_I2S0:
-		pClockCtrl = &pChipcHw->I2S0Clock;
-		break;
-	case chipcHw_CLOCK_RTBUS:
-		pClockCtrl = &pChipcHw->RTBUSClock;
-		break;
-	case chipcHw_CLOCK_APM100:
-		pClockCtrl = &pChipcHw->APM100Clock;
-		break;
-	case chipcHw_CLOCK_TSC:
-		pClockCtrl = &pChipcHw->TSCClock;
-		break;
-	case chipcHw_CLOCK_LED:
-		pClockCtrl = &pChipcHw->LEDClock;
-		break;
-	case chipcHw_CLOCK_I2S1:
-		pClockCtrl = &pChipcHw->I2S1Clock;
-		break;
-	}
-
-	if (pPLLReg) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			/* PLL clock output enable/disable */
-			if (mode) {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock enable is inverted */
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			} else {
-				if (clock == chipcHw_CLOCK_DDR) {
-					/* DDR clock disable is inverted */
-					reg32_modify_or(pPLLReg,
-							chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				} else {
-					reg32_modify_and(pPLLReg,
-							 ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
-				}
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			/* PLL clock bypass enable/disable */
-			if (mode) {
-				reg32_modify_or(pPLLReg,
-						chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pPLLReg,
-						 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	} else if (pClockCtrl) {
-		switch (type) {
-		case chipcHw_OPTYPE_OUTPUT:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
-			}
-			break;
-		case chipcHw_OPTYPE_BYPASS:
-			if (mode) {
-				reg32_modify_or(pClockCtrl,
-						chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			} else {
-				reg32_modify_and(pClockCtrl,
-						 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
-			}
-			break;
-		}
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables a core clock of a certain device
-*
-*  This function disables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
-{
-
-	/* Disable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable a core clock of a certain device
-*
-*  This function enables a core clock
-*
-*  @note    no change in power consumption
-*/
-/****************************************************************************/
-static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
-{
-
-	/* Enable output of the clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables bypass clock of a certain device
-*
-*  This function enables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
-{
-	/* Enable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disabled bypass clock of a certain device
-*
-*  This function disables bypass clock
-*
-*  @note    Doesnot affect the bus interface clock
-*/
-/****************************************************************************/
-static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
-{
-	/* Disable bypass clock */
-	chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
-
-}
-
-/****************************************************************************/
-/**  @brief Checks if software strap is enabled
- *
- *   @return 1 : When enable
- *           0 : When disable
- */
-/****************************************************************************/
-static inline int chipcHw_isSoftwareStrapsEnable(void)
-{
-	return pChipcHw->SoftStraps & 0x00000001;
-}
-
-/****************************************************************************/
-/**  @brief Enable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsEnable(void)
-{
-	reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
-}
-
-/****************************************************************************/
-/**  @brief Disable software strap
- */
-/****************************************************************************/
-static inline void chipcHw_softwareStrapsDisable(void)
-{
-	reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
-}
-
-/****************************************************************************/
-/**  @brief PLL test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test enable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestEnable(void)
-{
-	reg32_modify_or(&pChipcHw->PLLConfig2,
-			chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test disable
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestDisable(void)
-{
-	reg32_modify_and(&pChipcHw->PLLConfig2,
-			 ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPllTestEnable(void)
-{
-	return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test status
- */
-/****************************************************************************/
-static inline int chipcHw_isPll2TestEnable(void)
-{
-	return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
-}
-
-/****************************************************************************/
-/**  @brief PLL test select
- */
-/****************************************************************************/
-static inline void chipcHw_pllTestSelect(uint32_t val)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief PLL2 test select
- */
-/****************************************************************************/
-static inline void chipcHw_pll2TestSelect(uint32_t val)
-{
-
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
-	pChipcHw->PLLConfig2 |=
-	    (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**  @brief Get PLL test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPllTestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**  @brief Get PLL2 test selected option
- */
-/****************************************************************************/
-static inline uint8_t chipcHw_getPll2TestSelected(void)
-{
-	return (uint8_t) ((pChipcHw->
-			   PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
-			  >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL1
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll1Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief  Disable the PLL2
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_pll2Disable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disables DDR SW phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM SW phase alignment interrupt mode
-*
-*  This function sets VPM phase alignment interrupt
-*/
-/****************************************************************************/
-static inline void
-chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
-{
-	REG_LOCAL_IRQ_SAVE;
-	if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
-		pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	} else {
-		pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
-	}
-	pChipcHw->VPMPhaseCtrl2 =
-	    (pChipcHw->
-	     VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
-			       chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable DDR phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in software
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmSwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Enable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Disable VPM phase alignment in hardware
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set DDR phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->DDRPhaseCtrl1 &=
-		    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->DDRPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Set VPM phase alignment margin in hardware
-*
-*/
-/****************************************************************************/
-static inline void
-chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
-{
-	uint32_t ge = 0;
-	uint32_t le = 0;
-
-	switch (margin) {
-	case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
-		ge = 0x0F;
-		le = 0x0F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
-		ge = 0x03;
-		le = 0x3F;
-		break;
-	case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
-		ge = 0x01;
-		le = 0x7F;
-		break;
-	}
-
-	{
-		REG_LOCAL_IRQ_SAVE;
-
-		pChipcHw->VPMPhaseCtrl1 &=
-		    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
-		       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
-			  chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		pChipcHw->VPMPhaseCtrl1 |=
-		    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
-		     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
-
-		REG_LOCAL_IRQ_RESTORE;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks DDR phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Checks VPM phase aligned status done by HW
-*
-*  @return  1: When aligned
-*           0: When not aligned
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase aligned status done by HW
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
-	    chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get DDR phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getDdrPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get VPM phase control value
-*
-*/
-/****************************************************************************/
-static inline uint32_t chipcHw_getVpmPhaseControl(void)
-{
-	return (pChipcHw->
-		PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
-	    chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a DDR phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &=
-	    ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->DDRPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout count
-*
-*  @note    If HW fails to perform the phase alignment, it will trigger
-*           a VPM phase alignment timeout interrupt.
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &=
-	    ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
-	      chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
-	pChipcHw->VPMPhaseCtrl2 |=
-	    (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
-	    chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear DDR phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Clear VPM phase alignment timeout interrupt
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	/* Clear timeout interrupt service bit */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_ddrHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt enable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	chipcHw_vpmHwPhaseAlignTimeoutInterruptClear();	/* Recommended */
-	/* Enable timeout interrupt */
-	pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   DDR phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-/****************************************************************************/
-/**
-*  @brief   VPM phase alignment timeout interrupt disable
-*
-*/
-/****************************************************************************/
-static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
-{
-	REG_LOCAL_IRQ_SAVE;
-	pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
-	REG_LOCAL_IRQ_RESTORE;
-}
-
-#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
deleted file mode 100644
index b162448..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    chipcHw_reg.h
-*
-*  @brief   Definitions for low level chip control registers
-*
-*/
-/****************************************************************************/
-#ifndef CHIPCHW_REG_H
-#define CHIPCHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
-#include <mach/csp/ddrcReg.h>
-
-#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
-
-typedef struct {
-	uint32_t ChipId;	/* Chip ID */
-	uint32_t DDRClock;	/* PLL1 Channel 1 for DDR clock */
-	uint32_t ARMClock;	/* PLL1 Channel 2 for ARM clock */
-	uint32_t ESWClock;	/* PLL1 Channel 3 for ESW system clock */
-	uint32_t VPMClock;	/* PLL1 Channel 4 for VPM clock */
-	uint32_t ESW125Clock;	/* PLL1 Channel 5 for ESW 125MHz clock */
-	uint32_t UARTClock;	/* PLL1 Channel 6 for UART clock */
-	uint32_t SDIO0Clock;	/* PLL1 Channel 7 for SDIO 0 clock */
-	uint32_t SDIO1Clock;	/* PLL1 Channel 8 for SDIO 1 clock */
-	uint32_t SPIClock;	/* PLL1 Channel 9 for SPI master Clock  */
-	uint32_t ETMClock;	/* PLL1 Channel 10 for ARM ETM Clock  */
-
-	uint32_t ACLKClock;	/* ACLK Clock (Divider) */
-	uint32_t OTPClock;	/* OTP Clock  (Divider) */
-	uint32_t I2CClock;	/* I2C Clock (CK_13m) (Divider) */
-	uint32_t I2S0Clock;	/* I2S0 Clock (Divider) */
-	uint32_t RTBUSClock;	/* RTBUS (DDR PHY Config.) Clock (Divider) */
-	uint32_t pad1;
-	uint32_t APM100Clock;	/* APM 100MHz CLK Clock (Divider) */
-	uint32_t TSCClock;	/* TSC Clock (Divider) */
-	uint32_t LEDClock;	/* LED Clock (Divider) */
-
-	uint32_t USBClock;	/* PLL2 Channel 1 for USB clock */
-	uint32_t LCDClock;	/* PLL2 Channel 2 for LCD clock */
-	uint32_t APMClock;	/* PLL2 Channel 3 for APM 200 MHz clock */
-
-	uint32_t BusIntfClock;	/* Bus interface clock */
-
-	uint32_t PLLStatus;	/* PLL status register (PLL1) */
-	uint32_t PLLConfig;	/* PLL configuration register  (PLL1) */
-	uint32_t PLLPreDivider;	/* PLL pre-divider control register (PLL1) */
-	uint32_t PLLDivider;	/* PLL divider control register (PLL1) */
-	uint32_t PLLControl1;	/* PLL analog control register #1 (PLL1) */
-	uint32_t PLLControl2;	/* PLL analog control register #2 (PLL1) */
-
-	uint32_t I2S1Clock;	/* I2S1 Clock  */
-	uint32_t AudioEnable;	/* Enable/ disable audio channel */
-	uint32_t SoftReset1;	/* Reset blocks */
-	uint32_t SoftReset2;	/* Reset blocks */
-	uint32_t Spare1;	/* Phase align interrupts */
-	uint32_t Sticky;	/* Sticky bits */
-	uint32_t MiscCtrl;	/* Misc. control */
-	uint32_t pad3[3];
-
-	uint32_t PLLStatus2;	/* PLL status register (PLL2) */
-	uint32_t PLLConfig2;	/* PLL configuration register  (PLL2) */
-	uint32_t PLLPreDivider2;	/* PLL pre-divider control register (PLL2) */
-	uint32_t PLLDivider2;	/* PLL divider control register (PLL2) */
-	uint32_t PLLControl12;	/* PLL analog control register #1 (PLL2) */
-	uint32_t PLLControl22;	/* PLL analog control register #2 (PLL2) */
-
-	uint32_t DDRPhaseCtrl1;	/* DDR Clock Phase Alignment control1 */
-	uint32_t VPMPhaseCtrl1;	/* VPM Clock Phase Alignment control1 */
-	uint32_t PhaseAlignStatus;	/* DDR/VPM Clock Phase Alignment Status */
-	uint32_t PhaseCtrlStatus;	/* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
-	uint32_t DDRPhaseCtrl2;	/* DDR Clock Phase Alignment control2 */
-	uint32_t VPMPhaseCtrl2;	/* VPM Clock Phase Alignment control2 */
-	uint32_t pad4[9];
-
-	uint32_t SoftOTP1;	/* Software OTP control */
-	uint32_t SoftOTP2;	/* Software OTP control */
-	uint32_t SoftStraps;	/* Software strap */
-	uint32_t PinStraps;	/* Pin Straps */
-	uint32_t DiffOscCtrl;	/* Diff oscillator control */
-	uint32_t DiagsCtrl;	/* Diagnostic control */
-	uint32_t DiagsOutputCtrl;	/* Diagnostic output enable */
-	uint32_t DiagsReadBackCtrl;	/* Diagnostic read back control */
-
-	uint32_t LcdPifMode;	/* LCD/PIF Pin Sharing MUX Mode */
-
-	uint32_t GpioMux_0_7;	/* Pin Sharing MUX0 Control */
-	uint32_t GpioMux_8_15;	/* Pin Sharing MUX1 Control */
-	uint32_t GpioMux_16_23;	/* Pin Sharing MUX2 Control */
-	uint32_t GpioMux_24_31;	/* Pin Sharing MUX3 Control */
-	uint32_t GpioMux_32_39;	/* Pin Sharing MUX4 Control */
-	uint32_t GpioMux_40_47;	/* Pin Sharing MUX5 Control */
-	uint32_t GpioMux_48_55;	/* Pin Sharing MUX6 Control */
-	uint32_t GpioMux_56_63;	/* Pin Sharing MUX7 Control */
-
-	uint32_t GpioSR_0_7;	/* Slew rate for GPIO 0 - 7 */
-	uint32_t GpioSR_8_15;	/* Slew rate for GPIO 8 - 15 */
-	uint32_t GpioSR_16_23;	/* Slew rate for GPIO 16 - 23 */
-	uint32_t GpioSR_24_31;	/* Slew rate for GPIO 24 - 31 */
-	uint32_t GpioSR_32_39;	/* Slew rate for GPIO 32 - 39 */
-	uint32_t GpioSR_40_47;	/* Slew rate for GPIO 40 - 47 */
-	uint32_t GpioSR_48_55;	/* Slew rate for GPIO 48 - 55 */
-	uint32_t GpioSR_56_63;	/* Slew rate for GPIO 56 - 63 */
-	uint32_t MiscSR_0_7;	/* Slew rate for MISC 0 - 7 */
-	uint32_t MiscSR_8_15;	/* Slew rate for MISC 8 - 15 */
-
-	uint32_t GpioPull_0_15;	/* Pull up registers for GPIO 0 - 15 */
-	uint32_t GpioPull_16_31;	/* Pull up registers for GPIO 16 - 31 */
-	uint32_t GpioPull_32_47;	/* Pull up registers for GPIO 32 - 47 */
-	uint32_t GpioPull_48_63;	/* Pull up registers for GPIO 48 - 63 */
-	uint32_t MiscPull_0_15;	/* Pull up registers for MISC 0 - 15 */
-
-	uint32_t GpioInput_0_31;	/* Input type for GPIO 0 - 31 */
-	uint32_t GpioInput_32_63;	/* Input type for GPIO 32 - 63 */
-	uint32_t MiscInput_0_15;	/* Input type for MISC 0 - 16 */
-} chipcHw_REG_t;
-
-#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
-
-#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
-#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
-#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
-#define chipcHw_REG_REV_A0                              0xA00
-#define chipcHw_REG_REV_B0                              0x0B0
-
-#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000	/* Allow controlling PLL registers */
-#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001	/* PLL is settled */
-#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008	/* Digital reset */
-#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004	/* Analog reset */
-#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020	/* Bypass enable */
-#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010	/* Output enable */
-#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001	/* Power down */
-#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000	/* 1.6GHz VCO split frequency */
-#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000	/* VCO range 800-1600 MHz */
-#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080	/* VCO range 1601-3200 MHz */
-#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000	/* PLL test output enable */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000	/* Mask to set test values */
-#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
-
-#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000	/* Phase comparator output */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000	/* Clock to bus ratio mask */
-#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20	/* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000	/* PLL channel power down */
-#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000	/* Use GPIO as source */
-#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000	/* Select bypass clock */
-#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000	/* Clock gated ON */
-#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000	/* Clock phase update enable */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8	/* Number of bits to be shifted */
-#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00	/* Phase control mask */
-#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF	/* Clock post divider mask
-
-									   00000000 = divide-by-256
-									   00000001 = divide-by-1
-									   00000010 = divide-by-2
-									   00000011 = divide-by-3
-									   00000100 = divide-by-4
-									   00000101 = divide-by-5
-									   00000110 = divide-by-6
-									   .
-									   .
-									   11111011 = divide-by-251
-									   11111100 = divide-by-252
-									   11111101 = divide-by-253
-									   11111110 = divide-by-254
-									 */
-
-#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000	/* NON-PLL clock source select */
-#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000	/* NON-PLL clock bypass enable */
-#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000	/* NON-PLL clock output enable */
-#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF	/* NON-PLL clock post-divide mask */
-#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000	/* NON-PLL clock post-divide by 256 */
-
-#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
-#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
-#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000	/* Divider mask */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000	/* Integer-N Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000	/* MASH Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000	/* MFB Sigma-Delta Modulator Unit Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000	/* MASH Sigma-Delta Modulator 1/8 Mode */
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000	/* MFB Sigma-Delta Modulator 1/8 Mode */
-
-#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / chipcHw_XTAL_FREQ_Hz)
-#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
-#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
-
-#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
-#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF	/* Fractional divider */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)	/* To attain spread with max frequency */
-
-#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0	/* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
-								   chipcHw_REG_PLL_DIVIDER_FRAC
-								   = 0, when SS is disable
-								 */
-
-#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz)           ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
-
-#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
-
-/* System booting strap options */
-#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001	/* Software Strap Override */
-
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000	/* 8 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002	/* 16 bit NOR FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004	/* Serial FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006	/* 16 bit NAND FLASH Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008	/* UART Boot */
-#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E	/* Mask */
-
-/* System boot option */
-#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000	/* Boot from Boot ROM */
-#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020	/* Boot from ARAM */
-#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030	/* Boot from NOR flash */
-
-/* NAND Flash page size strap options */
-#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000	/* NAND FLASH page size of 512 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040	/* NAND FLASH page size of 2048 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080	/* NAND FLASH page size of 4096 bytes */
-#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0	/* NAND FLASH page of extened size */
-#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0	/* Mask */
-
-#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400	/* NAND FLASH address cycle configuration */
-#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800	/* Reboot to UART on error */
-
-/* Secure boot mode strap options */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000	/* Normal Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100	/* Software debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200	/* Boot rom debugging Boot */
-#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300	/* Normal Boot (Quiet BootRom) */
-#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300	/* Mask */
-
-/* Slave Mode straps */
-#define chipcHw_STRAPS_I2CS                             0x02000000	/* I2C Slave  */
-#define chipcHw_STRAPS_SPIS                             0x01000000	/* SPI Slave  */
-
-/* Strap pin options */
-#define chipcHw_REG_SW_STRAPS                           ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
-
-/* PIF/LCD pin sharing defines */
-#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001	/* LCD Controller is used and the pins have LCD functions */
-#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002	/* LCD pins are used to perform PIF functions  */
-
-#define chipcHw_GPIO_COUNT                              61	/* Number of GPIO pin accessible thorugh CHIPC */
-
-/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
-#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001	/* GPIO mux for Keypad */
-#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002	/* GPIO mux for I2CH */
-#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003	/* GPIO mux for SPI */
-#define chipcHw_REG_GPIO_MUX_UART                       0x00000004	/* GPIO mux for UART */
-#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005	/* GPIO mux for LEDMTXP */
-#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006	/* GPIO mux for LEDMTXS */
-#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007	/* GPIO mux for SDIO0 */
-#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008	/* GPIO mux for SDIO1 */
-#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009	/* GPIO mux for PCM */
-#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A	/* GPIO mux for I2S */
-#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B	/* GPIO mux for ETM */
-#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C	/* GPIO mux for DEBUG */
-#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D	/* GPIO mux for MISC */
-#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000	/* GPIO mux for GPIO */
-#define chipcHw_REG_GPIO_MUX(pin)                       (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
-#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 0x00000007) << 2)
-#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F	/* Mask */
-
-#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000	/* High speed slew rate */
-#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008	/* Normal slew rate */
-							/* Pins beyond 42 are defined by skipping 8 bits within the register */
-#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008	/* Mask */
-
-#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001	/* Current driving strength 2 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002	/* Current driving strength 4 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004	/* Current driving strength 6 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005	/* Current driving strength 8 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006	/* Current driving strength 10 milli ampere */
-#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007	/* Current driving strength 12 milli ampere */
-#define chipcHw_REG_CURRENT_MASK                        0x00000007	/* Mask */
-							/* Pins beyond 42 are defined by skipping 8 bits */
-#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
-#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
-
-#define chipcHw_REG_PULL_NONE                           0x00000000	/* No pull up register */
-#define chipcHw_REG_PULL_UP                             0x00000001	/* Pull up register enable */
-#define chipcHw_REG_PULL_DOWN                           0x00000002	/* Pull down register enable */
-#define chipcHw_REG_PULLUP_MASK                         0x00000003	/* Mask */
-							/* Pins beyond 42 are defined by skipping 4 bits */
-#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
-#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
-
-#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000	/* Normal CMOS logic */
-#define chipcHw_REG_INPUTTYPE_ST                        0x00000001	/* High speed Schmitt Trigger */
-#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001	/* Mask */
-							/* Pins beyond 42 are defined by skipping 2 bits */
-#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
-#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
-
-/* Device connected to the bus clock */
-#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001	/* Bus interface clock for ARM */
-#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002	/* Bus interface clock for VDEC */
-#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004	/* Bus interface clock for ARAM */
-#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008	/* Bus interface clock for HPM */
-#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010	/* Bus interface clock for DDRC */
-#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020	/* Bus interface clock for DMAC0 */
-#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040	/* Bus interface clock for DMAC1 */
-#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080	/* Bus interface clock for NVI */
-#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100	/* Bus interface clock for ESW */
-#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200	/* Bus interface clock for GE */
-#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400	/* Bus interface clock for I2CH */
-#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800	/* Bus interface clock for I2S0 */
-#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000	/* Bus interface clock for I2S1 */
-#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000	/* Bus interface clock for VRAM */
-#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000	/* Bus interface clock for CLCD */
-#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000	/* Bus interface clock for LDK */
-#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000	/* Bus interface clock for LED */
-#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000	/* Bus interface clock for OTP */
-#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000	/* Bus interface clock for PIF */
-#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000	/* Bus interface clock for SPU */
-#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000	/* Bus interface clock for SDIO0 */
-#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000	/* Bus interface clock for SDIO1 */
-#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000	/* Bus interface clock for SPIH */
-#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000	/* Bus interface clock for SPIS */
-#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000	/* Bus interface clock for UART0 */
-#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000	/* Bus interface clock for UART1 */
-#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000	/* Bus interface clock for BBL */
-#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000	/* Bus interface clock for I2CS */
-#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000	/* Bus interface clock for USB Host */
-#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000	/* Bus interface clock for USB Device */
-#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000	/* Bus interface clock for Boot ROM */
-#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000	/* Bus interface clock for Touch screen */
-
-/* Software resets defines */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD          0x0000000080000000ULL	/* Reset Global VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_HOLD                 0x0000000040000000ULL	/* Reset VPM and hold */
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL               0x0000000020000000ULL	/* Reset Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM                      0x0000000010000000ULL	/* Reset VPM */
-#define chipcHw_REG_SOFT_RESET_KEYPAD                   0x0000000008000000ULL	/* Reset Key pad */
-#define chipcHw_REG_SOFT_RESET_LED                      0x0000000004000000ULL	/* Reset LED */
-#define chipcHw_REG_SOFT_RESET_SPU                      0x0000000002000000ULL	/* Reset SPU */
-#define chipcHw_REG_SOFT_RESET_RNG                      0x0000000001000000ULL	/* Reset RNG */
-#define chipcHw_REG_SOFT_RESET_PKA                      0x0000000000800000ULL	/* Reset PKA */
-#define chipcHw_REG_SOFT_RESET_LCD                      0x0000000000400000ULL	/* Reset LCD */
-#define chipcHw_REG_SOFT_RESET_PIF                      0x0000000000200000ULL	/* Reset PIF */
-#define chipcHw_REG_SOFT_RESET_I2CS                     0x0000000000100000ULL	/* Reset I2C Slave */
-#define chipcHw_REG_SOFT_RESET_I2CH                     0x0000000000080000ULL	/* Reset I2C Host */
-#define chipcHw_REG_SOFT_RESET_SDIO1                    0x0000000000040000ULL	/* Reset SDIO 1 */
-#define chipcHw_REG_SOFT_RESET_SDIO0                    0x0000000000020000ULL	/* Reset SDIO 0 */
-#define chipcHw_REG_SOFT_RESET_BBL                      0x0000000000010000ULL	/* Reset BBL */
-#define chipcHw_REG_SOFT_RESET_I2S1                     0x0000000000008000ULL	/* Reset I2S1 */
-#define chipcHw_REG_SOFT_RESET_I2S0                     0x0000000000004000ULL	/* Reset I2S0 */
-#define chipcHw_REG_SOFT_RESET_SPIS                     0x0000000000002000ULL	/* Reset SPI Slave */
-#define chipcHw_REG_SOFT_RESET_SPIH                     0x0000000000001000ULL	/* Reset SPI Host */
-#define chipcHw_REG_SOFT_RESET_GPIO1                    0x0000000000000800ULL	/* Reset GPIO block 1 */
-#define chipcHw_REG_SOFT_RESET_GPIO0                    0x0000000000000400ULL	/* Reset GPIO block 0 */
-#define chipcHw_REG_SOFT_RESET_UART1                    0x0000000000000200ULL	/* Reset UART 1 */
-#define chipcHw_REG_SOFT_RESET_UART0                    0x0000000000000100ULL	/* Reset UART 0 */
-#define chipcHw_REG_SOFT_RESET_NVI                      0x0000000000000080ULL	/* Reset NVI */
-#define chipcHw_REG_SOFT_RESET_WDOG                     0x0000000000000040ULL	/* Reset Watch dog */
-#define chipcHw_REG_SOFT_RESET_TMR                      0x0000000000000020ULL	/* Reset Timer */
-#define chipcHw_REG_SOFT_RESET_ETM                      0x0000000000000010ULL	/* Reset ETM */
-#define chipcHw_REG_SOFT_RESET_ARM_HOLD                 0x0000000000000008ULL	/* Reset ARM and HOLD */
-#define chipcHw_REG_SOFT_RESET_ARM                      0x0000000000000004ULL	/* Reset ARM */
-#define chipcHw_REG_SOFT_RESET_CHIP_WARM                0x0000000000000002ULL	/* Chip warm reset */
-#define chipcHw_REG_SOFT_RESET_CHIP_SOFT                0x0000000000000001ULL	/* Chip soft reset */
-#define chipcHw_REG_SOFT_RESET_VDEC                     0x0000100000000000ULL	/* Video decoder */
-#define chipcHw_REG_SOFT_RESET_GE                       0x0000080000000000ULL	/* Graphics engine */
-#define chipcHw_REG_SOFT_RESET_OTP                      0x0000040000000000ULL	/* Reset OTP */
-#define chipcHw_REG_SOFT_RESET_USB2                     0x0000020000000000ULL	/* Reset USB2 */
-#define chipcHw_REG_SOFT_RESET_USB1                     0x0000010000000000ULL	/* Reset USB 1 */
-#define chipcHw_REG_SOFT_RESET_USB                      0x0000008000000000ULL	/* Reset USB 1 and USB2 soft reset */
-#define chipcHw_REG_SOFT_RESET_ESW                      0x0000004000000000ULL	/* Reset Ethernet switch */
-#define chipcHw_REG_SOFT_RESET_ESWCLK                   0x0000002000000000ULL	/* Reset Ethernet switch clock */
-#define chipcHw_REG_SOFT_RESET_DDRPHY                   0x0000001000000000ULL	/* Reset DDR Physical */
-#define chipcHw_REG_SOFT_RESET_DDR                      0x0000000800000000ULL	/* Reset DDR Controller */
-#define chipcHw_REG_SOFT_RESET_TSC                      0x0000000400000000ULL	/* Reset Touch screen */
-#define chipcHw_REG_SOFT_RESET_PCM                      0x0000000200000000ULL	/* Reset PCM device */
-#define chipcHw_REG_SOFT_RESET_APM                      0x0000200100000000ULL	/* Reset APM device */
-
-#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD        0x8000000000000000ULL	/* Unhold Global VPM */
-#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD               0x4000000000000000ULL	/* Unhold VPM */
-#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD               0x2000000000000000ULL	/* Unhold ARM reset  */
-#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK              0xF000000000000000ULL	/* Mask to handle unhold request */
-
-/* Audio channel control defines */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001	/* Enable all audio channel */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002	/* Enable channel A */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004	/* Enable channel B */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008	/* Enable channel C */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010	/* Enable NTP clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020	/* Enable PCM0 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040	/* Enable PCM1 clock */
-#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080	/* Enable APM clock */
-
-/* Misc. chip control defines */
-#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000	/* Select GE2/GE3 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000	/* Use on chip clock for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000	/* Use external clock via GPIO pin 26 for I2S1 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000	/* Use on chip clock for I2S0 */
-#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000	/* Use external clock via GPIO pin 45 for I2S0 */
-#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000	/* Disable ARM CP15 bit */
-#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008	/* Disable RTC registers */
-#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004	/* Disable Battery Backed RAM */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002	/* Set USB as host */
-#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD	/* Set USB as device */
-#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE	/* Power up USB */
-#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001	/* Power down USB */
-
-/* OTP configuration defines */
-#define chipcHw_REG_OTP_SECURITY_OFF                    0x0000020000000000ULL	/* Security support is OFF */
-#define chipcHw_REG_OTP_SPU_SLOW                        0x0000010000000000ULL	/* Limited SPU throughput */
-#define chipcHw_REG_OTP_LCD_SPEED                       0x0000000600000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_1                     0x0000000100000000ULL	/* Set VPM speed one */
-#define chipcHw_REG_OTP_VPM_SPEED_0                     0x0000000080000000ULL	/* Set VPM speed zero */
-#define chipcHw_REG_OTP_AXI_SPEED                       0x0000000060000000ULL	/* Set maximum AXI bus speed */
-#define chipcHw_REG_OTP_APM_DISABLE                     0x000000001F000000ULL	/* Disable APM */
-#define chipcHw_REG_OTP_PIF_DISABLE                     0x0000000000200000ULL	/* Disable PIF */
-#define chipcHw_REG_OTP_VDEC_DISABLE                    0x0000000000100000ULL	/* Disable Video decoder */
-#define chipcHw_REG_OTP_BBL_DISABLE                     0x0000000000080000ULL	/* Disable RTC and BBRAM */
-#define chipcHw_REG_OTP_LED_DISABLE                     0x0000000000040000ULL	/* Disable LED */
-#define chipcHw_REG_OTP_GE_DISABLE                      0x0000000000020000ULL	/* Disable Graphics Engine */
-#define chipcHw_REG_OTP_LCD_DISABLE                     0x0000000000010000ULL	/* Disable LCD */
-#define chipcHw_REG_OTP_KEYPAD_DISABLE                  0x0000000000008000ULL	/* Disable keypad */
-#define chipcHw_REG_OTP_UART_DISABLE                    0x0000000000004000ULL	/* Disable UART */
-#define chipcHw_REG_OTP_SDIOH_DISABLE                   0x0000000000003000ULL	/* Disable SDIO host */
-#define chipcHw_REG_OTP_HSS_DISABLE                     0x0000000000000C00ULL	/* Disable HSS */
-#define chipcHw_REG_OTP_TSC_DISABLE                     0x0000000000000200ULL	/* Disable touch screen */
-#define chipcHw_REG_OTP_USB_DISABLE                     0x0000000000000180ULL	/* Disable USB */
-#define chipcHw_REG_OTP_SGMII_DISABLE                   0x0000000000000060ULL	/* Disable SGMII */
-#define chipcHw_REG_OTP_ETH_DISABLE                     0x0000000000000018ULL	/* Disable gigabit ethernet */
-#define chipcHw_REG_OTP_ETH_PHY_DISABLE                 0x0000000000000006ULL	/* Disable ethernet PHY */
-#define chipcHw_REG_OTP_VPM_DISABLE                     0x0000000000000001ULL	/* Disable VPM */
-
-/* Sticky bit defines */
-#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001	/* Boot done */
-#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002	/* ARM soft reset */
-#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004	/* General purpose bit 1 */
-#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008	/* General purpose bit 2 */
-#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010	/* General purpose bit 3 */
-#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020	/* General purpose bit 4 */
-#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040	/* General purpose bit 5 */
-#define chipcHw_REG_STICKY_POR_BROM                     0x00000080	/* Special sticky bit for security - set in BROM to avoid other modes being entered */
-#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100	/* ARM reset */
-#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200	/* Chip soft reset */
-#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400	/* Chip warm reset */
-#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800	/* Watchdog reset */
-#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000	/* OTP reset */
-
-							/* HW phase alignment defines *//* Spare1 register definitions */
-#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000	/* Enable DDR phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000	/* Enable VPM phase align panic interrupt */
-#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002	/* Enable access to VPM using system BUS */
-#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001	/* Enable access to DDR using system BUS */
-							/* DDRPhaseCtrl1 register definitions */
-#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000	/* Enable DDR SW phase alignment */
-#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000	/* Enable DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F	/* DDR lower threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F	/* DDR upper threshold for phase alignment */
-#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* BUS Cycle to wait to run next DDR phase alignment */
-#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* VPMPhaseCtrl1 register definitions */
-#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000	/* Enable VPM SW phase alignment */
-#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000	/* Enable VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F	/* VPM lower threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F	/* VPM upper threshold for phase alignment */
-#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF	/* BUS Cycle to wait to complete the VPM phase alignment */
-#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
-							/* PhaseAlignStatus register definitions */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000	/* DDR time out interrupt status */
-#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F	/* DDR phase status value */
-#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
-#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000	/* DDR Phase aligned status */
-#define chipcHw_REG_DDR_LOAD                            0x00400000	/* Load DDR phase status */
-#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F	/* DDR phase control value */
-#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
-#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000	/* VPM time out interrupt status */
-#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F	/* VPM phase status value */
-#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
-#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080	/* VPM Phase aligned status */
-#define chipcHw_REG_VPM_LOAD                            0x00000040	/* Load VPM phase status */
-#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F	/* VPM phase control value */
-#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
-							/* DDRPhaseCtrl2 register definitions */
-#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000	/* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000	/* Enable time out interrupt */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* Wait before toggling load_ch */
-#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* Total wait to settle ph_ctrl and load_ch */
-#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* Time out value for DDR HW phase alignment */
-#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
-							/* VPMPhaseCtrl2 register definitions */
-#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003	/* Interrupt select */
-#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
-#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
-#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
-#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000	/* Acknowledge that interrupt was serviced */
-#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000	/* Enable time out interrupt */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F	/* Wait before toggling load_ch */
-#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F	/* Total wait cycle to settle ph_ctrl and load_ch */
-#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF	/* Time out value for VPM HW phase alignment */
-#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
-
-#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
deleted file mode 100644
index f1b68e2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ /dev/null
@@ -1,872 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    ddrcReg.h
-*
-*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
-*
-*/
-/****************************************************************************/
-
-#ifndef DDRC_REG_H
-#define DDRC_REG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/reg.h>
-#include <csp/stdint.h>
-
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-/*********************************************************************/
-/* DDR2 Controller (ARM PL341) register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 DDR2 configuration registers, offset 0x000 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t memcStatus;
-		uint32_t memcCmd;
-		uint32_t directCmd;
-		uint32_t memoryCfg;
-		uint32_t refreshPrd;
-		uint32_t casLatency;
-		uint32_t writeLatency;
-		uint32_t tMrd;
-		uint32_t tRas;
-		uint32_t tRc;
-		uint32_t tRcd;
-		uint32_t tRfc;
-		uint32_t tRp;
-		uint32_t tRrd;
-		uint32_t tWr;
-		uint32_t tWtr;
-		uint32_t tXp;
-		uint32_t tXsr;
-		uint32_t tEsr;
-		uint32_t memoryCfg2;
-		uint32_t memoryCfg3;
-		uint32_t tFaw;
-	} ddrcReg_CTLR_MEMC_REG_t;
-
-#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
-#define ddrcReg_CTLR_MEMC_REGP                          ((volatile ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
-#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
-
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
-#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
-
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
-#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
-
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
-#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
-
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
-#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
-
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
-#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
-#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
-#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
-
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
-#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
-
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
-#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
-#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
-
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
-#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
-
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
-#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)	/* @note Not supported in PL341 */
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
-
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
-#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
-#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
-#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
-#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_MRD_SHIFT                        0
-#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RAS_SHIFT                        0
-#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RC_SHIFT                         0
-#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RCD_SHIFT                        0
-#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RFC_SHIFT                        0
-#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
-#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_RP_SHIFT                         0
-#define ddrcReg_CTLR_T_RP_MASK                          (0xf << ddrcReg_CTLR_T_RP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_RRD_SHIFT                        0
-#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WR_SHIFT                         0
-#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_WTR_SHIFT                        0
-#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XP_SHIFT                         0
-#define ddrcReg_CTLR_T_XP_MASK                          (0xff << ddrcReg_CTLR_T_XP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_XSR_SHIFT                        0
-#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_ESR_SHIFT                        0
-#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
-#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
-#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
-#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
-#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
-
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
-#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
-#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
-#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
-
-#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
-#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CNT                            16
-#define ddrcReg_CTLR_QOS_MAX                            (ddrcReg_CTLR_QOS_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
-	} ddrcReg_CTLR_QOS_REG_t;
-
-#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
-#define ddrcReg_CTLR_QOS_REGP                           ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
-#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
-#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
-
-#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 Memory chip configuration registers, offset 0x200 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CNT                           4
-#define ddrcReg_CTLR_CHIP_MAX                           (ddrcReg_CTLR_CHIP_CNT - 1)
-
-	typedef struct {
-		uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
-	} ddrcReg_CTLR_CHIP_REG_t;
-
-#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
-#define ddrcReg_CTLR_CHIP_REGP                          ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
-#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
-
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
-#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* ARM PL341 User configuration registers, offset 0x300 */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
-
-	typedef struct {
-		uint32_t input;
-		uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
-		uint32_t feature;
-	} ddrcReg_CTLR_USER_REG_t;
-
-#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
-#define ddrcReg_CTLR_USER_REGP                          ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
-#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
-#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
-
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
-#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
-
-/*********************************************************************/
-/* Broadcom DDR23 PHY register definitions */
-/*********************************************************************/
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Address and Control register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t pmCtl;
-		 REG32_RSVD(0x0008, 0x0010);
-		uint32_t pllStatus;
-		uint32_t pllCfg;
-		uint32_t pllPreDiv;
-		uint32_t pllDiv;
-		uint32_t pllCtl1;
-		uint32_t pllCtl2;
-		uint32_t ssCtl;
-		uint32_t ssCfg;
-		uint32_t vdlStatic;
-		uint32_t vdlDynamic;
-		uint32_t padIdle;
-		uint32_t pvtComp;
-		uint32_t padDrive;
-		uint32_t clkRgltrCtl;
-	} ddrcReg_PHY_ADDR_CTL_REG_t;
-
-#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
-
-/* @todo These SS definitions are duplicates of ones below */
-
-#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
-#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
-#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10	/* Higher the value, lower the SS modulation frequency */
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
-#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
-#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
-#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
-#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
-
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
-#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
-#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
-
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-/* Broadcom DDR23 PHY Byte Lane register definitions */
-/* -------------------------------------------------------------------- */
-/* -------------------------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CNT                       2
-#define ddrcReg_PHY_BYTE_LANE_MAX                       (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
-
-	typedef struct {
-		uint32_t revision;
-		uint32_t vdlCalibrate;
-		uint32_t vdlStatus;
-		 REG32_RSVD(0x000c, 0x0010);
-		uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
-		uint32_t readCtl;
-		uint32_t readStatus;
-		uint32_t readClear;
-		uint32_t padIdleCtl;
-		uint32_t padDriveCtl;
-		uint32_t padClkCtl;
-		uint32_t writeCtl;
-		uint32_t clkRegCtl;
-	} ddrcReg_PHY_BYTE_LANE_REG_t;
-
-/* There are 2 instances of the byte Lane registers, one for each byte lane. */
-#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
-#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
-
-#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
-#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
-#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
-
-/* ----------------------------------------------------- */
-
-/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
-/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
-/* register. The fine rise and fall are no longer used, so add some definitions for just */
-/* the step setting to simplify things. */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
-#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
-#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u << 31)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 << 19)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 << 18)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 << 17)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 << 16)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 << 15)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 << 14)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 << 13)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 << 12)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 << 11)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 << 10)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 << 9)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 << 8)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 << 7)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 << 6)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 << 5)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 << 4)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 << 3)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 << 2)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 << 0)
-
-/* ----------------------------------------------------- */
-
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 << 1)
-#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 << 0)
-
-/*********************************************************************/
-/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
-/*********************************************************************/
-
-	typedef struct {
-		uint32_t cfg;
-		uint32_t actMonCnt;
-		uint32_t ctl;
-		uint32_t lbistCtl;
-		uint32_t lbistSeed;
-		uint32_t lbistStatus;
-		uint32_t tieOff;
-		uint32_t actMonClear;
-		uint32_t status;
-		uint32_t user;
-	} ddrcReg_CTLR_PHY_GLUE_REG_t;
-
-#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
-#define ddrcReg_CTLR_PHY_GLUE_REGP                              ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
-
-/* ----------------------------------------------------- */
-
-/* DDR2 / AXI block phase alignment interrupt control */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED   ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED        ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
-
-/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
-/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
-/* controller. If 2 chips selects are being used, then software control must be enabled. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
-
-/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
-
-/* Chip select count */
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
-
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
-#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
-
-/* ----------------------------------------------------- */
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
-#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
-
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#ifdef __cplusplus
-}				/* end extern "C" */
-#endif
-#endif				/* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
deleted file mode 100644
index d67e2f8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_priv.h
-*
-*  @brief   Private Definitions for low level DMA driver
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_PRIV_H
-#define _DMACHW_PRIV_H
-
-#include <csp/stdint.h>
-
-/* Data type for DMA Link List Item */
-typedef struct {
-	uint32_t sar;		/* Source Address Register.
-				   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
-	uint32_t dar;		/* Destination Address Register.
-				   Address must be aligned to CTLx.DST_TR_WIDTH.             */
-	uint32_t llpPhy;	/* LLP contains the physical address of the next descriptor for block chaining using linked lists.
-				   Address MUST be aligned to a 32-bit boundary.             */
-	dmacHw_REG64_t ctl;	/* Control Register. 64 bits */
-	uint32_t sstat;		/* Source Status Register */
-	uint32_t dstat;		/* Destination Status Register */
-	uint32_t devCtl;	/* Device specific control information */
-	uint32_t llp;		/* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
-} dmacHw_DESC_t;
-
-/*
- *  Descriptor ring pointers
- */
-typedef struct {
-	int num;		/* Number of link items */
-	dmacHw_DESC_t *pHead;	/* Head of descriptor ring (for writing) */
-	dmacHw_DESC_t *pTail;	/* Tail of descriptor ring (for reading) */
-	dmacHw_DESC_t *pProg;	/* Descriptor to program the channel (for programming the channel register) */
-	dmacHw_DESC_t *pEnd;	/* End of current descriptor chain */
-	dmacHw_DESC_t *pFree;	/* Descriptor to free memory (freeing dynamic memory) */
-	uint32_t virt2PhyOffset;	/* Virtual to physical address offset for the descriptor ring */
-} dmacHw_DESC_RING_t;
-
-/*
- *  DMA channel control block
- */
-typedef struct {
-	uint32_t module;	/* DMA controller module (0-1) */
-	uint32_t channel;	/* DMA channel (0-7) */
-	volatile uint32_t varDataStarted;	/* Flag indicating variable data channel is enabled */
-	volatile uint32_t descUpdated;	/* Flag to indicate descriptor update is complete */
-	void *userData;		/* Channel specifc user data */
-} dmacHw_CBLK_t;
-
-#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
-#define dmacHw_MAX_CHANNEL_COUNT          16
-#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
-#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
-#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
-#define dmacHw_MAX_BLOCKSIZE              4064
-#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
-#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
-#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
-#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
-#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
-#define dmacHw_DST_IS_MEMORY(tt)          (((tt) ==  dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
-
-/****************************************************************************/
-/**
-*  @brief   Get next available transaction width
-*
-*
-*  @return  On success  : Next available transaction width
-*           On failure : dmacHw_TRANSACTION_WIDTH_8
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw	/*   [ IN ] Current transaction width */
-    ) {
-	if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
-	} else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
-		return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
-			 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
-	}
-
-	/* Default return  */
-	return dmacHw_SRC_TRANSACTION_WIDTH_8;
-}
-
-/****************************************************************************/
-/**
-*  @brief   Get number of bytes per transaction
-*
-*  @return  Number of bytes per transaction
-*
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw	/*   [ IN ]  Transaction width */
-    ) {
-	int width = 1;
-	switch (tw) {
-	case dmacHw_SRC_TRANSACTION_WIDTH_8:
-		width = 1;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_16:
-	case dmacHw_DST_TRANSACTION_WIDTH_16:
-		width = 2;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_32:
-	case dmacHw_DST_TRANSACTION_WIDTH_32:
-		width = 4;
-		break;
-	case dmacHw_SRC_TRANSACTION_WIDTH_64:
-	case dmacHw_DST_TRANSACTION_WIDTH_64:
-		width = 8;
-		break;
-	default:
-		dmacHw_ASSERT(0);
-	}
-
-	/* Default transaction width */
-	return width;
-}
-
-#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
deleted file mode 100644
index f1ecf96f2..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    dmacHw_reg.h
-*
-*  @brief   Definitions for low level DMA registers
-*
-*/
-/****************************************************************************/
-
-#ifndef _DMACHW_REG_H
-#define _DMACHW_REG_H
-
-#include <csp/stdint.h>
-#include <mach/csp/mm_io.h>
-
-/* Data type for 64 bit little endian register */
-typedef struct {
-	volatile uint32_t lo;	/* Lower 32 bit in little endian mode */
-	volatile uint32_t hi;	/* Upper 32 bit in little endian mode */
-} dmacHw_REG64_t;
-
-/* Data type representing DMA channel registers */
-typedef struct {
-	dmacHw_REG64_t ChannelSar;	/*  Source Address Register. 64 bits (upper 32 bits are reserved)
-					   Address must be aligned to CTLx.SRC_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelDar;	/*  Destination Address Register.64 bits (upper 32 bits are reserved)
-					   Address must be aligned to CTLx.DST_TR_WIDTH.
-					 */
-	dmacHw_REG64_t ChannelLlp;	/*  Link List Pointer.64 bits (upper 32 bits are reserved)
-					   LLP contains the pointer to the next LLI for block chaining using linked lists.
-					   If LLPis set to 0x0, then transfers using linked lists are not enabled.
-					   Address MUST be aligned to a 32-bit boundary.
-					 */
-	dmacHw_REG64_t ChannelCtl;	/* Control Register. 64 bits */
-	dmacHw_REG64_t ChannelSstat;	/* Source Status Register */
-	dmacHw_REG64_t ChannelDstat;	/* Destination Status Register */
-	dmacHw_REG64_t ChannelSstatAddr;	/* Source Status Address Register */
-	dmacHw_REG64_t ChannelDstatAddr;	/* Destination Status Address Register */
-	dmacHw_REG64_t ChannelConfig;	/* Channel Configuration Register */
-	dmacHw_REG64_t SrcGather;	/* Source gather register */
-	dmacHw_REG64_t DstScatter;	/* Destination scatter register */
-} dmacHw_CH_REG_t;
-
-/* Data type for RAW interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t RawTfr;	/* Raw Status for IntTfr Interrupt */
-	dmacHw_REG64_t RawBlock;	/* Raw Status for IntBlock Interrupt */
-	dmacHw_REG64_t RawSrcTran;	/* Raw Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t RawDstTran;	/* Raw Status for IntDstTran Interrupt */
-	dmacHw_REG64_t RawErr;	/* Raw Status for IntErr Interrupt */
-} dmacHw_INT_RAW_t;
-
-/* Data type for interrupt status registers */
-typedef struct {
-	dmacHw_REG64_t StatusTfr;	/* Status for IntTfr Interrupt */
-	dmacHw_REG64_t StatusBlock;	/* Status for IntBlock Interrupt */
-	dmacHw_REG64_t StatusSrcTran;	/* Status for IntSrcTran Interrupt */
-	dmacHw_REG64_t StatusDstTran;	/* Status for IntDstTran Interrupt */
-	dmacHw_REG64_t StatusErr;	/* Status for IntErr Interrupt */
-} dmacHw_INT_STATUS_t;
-
-/* Data type for interrupt mask registers*/
-typedef struct {
-	dmacHw_REG64_t MaskTfr;	/* Mask for IntTfr Interrupt */
-	dmacHw_REG64_t MaskBlock;	/* Mask for IntBlock Interrupt */
-	dmacHw_REG64_t MaskSrcTran;	/* Mask for IntSrcTran Interrupt */
-	dmacHw_REG64_t MaskDstTran;	/* Mask for IntDstTran Interrupt */
-	dmacHw_REG64_t MaskErr;	/* Mask for IntErr Interrupt */
-} dmacHw_INT_MASK_t;
-
-/* Data type for interrupt clear registers */
-typedef struct {
-	dmacHw_REG64_t ClearTfr;	/* Clear for IntTfr Interrupt */
-	dmacHw_REG64_t ClearBlock;	/* Clear for IntBlock Interrupt */
-	dmacHw_REG64_t ClearSrcTran;	/* Clear for IntSrcTran Interrupt */
-	dmacHw_REG64_t ClearDstTran;	/* Clear for IntDstTran Interrupt */
-	dmacHw_REG64_t ClearErr;	/* Clear for IntErr Interrupt */
-	dmacHw_REG64_t StatusInt;	/* Status for each interrupt type */
-} dmacHw_INT_CLEAR_t;
-
-/* Data type for software handshaking registers */
-typedef struct {
-	dmacHw_REG64_t ReqSrcReg;	/* Source Software Transaction Request Register */
-	dmacHw_REG64_t ReqDstReg;	/* Destination Software Transaction Request Register */
-	dmacHw_REG64_t SglReqSrcReg;	/* Single Source Transaction Request Register */
-	dmacHw_REG64_t SglReqDstReg;	/* Single Destination Transaction Request Register */
-	dmacHw_REG64_t LstSrcReg;	/* Last Source Transaction Request Register */
-	dmacHw_REG64_t LstDstReg;	/* Last Destination Transaction Request Register */
-} dmacHw_SW_HANDSHAKE_t;
-
-/* Data type for misc. registers */
-typedef struct {
-	dmacHw_REG64_t DmaCfgReg;	/* DMA Configuration Register */
-	dmacHw_REG64_t ChEnReg;	/* DMA Channel Enable Register */
-	dmacHw_REG64_t DmaIdReg;	/* DMA ID Register */
-	dmacHw_REG64_t DmaTestReg;	/* DMA Test Register */
-	dmacHw_REG64_t Reserved0;	/* Reserved */
-	dmacHw_REG64_t Reserved1;	/* Reserved */
-	dmacHw_REG64_t CompParm6;	/* Component Parameter 6 */
-	dmacHw_REG64_t CompParm5;	/* Component Parameter 5 */
-	dmacHw_REG64_t CompParm4;	/* Component Parameter 4 */
-	dmacHw_REG64_t CompParm3;	/* Component Parameter 3 */
-	dmacHw_REG64_t CompParm2;	/* Component Parameter 2 */
-	dmacHw_REG64_t CompParm1;	/* Component Parameter 1 */
-	dmacHw_REG64_t CompId;	/* Compoent ID */
-} dmacHw_MISC_t;
-
-/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0	/* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1	/* DMAC 1 module's base address */
-
-extern uint32_t dmaChannelCount_0;
-extern uint32_t dmaChannelCount_1;
-
-/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
-
-/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
-
-/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
-
-/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
-
-/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
-
-/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
-
-/* Channel control registers */
-#define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
-#define dmacHw_REG_DAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
-#define dmacHw_REG_LLP(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
-
-#define dmacHw_REG_CTL_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
-#define dmacHw_REG_CTL_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
-
-#define dmacHw_REG_SSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
-#define dmacHw_REG_DSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
-#define dmacHw_REG_SSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
-#define dmacHw_REG_DSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
-
-#define dmacHw_REG_CFG_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
-#define dmacHw_REG_CFG_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
-
-#define dmacHw_REG_SGR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
-#define dmacHw_REG_SGR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
-
-#define dmacHw_REG_DSR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
-#define dmacHw_REG_DSR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
-
-#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
-#define CHANNEL_BUSY(mod, channel)              (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
-
-/* Bit mask for REG_DMACx_CTL_LO */
-
-#define dmacHw_REG_CTL_INT_EN                       0x00000001	/* Channel interrupt enable */
-
-#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E	/* Destination transaction width mask */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
-#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000	/* Destination transaction width 8 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002	/* Destination transaction width 16 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004	/* Destination transaction width 32 bit */
-#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006	/* Destination transaction width 64 bit */
-
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070	/* Source transaction width mask */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000	/* Source transaction width 8 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010	/* Source transaction width 16 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020	/* Source transaction width 32 bit */
-#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030	/* Source transaction width 64 bit */
-
-#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000	/* Destination scatter enable */
-#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000	/* Source gather enable */
-
-#define dmacHw_REG_CTL_DINC_MASK                    0x00000180	/* Destination address inc/dec mask */
-#define dmacHw_REG_CTL_DINC_INC                     0x00000000	/* Destination address increment */
-#define dmacHw_REG_CTL_DINC_DEC                     0x00000080	/* Destination address decrement */
-#define dmacHw_REG_CTL_DINC_NC                      0x00000100	/* Destination address no change */
-
-#define dmacHw_REG_CTL_SINC_MASK                    0x00000600	/* Source address inc/dec mask */
-#define dmacHw_REG_CTL_SINC_INC                     0x00000000	/* Source address increment */
-#define dmacHw_REG_CTL_SINC_DEC                     0x00000200	/* Source address decrement */
-#define dmacHw_REG_CTL_SINC_NC                      0x00000400	/* Source address no change */
-
-#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800	/* Destination burst transaction length */
-#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000	/* No Destination burst */
-#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800	/* Destination burst transaction length 4 */
-#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000	/* Destination burst transaction length 8 */
-#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800	/* Destination burst transaction length 16 */
-
-#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000	/* Source burst transaction length */
-#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000	/* No Source burst */
-#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000	/* Source burst transaction length 4 */
-#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000	/* Source burst transaction length 8 */
-#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000	/* Source burst transaction length 16 */
-
-#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000	/* Transfer type and flow controller */
-#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000	/* Memory to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000	/* Memory to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000	/* Peripheral to Memory with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000	/* Peripheral to Peripheral with DMAC as flow controller */
-#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000	/* Peripheral to Memory with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000	/* Peripheral to Peripheral with Source Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000	/* Memory to Peripheral with Peripheral as flow controller */
-#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000	/* Peripheral to Peripheral with Destination Peripheral as flow controller */
-
-#define dmacHw_REG_CTL_DMS_MASK                     0x01800000	/* Destination AHB master interface */
-#define dmacHw_REG_CTL_DMS_1                        0x00000000	/* Destination AHB master interface 1 */
-#define dmacHw_REG_CTL_DMS_2                        0x00800000	/* Destination AHB master interface 2 */
-
-#define dmacHw_REG_CTL_SMS_MASK                     0x06000000	/* Source AHB master interface */
-#define dmacHw_REG_CTL_SMS_1                        0x00000000	/* Source AHB master interface 1 */
-#define dmacHw_REG_CTL_SMS_2                        0x02000000	/* Source AHB master interface 2 */
-
-#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000	/* Block chaining enable for destination side */
-#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000	/* Block chaining enable for source side */
-
-/* Bit mask for REG_DMACx_CTL_HI */
-#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF	/* Block transfer size */
-#define dmacHw_REG_CTL_DONE                         0x00001000	/* Block trasnfer done */
-
-/* Bit mask for REG_DMACx_CFG_LO */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5	/* Channel priority shift */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0	/* Channel priority mask */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000	/* Channel priority 0 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020	/* Channel priority 1 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040	/* Channel priority 2 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060	/* Channel priority 3 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080	/* Channel priority 4 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0	/* Channel priority 5 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0	/* Channel priority 6 */
-#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0	/* Channel priority 7 */
-
-#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100	/* Channel suspend */
-#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200	/* Channel FIFO empty */
-#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400	/* Destination channel SW handshaking */
-#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800	/* Source channel SW handshaking */
-
-#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000	/* Channel locking mask */
-#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000	/* Channel lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000	/* Channel lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000	/* Channel lock over the transaction */
-#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000	/* Channel lock enable */
-
-#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000	/* Bus locking mask */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000	/* Bus lock over the entire DMA transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000	/* Bus lock over the block transfer operation */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000	/* Bus lock over the transaction */
-#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000	/* Bus lock enable */
-
-#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000	/* Destination channel handshaking signal polarity low */
-#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000	/* Source channel handshaking signal polarity low */
-
-#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000	/* Maximum AMBA burst length */
-
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000	/* Source address auto reload */
-#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000	/* Destination address auto reload */
-
-/* Bit mask for REG_DMACx_CFG_HI */
-#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001	/* Source transaction request is serviced when destination is ready */
-#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002	/* Initiate burst transaction when enough data in available in FIFO */
-
-#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C	/* AHB protection mask */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004	/* AHB protection 1 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008	/* AHB protection 2 */
-#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010	/* AHB protection 3 */
-
-#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020	/* Destination status update enable */
-#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040	/* Source status update enable */
-
-#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780	/* Source peripheral hardware interface mask */
-#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800	/* Destination peripheral hardware interface mask */
-
-/* DMA Configuration Parameters */
-#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700	/* Number of channels */
-#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800	/* Number of master interface */
-#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f	/* Maximum brust size */
-#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000	/* Data transfer width */
-
-/* Define GET/SET macros to program the registers */
-#define dmacHw_SET_SAR(module, channel, addr)          (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DAR(module, channel, addr)          (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_LLP(module, channel, ptr)           (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
-
-#define dmacHw_GET_SSTAT(module, channel)              (dmacHw_REG_SSTAT((module), (channel)))
-#define dmacHw_GET_DSTAT(module, channel)              (dmacHw_REG_DSTAT((module), (channel)))
-
-#define dmacHw_SET_SSTATAR(module, channel, addr)      (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
-#define dmacHw_SET_DSTATAR(module, channel, addr)      (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
-
-#define dmacHw_SET_CONTROL_LO(module, channel, ctl)    (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_LO(module, channel)       (dmacHw_REG_CTL_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_LO(module, channel)         (dmacHw_REG_CTL_LO((module), (channel)))
-
-#define dmacHw_SET_CONTROL_HI(module, channel, ctl)    (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
-#define dmacHw_RESET_CONTROL_HI(module, channel)       (dmacHw_REG_CTL_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONTROL_HI(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)))
-
-#define dmacHw_GET_BLOCK_SIZE(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
-#define dmacHw_DMA_COMPLETE(module, channel)           (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
-
-#define dmacHw_SET_CONFIG_LO(module, channel, cfg)     (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_LO(module, channel)        (dmacHw_REG_CFG_LO((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_LO(module, channel)          (dmacHw_REG_CFG_LO((module), (channel)))
-#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len)    (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
-#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
-#define dmacHw_SET_AHB_HPROT(module, channel, protect)  (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
-
-#define dmacHw_SET_CONFIG_HI(module, channel, cfg)      (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
-#define dmacHw_RESET_CONFIG_HI(module, channel)         (dmacHw_REG_CFG_HI((module), (channel)) = 0)
-#define dmacHw_GET_CONFIG_HI(module, channel)           (dmacHw_REG_CFG_HI((module), (channel)))
-#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
-#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
-#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
-#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
-
-#define dmacHw_DMA_START(module, channel)              (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_DMA_STOP(module, channel)               (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DMA_ENABLE(module)                      (dmacHw_REG_MISC_CFG((module)) = 1)
-#define dmacHw_DMA_DISABLE(module)                     (dmacHw_REG_MISC_CFG((module)) = 0)
-
-#define dmacHw_TRAN_INT_ENABLE(module, channel)        (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
-
-#define dmacHw_TRAN_INT_DISABLE(module, channel)       (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_BLOCK_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_ERROR_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_STRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
-#define dmacHw_DTRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
-
-#define dmacHw_TRAN_INT_CLEAR(module, channel)         (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
-#define dmacHw_BLOCK_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
-#define dmacHw_ERROR_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
-
-#define dmacHw_GET_NUM_CHANNEL(module)                 (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
-#define dmacHw_GET_NUM_INTERFACE(module)               (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
-#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel)     ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
-#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
-
-#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
deleted file mode 100644
index cfa91be..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_HW_CFG_H
-#define CSP_HW_CFG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <cfg_global.h>
-#include <mach/csp/cap_inline.h>
-
-#if defined(__KERNEL__)
-#include <mach/memory_settings.h>
-#else
-#include <hw_cfg.h>
-#endif
-
-/* Some items that can be defined externally, but will be set to default values */
-/* if they are not defined. */
-/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS is enabled. */
-/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
-/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
-
-#if defined(CFG_GLOBAL_CHIP)
-  #if (CFG_GLOBAL_CHIP == FPGA11107)
-     #define HW_CFG_BUS_CLK_HZ            5000000
-     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
-     #define HW_CFG_DDR_PHY_OMIT
-     #define HW_CFG_UART_CLK_HZ           7500000
-  #else
-     #define HW_CFG_PLL_VCO_HZ           2000000000
-     #define HW_CFG_PLL2_VCO_HZ          1800000000
-     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
-     #define HW_CFG_BUS_CLK_HZ            166666666
-     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
-     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-     #define HW_CFG_UART_CLK_HZ           142857142
-     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
-  #endif
-#else
-   #define HW_CFG_PLL_VCO_HZ           1800000000
-   #define HW_CFG_PLL2_VCO_HZ          1800000000
-   #define HW_CFG_ARM_CLK_HZ            450000000
-   #define HW_CFG_BUS_CLK_HZ            150000000
-   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
-   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
-   #define HW_CFG_UART_CLK_HZ           150000000
-   #define HW_CFG_VPM_CLK_HZ            300000000
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_HW_CFG_H */
-
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
deleted file mode 100644
index 0aeb6a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    intcHw_reg.h
-*
-*  @brief   platform specific interrupt controller bit assignments
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_REG_H
-#define _INTCHW_REG_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define INTCHW_NUM_IRQ_PER_INTC   32	/* Maximum number of interrupt controllers */
-#define INTCHW_NUM_INTC           3
-
-/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
-
-/* INTC0 - interrupt controller 0 */
-#define INTCHW_INTC0_PIF_BITNUM           31	/* Peripheral interface interrupt */
-#define INTCHW_INTC0_CLCD_BITNUM          30	/* LCD Controller interrupt */
-#define INTCHW_INTC0_GE_BITNUM            29	/* Graphic engine interrupt */
-#define INTCHW_INTC0_APM_BITNUM           28	/* Audio process module interrupt */
-#define INTCHW_INTC0_ESW_BITNUM           27	/* Ethernet switch interrupt */
-#define INTCHW_INTC0_SPIH_BITNUM          26	/* SPI host interrupt */
-#define INTCHW_INTC0_TIMER3_BITNUM        25	/* Timer3 interrupt */
-#define INTCHW_INTC0_TIMER2_BITNUM        24	/* Timer2 interrupt */
-#define INTCHW_INTC0_TIMER1_BITNUM        23	/* Timer1 interrupt */
-#define INTCHW_INTC0_TIMER0_BITNUM        22	/* Timer0 interrupt */
-#define INTCHW_INTC0_SDIOH1_BITNUM        21	/* SDIO1 host interrupt */
-#define INTCHW_INTC0_SDIOH0_BITNUM        20	/* SDIO0 host interrupt */
-#define INTCHW_INTC0_USBD_BITNUM          19	/* USB device interrupt */
-#define INTCHW_INTC0_USBH1_BITNUM         18	/* USB1 host interrupt */
-#define INTCHW_INTC0_USBHD2_BITNUM        17	/* USB host2/device2 interrupt */
-#define INTCHW_INTC0_VPM_BITNUM           16	/* Voice process module interrupt */
-#define INTCHW_INTC0_DMA1C7_BITNUM        15	/* DMA1 channel 7 interrupt */
-#define INTCHW_INTC0_DMA1C6_BITNUM        14	/* DMA1 channel 6 interrupt */
-#define INTCHW_INTC0_DMA1C5_BITNUM        13	/* DMA1 channel 5 interrupt */
-#define INTCHW_INTC0_DMA1C4_BITNUM        12	/* DMA1 channel 4 interrupt */
-#define INTCHW_INTC0_DMA1C3_BITNUM        11	/* DMA1 channel 3 interrupt */
-#define INTCHW_INTC0_DMA1C2_BITNUM        10	/* DMA1 channel 2 interrupt */
-#define INTCHW_INTC0_DMA1C1_BITNUM         9	/* DMA1 channel 1 interrupt */
-#define INTCHW_INTC0_DMA1C0_BITNUM         8	/* DMA1 channel 0 interrupt */
-#define INTCHW_INTC0_DMA0C7_BITNUM         7	/* DMA0 channel 7 interrupt */
-#define INTCHW_INTC0_DMA0C6_BITNUM         6	/* DMA0 channel 6 interrupt */
-#define INTCHW_INTC0_DMA0C5_BITNUM         5	/* DMA0 channel 5 interrupt */
-#define INTCHW_INTC0_DMA0C4_BITNUM         4	/* DMA0 channel 4 interrupt */
-#define INTCHW_INTC0_DMA0C3_BITNUM         3	/* DMA0 channel 3 interrupt */
-#define INTCHW_INTC0_DMA0C2_BITNUM         2	/* DMA0 channel 2 interrupt */
-#define INTCHW_INTC0_DMA0C1_BITNUM         1	/* DMA0 channel 1 interrupt */
-#define INTCHW_INTC0_DMA0C0_BITNUM         0	/* DMA0 channel 0 interrupt */
-
-#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
-#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
-#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
-#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
-#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
-#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
-#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
-#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
-#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
-#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
-#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
-#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
-#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
-#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
-#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
-#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
-#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
-#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
-#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
-#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
-#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
-#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
-#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
-#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
-#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
-#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
-#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
-#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
-#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
-#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
-#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
-#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
-
-/* INTC1 - interrupt controller 1 */
-#define INTCHW_INTC1_DDRVPMP_BITNUM       27	/* DDR and VPM PLL clock phase relationship interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRVPMT_BITNUM       26	/* DDR and VPM HW phase align timeout interrupt (Not for A0) */
-#define INTCHW_INTC1_DDRP_BITNUM          26	/* DDR and PLL clock phase relationship interrupt (For A0 only)) */
-#define INTCHW_INTC1_RTC2_BITNUM          25	/* Real time clock tamper interrupt */
-#define INTCHW_INTC1_VDEC_BITNUM          24	/* Hantro Video Decoder interrupt */
-/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
-#define INTCHW_INTC1_SPUM_BITNUM          23	/* Secure process module interrupt */
-#define INTCHW_INTC1_RTC1_BITNUM          22	/* Real time clock one-shot interrupt */
-#define INTCHW_INTC1_RTC0_BITNUM          21	/* Real time clock periodic interrupt */
-#define INTCHW_INTC1_RNG_BITNUM           20	/* Random number generator interrupt */
-#define INTCHW_INTC1_FMPU_BITNUM          19	/* Flash memory parition unit interrupt */
-#define INTCHW_INTC1_VMPU_BITNUM          18	/* VRAM memory partition interrupt */
-#define INTCHW_INTC1_DMPU_BITNUM          17	/* DDR2 memory partition interrupt */
-#define INTCHW_INTC1_KEYC_BITNUM          16	/* Key pad controller interrupt */
-#define INTCHW_INTC1_TSC_BITNUM           15	/* Touch screen controller interrupt */
-#define INTCHW_INTC1_UART0_BITNUM         14	/* UART 0 */
-#define INTCHW_INTC1_WDOG_BITNUM          13	/* Watchdog timer interrupt */
-
-#define INTCHW_INTC1_UART1_BITNUM         12	/* UART 1 */
-#define INTCHW_INTC1_PMUIRQ_BITNUM        11	/* ARM performance monitor interrupt */
-#define INTCHW_INTC1_COMMRX_BITNUM        10	/* ARM DDC receive interrupt */
-#define INTCHW_INTC1_COMMTX_BITNUM         9	/* ARM DDC transmit interrupt */
-#define INTCHW_INTC1_FLASHC_BITNUM         8	/* Flash controller interrupt */
-#define INTCHW_INTC1_GPHY_BITNUM           7	/* Gigabit Phy interrupt */
-#define INTCHW_INTC1_SPIS_BITNUM           6	/* SPI slave interrupt */
-#define INTCHW_INTC1_I2CS_BITNUM           5	/* I2C slave interrupt */
-#define INTCHW_INTC1_I2CH_BITNUM           4	/* I2C host interrupt */
-#define INTCHW_INTC1_I2S1_BITNUM           3	/* I2S1 interrupt */
-#define INTCHW_INTC1_I2S0_BITNUM           2	/* I2S0 interrupt */
-#define INTCHW_INTC1_GPIO1_BITNUM          1	/* GPIO bit 64//32 combined interrupt */
-#define INTCHW_INTC1_GPIO0_BITNUM          0	/* GPIO bit 31//0 combined interrupt */
-
-#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
-#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
-#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
-#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
-#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
-#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
-#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
-#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
-#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
-#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
-#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
-#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
-#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
-#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
-#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
-#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
-#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
-#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
-#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
-#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
-#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
-#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
-#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
-#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
-#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
-#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
-#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
-#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
-#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
-
-/* SINTC secure int controller */
-#define INTCHW_SINTC_RTC2_BITNUM          15	/* Real time clock tamper interrupt */
-#define INTCHW_SINTC_TIMER3_BITNUM        14	/* Secure timer3 interrupt */
-#define INTCHW_SINTC_TIMER2_BITNUM        13	/* Secure timer2 interrupt */
-#define INTCHW_SINTC_TIMER1_BITNUM        12	/* Secure timer1 interrupt */
-#define INTCHW_SINTC_TIMER0_BITNUM        11	/* Secure timer0 interrupt */
-#define INTCHW_SINTC_SPUM_BITNUM          10	/* Secure process module interrupt */
-#define INTCHW_SINTC_RTC1_BITNUM           9	/* Real time clock one-shot interrupt */
-#define INTCHW_SINTC_RTC0_BITNUM           8	/* Real time clock periodic interrupt */
-#define INTCHW_SINTC_RNG_BITNUM            7	/* Random number generator interrupt */
-#define INTCHW_SINTC_FMPU_BITNUM           6	/* Flash memory parition unit interrupt */
-#define INTCHW_SINTC_VMPU_BITNUM           5	/* VRAM memory partition interrupt */
-#define INTCHW_SINTC_DMPU_BITNUM           4	/* DDR2 memory partition interrupt */
-#define INTCHW_SINTC_KEYC_BITNUM           3	/* Key pad controller interrupt */
-#define INTCHW_SINTC_TSC_BITNUM            2	/* Touch screen controller interrupt */
-#define INTCHW_SINTC_UART0_BITNUM          1	/* UART0 interrupt */
-#define INTCHW_SINTC_WDOG_BITNUM           0	/* Watchdog timer interrupt */
-
-#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
-#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
-#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
-#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
-#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
-#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
-#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
-#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
-#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
-#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
-#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
-#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
-#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
-#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
-#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
-#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
-
-/* PL192 Vectored Interrupt Controller (VIC) layout */
-#define INTCHW_IRQSTATUS      0x00	/* IRQ status register */
-#define INTCHW_FIQSTATUS      0x04	/* FIQ status register */
-#define INTCHW_RAWINTR        0x08	/* Raw Interrupt Status register */
-#define INTCHW_INTSELECT      0x0c	/* Interrupt Select Register */
-#define INTCHW_INTENABLE      0x10	/* Interrupt Enable Register */
-#define INTCHW_INTENCLEAR     0x14	/* Interrupt Enable Clear Register */
-#define INTCHW_SOFTINT        0x18	/* Soft Interrupt Register */
-#define INTCHW_SOFTINTCLEAR   0x1c	/* Soft Interrupt Clear Register */
-#define INTCHW_PROTECTION     0x20	/* Protection Enable Register */
-#define INTCHW_SWPRIOMASK     0x24	/* Software Priority Mask Register */
-#define INTCHW_PRIODAISY      0x28	/* Priority Daisy Chain Register */
-#define INTCHW_VECTADDR0      0x100	/* Vector Address Registers */
-#define INTCHW_VECTPRIO0      0x200	/* Vector Priority Registers 0-31 */
-#define INTCHW_ADDRESS        0xf00	/* Vector Address Register 0-31 */
-#define INTCHW_PID            0xfe0	/* Peripheral ID Register 0-3 */
-#define INTCHW_PCELLID        0xff0	/* PrimeCell ID Register 0-3 */
-
-/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
-/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
-/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENCLEAR) = mask;
-}
-
-/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
-{
-	__REG32(basep + INTCHW_INTENABLE) = mask;
-}
-
-#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
deleted file mode 100644
index ad58cf8..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_addr.h
-*
-*  @brief   Memory Map address definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_ADDR_H
-#define _MM_ADDR_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-/*  Memory Map address definitions */
-
-#define MM_ADDR_DDR                0x00000000
-
-#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000	/* 16 MB - Reserved external memory for VPM use */
-
-#define MM_ADDR_IO_FLASHC          0x20000000
-#define MM_ADDR_IO_BROM            0x30000000
-#define MM_ADDR_IO_ARAM            0x30100000	/* 64 KB - extra cycle latency - WS switch */
-#define MM_ADDR_IO_DMA0            0x30200000
-#define MM_ADDR_IO_DMA1            0x30300000
-#define MM_ADDR_IO_ESW             0x30400000
-#define MM_ADDR_IO_CLCD            0x30500000
-#define MM_ADDR_IO_PIF             0x30580000
-#define MM_ADDR_IO_APM             0x30600000
-#define MM_ADDR_IO_SPUM            0x30700000
-#define MM_ADDR_IO_VPM_PROG        0x30800000
-#define MM_ADDR_IO_VPM_DATA        0x30A00000
-#define MM_ADDR_IO_VRAM            0x40000000	/* 64 KB  - security block in front of it */
-#define MM_ADDR_IO_CHIPC           0x80000000
-#define MM_ADDR_IO_UMI             0x80001000
-#define MM_ADDR_IO_NAND            0x80001800
-#define MM_ADDR_IO_LEDM            0x80002000
-#define MM_ADDR_IO_PWM             0x80002040
-#define MM_ADDR_IO_VINTC           0x80003000
-#define MM_ADDR_IO_GPIO0           0x80004000
-#define MM_ADDR_IO_GPIO1           0x80004800
-#define MM_ADDR_IO_I2CS            0x80005000
-#define MM_ADDR_IO_SPIS            0x80006000
-#define MM_ADDR_IO_HPM             0x80007400
-#define MM_ADDR_IO_HPM_REMAP       0x80007800
-#define MM_ADDR_IO_TZPC            0x80008000
-#define MM_ADDR_IO_MPU             0x80009000
-#define MM_ADDR_IO_SPUMP           0x8000a000
-#define MM_ADDR_IO_PKA             0x8000b000
-#define MM_ADDR_IO_RNG             0x8000c000
-#define MM_ADDR_IO_KEYC            0x8000d000
-#define MM_ADDR_IO_BBL             0x8000e000
-#define MM_ADDR_IO_OTP             0x8000f000
-#define MM_ADDR_IO_I2S0            0x80010000
-#define MM_ADDR_IO_I2S1            0x80011000
-#define MM_ADDR_IO_UARTA           0x80012000
-#define MM_ADDR_IO_UARTB           0x80013000
-#define MM_ADDR_IO_I2CH            0x80014020
-#define MM_ADDR_IO_SPIH            0x80015000
-#define MM_ADDR_IO_TSC             0x80016000
-#define MM_ADDR_IO_TMR             0x80017000
-#define MM_ADDR_IO_WATCHDOG        0x80017800
-#define MM_ADDR_IO_ETM             0x80018000
-#define MM_ADDR_IO_DDRC            0x80019000
-#define MM_ADDR_IO_SINTC           0x80100000
-#define MM_ADDR_IO_INTC0           0x80200000
-#define MM_ADDR_IO_INTC1           0x80201000
-#define MM_ADDR_IO_GE              0x80300000
-#define MM_ADDR_IO_USB_CTLR0       0x80400000
-#define MM_ADDR_IO_USB_CTLR1       0x80410000
-#define MM_ADDR_IO_USB_PHY         0x80420000
-#define MM_ADDR_IO_SDIOH0          0x80500000
-#define MM_ADDR_IO_SDIOH1          0x80600000
-#define MM_ADDR_IO_VDEC            0x80700000
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
deleted file mode 100644
index de92ec6..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    mm_io.h
-*
-*  @brief   Memory Map I/O definitions
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef _MM_IO_H
-#define _MM_IO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/mm_addr.h>
-
-#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(CONFIG_MMU)
-
-/* This macro is referenced in <mach/io.h>
- * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
- * This macro is referenced in <asm/arch/io.h>
- *
- * Assume VPM address is the last x MB of memory.  For VPM, map to
- * 0xf0000000 and up.
- */
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#ifdef __ASSEMBLY__
-#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
-#else
-#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
-			(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
-#endif
-#endif
-
-/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#ifdef __ASSEMBLY__
-#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
-#else
-#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
-			((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
-#endif
-#endif
-
-#else
-
-#ifndef MM_IO_PHYS_TO_VIRT
-#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
-#endif
-
-#ifndef MM_IO_VIRT_TO_PHYS
-#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
-#endif
-
-#endif
-
-/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
-#define MM_IO_BASE_FLASHC              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
-#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
-#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
-
-#define MM_IO_START MM_ADDR_IO_FLASHC	/* Physical beginning of IO mapped memory */
-#define MM_IO_BASE  MM_IO_BASE_FLASHC	/* Virtual beginning of IO mapped memory */
-
-#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
-#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
-#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
-#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
-#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
-#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
-#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
-#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
-#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
-#define MM_IO_BASE_VPM_PROG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
-#define MM_IO_BASE_VPM_DATA            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
-
-#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
-
-#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
-#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
-#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
-#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
-#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
-#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
-#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
-#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
-#define MM_IO_BASE_WATCHDOG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
-#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
-#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
-#define MM_IO_BASE_HPM_REMAP           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
-#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
-#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
-#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
-#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
-#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
-#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
-#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
-#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
-#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
-#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
-#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
-#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
-#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
-#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
-#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
-#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
-#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
-#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
-#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
-#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
-#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
-#define MM_IO_BASE_USB_CTLR0           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
-#define MM_IO_BASE_USB_CTLR1           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
-#define MM_IO_BASE_USB_PHY             MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
-#define MM_IO_BASE_SDIOH0              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
-#define MM_IO_BASE_SDIOH1              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
-#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
-
-#define MM_IO_BASE_VPM_EXTMEM_RSVD     MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
deleted file mode 100644
index d15f5f3..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_def.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_DEF_H
-#define SECHW_DEF_H
-
-#include <mach/csp/mm_io.h>
-
-/* Bit mask for various secure device */
-#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
-#define secHw_BLK_MASK_KEY_SCAN         0x00000002
-#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
-#define secHw_BLK_MASK_UART0            0x00000008
-#define secHw_BLK_MASK_UART1            0x00000010
-#define secHw_BLK_MASK_WATCHDOG         0x00000020
-#define secHw_BLK_MASK_SPUM             0x00000040
-#define secHw_BLK_MASK_DDR2             0x00000080
-#define secHw_BLK_MASK_EXT_MEM          0x00000100
-#define secHw_BLK_MASK_ESW              0x00000200
-#define secHw_BLK_MASK_SPU              0x00010000
-#define secHw_BLK_MASK_PKA              0x00020000
-#define secHw_BLK_MASK_RNG              0x00040000
-#define secHw_BLK_MASK_RTC              0x00080000
-#define secHw_BLK_MASK_OTP              0x00100000
-#define secHw_BLK_MASK_BOOT             0x00200000
-#define secHw_BLK_MASK_MPU              0x00400000
-#define secHw_BLK_MASK_TZCTRL           0x00800000
-#define secHw_BLK_MASK_INTR             0x01000000
-
-/* Trustzone register set */
-typedef struct {
-	volatile uint32_t status;	/* read only - reflects status of writes of 2 write registers */
-	volatile uint32_t setUnsecure;	/* write only. reads back as 0 */
-	volatile uint32_t setSecure;	/* write only. reads back as 0 */
-} secHw_TZREG_t;
-
-/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
-/* is for the higher 16 bits. */
-
-typedef enum {
-	secHw_IDX_LS = 0,
-	secHw_IDX_MS = 1,
-	secHw_IDX_NUM
-} secHw_IDX_e;
-
-typedef struct {
-	volatile secHw_TZREG_t reg[secHw_IDX_NUM];
-} secHw_REGS_t;
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MASK_XXXXXX */
-    );
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void);
-
-#include <mach/csp/secHw_inline.h>
-
-#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
deleted file mode 100644
index 9cd6a03..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    secHw_inline.h
-*
-*  @brief   Definitions for configuring/testing secure blocks
-*
-*  @note
-*     None
-*/
-/****************************************************************************/
-
-#ifndef SECHW_INLINE_H
-#define SECHW_INLINE_H
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setSecure(uint32_t mask	/*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
-	}
-
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Configures a device as a non-secure device
-*
-*/
-/****************************************************************************/
-static inline void secHw_setUnsecure(uint32_t mask	/*  mask of type secHw_BLK_MASK_XXXXXX */
-    ) {
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	if (mask & 0x0000FFFF) {
-		regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
-	}
-	if (mask & 0xFFFF0000) {
-		regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
-	}
-}
-
-/****************************************************************************/
-/**
-*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
-*
-*/
-/****************************************************************************/
-static inline uint32_t secHw_getStatus(void)
-{
-	secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
-
-	return (regp->reg[1].status << 16) + regp->reg[0].status;
-}
-
-#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
deleted file mode 100644
index 3080ac7..0000000
--- a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*  @file    tmrHw_reg.h
-*
-*  @brief   Definitions for low level Timer registers
-*
-*/
-/****************************************************************************/
-#ifndef _TMRHW_REG_H
-#define _TMRHW_REG_H
-
-#include <mach/csp/mm_io.h>
-#include <mach/csp/hw_cfg.h>
-/* Base address */
-#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
-
-/*
-This platform has four different timers running at different clock speed
-
-Timer one   (Timer ID 0) runs at  25 MHz
-Timer two   (Timer ID 1) runs at  25 MHz
-Timer three (Timer ID 2) runs at 150 MHz
-Timer four  (Timer ID 3) runs at 150 MHz
-*/
-#define tmrHw_LOW_FREQUENCY_MHZ         25	/* Always 25MHz from XTAL */
-#define tmrHw_LOW_FREQUENCY_HZ          25000000
-
-#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
-#define tmrHw_HIGH_FREQUENCY_MHZ        150	/* Always 150MHz for FPGA */
-#define tmrHw_HIGH_FREQUENCY_HZ         150000000
-#else
-#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
-#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
-#endif
-
-#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
-#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
-#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)	/* maximum number of count a timer can count */
-#define tmrHw_TIMER_NUM_COUNT           (4)	/* Number of timer module supported */
-
-typedef struct {
-	uint32_t LoadValue;	/* Load value for timer */
-	uint32_t CurrentValue;	/* Current value for timer */
-	uint32_t Control;	/* Control register */
-	uint32_t InterruptClear;	/* Interrupt clear register */
-	uint32_t RawInterruptStatus;	/* Raw interrupt status */
-	uint32_t InterruptStatus;	/* Masked interrupt status */
-	uint32_t BackgroundLoad;	/* Background load value */
-	uint32_t padding;	/* Padding register */
-} tmrHw_REG_t;
-
-/* Control bot masks */
-#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
-#define tmrHw_CONTROL_PERIODIC                0x00000040
-#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
-#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
-#define tmrHw_CONTROL_PRESCALE_1              0x00000000
-#define tmrHw_CONTROL_PRESCALE_16             0x00000004
-#define tmrHw_CONTROL_PRESCALE_256            0x00000008
-#define tmrHw_CONTROL_32BIT                   0x00000002
-#define tmrHw_CONTROL_ONESHOT                 0x00000001
-#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
-
-#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
-
-#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
-
-#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
deleted file mode 100644
index 7254378..0000000
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ /dev/null
@@ -1,630 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-*   @file   dma.h
-*
-*   @brief  API definitions for the linux DMA interface.
-*/
-/****************************************************************************/
-
-#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
-#define ASM_ARM_ARCH_BCMRING_DMA_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <linux/kernel.h>
-#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
-#include <mach/timer.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
-/* and line number of the reservation request will be recorded in the channel table */
-
-#define DMA_DEBUG_TRACK_RESERVATION   1
-
-#define DMA_NUM_CONTROLLERS     2
-#define DMA_NUM_CHANNELS        8	/* per controller */
-
-typedef enum {
-	DMA_DEVICE_MEM_TO_MEM,	/* For memory to memory transfers */
-	DMA_DEVICE_I2S0_DEV_TO_MEM,
-	DMA_DEVICE_I2S0_MEM_TO_DEV,
-	DMA_DEVICE_I2S1_DEV_TO_MEM,
-	DMA_DEVICE_I2S1_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
-	DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
-	DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,	/* Additional mic input for beam-forming */
-	DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
-	DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
-	DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
-	DMA_DEVICE_SPUM_DEV_TO_MEM,
-	DMA_DEVICE_SPUM_MEM_TO_DEV,
-	DMA_DEVICE_SPIH_DEV_TO_MEM,
-	DMA_DEVICE_SPIH_MEM_TO_DEV,
-	DMA_DEVICE_UART_A_DEV_TO_MEM,
-	DMA_DEVICE_UART_A_MEM_TO_DEV,
-	DMA_DEVICE_UART_B_DEV_TO_MEM,
-	DMA_DEVICE_UART_B_MEM_TO_DEV,
-	DMA_DEVICE_PIF_MEM_TO_DEV,
-	DMA_DEVICE_PIF_DEV_TO_MEM,
-	DMA_DEVICE_ESW_DEV_TO_MEM,
-	DMA_DEVICE_ESW_MEM_TO_DEV,
-	DMA_DEVICE_VPM_MEM_TO_MEM,
-	DMA_DEVICE_CLCD_MEM_TO_MEM,
-	DMA_DEVICE_NAND_MEM_TO_MEM,
-	DMA_DEVICE_MEM_TO_VRAM,
-	DMA_DEVICE_VRAM_TO_MEM,
-
-	/* Add new entries before this line. */
-
-	DMA_NUM_DEVICE_ENTRIES,
-	DMA_DEVICE_NONE = 0xff,	/* Special value to indicate that no device is currently assigned. */
-
-} DMA_Device_t;
-
-/****************************************************************************
-*
-*   The DMA_Handle_t is the primary object used by callers of the API.
-*
-*****************************************************************************/
-
-#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
-
-typedef int DMA_Handle_t;
-
-/****************************************************************************
-*
-*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
-*   to point to regions of memory.
-*
-*****************************************************************************/
-
-typedef struct {
-	void *virtAddr;		/* Virtual Address of the descriptor ring */
-	dma_addr_t physAddr;	/* Physical address of the descriptor ring */
-	int descriptorsAllocated;	/* Number of descriptors allocated in the descriptor ring */
-	size_t bytesAllocated;	/* Number of bytes allocated in the descriptor ring */
-
-} DMA_DescriptorRing_t;
-
-/****************************************************************************
-*
-*   The DMA_DeviceAttribute_t contains information which describes a
-*   particular DMA device (or peripheral).
-*
-*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
-*   statically initialized.
-*
-*****************************************************************************/
-
-/* The device handler is called whenever a DMA operation completes. The reaon */
-/* for it to be called will be a bitmask with one or more of the following bits */
-/* set. */
-
-#define DMA_HANDLER_REASON_BLOCK_COMPLETE       dmacHw_INTERRUPT_STATUS_BLOCK
-#define DMA_HANDLER_REASON_TRANSFER_COMPLETE    dmacHw_INTERRUPT_STATUS_TRANS
-#define DMA_HANDLER_REASON_ERROR                dmacHw_INTERRUPT_STATUS_ERROR
-
-typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
-				     void *userData);
-
-#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
-#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
-#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004	/* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
-#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008	/* If set, allocate from DMA1 before allocating from DMA0 */
-#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
-#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
-#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
-#define DMA_DEVICE_FLAG_IN_USE              0x00000800	/* If set, device is in use on a channel */
-
-/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
-/*       determine which DMA controllers a given device can be used from, and the interface */
-/*       array determeines the actual interface number to use for a given controller. */
-
-typedef struct {
-	uint32_t flags;		/* Bitmask of DMA_DEVICE_FLAG_xxx constants */
-	uint8_t dedicatedController;	/* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	uint8_t dedicatedChannel;	/* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
-	const char *name;	/* Will show up in the /proc entry */
-
-	uint32_t dmacPort[DMA_NUM_CONTROLLERS];	/* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
-
-	dmacHw_CONFIG_t config;	/* Configuration to use when DMA'ing using this device */
-
-	void *userData;		/* Passed to the devHandler */
-	DMA_DeviceHandler_t devHandler;	/* Called when DMA operations finish. */
-
-	timer_tick_count_t transferStartTime;	/* Time the current transfer was started */
-
-	/* The following statistical information will be collected and presented in a proc entry. */
-	/* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
-	/*       a 64 bit counter. */
-
-	uint64_t numTransfers;	/* Number of DMA transfers performed */
-	uint64_t transferTicks;	/* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
-	uint64_t transferBytes;	/* Total bytes transferred */
-	uint32_t timesBlocked;	/* Number of times a channel was unavailable */
-	uint32_t numBytes;	/* Last transfer size */
-
-	/* It's not possible to free memory which is allocated for the descriptors from within */
-	/* the ISR. So make the presumption that a given device will tend to use the */
-	/* same sized buffers over and over again, and we keep them around. */
-
-	DMA_DescriptorRing_t ring;	/* Ring of descriptors allocated for this device */
-
-	/* We stash away some of the information from the previous transfer. If back-to-back */
-	/* transfers are performed from the same buffer, then we don't have to keep re-initializing */
-	/* the descriptor buffers. */
-
-	uint32_t prevNumBytes;
-	dma_addr_t prevSrcData;
-	dma_addr_t prevDstData;
-
-} DMA_DeviceAttribute_t;
-
-/****************************************************************************
-*
-*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
-*   data structures and don't belong in this header file, but are included
-*   merely for discussion.
-*
-*   By the time this is implemented, these structures will be moved out into
-*   the appropriate C source file instead.
-*
-*****************************************************************************/
-
-/****************************************************************************
-*
-*   The DMA_Channel_t contains state information about each DMA channel. Some
-*   of the channels are dedicated. Non-dedicated channels are shared
-*   amongst the other devices.
-*
-*****************************************************************************/
-
-#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
-#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
-#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
-#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
-
-typedef struct {
-	uint32_t flags;		/* bitmask of DMA_CHANNEL_FLAG_xxx constants */
-	DMA_Device_t devType;	/* Device this channel is currently reserved for */
-	DMA_Device_t lastDevType;	/* Device type that used this previously */
-	char name[20];		/* Name passed onto request_irq */
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-	const char *fileName;	/* Place where channel reservation took place */
-	int lineNum;		/* Place where channel reservation took place */
-#endif
-	dmacHw_HANDLE_t dmacHwHandle;	/* low level channel handle. */
-
-} DMA_Channel_t;
-
-/****************************************************************************
-*
-*   The DMA_Controller_t contains state information about each DMA controller.
-*
-*   The freeChannelQ is stored in the controller data structure rather than
-*   the channel data structure since several of the devices are accessible
-*   from multiple controllers, and there is no way to know which controller
-*   will become available first.
-*
-*****************************************************************************/
-
-typedef struct {
-	DMA_Channel_t channel[DMA_NUM_CHANNELS];
-
-} DMA_Controller_t;
-
-/****************************************************************************
-*
-*   The DMA_Global_t contains all of the global state information used by
-*   the DMA code.
-*
-*   Callers which need to allocate a shared channel will be queued up
-*   on the freeChannelQ until a channel becomes available.
-*
-*****************************************************************************/
-
-typedef struct {
-	struct semaphore lock;	/* acquired when manipulating table entries */
-	wait_queue_head_t freeChannelQ;
-
-	DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
-
-} DMA_Global_t;
-
-/* ---- Variable Externs ------------------------------------------------- */
-
-extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
-
-/* ---- Function Prototypes ---------------------------------------------- */
-
-#if defined(__KERNEL__)
-
-/****************************************************************************/
-/**
-*   Initializes the DMA module.
-*
-*   @return
-*       0       - Success
-*       < 0     - Error
-*/
-/****************************************************************************/
-
-int dma_init(void);
-
-#if (DMA_DEBUG_TRACK_RESERVATION)
-DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
-				     int lineNum);
-#define dma_request_channel(dev)  dma_request_channel_dbg(dev, __FILE__, __LINE__)
-#else
-
-/****************************************************************************/
-/**
-*   Reserves a channel for use with @a dev. If the device is setup to use
-*   a shared channel, then this function will block until a free channel
-*   becomes available.
-*
-*   @return
-*       >= 0    - A valid DMA Handle.
-*       -EBUSY  - Device is currently being used.
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-DMA_Handle_t dma_request_channel(DMA_Device_t dev	/* Device to use with the allocated channel. */
-    );
-#endif
-
-/****************************************************************************/
-/**
-*   Frees a previously allocated DMA Handle.
-*
-*   @return
-*        0      - DMA Handle was released successfully.
-*       -EINVAL - Invalid DMA handle
-*/
-/****************************************************************************/
-
-int dma_free_channel(DMA_Handle_t channel	/* DMA handle. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines if a given device has been configured as using a shared
-*   channel.
-*
-*   @return boolean
-*       0           Device uses a dedicated channel
-*       non-zero    Device uses a shared channel
-*/
-/****************************************************************************/
-
-int dma_device_is_channel_shared(DMA_Device_t dev	/* Device to check. */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates memory to hold a descriptor ring. The descriptor ring then
-*   needs to be populated by making one or more calls to
-*   dna_add_descriptors.
-*
-*   The returned descriptor ring will be automatically initialized.
-*
-*   @return
-*       0           Descriptor ring was allocated successfully
-*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor ring to populate */
-			      int numDescriptors	/* Number of descriptors that need to be allocated. */
-    );
-
-/****************************************************************************/
-/**
-*   Releases the memory which was previously allocated for a descriptor ring.
-*/
-/****************************************************************************/
-
-void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring	/* Descriptor to release */
-    );
-
-/****************************************************************************/
-/**
-*   Initializes a descriptor ring, so that descriptors can be added to it.
-*   Once a descriptor ring has been allocated, it may be reinitialized for
-*   use with additional/different regions of memory.
-*
-*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
-*   initialize the ring with a smaller number of descriptors. The amount
-*   of memory allocated for the descriptor ring will not be reduced, and
-*   the descriptor ring may be reinitialized later
-*
-*   @return
-*       0           Descriptor ring was initialized successfully
-*       -ENOMEM     The descriptor which was passed in has insufficient space
-*                   to hold the desired number of descriptors.
-*/
-/****************************************************************************/
-
-int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,	/* Descriptor ring to initialize */
-			     int numDescriptors	/* Number of descriptors to initialize. */
-    );
-
-/****************************************************************************/
-/**
-*   Determines the number of descriptors which would be required for a
-*   transfer of the indicated memory region.
-*
-*   This function also needs to know which DMA device this transfer will
-*   be destined for, so that the appropriate DMA configuration can be retrieved.
-*   DMA parameters such as transfer width, and whether this is a memory-to-memory
-*   or memory-to-peripheral, etc can all affect the actual number of descriptors
-*   required.
-*
-*   @return
-*       > 0     Returns the number of descriptors required for the indicated transfer
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_calculate_descriptor_count(DMA_Device_t device,	/* DMA Device that this will be associated with */
-				   dma_addr_t srcData,	/* Place to get data to write to device */
-				   dma_addr_t dstData,	/* Pointer to device data address */
-				   size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Adds a region of memory to the descriptor ring. Note that it may take
-*   multiple descriptors for each region of memory. It is the callers
-*   responsibility to allocate a sufficiently large descriptor ring.
-*
-*   @return
-*       0       Descriptors were added successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_add_descriptors(DMA_DescriptorRing_t *ring,	/* Descriptor ring to add descriptors to */
-			DMA_Device_t device,	/* DMA Device that descriptors are for */
-			dma_addr_t srcData,	/* Place to get data (memory or device) */
-			dma_addr_t dstData,	/* Place to put data (memory or device) */
-			size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Sets the descriptor ring associated with a device.
-*
-*   Once set, the descriptor ring will be associated with the device, even
-*   across channel request/free calls. Passing in a NULL descriptor ring
-*   will release any descriptor ring currently associated with the device.
-*
-*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
-*         the descriptor ring may be released and reallocated.
-*
-*   Note: This function will release the descriptor memory for any current
-*         descriptor ring associated with this device.
-*/
-/****************************************************************************/
-
-int dma_set_device_descriptor_ring(DMA_Device_t device,	/* Device to update the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Descriptor ring to add descriptors to */
-    );
-
-/****************************************************************************/
-/**
-*   Retrieves the descriptor ring associated with a device.
-*/
-/****************************************************************************/
-
-int dma_get_device_descriptor_ring(DMA_Device_t device,	/* Device to retrieve the descriptor ring for. */
-				   DMA_DescriptorRing_t *ring	/* Place to store retrieved ring */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates buffers for the descriptors. This is normally done automatically
-*   but needs to be done explicitly when initiating a dma from interrupt
-*   context.
-*
-*   @return
-*       0       Descriptors were allocated successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-			  dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being performed */
-			  dma_addr_t srcData,	/* Place to get data to write to device */
-			  dma_addr_t dstData,	/* Pointer to device data address */
-			  size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Allocates and sets up descriptors for a double buffered circular buffer.
-*
-*   This is primarily intended to be used for things like the ingress samples
-*   from a microphone.
-*
-*   @return
-*       > 0     Number of descriptors actually allocated.
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*       -ENOMEM Memory exhausted
-*/
-/****************************************************************************/
-
-int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,	/* DMA Handle */
-				     dma_addr_t srcData,	/* Physical address of source data */
-				     dma_addr_t dstData1,	/* Physical address of first destination buffer */
-				     dma_addr_t dstData2,	/* Physical address of second destination buffer */
-				     size_t numBytes	/* Number of bytes in each destination buffer */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer when the descriptors have already been setup.
-*
-*   This is a special case, and normally, the dma_transfer_xxx functions should
-*   be used.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_start_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Stops a previously started DMA transfer.
-*
-*   @return
-*       0       Transfer was stopped successfully
-*       -ENODEV Invalid handle
-*/
-/****************************************************************************/
-
-int dma_stop_transfer(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Waits for a DMA to complete by polling. This function is only intended
-*   to be used for testing. Interrupts should be used for most DMA operations.
-*/
-/****************************************************************************/
-
-int dma_wait_transfer_done(DMA_Handle_t handle);
-
-/****************************************************************************/
-/**
-*   Initiates a DMA transfer
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-int dma_transfer(DMA_Handle_t handle,	/* DMA Handle */
-		 dmacHw_TRANSFER_TYPE_e transferType,	/* Type of transfer being performed */
-		 dma_addr_t srcData,	/* Place to get data to write to device */
-		 dma_addr_t dstData,	/* Pointer to device data address */
-		 size_t numBytes	/* Number of bytes to transfer to the device */
-    );
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from memory to a device.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_to_device(DMA_Handle_t handle,	/* DMA Handle */
-					 dma_addr_t srcData,	/* Place to get data to write to device (physical address) */
-					 dma_addr_t dstData,	/* Pointer to device data address (physical address) */
-					 size_t numBytes	/* Number of bytes to transfer to the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a transfer from a device to memory.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_from_device(DMA_Handle_t handle,	/* DMA Handle */
-					   dma_addr_t srcData,	/* Pointer to the device data address (physical address) */
-					   dma_addr_t dstData,	/* Place to store data retrieved from the device (physical address) */
-					   size_t numBytes	/* Number of bytes to retrieve from the device */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Initiates a memory to memory transfer.
-*
-*   @return
-*       0       Transfer was started successfully
-*       -EINVAL Invalid device type for this kind of transfer
-*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
-*/
-/****************************************************************************/
-
-static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,	/* DMA Handle */
-					  dma_addr_t srcData,	/* Place to transfer data from (physical address) */
-					  dma_addr_t dstData,	/* Place to transfer data to (physical address) */
-					  size_t numBytes	/* Number of bytes to transfer */
-    ) {
-	return dma_transfer(handle,
-			    dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
-			    srcData, dstData, numBytes);
-}
-
-/****************************************************************************/
-/**
-*   Set the callback function which will be called when a transfer completes.
-*   If a NULL callback function is set, then no callback will occur.
-*
-*   @note   @a devHandler will be called from IRQ context.
-*
-*   @return
-*       0       - Success
-*       -ENODEV - Device handed in is invalid.
-*/
-/****************************************************************************/
-
-int dma_set_device_handler(DMA_Device_t dev,	/* Device to set the callback for. */
-			   DMA_DeviceHandler_t devHandler,	/* Function to call when the DMA completes */
-			   void *userData	/* Pointer which will be passed to devHandler. */
-    );
-
-#endif
-
-#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
deleted file mode 100644
index 2f316f0..0000000
--- a/arch/arm/mach-bcmring/include/mach/entry-macro.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/*****************************************************************************
-* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
- *
- * Low-level IRQ helper macros for BCMRing-based platforms
- *
- */
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\base, =(MM_IO_BASE_INTC0)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC0_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_INTC1)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #IRQ_INTC1_START
-		cmp	\irqstat, #0
-		bne	1001f
-
-		ldr	\base, =(MM_IO_BASE_SINTC)
-		ldr	\irqstat, [\base, #0]		@ get status
-                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
-                ands    \irqstat, \irqstat, \irqnr
-		mov	\irqnr, #0xffffffff             @ code meaning no interrupt bits set
-		cmp	\irqstat, #0
-		beq	1002f
-
-		mov	\irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
-
-1001:
-		movs	\tmp, \irqstat, lsl #16
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #16
-
-		movs	\tmp, \irqstat, lsl #8
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #8
-
-		movs	\tmp, \irqstat, lsl #4
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #4
-
-		movs	\tmp, \irqstat, lsl #2
-		movne	\irqstat, \tmp
-		addeq	\irqnr, \irqnr, #2
-
-		movs	\tmp, \irqstat, lsl #1
-		addeq	\irqnr, \irqnr, #1
-		orrs	\base, \base, #1
-
-1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
-		.endm
-
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
deleted file mode 100644
index 6ae20a6..0000000
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- *  This file contains the hardware definitions of the BCMRing.
- *
- *  Copyright (C) 1999 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <cfg_global.h>
-#include <mach/csp/mm_io.h>
-
-/* Hardware addresses of major areas.
- *  *_START is the physical address
- *  *_SIZE  is the size of the region
- *  *_BASE  is the virtual address
- */
-#define RAM_START               PHYS_OFFSET
-
-#define RAM_SIZE                (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
-#define RAM_BASE                PAGE_OFFSET
-
-/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
-/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
-#if defined(__KERNEL__)
-#define HW_DECLARE_SPINLOCK(name)  DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
-#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t bcmring_##name##_reg_lock;
-#define HW_IRQ_SAVE(name, val)     spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
-#define HW_IRQ_RESTORE(name, val)  spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
-#else
-#define HW_DECLARE_SPINLOCK(name)
-#define HW_EXTERN_SPINLOCK(name)
-#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
-#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
-#endif
-
-#ifndef HW_IO_PHYS_TO_VIRT
-#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
-#endif
-#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
deleted file mode 100644
index b279b82..0000000
--- a/arch/arm/mach-bcmring/include/mach/irqs.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- *  Copyright (C) 2007 Broadcom
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(ARCH_BCMRING_IRQS_H)
-#define ARCH_BCMRING_IRQS_H
-
-/* INTC0 - interrupt controller 0 */
-#define IRQ_INTC0_START     0
-#define IRQ_DMA0C0          0	/* DMA0 channel 0 interrupt */
-#define IRQ_DMA0C1          1	/* DMA0 channel 1 interrupt */
-#define IRQ_DMA0C2          2	/* DMA0 channel 2 interrupt */
-#define IRQ_DMA0C3          3	/* DMA0 channel 3 interrupt */
-#define IRQ_DMA0C4          4	/* DMA0 channel 4 interrupt */
-#define IRQ_DMA0C5          5	/* DMA0 channel 5 interrupt */
-#define IRQ_DMA0C6          6	/* DMA0 channel 6 interrupt */
-#define IRQ_DMA0C7          7	/* DMA0 channel 7 interrupt */
-#define IRQ_DMA1C0          8	/* DMA1 channel 0 interrupt */
-#define IRQ_DMA1C1          9	/* DMA1 channel 1 interrupt */
-#define IRQ_DMA1C2         10	/* DMA1 channel 2 interrupt */
-#define IRQ_DMA1C3         11	/* DMA1 channel 3 interrupt */
-#define IRQ_DMA1C4         12	/* DMA1 channel 4 interrupt */
-#define IRQ_DMA1C5         13	/* DMA1 channel 5 interrupt */
-#define IRQ_DMA1C6         14	/* DMA1 channel 6 interrupt */
-#define IRQ_DMA1C7         15	/* DMA1 channel 7 interrupt */
-#define IRQ_VPM            16	/* Voice process module interrupt */
-#define IRQ_USBHD2         17	/* USB host2/device2 interrupt */
-#define IRQ_USBH1          18	/* USB1 host interrupt */
-#define IRQ_USBD           19	/* USB device interrupt */
-#define IRQ_SDIOH0         20	/* SDIO0 host interrupt */
-#define IRQ_SDIOH1         21	/* SDIO1 host interrupt */
-#define IRQ_TIMER0         22	/* Timer0 interrupt */
-#define IRQ_TIMER1         23	/* Timer1 interrupt */
-#define IRQ_TIMER2         24	/* Timer2 interrupt */
-#define IRQ_TIMER3         25	/* Timer3 interrupt */
-#define IRQ_SPIH           26	/* SPI host interrupt */
-#define IRQ_ESW            27	/* Ethernet switch interrupt */
-#define IRQ_APM            28	/* Audio process module interrupt */
-#define IRQ_GE             29	/* Graphic engine interrupt */
-#define IRQ_CLCD           30	/* LCD Controller interrupt */
-#define IRQ_PIF            31	/* Peripheral interface interrupt */
-#define IRQ_INTC0_END      31
-
-/* INTC1 - interrupt controller 1 */
-#define IRQ_INTC1_START    32
-#define IRQ_GPIO0          32	/*  0 GPIO bit 31//0 combined interrupt */
-#define IRQ_GPIO1          33	/*  1 GPIO bit 64//32 combined interrupt */
-#define IRQ_I2S0           34	/*  2 I2S0 interrupt */
-#define IRQ_I2S1           35	/*  3 I2S1 interrupt */
-#define IRQ_I2CH           36	/*  4 I2C host interrupt */
-#define IRQ_I2CS           37	/*  5 I2C slave interrupt */
-#define IRQ_SPIS           38	/*  6 SPI slave interrupt */
-#define IRQ_GPHY           39	/*  7 Gigabit Phy interrupt */
-#define IRQ_FLASHC         40	/*  8 Flash controller interrupt */
-#define IRQ_COMMTX         41	/*  9 ARM DDC transmit interrupt */
-#define IRQ_COMMRX         42	/* 10 ARM DDC receive interrupt */
-#define IRQ_PMUIRQ         43	/* 11 ARM performance monitor interrupt */
-#define IRQ_UARTB          44	/* 12 UARTB */
-#define IRQ_WATCHDOG       45	/* 13 Watchdog timer interrupt */
-#define IRQ_UARTA          46	/* 14 UARTA */
-#define IRQ_TSC            47	/* 15 Touch screen controller interrupt */
-#define IRQ_KEYC           48	/* 16 Key pad controller interrupt */
-#define IRQ_DMPU           49	/* 17 DDR2 memory partition interrupt */
-#define IRQ_VMPU           50	/* 18 VRAM memory partition interrupt */
-#define IRQ_FMPU           51	/* 19 Flash memory parition unit interrupt */
-#define IRQ_RNG            52	/* 20 Random number generator interrupt */
-#define IRQ_RTC0           53	/* 21 Real time clock periodic interrupt */
-#define IRQ_RTC1           54	/* 22 Real time clock one-shot interrupt */
-#define IRQ_SPUM           55	/* 23 Secure process module interrupt */
-#define IRQ_VDEC           56	/* 24 Hantro video decoder interrupt */
-#define IRQ_RTC2           57	/* 25 Real time clock tamper interrupt */
-#define IRQ_DDRP           58	/* 26 DDR Panic interrupt */
-#define IRQ_INTC1_END      58
-
-/* SINTC secure int controller */
-#define IRQ_SINTC_START    59
-#define IRQ_SEC_WATCHDOG   59	/*  0 Watchdog timer interrupt */
-#define IRQ_SEC_UARTA      60	/*  1 UARTA interrupt */
-#define IRQ_SEC_TSC        61	/*  2 Touch screen controller interrupt */
-#define IRQ_SEC_KEYC       62	/*  3 Key pad controller interrupt */
-#define IRQ_SEC_DMPU       63	/*  4 DDR2 memory partition interrupt */
-#define IRQ_SEC_VMPU       64	/*  5 VRAM memory partition interrupt */
-#define IRQ_SEC_FMPU       65	/*  6 Flash memory parition unit interrupt */
-#define IRQ_SEC_RNG        66	/*  7 Random number generator interrupt */
-#define IRQ_SEC_RTC0       67	/*  8 Real time clock periodic interrupt */
-#define IRQ_SEC_RTC1       68	/*  9 Real time clock one-shot interrupt */
-#define IRQ_SEC_SPUM       69	/* 10 Secure process module interrupt */
-#define IRQ_SEC_TIMER0     70	/* 11 Secure timer0 interrupt */
-#define IRQ_SEC_TIMER1     71	/* 12 Secure timer1 interrupt */
-#define IRQ_SEC_TIMER2     72	/* 13 Secure timer2 interrupt */
-#define IRQ_SEC_TIMER3     73	/* 14 Secure timer3 interrupt */
-#define IRQ_SEC_RTC2       74	/* 15 Real time clock tamper interrupt */
-
-#define IRQ_SINTC_END      74
-
-/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
-/*       Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
-/*       to make the mapping easy for humans to decipher. */
-
-#define IRQ_GPIO_0                  100
-
-#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
-
-/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
-/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
-#define NUM_GPIO_IRQS               62
-
-#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
-
-#define IRQ_UNKNOWN                 -1
-
-/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
-#define IRQ_INTC0_VALID_MASK        0xffffffff
-#define IRQ_INTC1_VALID_MASK        0x07ffffff
-#define IRQ_SINTC_VALID_MASK        0x0000ffff
-
-#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
deleted file mode 100644
index ce5cd16..0000000
--- a/arch/arm/mach-bcmring/include/mach/memory_settings.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef MEMORY_SETTINGS_H
-#define MEMORY_SETTINGS_H
-
-/* ---- Include Files ---------------------------------------- */
-/* ---- Constants and Types ---------------------------------- */
-
-/* Memory devices */
-/* NAND Flash timing for 166 MHz setting */
-#define HW_CFG_NAND_tBTA  (5 << 16)	/* Bus turnaround cycle (n)        0-7  (30 ns) */
-#define HW_CFG_NAND_tWP   (4 << 11)	/* Write pulse width cycle (n+1)   0-31 (25 ns) */
-#define HW_CFG_NAND_tWR   (1 << 9)	/* Write recovery cycle (n+1)      0-3  (10 ns) */
-#define HW_CFG_NAND_tAS   (0 << 7)	/* Write address setup cycle (n+1) 0-3  ( 0 ns) */
-#define HW_CFG_NAND_tOE   (3 << 5)	/* Output enable delay cycle (n)   0-3  (15 ns) */
-#define HW_CFG_NAND_tRC   (7 << 0)	/* Read access cycle (n+2)         0-31 (50 ns) */
-
-#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
-	| HW_CFG_NAND_tWP  \
-	| HW_CFG_NAND_tWR  \
-	| HW_CFG_NAND_tAS  \
-	| HW_CFG_NAND_tOE  \
-	| HW_CFG_NAND_tRC)
-
-/* NOR Flash timing for 166 MHz setting */
-#define HW_CFG_NOR_TPRC_TWLC (0 << 19)	/* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
-#define HW_CFG_NOR_TBTA      (0 << 16)	/* Bus turnaround cycle (n)                                 (DNA)      */
-#define HW_CFG_NOR_TWP       (6 << 11)	/* Write pulse width cycle (n+1)                            (35ns)     */
-#define HW_CFG_NOR_TWR       (0 << 9)	/* Write recovery cycle (n+1)                               (0ns)      */
-#define HW_CFG_NOR_TAS       (0 << 7)	/* Write address setup cycle (n+1)                          (0ns)      */
-#define HW_CFG_NOR_TOE       (0 << 5)	/* Output enable delay cycle (n)                            (max 25ns) */
-#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)	/* Read access cycle / Burst read latency (n+2 / n+1)       (100ns)    */
-
-#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
-	| HW_CFG_NOR_TBTA      \
-	| HW_CFG_NOR_TWP       \
-	| HW_CFG_NOR_TWR       \
-	| HW_CFG_NOR_TAS       \
-	| HW_CFG_NOR_TOE       \
-	| HW_CFG_NOR_TRC_TLC)
-
-#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
-#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
-
-/* SDRAM Settings */
-/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
-/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
-/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
-/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
-#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000	/* Total memory, not per device size */
-
-/* ---- Variable Externs ------------------------------------- */
-/* ---- Function Prototypes ---------------------------------- */
-
-#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
deleted file mode 100644
index 387376f..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*****************************************************************************
-* Copyright 2001 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_NAND.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_NAND_H)
-#define __ASM_ARCH_REG_NAND_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/reg_umi.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-#define HW_NAND_BASE       MM_IO_BASE_NAND	/* NAND Flash */
-
-/* DMA accesses by the bootstrap need hard nonvirtual addresses */
-#define REG_NAND_CMD            __REG16(HW_NAND_BASE + 0)
-#define REG_NAND_ADDR           __REG16(HW_NAND_BASE + 4)
-
-#define REG_NAND_PHYS_DATA16   (HW_NAND_BASE + 8)
-#define REG_NAND_PHYS_DATA8    (HW_NAND_BASE + 8)
-#define REG_NAND_DATA16         __REG16(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8          __REG8(REG_NAND_PHYS_DATA8)
-
-/* use appropriate offset to make sure it start at the 1K boundary */
-#define REG_NAND_PHYS_DATA_DMA   (HW_NAND_BASE + 0x400)
-#define REG_NAND_DATA_DMA         __REG32(REG_NAND_PHYS_DATA_DMA)
-
-/* Linux DMA requires physical address of the data register */
-#define REG_NAND_DATA16_PADDR    HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA16)
-#define REG_NAND_DATA8_PADDR     HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA8)
-#define REG_NAND_DATA_PADDR      HW_IO_VIRT_TO_PHYS(REG_NAND_PHYS_DATA_DMA)
-
-#define NAND_BUS_16BIT()        (0)
-#define NAND_BUS_8BIT()         (!NAND_BUS_16BIT())
-
-/* Register offsets */
-#define REG_NAND_CMD_OFFSET     (0)
-#define REG_NAND_ADDR_OFFSET    (4)
-#define REG_NAND_DATA8_OFFSET   (8)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
deleted file mode 100644
index 0992842..0000000
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ /dev/null
@@ -1,237 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  REG_UMI.h
-*
-*  PURPOSE:
-*
-*     This file contains definitions for the nand registers:
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(__ASM_ARCH_REG_UMI_H)
-#define __ASM_ARCH_REG_UMI_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <mach/csp/mm_io.h>
-
-/* ---- Constants and Types ---------------------------------------------- */
-
-/* Unified Memory Interface Ctrl Register */
-#define HW_UMI_BASE       MM_IO_BASE_UMI
-
-/* Flash bank 0 timing and control register */
-#define REG_UMI_FLASH0_TCR         __REG32(HW_UMI_BASE  + 0x00)
-/* Flash bank 1 timing and control register */
-#define REG_UMI_FLASH1_TCR         __REG32(HW_UMI_BASE  + 0x04)
-/* Flash bank 2 timing and control register */
-#define REG_UMI_FLASH2_TCR         __REG32(HW_UMI_BASE  + 0x08)
-/* MMD interface and control register */
-#define REG_UMI_MMD_ICR            __REG32(HW_UMI_BASE  + 0x0c)
-/* NAND timing and control register */
-#define REG_UMI_NAND_TCR           __REG32(HW_UMI_BASE  + 0x18)
-/* NAND ready/chip select register */
-#define REG_UMI_NAND_RCSR          __REG32(HW_UMI_BASE  + 0x1c)
-/* NAND ECC control & status register */
-#define REG_UMI_NAND_ECC_CSR       __REG32(HW_UMI_BASE  + 0x20)
-/* NAND ECC data register XXB2B1B0 */
-#define REG_UMI_NAND_ECC_DATA      __REG32(HW_UMI_BASE  + 0x24)
-/* BCH ECC Parameter N */
-#define REG_UMI_BCH_N              __REG32(HW_UMI_BASE  + 0x40)
-/* BCH ECC Parameter T */
-#define REG_UMI_BCH_K              __REG32(HW_UMI_BASE  + 0x44)
-/* BCH ECC Parameter K */
-#define REG_UMI_BCH_T              __REG32(HW_UMI_BASE  + 0x48)
-/* BCH ECC Contro Status */
-#define REG_UMI_BCH_CTRL_STATUS    __REG32(HW_UMI_BASE  + 0x4C)
-/* BCH WR ECC 31:0 */
-#define REG_UMI_BCH_WR_ECC_0       __REG32(HW_UMI_BASE  + 0x50)
-/* BCH WR ECC 63:32 */
-#define REG_UMI_BCH_WR_ECC_1       __REG32(HW_UMI_BASE  + 0x54)
-/* BCH WR ECC 95:64 */
-#define REG_UMI_BCH_WR_ECC_2       __REG32(HW_UMI_BASE  + 0x58)
-/* BCH WR ECC 127:96 */
-#define REG_UMI_BCH_WR_ECC_3       __REG32(HW_UMI_BASE  + 0x5c)
-/* BCH WR ECC 155:128 */
-#define REG_UMI_BCH_WR_ECC_4       __REG32(HW_UMI_BASE  + 0x60)
-/* BCH Read Error Location 1,0 */
-#define REG_UMI_BCH_RD_ERR_LOC_1_0 __REG32(HW_UMI_BASE  + 0x64)
-/* BCH Read Error Location 3,2 */
-#define REG_UMI_BCH_RD_ERR_LOC_3_2 __REG32(HW_UMI_BASE  + 0x68)
-/* BCH Read Error Location 5,4 */
-#define REG_UMI_BCH_RD_ERR_LOC_5_4 __REG32(HW_UMI_BASE  + 0x6c)
-/* BCH Read Error Location 7,6 */
-#define REG_UMI_BCH_RD_ERR_LOC_7_6 __REG32(HW_UMI_BASE  + 0x70)
-/* BCH Read Error Location 9,8 */
-#define REG_UMI_BCH_RD_ERR_LOC_9_8 __REG32(HW_UMI_BASE  + 0x74)
-/* BCH Read Error Location 11,10 */
-#define REG_UMI_BCH_RD_ERR_LOC_B_A __REG32(HW_UMI_BASE  + 0x78)
-
-/* REG_UMI_FLASH0/1/2_TCR, REG_UMI_SRAM0/1_TCR bits */
-/* Enable wait pin during burst write or read */
-#define REG_UMI_TCR_WAITEN              0x80000000
-/* Enable mem ctrlr to work with ext mem of lower freq than AHB clk */
-#define REG_UMI_TCR_LOWFREQ             0x40000000
-/* 1=synch write, 0=async write */
-#define REG_UMI_TCR_MEMTYPE_SYNCWRITE   0x20000000
-/* 1=synch read, 0=async read */
-#define REG_UMI_TCR_MEMTYPE_SYNCREAD    0x10000000
-/* 1=page mode read, 0=normal mode read */
-#define REG_UMI_TCR_MEMTYPE_PAGEREAD    0x08000000
-/* page size/burst size (wrap only) */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_MASK   0x07000000
-/* 4 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_4      0x00000000
-/* 8 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_8      0x01000000
-/* 16 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_16     0x02000000
-/* 32 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_32     0x03000000
-/* 64 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_64     0x04000000
-/* 128 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_128    0x05000000
-/* 256 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_256    0x06000000
-/* 512 word */
-#define REG_UMI_TCR_MEMTYPE_PGSZ_512    0x07000000
-/* Page read access cycle / Burst write latency (n+2 / n+1) */
-#define REG_UMI_TCR_TPRC_TWLC_MASK      0x00f80000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_TCR_TBTA_MASK           0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_TCR_TWP_MASK            0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_TCR_TWR_MASK            0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_TCR_TAS_MASK            0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_TCR_TOE_MASK            0x00000060
-/* Read access cycle / Burst read latency (n+2 / n+1) */
-#define REG_UMI_TCR_TRC_TLC_MASK        0x0000001f
-
-/* REG_UMI_MMD_ICR bits */
-/* Flash write protection pin control */
-#define REG_UMI_MMD_ICR_FLASH_WP            0x8000
-/* Extend hold time for sram0, sram1 csn (39 MHz operation) */
-#define REG_UMI_MMD_ICR_XHCS                0x4000
-/* Enable SDRAM 2 interface control */
-#define REG_UMI_MMD_ICR_SDRAM2EN            0x2000
-/* Enable merge of flash banks 0/1 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_INST512             0x1000
-/* Enable merge of flash banks 1/2 to 512 MBit bank */
-#define REG_UMI_MMD_ICR_DATA512             0x0800
-/* Enable SDRAM interface control */
-#define REG_UMI_MMD_ICR_SDRAMEN             0x0400
-/* Polarity of busy state of Burst Wait Signal */
-#define REG_UMI_MMD_ICR_WAITPOL             0x0200
-/* Enable burst clock stopped when not accessing external burst flash/sram */
-#define REG_UMI_MMD_ICR_BCLKSTOP            0x0100
-/* Enable the peri1_csn to replace flash1_csn in 512 Mb flash mode */
-#define REG_UMI_MMD_ICR_PERI1EN             0x0080
-/* Enable the peri2_csn to replace sdram_csn */
-#define REG_UMI_MMD_ICR_PERI2EN             0x0040
-/* Enable the peri3_csn to replace sdram2_csn */
-#define REG_UMI_MMD_ICR_PERI3EN             0x0020
-/* Enable sram bank1 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB1               0x0010
-/* Enable sram bank0 for H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSB0               0x0008
-/* Polarity for assert3ed state of H/W controlled MRS */
-#define REG_UMI_MMD_ICR_MRSPOL              0x0004
-/* 0: S/W controllable ZZ/MRS/CRE/P-Mode pin */
-/* 1: H/W controlled ZZ/MRS/CRE/P-Mode, same timing as CS */
-#define REG_UMI_MMD_ICR_MRSMODE             0x0002
-/* MRS state for S/W controlled mode */
-#define REG_UMI_MMD_ICR_MRSSTATE            0x0001
-
-/* REG_UMI_NAND_TCR bits */
-/* Enable software to control CS */
-#define REG_UMI_NAND_TCR_CS_SWCTRL          0x80000000
-/* 16-bit nand wordsize if set */
-#define REG_UMI_NAND_TCR_WORD16             0x40000000
-/* Bus turnaround cycle (n) */
-#define REG_UMI_NAND_TCR_TBTA_MASK          0x00070000
-/* Write pulse width cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWP_MASK           0x0000f800
-/* Write recovery cycle (n+1) */
-#define REG_UMI_NAND_TCR_TWR_MASK           0x00000600
-/* Write address setup cycle (n+1) */
-#define REG_UMI_NAND_TCR_TAS_MASK           0x00000180
-/* Output enable delay cycle (n) */
-#define REG_UMI_NAND_TCR_TOE_MASK           0x00000060
-/* Read access cycle (n+2) */
-#define REG_UMI_NAND_TCR_TRC_TLC_MASK       0x0000001f
-
-/* REG_UMI_NAND_RCSR bits */
-/* Status: Ready=1, Busy=0 */
-#define REG_UMI_NAND_RCSR_RDY               0x02
-/* Keep CS asserted during operation */
-#define REG_UMI_NAND_RCSR_CS_ASSERTED       0x01
-
-/* REG_UMI_NAND_ECC_CSR bits */
-/* Interrupt status - read-only */
-#define REG_UMI_NAND_ECC_CSR_NANDINT        0x80000000
-/* Read: Status of ECC done, Write: clear ECC interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_RAW     0x00800000
-/* Read: Status of R/B, Write: clear R/B interrupt */
-#define REG_UMI_NAND_ECC_CSR_RBINT_RAW      0x00400000
-/* 1 = Enable ECC Interrupt */
-#define REG_UMI_NAND_ECC_CSR_ECCINT_ENABLE  0x00008000
-/* 1 = Assert interrupt at rising edge of R/B_ */
-#define REG_UMI_NAND_ECC_CSR_RBINT_ENABLE   0x00004000
-/* Calculate ECC by 0=512 bytes, 1=256 bytes */
-#define REG_UMI_NAND_ECC_CSR_256BYTE        0x00000080
-/* Enable ECC in hardware */
-#define REG_UMI_NAND_ECC_CSR_ECC_ENABLE     0x00000001
-
-/* REG_UMI_BCH_CTRL_STATUS bits */
-/* Shift to Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR_SHIFT 20
-/* Indicate Number of correctable errors detected */
-#define REG_UMI_BCH_CTRL_STATUS_NB_CORR_ERROR 0x00F00000
-/* Indicate Errors detected during read but uncorrectable */
-#define REG_UMI_BCH_CTRL_STATUS_UNCORR_ERR    0x00080000
-/* Indicate Errors detected during read and are correctable */
-#define REG_UMI_BCH_CTRL_STATUS_CORR_ERR      0x00040000
-/* Flag indicates BCH's ECC status of read process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID  0x00020000
-/* Flag indicates BCH's ECC status of write process are valid */
-#define REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID  0x00010000
-/* Pause ECC calculation */
-#define REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC 0x00000010
-/* Enable Interrupt */
-#define REG_UMI_BCH_CTRL_STATUS_INT_EN        0x00000004
-/* Enable ECC during read */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN     0x00000002
-/* Enable ECC during write */
-#define REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN     0x00000001
-/* Mask for location */
-#define REG_UMI_BCH_ERR_LOC_MASK              0x00001FFF
-/* location within a byte */
-#define REG_UMI_BCH_ERR_LOC_BYTE              0x00000007
-/* location within a word */
-#define REG_UMI_BCH_ERR_LOC_WORD              0x00000018
-/* location within a page (512 byte) */
-#define REG_UMI_BCH_ERR_LOC_PAGE              0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index)     (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
deleted file mode 100644
index 5a94bbb..0000000
--- a/arch/arm/mach-bcmring/include/mach/timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/*
-*
-*****************************************************************************
-*
-*  timer.h
-*
-*  PURPOSE:
-*
-*
-*
-*  NOTES:
-*
-*****************************************************************************/
-
-#if !defined(BCM_LINUX_TIMER_H)
-#define BCM_LINUX_TIMER_H
-
-#if defined(__KERNEL__)
-
-/* ---- Include Files ---------------------------------------------------- */
-/* ---- Constants and Types ---------------------------------------------- */
-
-typedef unsigned int timer_tick_count_t;
-typedef unsigned int timer_tick_rate_t;
-typedef unsigned int timer_msec_t;
-
-/* ---- Variable Externs ------------------------------------------------- */
-/* ---- Function Prototypes ---------------------------------------------- */
-
-/****************************************************************************
-*
-*  timer_get_tick_count
-*
-*
-***************************************************************************/
-timer_tick_count_t timer_get_tick_count(void);
-
-/****************************************************************************
-*
-*  timer_get_tick_rate
-*
-*
-***************************************************************************/
-timer_tick_rate_t timer_get_tick_rate(void);
-
-/****************************************************************************
-*
-*  timer_get_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_get_msec(void);
-
-/****************************************************************************
-*
-*  timer_ticks_to_msec
-*
-*
-***************************************************************************/
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
-
-#endif /* __KERNEL__ */
-#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
deleted file mode 100644
index 40d033e..0000000
--- a/arch/arm/mach-bcmring/include/mach/timex.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *
- *  Integrator architecture timex specifications
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Specifies the number of ticks per second
- */
-#define CLOCK_TICK_RATE		100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
deleted file mode 100644
index 9c9821b..0000000
--- a/arch/arm/mach-bcmring/include/mach/uncompress.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*****************************************************************************
-* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-#include <mach/csp/mm_addr.h>
-
-#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
-#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
-/*
- * This does not append a newline
- */
-static inline void putc(int c)
-{
-	/* Send out UARTA */
-	while (BCMRING_UART_0_FR & (1 << 5))
-		;
-
-	BCMRING_UART_0_DR = c;
-}
-
-
-static inline void flush(void)
-{
-	/* Wait for the tx fifo to be empty */
-	while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
-		;
-
-	/* Wait for the final character to be sent on the txd line */
-	while (BCMRING_UART_0_FR & (1 << 3))
-		;
-}
-
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
deleted file mode 100644
index 437fa68..0000000
--- a/arch/arm/mach-bcmring/irq.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- *
- *  Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/init.h>
-#include <linux/stddef.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <asm/mach/irq.h>
-#include <mach/csp/intcHw_reg.h>
-#include <mach/csp/mm_io.h>
-
-static void bcmring_mask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq0(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC0_START),
-	       MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq1(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_INTC1_START),
-	       MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
-}
-
-static void bcmring_mask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
-}
-
-static void bcmring_unmask_irq2(struct irq_data *d)
-{
-	writel(1 << (d->irq - IRQ_SINTC_START),
-	       MM_IO_BASE_SINTC + INTCHW_INTENABLE);
-}
-
-static struct irq_chip bcmring_irq0_chip = {
-	.name = "ARM-INTC0",
-	.irq_ack = bcmring_mask_irq0,
-	.irq_mask = bcmring_mask_irq0,	/* mask a specific interrupt, blocking its delivery. */
-	.irq_unmask = bcmring_unmask_irq0,	/* unmaks an interrupt */
-};
-
-static struct irq_chip bcmring_irq1_chip = {
-	.name = "ARM-INTC1",
-	.irq_ack = bcmring_mask_irq1,
-	.irq_mask = bcmring_mask_irq1,
-	.irq_unmask = bcmring_unmask_irq1,
-};
-
-static struct irq_chip bcmring_irq2_chip = {
-	.name = "ARM-SINTC",
-	.irq_ack = bcmring_mask_irq2,
-	.irq_mask = bcmring_mask_irq2,
-	.irq_unmask = bcmring_unmask_irq2,
-};
-
-static void vic_init(void __iomem *base, struct irq_chip *chip,
-		     unsigned int irq_start, unsigned int vic_sources)
-{
-	unsigned int i;
-	for (i = 0; i < 32; i++) {
-		unsigned int irq = irq_start + i;
-		irq_set_chip(irq, chip);
-		irq_set_chip_data(irq, base);
-
-		if (vic_sources & (1 << i)) {
-			irq_set_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-		}
-	}
-	writel(0, base + INTCHW_INTSELECT);
-	writel(0, base + INTCHW_INTENABLE);
-	writel(~0, base + INTCHW_INTENCLEAR);
-	writel(0, base + INTCHW_IRQSTATUS);
-	writel(~0, base + INTCHW_SOFTINTCLEAR);
-}
-
-void __init bcmring_init_irq(void)
-{
-	vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
-		 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
-		 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
-	vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
-		 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
-
-	/* special cases */
-	if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO0, handle_simple_irq);
-	}
-	if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-		irq_set_handler(IRQ_GPIO1, handle_simple_irq);
-	}
-}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
deleted file mode 100644
index 1adec78e..0000000
--- a/arch/arm/mach-bcmring/mm.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/csp/mm_io.h>
-
-#define IO_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_DEVICE }
-
-#define MEM_DESC(va, sz) { .virtual = va, \
-	.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
-	.length = sz, \
-	.type = MT_MEMORY }
-
-static struct map_desc bcmring_io_desc[] __initdata = {
-	IO_DESC(MM_IO_BASE_NAND, SZ_64K),	/* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_UMI, SZ_64K),	/* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
-
-	IO_DESC(MM_IO_BASE_BROM, SZ_64K),	/* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
-	MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),	/* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA0, SZ_1M),	/* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_DMA1, SZ_1M),	/* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_ESW, SZ_1M),	/* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_CLCD, SZ_1M),	/* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_APM, SZ_1M),	/* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_SPUM, SZ_1M),	/* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),	/* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),	/* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
-
-	IO_DESC(MM_IO_BASE_VRAM, SZ_64K),	/* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
-	IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),	/* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
-	IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
-		SZ_16M),	/* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
-};
-
-void __init bcmring_map_io(void)
-{
-
-	iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
-	/* Maximum DMA memory allowed is 14M */
-	init_consistent_dma_size(14 << 20);
-}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
deleted file mode 100644
index af9c3d7..0000000
--- a/arch/arm/mach-bcmring/timer.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#include <linux/types.h>
-#include <linux/module.h>
-#include <csp/tmrHw.h>
-
-#include <mach/timer.h>
-/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
-/* The real time clock should probably be the real linux clocksource. */
-/* In the meantime, this file should agree with core.c as to the */
-/* profiling timer. If the clocksource is moved to rtc later, then */
-/* we can init the profiling timer here instead. */
-
-/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
-/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
-/* affect synchronization with scheduling and APM timing. */
-
-#define PROF_TIMER 1
-
-timer_tick_rate_t timer_get_tick_rate(void)
-{
-	return tmrHw_getCountRate(PROF_TIMER);
-}
-
-timer_tick_count_t timer_get_tick_count(void)
-{
-	return tmrHw_GetCurrentCount(PROF_TIMER);	/* change downcounter to upcounter */
-}
-
-timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
-{
-	static int tickRateMsec;
-
-	if (tickRateMsec == 0) {
-		tickRateMsec = timer_get_tick_rate() / 1000;
-	}
-
-	return ticks / tickRateMsec;
-}
-
-timer_msec_t timer_get_msec(void)
-{
-	return timer_ticks_to_msec(timer_get_tick_count());
-}
-
-EXPORT_SYMBOL(timer_get_tick_count);
-EXPORT_SYMBOL(timer_ticks_to_msec);
-EXPORT_SYMBOL(timer_get_tick_rate);
-EXPORT_SYMBOL(timer_get_msec);
-- 
1.7.9.5




From sachin.kamat at linaro.org  Sat Sep 22 02:12:31 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Sat, 22 Sep 2012 11:42:31 +0530
Subject: [PATCH] mtd: onenand: Make flexonenand_set_boundary static
Message-ID: <1348294351-27182-1-git-send-email-sachin.kamat@linaro.org>

Fixes the following sparse warning:
drivers/mtd/onenand/onenand_base.c:3697:5: warning:
symbol 'flexonenand_set_boundary' was not declared. Should it be static?

Cc: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
---
 drivers/mtd/onenand/onenand_base.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c
index 7153e0d..b3f41f2 100644
--- a/drivers/mtd/onenand/onenand_base.c
+++ b/drivers/mtd/onenand/onenand_base.c
@@ -3694,7 +3694,7 @@ static int flexonenand_check_blocks_erased(struct mtd_info *mtd, int start, int
  * flexonenand_set_boundary	- Writes the SLC boundary
  * @param mtd			- mtd info structure
  */
-int flexonenand_set_boundary(struct mtd_info *mtd, int die,
+static int flexonenand_set_boundary(struct mtd_info *mtd, int die,
 				    int boundary, int lock)
 {
 	struct onenand_chip *this = mtd->priv;
-- 
1.7.4.1



From kyungmin.park at samsung.com  Sat Sep 22 02:40:45 2012
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Sat, 22 Sep 2012 15:40:45 +0900
Subject: [PATCH] mtd: onenand: Make flexonenand_set_boundary static
In-Reply-To: <1348294351-27182-1-git-send-email-sachin.kamat@linaro.org>
References: <1348294351-27182-1-git-send-email-sachin.kamat@linaro.org>
Message-ID: <CAH9JG2W4jVxrTQVwoLrnMmypcHhM5mfciyK=tvGmi+8i_L78vQ@mail.gmail.com>

On 9/22/12, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> Fixes the following sparse warning:
> drivers/mtd/onenand/onenand_base.c:3697:5: warning:
> symbol 'flexonenand_set_boundary' was not declared. Should it be static?
>
> Cc: Kyungmin Park <kyungmin.park at samsung.com>
Acked-by: Kyungmin Park <kyungmin.park at samsung.com>
> Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
> ---
>  drivers/mtd/onenand/onenand_base.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mtd/onenand/onenand_base.c
> b/drivers/mtd/onenand/onenand_base.c
> index 7153e0d..b3f41f2 100644
> --- a/drivers/mtd/onenand/onenand_base.c
> +++ b/drivers/mtd/onenand/onenand_base.c
> @@ -3694,7 +3694,7 @@ static int flexonenand_check_blocks_erased(struct
> mtd_info *mtd, int start, int
>   * flexonenand_set_boundary	- Writes the SLC boundary
>   * @param mtd			- mtd info structure
>   */
> -int flexonenand_set_boundary(struct mtd_info *mtd, int die,
> +static int flexonenand_set_boundary(struct mtd_info *mtd, int die,
>  				    int boundary, int lock)
>  {
>  	struct onenand_chip *this = mtd->priv;
> --
> 1.7.4.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
>


From olof at lixom.net  Sat Sep 22 03:41:32 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 22 Sep 2012 00:41:32 -0700
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <20120921165305.GB5394@S2101-09.ap.freescale.net>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
 <20120921164622.GA5394@S2101-09.ap.freescale.net>
 <20120921165305.GB5394@S2101-09.ap.freescale.net>
Message-ID: <CAOesGMiHJnt7zq19ZycxaNUD64QzLYw7o79pP-Y91-zi60ny6g@mail.gmail.com>

Hi,

On Fri, Sep 21, 2012 at 9:53 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
> On Sat, Sep 22, 2012 at 12:46:26AM +0800, Shawn Guo wrote:
>> I just published the branch below with this series rebased on top of
>> the necessary dependant branches.
>>
>>   git://git.linaro.org/people/shawnguo/linux-2.6.git staging/imx-multiplatform
>>
>> The dependant branches include:
>>
>
> Forgot the base:
>
>   * arm-soc/next/multiplatform
>
> Shawn
>
>> * arm-soc/multiplatform/platform-data
>>
>> * arm-soc/multiplatform/smp_ops
>>
>> * git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-3.7
>>
>>   It contains dependant patch "ASoC: mx27vis: retrieve gpio numbers
>>   from platform_data"
>>
>> * git://git.infradead.org/mtd-2.6.git master
>>
>>   The series is based on this tree to solve some non-trivial conflicts
>>   on mxc_nand driver.  Because mtd tree completely missed 3.6 merge
>>   window, having the series base on 3.6-rc actually means 3.5 code base
>>   in term of mtd support.  There are currently two cycles changes
>>   accumulated on mtd, and we need to base the series on it to sort out
>>   the conflicts.
>>
>> * git://linuxtv.org/mchehab/media-next.git master
>>
>>   The media tree renames mx2/mx3 camera drivers twice.  I'm not sure
>>   if git merge can detect them, so I just rebased the series on media
>>   tree to solve that.  The bonus point is that a number of trivial
>>   conflicts with imx27-coda support on media tree gets solved as well.
>>
>> I'm not requesting you to pull the branch into arm-soc as a stable
>> branch but staging one, because the external dependencies which might
>> not be stable.  I attempt to use it for exposing the series on
>> linux-next, so that we can send it to Linus for 3.7 if there is chance
>> for us to (e.g. all the dependant branches hit mainline early during
>> 3.7 merge window).

I've pulled this in now as staging/imx-multiplatform.

As you mention, it might or might not make sense to send this up. It
also accrued a few more merge conflicts with other branches in
arm-soc, so we'll see how things play out.

Either way, we'll for sure queue it for 3.8.


-Olof


From olof at lixom.net  Sat Sep 22 04:09:27 2012
From: olof at lixom.net (Olof Johansson)
Date: Sat, 22 Sep 2012 01:09:27 -0700
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <CAOesGMiHJnt7zq19ZycxaNUD64QzLYw7o79pP-Y91-zi60ny6g@mail.gmail.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
 <20120921164622.GA5394@S2101-09.ap.freescale.net>
 <20120921165305.GB5394@S2101-09.ap.freescale.net>
 <CAOesGMiHJnt7zq19ZycxaNUD64QzLYw7o79pP-Y91-zi60ny6g@mail.gmail.com>
Message-ID: <CAOesGMg+FvoVmiCee5hhe+_ZtBpvsnsi2N3vvLmZz1Tq3pOBWw@mail.gmail.com>

On Sat, Sep 22, 2012 at 12:41 AM, Olof Johansson <olof at lixom.net> wrote:
> Hi,
>
> On Fri, Sep 21, 2012 at 9:53 AM, Shawn Guo <shawn.guo at linaro.org> wrote:
>> On Sat, Sep 22, 2012 at 12:46:26AM +0800, Shawn Guo wrote:
>>> I just published the branch below with this series rebased on top of
>>> the necessary dependant branches.
>>>
>>>   git://git.linaro.org/people/shawnguo/linux-2.6.git staging/imx-multiplatform
>>>
>>> The dependant branches include:
>>>
>>
>> Forgot the base:
>>
>>   * arm-soc/next/multiplatform
>>
>> Shawn
>>
>>> * arm-soc/multiplatform/platform-data
>>>
>>> * arm-soc/multiplatform/smp_ops
>>>
>>> * git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-3.7
>>>
>>>   It contains dependant patch "ASoC: mx27vis: retrieve gpio numbers
>>>   from platform_data"
>>>
>>> * git://git.infradead.org/mtd-2.6.git master
>>>
>>>   The series is based on this tree to solve some non-trivial conflicts
>>>   on mxc_nand driver.  Because mtd tree completely missed 3.6 merge
>>>   window, having the series base on 3.6-rc actually means 3.5 code base
>>>   in term of mtd support.  There are currently two cycles changes
>>>   accumulated on mtd, and we need to base the series on it to sort out
>>>   the conflicts.
>>>
>>> * git://linuxtv.org/mchehab/media-next.git master
>>>
>>>   The media tree renames mx2/mx3 camera drivers twice.  I'm not sure
>>>   if git merge can detect them, so I just rebased the series on media
>>>   tree to solve that.  The bonus point is that a number of trivial
>>>   conflicts with imx27-coda support on media tree gets solved as well.
>>>
>>> I'm not requesting you to pull the branch into arm-soc as a stable
>>> branch but staging one, because the external dependencies which might
>>> not be stable.  I attempt to use it for exposing the series on
>>> linux-next, so that we can send it to Linus for 3.7 if there is chance
>>> for us to (e.g. all the dependant branches hit mainline early during
>>> 3.7 merge window).
>
> I've pulled this in now as staging/imx-multiplatform.
>
> As you mention, it might or might not make sense to send this up. It
> also accrued a few more merge conflicts with other branches in
> arm-soc, so we'll see how things play out.
>
> Either way, we'll for sure queue it for 3.8.

Hmm. Pulling it in gives me a few new build errors, in particular on
the configs that Russell use to build test omap3, as well as one of
his vexpress configs. So I dropped it again for now.

Let's have the current contents sit in linux-next for at least one
release before we bring in anything more, especially since it brings
in dependencies on external trees, and it also has a handful of new
merge conflicts. We're already exposing Stephen Rothwell to more merge
conflicts than I'm entirely comfortable with.


-Olof


From shawn.guo at linaro.org  Sat Sep 22 05:34:32 2012
From: shawn.guo at linaro.org (Shawn Guo)
Date: Sat, 22 Sep 2012 17:34:32 +0800
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <CAOesGMg+FvoVmiCee5hhe+_ZtBpvsnsi2N3vvLmZz1Tq3pOBWw@mail.gmail.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
 <20120921164622.GA5394@S2101-09.ap.freescale.net>
 <20120921165305.GB5394@S2101-09.ap.freescale.net>
 <CAOesGMiHJnt7zq19ZycxaNUD64QzLYw7o79pP-Y91-zi60ny6g@mail.gmail.com>
 <CAOesGMg+FvoVmiCee5hhe+_ZtBpvsnsi2N3vvLmZz1Tq3pOBWw@mail.gmail.com>
Message-ID: <20120922093430.GC5394@S2101-09.ap.freescale.net>

On Sat, Sep 22, 2012 at 01:09:27AM -0700, Olof Johansson wrote:
> > I've pulled this in now as staging/imx-multiplatform.
> >
> > As you mention, it might or might not make sense to send this up. It
> > also accrued a few more merge conflicts with other branches in
> > arm-soc, so we'll see how things play out.
> >
> > Either way, we'll for sure queue it for 3.8.
> 
> Hmm. Pulling it in gives me a few new build errors, in particular on
> the configs that Russell use to build test omap3, as well as one of
> his vexpress configs. So I dropped it again for now.
> 
> Let's have the current contents sit in linux-next for at least one
> release before we bring in anything more, especially since it brings
> in dependencies on external trees, and it also has a handful of new
> merge conflicts. We're already exposing Stephen Rothwell to more merge
> conflicts than I'm entirely comfortable with.
> 
Ok.  I will rebase the series against 3.7-rc1 and then send you then.

Shawn


From dedekind1 at gmail.com  Sat Sep 22 10:58:51 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 22 Sep 2012 17:58:51 +0300
Subject: [PATCH] mtd: gpmi-nand: Improve logging style
In-Reply-To: <1346851653-28117-1-git-send-email-festevam@gmail.com>
References: <1346851653-28117-1-git-send-email-festevam@gmail.com>
Message-ID: <1348325931.1894.0.camel@kyv>

On Wed, 2012-09-05 at 10:27 -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Improve logging style by prefixing the pr_ messages with "gpmi_nand".
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120922/a5bef44d/attachment-0001.sig>

From dedekind1 at gmail.com  Sat Sep 22 10:59:26 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 22 Sep 2012 17:59:26 +0300
Subject: [PATCH 1/2] mtd: gpmi-nand: Convert to platform driver
In-Reply-To: <1346855725-31726-1-git-send-email-festevam@gmail.com>
References: <1346855725-31726-1-git-send-email-festevam@gmail.com>
Message-ID: <1348325966.1894.1.camel@kyv>

On Wed, 2012-09-05 at 11:35 -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> Using module_platform_driver() makes the code smaller and cleaner.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Pushed both to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120922/fcf0abe1/attachment.sig>

From dedekind1 at gmail.com  Sat Sep 22 10:59:45 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 22 Sep 2012 17:59:45 +0300
Subject: [PATCH] mtd: mxc_nand: Adapt the clock name to the new clock
 framework
In-Reply-To: <1346856747-32694-1-git-send-email-festevam@gmail.com>
References: <1346856747-32694-1-git-send-email-festevam@gmail.com>
Message-ID: <1348325985.1894.2.camel@kyv>

On Wed, 2012-09-05 at 11:52 -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam at freescale.com>
> 
> With the new i.mx clock framework the mxc_nand clock is registered as:
>     
> clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");0")
>     
> So we do not need to pass "nfc" string and can use NULL instead.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120922/0d6f4b41/attachment.sig>

From broonie at opensource.wolfsonmicro.com  Sat Sep 22 11:43:03 2012
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 22 Sep 2012 11:43:03 -0400
Subject: [alsa-devel] [PATCH v2 00/34] i.MX multi-platform support
In-Reply-To: <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
References: <1348123547-31082-1-git-send-email-shawn.guo@linaro.org>
 <201209200739.34899.arnd@arndb.de>
 <20120920145342.GI2450@S2101-09.ap.freescale.net>
 <201209201556.57171.arnd@arndb.de>
 <20120921080123.GM2450@S2101-09.ap.freescale.net>
 <CAOesGMi6CbvFikycJVdE8W-DxLD3W7+CyScz+YT103dxR31U9g@mail.gmail.com>
Message-ID: <20120922154303.GO4495@opensource.wolfsonmicro.com>

On Fri, Sep 21, 2012 at 01:26:43AM -0700, Olof Johansson wrote:

> I'll take a look at merging it tomorrow after I've dealt with smp_ops;
> if it looks reasonably conflict-free I'll pull it in. We need the
> sound dependency sorted out (or agreed upon) first though.

I guess in the light of the rest of the thread it doesn't much matter
for this merge window but I just pushed:

 git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git tags/asoc-3.7

which is signed so can happily be merged elsewhere.


From dedekind1 at gmail.com  Sat Sep 22 11:56:51 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 22 Sep 2012 18:56:51 +0300
Subject: [PATCH] mtd: nand/gpio: Use module_platform_driver macro
In-Reply-To: <1346839292-31001-1-git-send-email-sachin.kamat@linaro.org>
References: <1346839292-31001-1-git-send-email-sachin.kamat@linaro.org>
Message-ID: <1348329411.1894.3.camel@kyv>

On Wed, 2012-09-05 at 15:31 +0530, Sachin Kamat wrote:
> module_platform_driver simplifies the code by eliminating
> module_init and module_exit calls.
> 
> Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120922/6c163a08/attachment.sig>

From dedekind1 at gmail.com  Sat Sep 22 12:01:29 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sat, 22 Sep 2012 19:01:29 +0300
Subject: [PATCH 1/3] mtd: cmdlinepart: make the partitions rule more strict
In-Reply-To: <20120905083020.0bf6b0bd@halley>
References: <1346001700-26895-1-git-send-email-shijie8@gmail.com>
 <1346656701.3061.8.camel@sauron.fi.intel.com>
 <CAMiH66GX7h5tve9CLHzj8MMrUv90fL+4BWYPZ6KQkP5bbXY9ag@mail.gmail.com>
 <1346686544.3061.75.camel@sauron.fi.intel.com>
 <20120904144826.7b9b7518@halley> <5046B504.6000608@freescale.com>
 <20120905083020.0bf6b0bd@halley>
Message-ID: <1348329689.1894.4.camel@kyv>

On Wed, 2012-09-05 at 08:30 +0300, Shmulik Ladkani wrote:
> On Wed, 5 Sep 2012 10:12:20 +0800 Huang Shijie <b32955 at freescale.com> wrote:
> > yes, it's really simple and flexible.
> > But I think it's not wise to export the 0-size partition to user.
> > The user may confused at this.
> > 
> > And the mtd-utils, such as mtd-info/mtd-debug, do they can work with a 
> > 0-size partition?
> 
> I think the 0 sized partition case is really seldom, don't worth the
> trouble, the user will probably observe something went wrong in his
> cmdline parts specification.
> 
> But nevertheless, if we think it's a MUST to forbid the 0 sized
> partitions, then amend my patch as follows:

OK, pushed this one to l2-mtd.git. Guys, if there are more patches on
top of this, please, re-send them.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120922/ef60c4c1/attachment.sig>

From shmulik.ladkani at gmail.com  Sat Sep 22 14:54:47 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sat, 22 Sep 2012 21:54:47 +0300
Subject: [PATCH] mtd: nand: Rename create_bbt()'s 'len' variable to
 'numpages'
In-Reply-To: <20120820162915.7f93e6c4@pixies.home.jungo.com>
References: <20120820162915.7f93e6c4@pixies.home.jungo.com>
Message-ID: <20120922215447.331f6480@halley>

Ping.

On Mon, 20 Aug 2012 16:29:15 +0300 Shmulik Ladkani <shmulik.ladkani at gmail.com> wrote:
> Rename 'len' variable of create_bbt/scan_block_fast/scan_block_full to
> 'numpages', since it really means number of pages to scan when
> searching for the BBM (and not the byte length of the scan).
> 
> Signed-off-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>
> ---
> diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c
> index 9a5402e..24b0a4c 100644
> --- a/drivers/mtd/nand/nand_bbt.c
> +++ b/drivers/mtd/nand/nand_bbt.c
> @@ -401,7 +401,7 @@ static void read_abs_bbts(struct mtd_info *mtd, uint8_t *buf,
>  /* Scan a given block full */
>  static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
>  			   loff_t offs, uint8_t *buf, size_t readlen,
> -			   int scanlen, int len)
> +			   int scanlen, int numpages)
>  {
>  	int ret, j;
>  
> @@ -410,7 +410,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
>  	if (ret && !mtd_is_bitflip_or_eccerr(ret))
>  		return ret;
>  
> -	for (j = 0; j < len; j++, buf += scanlen) {
> +	for (j = 0; j < numpages; j++, buf += scanlen) {
>  		if (check_pattern(buf, scanlen, mtd->writesize, bd))
>  			return 1;
>  	}
> @@ -419,7 +419,7 @@ static int scan_block_full(struct mtd_info *mtd, struct nand_bbt_descr *bd,
>  
>  /* Scan a given block partially */
>  static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
> -			   loff_t offs, uint8_t *buf, int len)
> +			   loff_t offs, uint8_t *buf, int numpages)
>  {
>  	struct mtd_oob_ops ops;
>  	int j, ret;
> @@ -430,7 +430,7 @@ static int scan_block_fast(struct mtd_info *mtd, struct nand_bbt_descr *bd,
>  	ops.datbuf = NULL;
>  	ops.mode = MTD_OPS_PLACE_OOB;
>  
> -	for (j = 0; j < len; j++) {
> +	for (j = 0; j < numpages; j++) {
>  		/*
>  		 * Read the full oob until read_oob is fixed to handle single
>  		 * byte reads for 16 bit buswidth.
> @@ -463,7 +463,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
>  	struct nand_bbt_descr *bd, int chip)
>  {
>  	struct nand_chip *this = mtd->priv;
> -	int i, numblocks, len, scanlen;
> +	int i, numblocks, numpages, scanlen;
>  	int startblock;
>  	loff_t from;
>  	size_t readlen;
> @@ -471,11 +471,11 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
>  	pr_info("Scanning device for bad blocks\n");
>  
>  	if (bd->options & NAND_BBT_SCANALLPAGES)
> -		len = 1 << (this->bbt_erase_shift - this->page_shift);
> +		numpages = 1 << (this->bbt_erase_shift - this->page_shift);
>  	else if (bd->options & NAND_BBT_SCAN2NDPAGE)
> -		len = 2;
> +		numpages = 2;
>  	else
> -		len = 1;
> +		numpages = 1;
>  
>  	if (!(bd->options & NAND_BBT_SCANEMPTY)) {
>  		/* We need only read few bytes from the OOB area */
> @@ -484,7 +484,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
>  	} else {
>  		/* Full page content should be read */
>  		scanlen = mtd->writesize + mtd->oobsize;
> -		readlen = len * mtd->writesize;
> +		readlen = numpages * mtd->writesize;
>  	}
>  
>  	if (chip == -1) {
> @@ -508,7 +508,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
>  	}
>  
>  	if (this->bbt_options & NAND_BBT_SCANLASTPAGE)
> -		from += mtd->erasesize - (mtd->writesize * len);
> +		from += mtd->erasesize - (mtd->writesize * numpages);
>  
>  	for (i = startblock; i < numblocks;) {
>  		int ret;
> @@ -517,9 +517,9 @@ static int create_bbt(struct mtd_info *mtd, uint8_t *buf,
>  
>  		if (bd->options & NAND_BBT_SCANALLPAGES)
>  			ret = scan_block_full(mtd, bd, from, buf, readlen,
> -					      scanlen, len);
> +					      scanlen, numpages);
>  		else
> -			ret = scan_block_fast(mtd, bd, from, buf, len);
> +			ret = scan_block_fast(mtd, bd, from, buf, numpages);
>  
>  		if (ret < 0)
>  			return ret;



From shmulik.ladkani at gmail.com  Sun Sep 23 03:52:29 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 23 Sep 2012 09:52:29 +0200
Subject: [PATCH v2] mtd: cmdlinepart: Simplify parse_cmdline_partitions
Message-ID: <20120923095229.5d0c6806@pixies.home.jungo.com>

From: Shmulik Ladkani <shmulik.ladkani at gmail.com>

Simply 'parse_cmdline_partitions': the outer loop iterating over
'partitions' is actually a search loop, it does not execute the inner
loop for each partition, only for the matched partition.

Let's break when search is successful, and move all inner code (relevant
only for the matched partition) outside of the outer loop.

Resulting code is much more readable, and makes the indent level sane.

Signed-off-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>
---
- coding fix only, semantics shouldn't change
- changes since v1:
  - applies to l2-mtd head
  - whitespace fixups

diff --git a/drivers/mtd/cmdlinepart.c b/drivers/mtd/cmdlinepart.c
index aed1b8a..4baab3b 100644
--- a/drivers/mtd/cmdlinepart.c
+++ b/drivers/mtd/cmdlinepart.c
@@ -308,48 +308,52 @@ static int parse_cmdline_partitions(struct mtd_info *master,
 			return err;
 	}
 
+	/*
+	 * Search for the partition definition matching master->name.
+	 * If master->name is not set, stop at first partition definition.
+	 */
 	for (part = partitions; part; part = part->next) {
-		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id))) {
-			for (i = 0, offset = 0; i < part->num_parts; i++) {
-				if (part->parts[i].offset == OFFSET_CONTINUOUS)
-					part->parts[i].offset = offset;
-				else
-					offset = part->parts[i].offset;
-
-				if (part->parts[i].size == SIZE_REMAINING)
-					part->parts[i].size = master->size - offset;
-
-				if (part->parts[i].size == 0) {
-					printk(KERN_WARNING ERRP
-					       "%s: skipping zero sized partition\n",
-					       part->mtd_id);
-					part->num_parts--;
-					memmove(&part->parts[i],
-						&part->parts[i + 1],
-						sizeof(*part->parts) * (part->num_parts - i));
-					continue;
-				}
-
-				if (offset + part->parts[i].size > master->size) {
-					printk(KERN_WARNING ERRP
-					       "%s: partitioning exceeds flash size, truncating\n",
-					       part->mtd_id);
-					part->parts[i].size = master->size - offset;
-				}
-				offset += part->parts[i].size;
-			}
-
-			*pparts = kmemdup(part->parts,
-					sizeof(*part->parts) * part->num_parts,
-					GFP_KERNEL);
-			if (!*pparts)
-				return -ENOMEM;
-
-			return part->num_parts;
+		if ((!mtd_id) || (!strcmp(part->mtd_id, mtd_id)))
+			break;
+	}
+
+	if (!part)
+		return 0;
+
+	for (i = 0, offset = 0; i < part->num_parts; i++) {
+		if (part->parts[i].offset == OFFSET_CONTINUOUS)
+			part->parts[i].offset = offset;
+		else
+			offset = part->parts[i].offset;
+
+		if (part->parts[i].size == SIZE_REMAINING)
+			part->parts[i].size = master->size - offset;
+
+		if (part->parts[i].size == 0) {
+			printk(KERN_WARNING ERRP
+			       "%s: skipping zero sized partition\n",
+			       part->mtd_id);
+			part->num_parts--;
+			memmove(&part->parts[i], &part->parts[i + 1],
+				sizeof(*part->parts) * (part->num_parts - i));
+			continue;
 		}
+
+		if (offset + part->parts[i].size > master->size) {
+			printk(KERN_WARNING ERRP
+			       "%s: partitioning exceeds flash size, truncating\n",
+			       part->mtd_id);
+			part->parts[i].size = master->size - offset;
+		}
+		offset += part->parts[i].size;
 	}
 
-	return 0;
+	*pparts = kmemdup(part->parts, sizeof(*part->parts) * part->num_parts,
+			  GFP_KERNEL);
+	if (!*pparts)
+		return -ENOMEM;
+
+	return part->num_parts;
 }
 
 


From vikram186 at gmail.com  Sun Sep 23 05:48:32 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sun, 23 Sep 2012 15:18:32 +0530
Subject: [PATCH] imx/gpmi: Make debug prints more clear
Message-ID: <505EDAF0.2040708@gmail.com>

Make the error messages more debugging friendly

Signed-off-by: Vikram Narayanan <vikram186 at gmail.com>
Cc: Huang Shijie <b32955 at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 5999b15..24fbfb8 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -222,7 +222,7 @@ void prepare_data_dma(struct gpmi_nand_data *this, enum dma_data_direction dr)
 
 		ret = dma_map_sg(this->dev, sgl, 1, dr);
 		if (ret == 0)
-			pr_err("map failed.\n");
+			pr_err("DMA mapping failed.\n");
 
 		this->direct_dma_map_ok = false;
 	}
@@ -456,7 +456,7 @@ static int __devinit acquire_dma_channels(struct gpmi_nand_data *this)
 
 	dma_chan = dma_request_channel(mask, gpmi_dma_filter, this);
 	if (!dma_chan) {
-		pr_err("dma_request_channel failed.\n");
+		pr_err("Failed to request DMA channel.\n");
 		goto acquire_err;
 	}
 
@@ -630,7 +630,8 @@ static int read_page_prepare(struct gpmi_nand_data *this,
 						length, DMA_FROM_DEVICE);
 		if (dma_mapping_error(dev, dest_phys)) {
 			if (alt_size < length) {
-				pr_err("Alternate buffer is too small\n");
+				pr_err("%s, Alternate buffer is too small\n",
+					__func__);
 				return -ENOMEM;
 			}
 			goto map_failed;
@@ -680,7 +681,8 @@ static int send_page_prepare(struct gpmi_nand_data *this,
 						DMA_TO_DEVICE);
 		if (dma_mapping_error(dev, source_phys)) {
 			if (alt_size < length) {
-				pr_err("Alternate buffer is too small\n");
+				pr_err("%s, Alternate buffer is too small\n",
+					__func__);
 				return -ENOMEM;
 			}
 			goto map_failed;
@@ -768,7 +770,7 @@ static int gpmi_alloc_dma_buffer(struct gpmi_nand_data *this)
 
 error_alloc:
 	gpmi_free_dma_buffer(this);
-	pr_err("allocate DMA buffer ret!!\n");
+	pr_err("Error allocating DMA buffers!\n");
 	return -ENOMEM;
 }
 
@@ -1479,7 +1481,7 @@ static int gpmi_set_geometry(struct gpmi_nand_data *this)
 	/* Set up the NFC geometry which is used by BCH. */
 	ret = bch_set_geometry(this);
 	if (ret) {
-		pr_err("set geometry ret : %d\n", ret);
+		pr_err("Error setting BCH geometry : %d\n", ret);
 		return ret;
 	}
 
-- 
1.7.4.1



From hechtb at googlemail.com  Sun Sep 23 06:49:43 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Sun, 23 Sep 2012 12:49:43 +0200
Subject: [PATCH] mtd: sh_flctl: Switch from tick-based to time-based
 timeout
In-Reply-To: <1345454375.2848.21.camel@sauron.fi.intel.com>
References: <1341410726-10562-1-git-send-email-hechtb@gmail.com>
 <CABYn4syMFh4smteHS-zCAy3ygKsyxoD2+FfaBeQxKvK_FA+5mA@mail.gmail.com>
 <1345454375.2848.21.camel@sauron.fi.intel.com>
Message-ID: <CABYn4syVz46ChwYkhP=5TMb4N+Q0sTnuMu+C_d4LPuxrQ=WM-g@mail.gmail.com>

Hi Artem,

commit 19f5f7364a1cc770b14692f609bb9b802fc334d5
is still in l2-mtd. Please drop it, so it doesn't get merged and I can
base my new patches on the clean code.

Thanks!

Bastian


2012/8/20 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Wed, 2012-07-25 at 17:21 +0200, Bastian Hecht wrote:
>> Hello Artem!
>>
>> Could you please pull out this patch of your tree? While reworking the
>> driver for IRQ-driven use, I've realized that this conversion makes no
>> sense as all loops use a udelay(1) in them. So the timeout is already
>> time based.
>
> Dropped, thanks!
>
> --
> Best Regards,
> Artem Bityutskiy


From hechtb at googlemail.com  Sun Sep 23 08:01:22 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Sun, 23 Sep 2012 14:01:22 +0200
Subject: [PATCH 1/2] mtd: sh_flctl: Setup and release DMA channels
Message-ID: <1348401683-15698-1-git-send-email-hechtb@gmail.com>

The code probes if DMA channels can get allocated and tears them down at
removal/failure if needed.

Based on Guennadi Liakhovetski's code from the sh_mmcif driver.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.

 drivers/mtd/nand/sh_flctl.c  |   74 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/sh_flctl.h |   10 ++++++
 2 files changed, 84 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 4fbfe96..2cf6871 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -856,6 +856,76 @@ static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+void flctl_setup_dma(struct sh_flctl *flctl)
+{
+	dma_cap_mask_t mask;
+	struct dma_slave_config cfg;
+	struct platform_device *pdev = flctl->pdev;
+	struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
+	int ret;
+
+	if (!pdata)
+		return;
+
+	if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
+		return;
+
+	/* We can only either use DMA for both Tx and Rx or not use it at all */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_tx);
+	dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
+		flctl->chan_fifo0_tx);
+
+	if (!flctl->chan_fifo0_tx)
+		return;
+
+	cfg.slave_id = pdata->slave_id_fifo0_tx;
+	cfg.direction = DMA_MEM_TO_DEV;
+	cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
+	cfg.src_addr = 0;
+	ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_rx);
+	dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
+		flctl->chan_fifo0_rx);
+
+	if (!flctl->chan_fifo0_rx)
+		goto err;
+
+	cfg.slave_id = pdata->slave_id_fifo0_rx;
+	cfg.direction = DMA_DEV_TO_MEM;
+	cfg.dst_addr = 0;
+	cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
+	ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	init_completion(&flctl->dma_complete);
+
+	return;
+
+err:
+	flctl_release_dma(flctl);
+}
+
+static void flctl_release_dma(struct sh_flctl *flctl)
+{
+	if (flctl->chan_fifo0_rx) {
+		dma_release_channel(flctl->chan_fifo0_rx);
+		flctl->chan_fifo0_rx = NULL;
+	}
+	if (flctl->chan_fifo0_tx) {
+		dma_release_channel(flctl->chan_fifo0_tx);
+		flctl->chan_fifo0_tx = NULL;
+	}
+}
+
 static int __devinit flctl_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -930,6 +1000,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_resume(&pdev->dev);
 
+	flctl_setup_dma(flctl);
+
 	ret = nand_scan_ident(flctl_mtd, 1, NULL);
 	if (ret)
 		goto err_chip;
@@ -947,6 +1019,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	return 0;
 
 err_chip:
+	flctl_release_dma(flctl);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(irq, flctl);
 err_flste:
@@ -960,6 +1033,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
 {
 	struct sh_flctl *flctl = platform_get_drvdata(pdev);
 
+	flctl_release_dma(flctl);
 	nand_release(&flctl->mtd);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(platform_get_irq(pdev, 0), flctl);
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 01e4b15..20d3f48 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -20,10 +20,12 @@
 #ifndef __SH_FLCTL_H__
 #define __SH_FLCTL_H__
 
+#include <linux/dmaengine.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/pm_qos.h>
+#include <linux/sh_dma.h>
 
 /* FLCTL registers */
 #define FLCMNCR(f)		(f->reg + 0x0)
@@ -161,6 +163,11 @@ struct sh_flctl {
 	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
 	unsigned holden:1;	/* Hardware has FLHOLDCR and HOLDEN is set */
 	unsigned qos_request:1;	/* QoS request to prevent deep power shutdown */
+
+	/* DMA related objects */
+	struct dma_chan		*chan_fifo0_rx;
+	struct dma_chan		*chan_fifo0_tx;
+	struct completion	dma_complete;
 };
 
 struct sh_flctl_platform_data {
@@ -170,6 +177,9 @@ struct sh_flctl_platform_data {
 
 	unsigned has_hwecc:1;
 	unsigned use_holden:1;
+
+	unsigned int            slave_id_fifo0_tx;
+	unsigned int            slave_id_fifo0_rx;
 };
 
 static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
-- 
1.7.5.4



From hechtb at googlemail.com  Sun Sep 23 08:01:23 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Sun, 23 Sep 2012 14:01:23 +0200
Subject: [PATCH 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when
 available
In-Reply-To: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
References: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
Message-ID: <1348401683-15698-2-git-send-email-hechtb@gmail.com>

Map and unmap DMA buffers, trigger the DMA and wait for the completion.
On failure we fallback to PIO mode.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
 drivers/mtd/nand/sh_flctl.c  |   99 +++++++++++++++++++++++++++++++++++++++++-
 include/linux/mtd/sh_flctl.h |    1 +
 2 files changed, 98 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 2cf6871..00211f9 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -24,6 +24,8 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
@@ -106,6 +108,13 @@ static void wait_completion(struct sh_flctl *flctl)
 	writeb(0x0, FLTRCR(flctl));
 }
 
+static void flctl_dma_complete(void *param)
+{
+	struct sh_flctl *flctl = param;
+
+	complete(&flctl->dma_complete);
+}
+
 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
 {
 	struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -261,6 +270,71 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
 	timeout_error(flctl, __func__);
 }
 
+static void flctl_release_dma(struct sh_flctl *flctl);
+
+static void flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
+					int len, enum dma_data_direction dir)
+{
+	struct dma_async_tx_descriptor *desc = NULL;
+	struct dma_chan *chan;
+	enum dma_transfer_direction tr_dir;
+	dma_addr_t dma_addr;
+	dma_cookie_t cookie = -EINVAL;
+	uint32_t reg;
+	int ret;
+
+	if (dir == DMA_FROM_DEVICE) {
+		chan = flctl->chan_fifo0_rx;
+		tr_dir = DMA_DEV_TO_MEM;
+	} else {
+		chan = flctl->chan_fifo0_tx;
+		tr_dir = DMA_MEM_TO_DEV;
+	}
+
+	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
+
+	if (dma_addr)
+		desc = dmaengine_prep_slave_single(chan, dma_addr, len,
+			tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+	if (desc) {
+		reg = readl(FLINTDMACR(flctl));
+		reg |= DREQ0EN;
+		writel(reg, FLINTDMACR(flctl));
+
+		desc->callback = flctl_dma_complete;
+		desc->callback_param = flctl;
+		cookie = dmaengine_submit(desc);
+
+		dma_async_issue_pending(chan);
+	}
+
+	if (!desc) {
+		/* DMA failed, fall back to PIO */
+		flctl_release_dma(flctl);
+		dev_warn(&flctl->pdev->dev,
+			 "DMA failed, falling back to PIO\n");
+		goto out;
+	}
+
+	ret =
+	wait_for_completion_timeout(&flctl->dma_complete,
+				msecs_to_jiffies(3000));
+
+	if (ret <= 0) {
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
+	}
+
+out:
+	reg = readl(FLINTDMACR(flctl));
+	reg &= ~DREQ0EN;
+	writel(reg, FLINTDMACR(flctl));
+
+	dma_unmap_single(chan->device->dev, dma_addr, len, dir);
+	init_completion(&flctl->dma_complete);
+}
+
 static void read_datareg(struct sh_flctl *flctl, int offset)
 {
 	unsigned long data;
@@ -279,6 +353,16 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 
 	len_4align = (rlen + 3) / 4;
 
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_rx && rlen >= 32) {
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM);
+		for (i = 0; i < len_4align; i++)
+			buf[i] = be32_to_cpu(buf[i]);
+
+		return;
+	}
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_rfifo_ready(flctl);
 		buf[i] = readl(FLDTFIFO(flctl));
@@ -308,13 +392,24 @@ static enum flctl_ecc_res_t read_ecfiforeg
 static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 {
 	int i, len_4align;
-	unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
+	unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
 	void *fifo_addr = (void *)FLDTFIFO(flctl);
 
 	len_4align = (rlen + 3) / 4;
+
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_tx && rlen >= 32) {
+		for (i = 0; i < len_4align; i++)
+			buf[i] = cpu_to_be32(buf[i]);
+
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV);
+		return;
+	}
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_wfifo_ready(flctl);
-		writel(cpu_to_be32(data[i]), fifo_addr);
+		writel(cpu_to_be32(buf[i]), fifo_addr);
 	}
 }
 
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 20d3f48..d55ec25 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -109,6 +109,7 @@
 #define ESTERINTE	(0x1 << 24)	/* ECC error interrupt enable */
 #define AC1CLR		(0x1 << 19)	/* ECC FIFO clear */
 #define AC0CLR		(0x1 << 18)	/* Data FIFO clear */
+#define DREQ0EN		(0x1 << 16)	/* FLDTFIFODMA Request Enable */
 #define ECERB		(0x1 << 9)	/* ECC error */
 #define STERB		(0x1 << 8)	/* Status error */
 #define STERINTE	(0x1 << 4)	/* Status error enable */
-- 
1.7.5.4



From dedekind1 at gmail.com  Sun Sep 23 08:02:29 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 15:02:29 +0300
Subject: [PATCH] mtd: nand: Rename create_bbt()'s 'len' variable to
 'numpages'
In-Reply-To: <20120922215447.331f6480@halley>
References: <20120820162915.7f93e6c4@pixies.home.jungo.com>
 <20120922215447.331f6480@halley>
Message-ID: <1348401749.1889.0.camel@kyv>

On Sat, 2012-09-22 at 21:54 +0300, Shmulik Ladkani wrote:
> Ping.

It is in my tree for a long time, I just somehow forgot to notify you.

commit 88b9e2c45297129863e0befc47881b3899402850
Author: Shmulik Ladkani <shmulik.ladkani at gmail.com>
Date:   Mon Aug 20 16:29:15 2012 +0300

    mtd: nand: rename create_bbt()'s 'len' variable to 'numpages'
    
    Rename 'len' variable of create_bbt/scan_block_fast/scan_block_full to
    'numpages', since it really means number of pages to scan when
    searching for the BBM (and not the byte length of the scan).
    
    Signed-off-by: Shmulik Ladkani <shmulik.ladkani at gmail.com>
    Reviewed-by: Brian Norris <computersforpeace at gmail.com>
    Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/836d331d/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 23 08:41:15 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 15:41:15 +0300
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
Message-ID: <1348404075.1889.1.camel@kyv>

On Tue, 2012-09-11 at 15:10 +0800, Josh Wu wrote:
> Add err_ecc_ioremap label to fix following errors:
> ---8<--- 
>   CC      drivers/mtd/nand/atmel_nand.o
> drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
> drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
> make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
> make[2]: *** [drivers/mtd/nand] Error 2
> make[1]: *** [drivers/mtd] Error 2
> make: *** [drivers] Error 2
> --->8---

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/26001d36/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 23 09:00:39 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 16:00:39 +0300
Subject: [PATCH 1/1] mxc_nand : allow swapping the Bad block Indicator
 for NFC v1.
In-Reply-To: <20120911071715.GB18243@pengutronix.de>
References: <1345811288.2848.308.camel@sauron.fi.intel.com>
 <1345825064-9147-1-git-send-email-gcembed@gmail.com>
 <201209061056.12386.jbe@pengutronix.de> <504DF9BB.8050509@gmail.com>
 <20120911071715.GB18243@pengutronix.de>
Message-ID: <1348405239.1889.2.camel@kyv>

On Tue, 2012-09-11 at 09:17 +0200, Sascha Hauer wrote:
> In this form the patch is simply not correct and should be dropped.
> 
OK, dropped it.
> 
-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/ebc7b4d5/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 23 09:01:49 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 16:01:49 +0300
Subject: [PATCH v2] mtd: atmel_nand: fix the compile error which miss
 label "err_ecc_ioremap".
In-Reply-To: <1348404075.1889.1.camel@kyv>
References: <1347347412-24214-1-git-send-email-josh.wu@atmel.com>
 <1348404075.1889.1.camel@kyv>
Message-ID: <1348405309.1889.3.camel@kyv>

On Sun, 2012-09-23 at 15:41 +0300, Artem Bityutskiy wrote:
> On Tue, 2012-09-11 at 15:10 +0800, Josh Wu wrote:
> > Add err_ecc_ioremap label to fix following errors:
> > ---8<--- 
> >   CC      drivers/mtd/nand/atmel_nand.o
> > drivers/mtd/nand/atmel_nand.c: In function 'atmel_nand_probe':
> > drivers/mtd/nand/atmel_nand.c:1423: error: label 'err_ecc_ioremap' used but not defined
> > make[3]: *** [drivers/mtd/nand/atmel_nand.o] Error 1
> > make[2]: *** [drivers/mtd/nand] Error 2
> > make[1]: *** [drivers/mtd] Error 2
> > make: *** [drivers] Error 2
> > --->8---
> 
> Pushed to l2-mtd.git, thanks!

Actually squashed it into the bogus patch.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/d7f838a4/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 23 09:41:40 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 16:41:40 +0300
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <6871BC8982B258468985EE735D2C57524E269AFB89@ntcex01.corp.netcomm.com.au>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 <1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 <1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
 ,<CAN8TOE_ax=8inGyZxS+nTfcSkskyNvHEh9ipnOTVu-moB4FqjA@mail.gmail.com>
 <6871BC8982B258468985EE735D2C57524E269AFB89@ntcex01.corp.netcomm.com.au>
Message-ID: <1348407700.1889.12.camel@kyv>

On Thu, 2012-09-06 at 13:37 +1000, Iwo Mergler wrote:
> I had to force myself ;-). My excuse is that I copied the style of
> the other tests, because of a probably misguided sense of consistency.

Oh, please, next time feel free better do things properly, then fix
other code for consistency.
> 
-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/dfdb7b5f/attachment-0001.sig>

From dedekind1 at gmail.com  Sun Sep 23 09:42:18 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 16:42:18 +0300
Subject: [PATCH] Test for multi-bit error correction
In-Reply-To: <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
References: <6871BC8982B258468985EE735D2C57524E269AFB52@ntcex01.corp.netcomm.com.au>
 ,<1346310033.2848.536.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB54@ntcex01.corp.netcomm.com.au>
 ,<1346315075.2848.538.camel@sauron.fi.intel.com>
 <6871BC8982B258468985EE735D2C57524E269AFB60@ntcex01.corp.netcomm.com.au>
Message-ID: <1348407738.1889.13.camel@kyv>

On Fri, 2012-08-31 at 08:59 +1000, Iwo Mergler wrote:
> This tests ECC biterror recovery on a single NAND page. Mostly intended
> to test ECC hardware and low-level NAND driver.

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/6ecdbc65/attachment.sig>

From dedekind1 at gmail.com  Sun Sep 23 10:00:41 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 17:00:41 +0300
Subject: [PATCH] mtd: sh_flctl: Switch from tick-based to time-based
 timeout
In-Reply-To: <CABYn4syVz46ChwYkhP=5TMb4N+Q0sTnuMu+C_d4LPuxrQ=WM-g@mail.gmail.com>
References: <1341410726-10562-1-git-send-email-hechtb@gmail.com>
 <CABYn4syMFh4smteHS-zCAy3ygKsyxoD2+FfaBeQxKvK_FA+5mA@mail.gmail.com>
 <1345454375.2848.21.camel@sauron.fi.intel.com>
 <CABYn4syVz46ChwYkhP=5TMb4N+Q0sTnuMu+C_d4LPuxrQ=WM-g@mail.gmail.com>
Message-ID: <1348408841.1889.14.camel@kyv>

On Sun, 2012-09-23 at 12:49 +0200, Bastian Hecht wrote:
> Hi Artem,
> 
> commit 19f5f7364a1cc770b14692f609bb9b802fc334d5
> is still in l2-mtd. Please drop it, so it doesn't get merged and I can
> base my new patches on the clean code.

I've dropped your patch now for real.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/b64f4784/attachment.sig>

From vikram186 at gmail.com  Sun Sep 23 10:31:16 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sun, 23 Sep 2012 20:01:16 +0530
Subject: [PATCH 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
References: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
Message-ID: <505F1D34.3040407@gmail.com>

On 9/23/2012 5:31 PM, Bastian Hecht wrote:
> The code probes if DMA channels can get allocated and tears them down at
> removal/failure if needed.
>
> Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
>
> Signed-off-by: Bastian Hecht<hechtb at gmail.com>
> ---
> Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.
>
>   drivers/mtd/nand/sh_flctl.c  |   74 ++++++++++++++++++++++++++++++++++++++++++
>   include/linux/mtd/sh_flctl.h |   10 ++++++
>   2 files changed, 84 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
> index 4fbfe96..2cf6871 100644
> --- a/drivers/mtd/nand/sh_flctl.c
> +++ b/drivers/mtd/nand/sh_flctl.c
> @@ -856,6 +856,76 @@ static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
>   	return IRQ_HANDLED;
>   }
>
> +void flctl_setup_dma(struct sh_flctl *flctl)

static?

~Vikram


From vikram186 at gmail.com  Sun Sep 23 10:32:18 2012
From: vikram186 at gmail.com (Vikram Narayanan)
Date: Sun, 23 Sep 2012 20:02:18 +0530
Subject: [PATCH 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when
 available
In-Reply-To: <1348401683-15698-2-git-send-email-hechtb@gmail.com>
References: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
 <1348401683-15698-2-git-send-email-hechtb@gmail.com>
Message-ID: <505F1D72.6020306@gmail.com>

On 9/23/2012 5:31 PM, Bastian Hecht wrote:
> Map and unmap DMA buffers, trigger the DMA and wait for the completion.
> On failure we fallback to PIO mode.
>
> Signed-off-by: Bastian Hecht<hechtb at gmail.com>
> ---
>   drivers/mtd/nand/sh_flctl.c  |   99 +++++++++++++++++++++++++++++++++++++++++-
>   include/linux/mtd/sh_flctl.h |    1 +
>   2 files changed, 98 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
> index 2cf6871..00211f9 100644
> --- a/drivers/mtd/nand/sh_flctl.c
> +++ b/drivers/mtd/nand/sh_flctl.c
> @@ -24,6 +24,8 @@
>   #include<linux/module.h>
>   #include<linux/kernel.h>
>   #include<linux/delay.h>
> +#include<linux/dmaengine.h>
> +#include<linux/dma-mapping.h>
>   #include<linux/interrupt.h>
>   #include<linux/io.h>
>   #include<linux/platform_device.h>
> @@ -106,6 +108,13 @@ static void wait_completion(struct sh_flctl *flctl)
>   	writeb(0x0, FLTRCR(flctl));
>   }
>
> +static void flctl_dma_complete(void *param)
> +{
> +	struct sh_flctl *flctl = param;
> +
> +	complete(&flctl->dma_complete);
> +}
> +
>   static void set_addr(struct mtd_info *mtd, int column, int page_addr)
>   {
>   	struct sh_flctl *flctl = mtd_to_flctl(mtd);
> @@ -261,6 +270,71 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
>   	timeout_error(flctl, __func__);
>   }
>
> +static void flctl_release_dma(struct sh_flctl *flctl);

I don't think the above statement is required.

~Vikram


From shmulik.ladkani at gmail.com  Sun Sep 23 10:38:41 2012
From: shmulik.ladkani at gmail.com (Shmulik Ladkani)
Date: Sun, 23 Sep 2012 16:38:41 +0200
Subject: [PATCH] mtd: nand: Rename create_bbt()'s 'len' variable to
 'numpages'
In-Reply-To: <1348401749.1889.0.camel@kyv>
References: <20120820162915.7f93e6c4@pixies.home.jungo.com>
 <20120922215447.331f6480@halley> <1348401749.1889.0.camel@kyv>
Message-ID: <20120923163841.656a5696@halley>

On Sun, 23 Sep 2012 15:02:29 +0300 Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> It is in my tree for a long time, I just somehow forgot to notify you.

OK, Thanks.


From dedekind1 at gmail.com  Sun Sep 23 11:25:15 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 18:25:15 +0300
Subject: [PATCH -next v4 0/5] mtd: mtd_nandecctest: add more tests
In-Reply-To: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
References: <1347036490-18258-1-git-send-email-akinobu.mita@gmail.com>
Message-ID: <1348413915.12104.0.camel@kyv>

On Sat, 2012-09-08 at 01:48 +0900, Akinobu Mita wrote:
> This patch series adds several tests cases to mtd_nandecctest module
> and tries to cover possible patterns of corruption which can be reliably
> corrected or detected.

Pushed all to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/8cfca0ae/attachment.sig>

From motobud at gmail.com  Sun Sep 23 11:48:28 2012
From: motobud at gmail.com (Brent Taylor)
Date: Sun, 23 Sep 2012 10:48:28 -0500
Subject: UBIFS Recovery Issue: 'grab_empty_leb: could not find an empty
 LEB'
In-Reply-To: <CAP+RiCAzOKvV00F8zppPxrL1CHKqR6eU2g08F+s_wm2R6jJ7Cg@mail.gmail.com>
References: <CAP+RiCC1afVbKAZESMcZGd1G3+7aKuLTQGggOEFGZxQM6o+QQA@mail.gmail.com>
 <1346413469.9709.44.camel@sauron.fi.intel.com>
 <CAP+RiCBRopbShAGf_fWCvK2R=uPPR1j4Pz12JfJxdEMUjwofNw@mail.gmail.com>
 <CAP+RiCAzOKvV00F8zppPxrL1CHKqR6eU2g08F+s_wm2R6jJ7Cg@mail.gmail.com>
Message-ID: <CAP+RiCDHZYMZPFYmE6YfkLoA1gH=z8cTSRZ+9iQqQ=ei1xXFYg@mail.gmail.com>

On Mon, Sep 17, 2012 at 8:34 AM, Brent Taylor <motobud at gmail.com> wrote:
> On Fri, Aug 31, 2012 at 8:23 AM, Brent Taylor <motobud at gmail.com> wrote:
>>
>> I'm currently running the test again, and will know the results on wed, sept 5.  If I do see a failure, I can send you an image, the problem is that the image will be either 256MB, 1GB, or 15GB depending on which partition fails.  Will either of the larger sizes be an issue for you?  What would be the best way to get the image to you?
>>
>> Thanks for your time.
>> Bud
>>
>> On Aug 31, 2012 7:39 AM, "Artem Bityutskiy" <dedekind1 at gmail.com> wrote:
>>>
>>> On Mon, 2012-07-16 at 13:22 -0500, Brent Taylor wrote:
>>> > I'm developing on custom hardware using an at91sam9g45 processor with
>>> > 64 MB of RAM and 64 MB of NOR flash running Linux 3.0.13.
>>> >
>>> > I'm doing some power-cycle testing and after several hours, UBIFS
>>> > failed to mount the root partition and printed the message
>>> > "grab_empty_leb: could not find an empty LEB".  The system boots and
>>> > starts a script that will power cycle the board anytime between 10 and
>>> > 20 seconds after the script has started.  Just before a power cycle
>>> > occurs, syslog and our main process are the only processes that could
>>> > be writing to disk.
>>> >
>>> I was trying to do power cut emulation testing with mtdram, and I see
>>> there are some issues which do not seem to exist on NAND. But they are
>>> different to yours. I remember I saw these -ENOSPC issues in the past,
>>> but they were very difficult to reproduce.
>>>
>>> I will try to investigate why power-cut emulation testing fails on
>>> mtdram, but I have limited amount of time and I do not know when I'll be
>>> able to do this.
>>>
>>> --
>>> Best Regards,
>>> Artem Bityutskiy
>
>
> Artem,
>    I was finally able to capture the issue again with linux version
> 3.5.1, and I now have a 64MB mtd image for you to look at.  The issue
> occurred in the root filesystem this time.  Let me know what's the
> best way to get this image to you.  The image was retrieved from a NOR
> flash chip instead of a NAND flash chip, but I've seen the error on
> both which leads me to believe it's not a flash driver issue and it's
> something in the UBIFS subsystem.  If there is more data you need from
> me to help track this down, just let me know.
>
> Thanks for your time,
> Bud

Ping,  I just didn't want to get lost in the e-mail shuffle.


From dedekind1 at gmail.com  Sun Sep 23 12:03:07 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 23 Sep 2012 19:03:07 +0300
Subject: UBIFS Recovery Issue: 'grab_empty_leb: could not find an empty
 LEB'
In-Reply-To: <CAP+RiCDHZYMZPFYmE6YfkLoA1gH=z8cTSRZ+9iQqQ=ei1xXFYg@mail.gmail.com>
References: <CAP+RiCC1afVbKAZESMcZGd1G3+7aKuLTQGggOEFGZxQM6o+QQA@mail.gmail.com>
 <1346413469.9709.44.camel@sauron.fi.intel.com>
 <CAP+RiCBRopbShAGf_fWCvK2R=uPPR1j4Pz12JfJxdEMUjwofNw@mail.gmail.com>
 <CAP+RiCAzOKvV00F8zppPxrL1CHKqR6eU2g08F+s_wm2R6jJ7Cg@mail.gmail.com>
 <CAP+RiCDHZYMZPFYmE6YfkLoA1gH=z8cTSRZ+9iQqQ=ei1xXFYg@mail.gmail.com>
Message-ID: <1348416187.12914.0.camel@kyv>

On Sun, 2012-09-23 at 10:48 -0500, Brent Taylor wrote:
> 
> Ping,  I just didn't want to get lost in the e-mail shuffle.

I simply do not have enough time. But at some point I should come to
this.
> 
-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120923/9b2e077c/attachment.sig>

From festevam at gmail.com  Sun Sep 23 14:31:02 2012
From: festevam at gmail.com (Fabio Estevam)
Date: Sun, 23 Sep 2012 15:31:02 -0300
Subject: [PATCH] nand: gpmi-nand: Fix clock registration
Message-ID: <1348425062-17427-1-git-send-email-festevam@gmail.com>

From: Fabio Estevam <fabio.estevam at freescale.com>

On a mx28 board the following error happens since commit 638064e56c 
(mtd: gpmi: change the code for clocks):

gpmi-nand: probe of 8000c000.gpmi-nand failed with error -12

Acquire the clock using "NULL" as it was done previously, so that the driver
can register on mx23/mx28 as well.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 drivers/mtd/nand/gpmi-nand/gpmi-nand.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index c46be6c..1f23cb4 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -492,7 +492,7 @@ static int __devinit gpmi_get_clks(struct gpmi_nand_data *this)
 	int i;
 
 	/* The main clock is stored in the first. */
-	r->clock[0] = clk_get(this->dev, "gpmi_io");
+	r->clock[0] = clk_get(this->dev, NULL);
 	if (IS_ERR(r->clock[0]))
 		goto err_clock;
 
-- 
1.7.9.5



From marex at denx.de  Sun Sep 23 21:30:56 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 24 Sep 2012 03:30:56 +0200
Subject: [PATCH V5] mtd: m25p80: Make fast read configurable via DT
In-Reply-To: <1348233550.7550.2.camel@sauron.fi.intel.com>
References: <1345923416-9293-1-git-send-email-marex@denx.de>
 <201209171610.28410.marex@denx.de>
 <1348233550.7550.2.camel@sauron.fi.intel.com>
Message-ID: <201209240330.56996.marex@denx.de>

Dear Artem Bityutskiy,

> On Mon, 2012-09-17 at 16:10 +0200, Marek Vasut wrote:
> > Bump, do you think we can get this into 3.7 please?
> 
> Aiaiai!

Damn I'm really lucky with this one ...

Best regards,
Marek Vasut


From marex at denx.de  Sun Sep 23 21:39:39 2012
From: marex at denx.de (Marek Vasut)
Date: Mon, 24 Sep 2012 03:39:39 +0200
Subject: =?UTF-8?q?=5BPATCH=20V6=5D=20mtd=3A=20m25p80=3A=20Make=20fast=20read=20configurable=20via=20DT?=
Message-ID: <1348450779-22495-1-git-send-email-marex@denx.de>

Add DT property "m25p,fast-read" that signalises the particular
chip supports "fast read" opcode.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Cc: David Woodhouse <david.woodhouse at intel.com>
---
 Documentation/devicetree/bindings/mtd/m25p80.txt |   29 ++++++++++++++++++
 drivers/mtd/devices/m25p80.c                     |   34 +++++++++++++---------
 2 files changed, 50 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/m25p80.txt
V2: Add documentation for the DT property.
V3: Use of_property_get_bool() instead of of_find_property().
V4: Adjust the documentation's "compatible:" section, make it not
    Linux-specific, but keep the reference to Linux's list of
    supported devices. Also, use the default name, spansion,m25p80
    in the example.
V5: Enclose of_property_read_bool() into CONFIG_OF for systems that do not
    use OF / Device Tree .
V6: Supress the following warning by using __maybe_unused on np:
    808:23: warning: unused variable ?np? [-Wunused-variable]

diff --git a/Documentation/devicetree/bindings/mtd/m25p80.txt b/Documentation/devicetree/bindings/mtd/m25p80.txt
new file mode 100644
index 0000000..6d3d576
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/m25p80.txt
@@ -0,0 +1,29 @@
+* MTD SPI driver for ST M25Pxx (and similar) serial flash chips
+
+Required properties:
+- #address-cells, #size-cells : Must be present if the device has sub-nodes
+  representing partitions.
+- compatible : Should be the manufacturer and the name of the chip. Bear in mind
+               the DT binding is not Linux-only, but in case of Linux, see the
+               "m25p_ids" table in drivers/mtd/devices/m25p80.c for the list of
+               supported chips.
+- reg : Chip-Select number
+- spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
+
+Optional properties:
+- m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
+                   of the usual "read" opcode. This opcode is not supported by
+                   all chips and support for it can not be detected at runtime.
+                   Refer to your chips' datasheet to check if this is supported
+                   by your chip.
+
+Example:
+
+	flash: m25p80 at 0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spansion,m25p80";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		m25p,fast-read;
+	};
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 33213c7..8741dbc 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -73,14 +73,6 @@
 #define	MAX_READY_WAIT_JIFFIES	(40 * HZ)	/* M25P16 specs 40s max chip erase */
 #define	MAX_CMD_SIZE		5
 
-#ifdef CONFIG_M25PXX_USE_FAST_READ
-#define OPCODE_READ 	OPCODE_FAST_READ
-#define FAST_READ_DUMMY_BYTE 1
-#else
-#define OPCODE_READ 	OPCODE_NORM_READ
-#define FAST_READ_DUMMY_BYTE 0
-#endif
-
 #define JEDEC_MFR(_jedec_id)	((_jedec_id) >> 16)
 
 /****************************************************************************/
@@ -93,6 +85,7 @@ struct m25p {
 	u16			addr_width;
 	u8			erase_opcode;
 	u8			*command;
+	bool			fast_read;
 };
 
 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
@@ -342,6 +335,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	struct m25p *flash = mtd_to_m25p(mtd);
 	struct spi_transfer t[2];
 	struct spi_message m;
+	uint8_t opcode;
 
 	pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
 			__func__, (u32)from, len);
@@ -354,7 +348,7 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	 * Should add 1 byte DUMMY_BYTE.
 	 */
 	t[0].tx_buf = flash->command;
-	t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
+	t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
 	spi_message_add_tail(&t[0], &m);
 
 	t[1].rx_buf = buf;
@@ -376,12 +370,14 @@ static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
 	 */
 
 	/* Set up the write data buffer. */
-	flash->command[0] = OPCODE_READ;
+	opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
+	flash->command[0] = opcode;
 	m25p_addr2cmd(flash, from, flash->command);
 
 	spi_sync(flash->spi, &m);
 
-	*retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
+	*retlen = m.actual_length - m25p_cmdsz(flash) -
+			(flash->fast_read ? 1 : 0);
 
 	mutex_unlock(&flash->lock);
 
@@ -809,9 +805,10 @@ static int __devinit m25p_probe(struct spi_device *spi)
 	struct flash_info		*info;
 	unsigned			i;
 	struct mtd_part_parser_data	ppdata;
+	struct device_node __maybe_unused *np = spi->dev.of_node;
 
 #ifdef CONFIG_MTD_OF_PARTS
-	if (!of_device_is_available(spi->dev.of_node))
+	if (!of_device_is_available(np))
 		return -ENODEV;
 #endif
 
@@ -863,7 +860,8 @@ static int __devinit m25p_probe(struct spi_device *spi)
 	flash = kzalloc(sizeof *flash, GFP_KERNEL);
 	if (!flash)
 		return -ENOMEM;
-	flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
+	flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
+					GFP_KERNEL);
 	if (!flash->command) {
 		kfree(flash);
 		return -ENOMEM;
@@ -920,6 +918,16 @@ static int __devinit m25p_probe(struct spi_device *spi)
 	flash->page_size = info->page_size;
 	flash->mtd.writebufsize = flash->page_size;
 
+	flash->fast_read = false;
+#ifdef CONFIG_OF
+	if (np && of_property_read_bool(np, "m25p,fast-read"))
+		flash->fast_read = true;
+#endif
+
+#ifdef CONFIG_M25PXX_USE_FAST_READ
+	flash->fast_read = true;
+#endif
+
 	if (info->addr_width)
 		flash->addr_width = info->addr_width;
 	else {
-- 
1.7.10.4



From will.deacon at arm.com  Mon Sep 24 04:37:59 2012
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 24 Sep 2012 09:37:59 +0100
Subject: [PATCH v3 2/2] ARM: Remove mach-bcmring
In-Reply-To: <1348263626-3087-3-git-send-email-csd@broadcom.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
 <1348263626-3087-3-git-send-email-csd@broadcom.com>
Message-ID: <20120924083758.GA16146@mudshark.cambridge.arm.com>

On Fri, Sep 21, 2012 at 10:40:26PM +0100, Christian Daudt wrote:
> Remove mach-bcmring as this is no longer maintained or used.
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
> ---

Acked-by: Will Deacon <will.deacon at arm.com>

Cheers,

Will


From hechtb at googlemail.com  Mon Sep 24 05:05:24 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Mon, 24 Sep 2012 11:05:24 +0200
Subject: [PATCH 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <505F1D34.3040407@gmail.com>
References: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
 <505F1D34.3040407@gmail.com>
Message-ID: <CABYn4syrqMwJr8Hu2qy3P6cmooc8jDi-Xh7n4Pf63pyYS1tgZA@mail.gmail.com>

2012/9/23 Vikram Narayanan <vikram186 at gmail.com>:
> On 9/23/2012 5:31 PM, Bastian Hecht wrote:
>>
>> The code probes if DMA channels can get allocated and tears them down at
>> removal/failure if needed.
>>
>> Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
>>
>>
>> +void flctl_setup_dma(struct sh_flctl *flctl)
>
>
> static?
>
> ~Vikram

Oh yes, thanks!


From hechtb at googlemail.com  Mon Sep 24 05:07:19 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Mon, 24 Sep 2012 11:07:19 +0200
Subject: [PATCH 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when
 available
In-Reply-To: <505F1D72.6020306@gmail.com>
References: <1348401683-15698-1-git-send-email-hechtb@gmail.com>
 <1348401683-15698-2-git-send-email-hechtb@gmail.com>
 <505F1D72.6020306@gmail.com>
Message-ID: <CABYn4szm3rjHYc=U3=jU4NNVROS8pBQwOkpJLqrVH7mB+Dtq7g@mail.gmail.com>

2012/9/23 Vikram Narayanan <vikram186 at gmail.com>:
> On 9/23/2012 5:31 PM, Bastian Hecht wrote:
>>
>> Map and unmap DMA buffers, trigger the DMA and wait for the completion.
>> On failure we fallback to PIO mode.
>>
>>
>> +static void flctl_release_dma(struct sh_flctl *flctl);
>
>
> I don't think the above statement is required.
>
> ~Vikram

I've grouped things a bit thematically but you are right, I don't win
much (if anything at all) so I've reordered it in the v2 series.

Thanks,

 Bastian


From hechtb at googlemail.com  Mon Sep 24 05:18:34 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Mon, 24 Sep 2012 11:18:34 +0200
Subject: [PATCH v2 1/2] mtd: sh_flctl: Setup and release DMA channels
Message-ID: <1348478315-10789-1-git-send-email-hechtb@gmail.com>

The code probes if DMA channels can get allocated and tears them down at
removal/failure if needed.

Based on Guennadi Liakhovetski's code from the sh_mmcif driver.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
v2: incorporated Vikram Narayanan's thoughts
	- added a missing "static".
	- reordered things to get rid of a forward declaration

Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.

 drivers/mtd/nand/sh_flctl.c  |   74 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/sh_flctl.h |   10 ++++++
 2 files changed, 84 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 4fbfe96..9659483 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -106,6 +106,76 @@ static void wait_completion(struct sh_flctl *flctl)
 	writeb(0x0, FLTRCR(flctl));
 }
 
+static void flctl_release_dma(struct sh_flctl *flctl)
+{
+	if (flctl->chan_fifo0_rx) {
+		dma_release_channel(flctl->chan_fifo0_rx);
+		flctl->chan_fifo0_rx = NULL;
+	}
+	if (flctl->chan_fifo0_tx) {
+		dma_release_channel(flctl->chan_fifo0_tx);
+		flctl->chan_fifo0_tx = NULL;
+	}
+}
+
+static void flctl_setup_dma(struct sh_flctl *flctl)
+{
+	dma_cap_mask_t mask;
+	struct dma_slave_config cfg;
+	struct platform_device *pdev = flctl->pdev;
+	struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
+	int ret;
+
+	if (!pdata)
+		return;
+
+	if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
+		return;
+
+	/* We can only either use DMA for both Tx and Rx or not use it at all */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_tx);
+	dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
+		flctl->chan_fifo0_tx);
+
+	if (!flctl->chan_fifo0_tx)
+		return;
+
+	cfg.slave_id = pdata->slave_id_fifo0_tx;
+	cfg.direction = DMA_MEM_TO_DEV;
+	cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
+	cfg.src_addr = 0;
+	ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_rx);
+	dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
+		flctl->chan_fifo0_rx);
+
+	if (!flctl->chan_fifo0_rx)
+		goto err;
+
+	cfg.slave_id = pdata->slave_id_fifo0_rx;
+	cfg.direction = DMA_DEV_TO_MEM;
+	cfg.dst_addr = 0;
+	cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
+	ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	init_completion(&flctl->dma_complete);
+
+	return;
+
+err:
+	flctl_release_dma(flctl);
+}
+
 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
 {
 	struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -930,6 +1000,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_resume(&pdev->dev);
 
+	flctl_setup_dma(flctl);
+
 	ret = nand_scan_ident(flctl_mtd, 1, NULL);
 	if (ret)
 		goto err_chip;
@@ -947,6 +1019,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	return 0;
 
 err_chip:
+	flctl_release_dma(flctl);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(irq, flctl);
 err_flste:
@@ -960,6 +1033,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
 {
 	struct sh_flctl *flctl = platform_get_drvdata(pdev);
 
+	flctl_release_dma(flctl);
 	nand_release(&flctl->mtd);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(platform_get_irq(pdev, 0), flctl);
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 01e4b15..20d3f48 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -20,10 +20,12 @@
 #ifndef __SH_FLCTL_H__
 #define __SH_FLCTL_H__
 
+#include <linux/dmaengine.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/pm_qos.h>
+#include <linux/sh_dma.h>
 
 /* FLCTL registers */
 #define FLCMNCR(f)		(f->reg + 0x0)
@@ -161,6 +163,11 @@ struct sh_flctl {
 	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
 	unsigned holden:1;	/* Hardware has FLHOLDCR and HOLDEN is set */
 	unsigned qos_request:1;	/* QoS request to prevent deep power shutdown */
+
+	/* DMA related objects */
+	struct dma_chan		*chan_fifo0_rx;
+	struct dma_chan		*chan_fifo0_tx;
+	struct completion	dma_complete;
 };
 
 struct sh_flctl_platform_data {
@@ -170,6 +177,9 @@ struct sh_flctl_platform_data {
 
 	unsigned has_hwecc:1;
 	unsigned use_holden:1;
+
+	unsigned int            slave_id_fifo0_tx;
+	unsigned int            slave_id_fifo0_rx;
 };
 
 static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
-- 
1.7.5.4



From hechtb at googlemail.com  Mon Sep 24 05:18:35 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Mon, 24 Sep 2012 11:18:35 +0200
Subject: [PATCH v2 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when
 available
In-Reply-To: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
Message-ID: <1348478315-10789-2-git-send-email-hechtb@gmail.com>

Map and unmap DMA buffers, trigger the DMA and wait for the completion.
On failure we fallback to PIO mode.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
log v2: dropped a forward declaration

 drivers/mtd/nand/sh_flctl.c  |   97 +++++++++++++++++++++++++++++++++++++++++-
 include/linux/mtd/sh_flctl.h |    1 +
 2 files changed, 96 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 9659483..0d90af8 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -24,6 +24,8 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
@@ -106,6 +108,13 @@ static void wait_completion(struct sh_flctl *flctl)
 	writeb(0x0, FLTRCR(flctl));
 }
 
+static void flctl_dma_complete(void *param)
+{
+	struct sh_flctl *flctl = param;
+
+	complete(&flctl->dma_complete);
+}
+
 static void flctl_release_dma(struct sh_flctl *flctl)
 {
 	if (flctl->chan_fifo0_rx) {
@@ -331,6 +340,69 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
 	timeout_error(flctl, __func__);
 }
 
+static void flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
+					int len, enum dma_data_direction dir)
+{
+	struct dma_async_tx_descriptor *desc = NULL;
+	struct dma_chan *chan;
+	enum dma_transfer_direction tr_dir;
+	dma_addr_t dma_addr;
+	dma_cookie_t cookie = -EINVAL;
+	uint32_t reg;
+	int ret;
+
+	if (dir == DMA_FROM_DEVICE) {
+		chan = flctl->chan_fifo0_rx;
+		tr_dir = DMA_DEV_TO_MEM;
+	} else {
+		chan = flctl->chan_fifo0_tx;
+		tr_dir = DMA_MEM_TO_DEV;
+	}
+
+	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
+
+	if (dma_addr)
+		desc = dmaengine_prep_slave_single(chan, dma_addr, len,
+			tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+	if (desc) {
+		reg = readl(FLINTDMACR(flctl));
+		reg |= DREQ0EN;
+		writel(reg, FLINTDMACR(flctl));
+
+		desc->callback = flctl_dma_complete;
+		desc->callback_param = flctl;
+		cookie = dmaengine_submit(desc);
+
+		dma_async_issue_pending(chan);
+	}
+
+	if (!desc) {
+		/* DMA failed, fall back to PIO */
+		flctl_release_dma(flctl);
+		dev_warn(&flctl->pdev->dev,
+			 "DMA failed, falling back to PIO\n");
+		goto out;
+	}
+
+	ret =
+	wait_for_completion_timeout(&flctl->dma_complete,
+				msecs_to_jiffies(3000));
+
+	if (ret <= 0) {
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
+	}
+
+out:
+	reg = readl(FLINTDMACR(flctl));
+	reg &= ~DREQ0EN;
+	writel(reg, FLINTDMACR(flctl));
+
+	dma_unmap_single(chan->device->dev, dma_addr, len, dir);
+	init_completion(&flctl->dma_complete);
+}
+
 static void read_datareg(struct sh_flctl *flctl, int offset)
 {
 	unsigned long data;
@@ -349,6 +421,16 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 
 	len_4align = (rlen + 3) / 4;
 
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_rx && rlen >= 32) {
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM);
+		for (i = 0; i < len_4align; i++)
+			buf[i] = be32_to_cpu(buf[i]);
+
+		return;
+	}
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_rfifo_ready(flctl);
 		buf[i] = readl(FLDTFIFO(flctl));
@@ -378,13 +460,24 @@ static enum flctl_ecc_res_t read_ecfiforeg
 static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 {
 	int i, len_4align;
-	unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
+	unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
 	void *fifo_addr = (void *)FLDTFIFO(flctl);
 
 	len_4align = (rlen + 3) / 4;
+
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_tx && rlen >= 32) {
+		for (i = 0; i < len_4align; i++)
+			buf[i] = cpu_to_be32(buf[i]);
+
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV);
+		return;
+	}
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_wfifo_ready(flctl);
-		writel(cpu_to_be32(data[i]), fifo_addr);
+		writel(cpu_to_be32(buf[i]), fifo_addr);
 	}
 }
 
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 20d3f48..d55ec25 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -109,6 +109,7 @@
 #define ESTERINTE	(0x1 << 24)	/* ECC error interrupt enable */
 #define AC1CLR		(0x1 << 19)	/* ECC FIFO clear */
 #define AC0CLR		(0x1 << 18)	/* Data FIFO clear */
+#define DREQ0EN		(0x1 << 16)	/* FLDTFIFODMA Request Enable */
 #define ECERB		(0x1 << 9)	/* ECC error */
 #define STERB		(0x1 << 8)	/* Status error */
 #define STERINTE	(0x1 << 4)	/* Status error enable */
-- 
1.7.5.4



From daynaz00sipla at yahoo.com  Mon Sep 24 06:39:42 2012
From: daynaz00sipla at yahoo.com (Velva Kwon)
Date: Mon, 24 Sep 2012 11:39:42 +0100 (BST)
Subject: R u interested in meeting new, interesting and nice people?:)
Message-ID: <1348483182.82330.YahooMailNeo@web132401.mail.ird.yahoo.com>

How's it going cutie! 
I'm Velva.
If you are interested in having great time in a company of interesting, sexual female then I'm right before u! 
I felt in love with your pics and that's why decided to create the mail! I think that u would not stay calm after examining mine too. 
So, I wait for an answer from you this letter and who knows we will go bar, drink some whiskey, discuss different things and who knows I will invite you to enter my house! ;)


From zajec5 at gmail.com  Mon Sep 24 07:14:19 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Mon, 24 Sep 2012 13:14:19 +0200
Subject: Problem with verify-ing patch (error: arch/m68k/Kconfig.cpu: patch
 does not apply)
Message-ID: <CACna6rwju0g+sq+vBAfCqFJm=EBLg79G2XoGEKs5n1Y=PcmKBg@mail.gmail.com>

I wanted to verify my patch before sending it.

TRY[0]:
> ./verify ../wireless-testing/ mips-bcm47xx_defconfig < ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
error: patch failed: arch/m68k/Kconfig.cpu:28
error: arch/m68k/Kconfig.cpu: patch does not apply

Weird. My patch doesn't touch m68k and applies cleanly to the
../wireless-testing tree:

> cd ../wireless-testing/
> git am ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
Applying: mtd: prepare place for BCMA NAND flash driver(s)

Help? :|

-- 
Rafa?


From artem.bityutskiy at linux.intel.com  Mon Sep 24 10:36:18 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 17:36:18 +0300
Subject: [PATCH] mtd:nand:clk: preparation for switch to common clock
 framework
In-Reply-To: <3E54258959B69E4282D79E01AB1F32B7041B6EDA@DFLE12.ent.ti.com>
References: <1346350624-27291-1-git-send-email-m-karicheri2@ti.com>
 <3E54258959B69E4282D79E01AB1F32B7041B6EDA@DFLE12.ent.ti.com>
Message-ID: <1348497378.4880.59.camel@sauron.fi.intel.com>

On Fri, 2012-09-07 at 18:39 +0000, Karicheri, Muralidharan wrote:
> subsystem owner,
> 
> Could you please review and apply this patch as needed? We need to get
> this upstream before submitting the patch for Common clock framework
> support for mach-davinci. If I need to follow a specific procedure to
> get this merged, please direct me to a process page.

Pushed to l2-mtd.git, thanks!

Artem.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/1085c445/attachment.sig>

From dedekind1 at gmail.com  Mon Sep 24 10:54:49 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 17:54:49 +0300
Subject: [PATCH] mtd: nand: expand description of read_page method in
 comment header
In-Reply-To: <1347379143-3607-1-git-send-email-mikedunn@newsguy.com>
References: <1347379143-3607-1-git-send-email-mikedunn@newsguy.com>
Message-ID: <1348498489.4880.60.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 08:59 -0700, Mike Dunn wrote:
> In the absence of any formal documentation of the nand interface, I thought this
> patch to the header file might be helpful.
> 
> Signed-off-by: Mike Dunn <mikedunn at newsguy.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/f806817c/attachment.sig>

From peter.barada at gmail.com  Mon Sep 24 11:04:40 2012
From: peter.barada at gmail.com (Peter Barada)
Date: Mon, 24 Sep 2012 11:04:40 -0400
Subject: Per-partition NAND ECC?
Message-ID: <50607688.6090601@gmail.com>

On the OMAP3 parts the bootrom has a hard requirement of using 1-bit
Hamming ECC to read the 2nd stage bootloader(x-loader / SPL) out of the
first four blocks of NAND.  The Micron MT29C4G48MAZAPAKQ5 PoP part we're
using requires 4-bit ECC for all the other NAND blocks to maintain an
acceptable UBER.

Currently this wasn't a problem since I could use u-boot to update the
2nd stage bootloader. I now have a need to be able to update the 2nd
stage bootloader from Linux only so I need the ability to write/read
pages in a NAND partition with a different ECC method than that
specified over the device.  I think it would be more elegant to solve
this by allowing partition entry/mtdparts to specify its ECC
methodology, track that as part of the MTD device down into the nand
driver, and switch ECC methods/entrypoints as it changes.

Does anyone have suggestions on how to best approach this?

Thanks in advance!

-- 
Peter Barada
peter.barada at gmail.com



From dedekind1 at gmail.com  Mon Sep 24 11:04:54 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 18:04:54 +0300
Subject: Problem with verify-ing patch (error: arch/m68k/Kconfig.cpu:
 patch does not apply)
In-Reply-To: <CACna6rwju0g+sq+vBAfCqFJm=EBLg79G2XoGEKs5n1Y=PcmKBg@mail.gmail.com>
References: <CACna6rwju0g+sq+vBAfCqFJm=EBLg79G2XoGEKs5n1Y=PcmKBg@mail.gmail.com>
Message-ID: <1348499094.4880.65.camel@sauron.fi.intel.com>

On Mon, 2012-09-24 at 13:14 +0200, Rafa? Mi?ecki wrote:
> I wanted to verify my patch before sending it.
> 
> TRY[0]:
> > ./verify ../wireless-testing/ mips-bcm47xx_defconfig < ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
> error: patch failed: arch/m68k/Kconfig.cpu:28
> error: arch/m68k/Kconfig.cpu: patch does not apply
> 
> Weird. My patch doesn't touch m68k and applies cleanly to the
> ../wireless-testing tree:
> 
> > cd ../wireless-testing/
> > git am ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
> Applying: mtd: prepare place for BCMA NAND flash driver(s)
> 
> Help? :|

It tries to apply quick fixes - I carry them because the kernel gets
broken in various places all the time. So you need to fix the quick
fixes patch - probably a fix was applied in upstream already.

Obviously, quick fixes are in maintaining.git, not in the generic aiaiai
tools. They are in 'quick_fixes.mbox'.

In this case it easy - the m68k patch get merged upstream and just can
be dropped from quick_fixes.mbox. Just done that and pushed out.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/6058b16a/attachment-0001.sig>

From dedekind1 at gmail.com  Mon Sep 24 11:06:27 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 18:06:27 +0300
Subject: [PATCH v3 1/2] ARM: Remove bcmring NAND driver
In-Reply-To: <1348263626-3087-2-git-send-email-csd@broadcom.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
 <1348263626-3087-2-git-send-email-csd@broadcom.com>
Message-ID: <1348499187.4880.66.camel@sauron.fi.intel.com>

On Fri, 2012-09-21 at 14:40 -0700, Christian Daudt wrote:
> This driver is being removed as part of the cleanup of the bcmring
> SoC from mainline as it is no longer maintained.
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
> Acked-by: Will Deacon <will.deacon at arm.com>

Pushed this patch to l2-mtd.git. But if you decide to merge it via
Arnd's tree (probably better idea) - let me know, I'll drop it.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/8db93cc8/attachment.sig>

From dedekind1 at gmail.com  Mon Sep 24 11:11:29 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 18:11:29 +0300
Subject: [PATCH] NAND BBT: use NAND_BBT_SCAN_MAXBLOCKS
In-Reply-To: <1347371454-17107-1-git-send-email-richard.genoud@gmail.com>
References: <1347371454-17107-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348499489.4880.67.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 15:50 +0200, Richard Genoud wrote:
> In nand_bbt.c, a hardcoded value was used instead of the define meant
> for that, so we use the define.
> 
> There's no functionnal change.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/3bdcf95d/attachment.sig>

From dedekind1 at gmail.com  Mon Sep 24 11:17:51 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Mon, 24 Sep 2012 18:17:51 +0300
Subject: [PATCH] mtd: nand: docg4: ecc.read_page() returns 0 on
 uncorrectible errors
In-Reply-To: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>
References: <1347378650-3522-1-git-send-email-mikedunn@newsguy.com>
Message-ID: <1348499871.4880.68.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 08:50 -0700, Mike Dunn wrote:
> Currently the docg4's ecc.read_page() method returns -EBADMSG when uncorrectible
> bitflips occur.  This is wrong; 0 should be returned in this case.  An error
> code should only be returned by this method in the case of a hardware error
> (probably -EIO).
> 
> Signed-off-by: Mike Dunn <mikedunn at newsguy.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120924/69c1692d/attachment.sig>

From olof at lixom.net  Mon Sep 24 11:21:00 2012
From: olof at lixom.net (Olof Johansson)
Date: Mon, 24 Sep 2012 08:21:00 -0700
Subject: [PATCH v3 1/2] ARM: Remove bcmring NAND driver
In-Reply-To: <1348499187.4880.66.camel@sauron.fi.intel.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
 <1348263626-3087-2-git-send-email-csd@broadcom.com>
 <1348499187.4880.66.camel@sauron.fi.intel.com>
Message-ID: <CAOesGMgs6Vq4yhKP6_4qHkJjo5vij=ww9VN7Yfz7QYxT95Ntaw@mail.gmail.com>

On Mon, Sep 24, 2012 at 8:06 AM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> On Fri, 2012-09-21 at 14:40 -0700, Christian Daudt wrote:
>> This driver is being removed as part of the cleanup of the bcmring
>> SoC from mainline as it is no longer maintained.
>>
>> Signed-off-by: Christian Daudt <csd at broadcom.com>
>> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>
>> Acked-by: Will Deacon <will.deacon at arm.com>
>
> Pushed this patch to l2-mtd.git. But if you decide to merge it via
> Arnd's tree (probably better idea) - let me know, I'll drop it.

Keeping it in mtd is fine.


-Olof


From biessmann at corscience.de  Mon Sep 24 11:29:35 2012
From: biessmann at corscience.de (=?ISO-8859-1?Q?Andreas_Bie=DFmann?=)
Date: Mon, 24 Sep 2012 17:29:35 +0200
Subject: Per-partition NAND ECC?
In-Reply-To: <50607688.6090601@gmail.com>
References: <50607688.6090601@gmail.com>
Message-ID: <50607C5F.3000501@corscience.de>

On 24.09.2012 17:04, Peter Barada wrote:
> On the OMAP3 parts the bootrom has a hard requirement of using 1-bit
> Hamming ECC to read the 2nd stage bootloader(x-loader / SPL) out of the
> first four blocks of NAND.  The Micron MT29C4G48MAZAPAKQ5 PoP part we're
> using requires 4-bit ECC for all the other NAND blocks to maintain an
> acceptable UBER.
> 
> Currently this wasn't a problem since I could use u-boot to update the
> 2nd stage bootloader. I now have a need to be able to update the 2nd
> stage bootloader from Linux only so I need the ability to write/read
> pages in a NAND partition with a different ECC method than that
> specified over the device.  I think it would be more elegant to solve
> this by allowing partition entry/mtdparts to specify its ECC
> methodology, track that as part of the MTD device down into the nand
> driver, and switch ECC methods/entrypoints as it changes.
> 
> Does anyone have suggestions on how to best approach this?

We have the same problem here. We modified the omap2 nand driver to have
the ecc type configurable as module parameter.
In our upgrade scenario we can unload the omap2 module cause we are
running from initrd and so we can switch the ecc type by module
parameter quite easy.
Your suggestion to switch ecc per mtd sound way better, but sorry I have
currently no insights how to implement this in a proper way. I don't
know if there is an generic way to bind the ecc information to an mtd.
You can find our solution attached (is added by c'n'p thus may have
wrong line wraps). If anybody is interested in this solution, I can
provide a proper patch.
And beware, you will need [1] and [2] for safe unloading of omap2 nand
driver.

Best regards

Andreas Bie?mann

[1]
http://git.infradead.org/users/dedekind/l2-mtd.git/commit/44552d26885a25b423c6606fd5f203aa95dc953f
[2]
http://git.infradead.org/users/dedekind/l2-mtd.git/commit/14178ea6dd8a6575616ce439389a8dd45e149aa8

---
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index c2b0bba..7f2ca2e 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -95,6 +95,10 @@
 #define P4e_s(a)	(TF(a & NAND_Ecc_P4e)		<< 0)
 #define P4o_s(a)	(TF(a & NAND_Ecc_P4o)		<< 1)

+static int eccmode = -1;
+module_param(eccmode, int, 0);
+MODULE_PARM_DESC(eccmode, "ECC mode (-1=platform data, 0=sw, 1=hw,
2=hwrom)");
+
 /* oob info generated runtime depending on ecc algorithm and layout
selected */
 static struct nand_ecclayout omap_oobinfo;
 /* Define some generic bad / good block scan pattern which are used
@@ -931,6 +935,7 @@ static int __devinit omap_nand_probe(struct
platform_device *pdev)
 	struct omap_nand_platform_data	*pdata;
 	int				err;
 	int				i, offset;
+	enum omap_ecc			ecc_opt;

 	pdata = pdev->dev.platform_data;
 	if (pdata == NULL) {
@@ -1052,10 +1057,13 @@ static int __devinit omap_nand_probe(struct
platform_device *pdev)
 	info->nand.verify_buf = omap_verify_buf;

 	/* selsect the ecc type */
-	if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
+	ecc_opt = (eccmode == -1) ? pdata->ecc_opt : eccmode;
+	dev_info(&pdev->dev, "Using ECC mode %d\n", ecc_opt);
+
+	if (ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
 		info->nand.ecc.mode = NAND_ECC_SOFT;
-	else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
-		(pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
+	else if ((ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
+		(ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
 		info->nand.ecc.bytes            = 3;
 		info->nand.ecc.size             = 512;
 		info->nand.ecc.strength         = 1;
@@ -1077,7 +1085,7 @@ static int __devinit omap_nand_probe(struct
platform_device *pdev)
 	}

 	/* rom code layout */
-	if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
+	if (ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {

 		if (info->nand.options & NAND_BUSWIDTH_16)
 			offset = 2;



From richard at nod.at  Mon Sep 24 14:31:26 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:26 +0200
Subject: [PATCH 04/10] UBI: Add self_check_eba()
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-5-git-send-email-richard@nod.at>

self_check_eba() compares two ubi_attach_info objects.
Fastmap uses this function for self checks.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   96 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 0910c2c..8af2ebf 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -1202,6 +1202,102 @@ static void print_rsvd_warning(struct ubi_device *ubi,
 }
 
 /**
+ * self_check_eba - run a self check on the EBA table constructed by fastmap.
+ * @ubi: UBI device description object
+ * @ai_fastmap: UBI attach info object created by fastmap
+ * @ai_scan: UBI attach info object created by scanning
+ *
+ * Returns < 0 in case of an internal error, 0 otherwise.
+ * If a bad EBA table entry was found it will be printed out and
+ * ubi_assert() triggers.
+ */
+int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap,
+		   struct ubi_attach_info *ai_scan)
+{
+	int i, j, num_volumes, ret = 0;
+	int **scan_eba, **fm_eba;
+	struct ubi_ainf_volume *av;
+	struct ubi_volume *vol;
+	struct ubi_ainf_peb *aeb;
+	struct rb_node *rb;
+
+	num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT;
+
+	scan_eba = kmalloc(sizeof(*scan_eba) * num_volumes, GFP_KERNEL);
+	if (!scan_eba)
+		return -ENOMEM;
+
+	fm_eba = kmalloc(sizeof(*fm_eba) * num_volumes, GFP_KERNEL);
+	if (!fm_eba) {
+		kfree(scan_eba);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < num_volumes; i++) {
+		vol = ubi->volumes[i];
+		if (!vol)
+			continue;
+
+		scan_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**scan_eba),
+				      GFP_KERNEL);
+		if (!scan_eba[i]) {
+			ret = -ENOMEM;
+			goto out_free;
+		}
+
+		fm_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**fm_eba),
+				    GFP_KERNEL);
+		if (!scan_eba[i]) {
+			ret = -ENOMEM;
+			goto out_free;
+		}
+
+		for (j = 0; j < vol->reserved_pebs; j++)
+			scan_eba[i][j] = fm_eba[i][j] = UBI_LEB_UNMAPPED;
+
+		av = ubi_find_av(ai_scan, idx2vol_id(ubi, i));
+		if (!av)
+			continue;
+
+		ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb)
+			scan_eba[i][aeb->lnum] = aeb->pnum;
+
+		av = ubi_find_av(ai_fastmap, idx2vol_id(ubi, i));
+		if (!av)
+			continue;
+
+		ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb)
+			fm_eba[i][aeb->lnum] = aeb->pnum;
+
+		for (j = 0; j < vol->reserved_pebs; j++) {
+			if (scan_eba[i][j] != fm_eba[i][j]) {
+				if (scan_eba[i][j] == UBI_LEB_UNMAPPED ||
+					fm_eba[i][j] == UBI_LEB_UNMAPPED)
+					continue;
+
+				ubi_err("LEB:%i:%i is PEB:%i instead of %i!",
+					vol->vol_id, i, fm_eba[i][j],
+					scan_eba[i][j]);
+				ubi_assert(0);
+			}
+		}
+	}
+
+out_free:
+	for (i = 0; i < num_volumes; i++) {
+		if (!ubi->volumes[i])
+			continue;
+
+		kfree(scan_eba[i]);
+		kfree(fm_eba[i]);
+	}
+
+	kfree(scan_eba);
+	kfree(fm_eba);
+	return ret;
+}
+
+/**
  * ubi_eba_init - initialize the EBA sub-system using attaching information.
  * @ubi: UBI device description object
  * @ai: attaching information
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:25 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:25 +0200
Subject: [PATCH 03/10] UBI: Export next_sqnum()
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-4-git-send-email-richard@nod.at>

Fastmap needs next_sqnum(), rename it to ubi_next_sqnum()
and make it non-static.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index a26d7d2..0910c2c 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -57,7 +57,7 @@
  * global sequence counter value. It also increases the global sequence
  * counter.
  */
-static unsigned long long next_sqnum(struct ubi_device *ubi)
+unsigned long long ubi_next_sqnum(struct ubi_device *ubi)
 {
 	unsigned long long sqnum;
 
@@ -521,7 +521,7 @@ retry:
 		goto out_put;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	err = ubi_io_write_vid_hdr(ubi, new_pnum, vid_hdr);
 	if (err)
 		goto write_error;
@@ -632,7 +632,7 @@ int ubi_eba_write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum,
 	}
 
 	vid_hdr->vol_type = UBI_VID_DYNAMIC;
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -692,7 +692,7 @@ write_error:
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -745,7 +745,7 @@ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol,
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -810,7 +810,7 @@ write_error:
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -862,7 +862,7 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol,
 	if (err)
 		goto out_mutex;
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -930,7 +930,7 @@ write_error:
 		goto out_leb_unlock;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -1089,7 +1089,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 		vid_hdr->data_size = cpu_to_be32(data_size);
 		vid_hdr->data_crc = cpu_to_be32(crc);
 	}
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 
 	err = ubi_io_write_vid_hdr(ubi, to, vid_hdr);
 	if (err) {
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:22 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:22 +0200
Subject: UBI: Fastmap request for inclusion (v18)
Message-ID: <1348511492-91606-1-git-send-email-richard@nod.at>

UBI Fastmap is an optional feature which stores the physical to
logical eraseblock relations in a checkpoint (called fastmap) to reduce
the initialization time of UBI. The current init time of UBI is
proportional to the number of physical erase blocks on the FLASH
device. With fastmap enabled the scan time is limited to a fixed
number of blocks.

Fastmap does not affect any of the existing UBI robustness
features and in fact the fastmap code falls back to scanning
mode when the found fastmap is corrupted.

A fastmap consists of two elements:

1) A primary super block, which contains merrily a pointer to the
   erase block(s) which hold the real fastmap data.

   This super block is guaranteed to be held within the first 64
   eraseblocks of a device.

2) The secondary fastmap blocks, which contain the real
   fastmap data (physical to logical eraseblock relations,
   erase counts, sequence numbers ...)

   Aside of that the fastmap data contains a list of blocks
   which belong to the active working pool. The active working pool is
   a fixed number of blocks to be used by the WL sub-system itself and the
   layer on top of UBI, which can be modified before the next fastmap
   is written to FLASH. These blocks need to be scanned in the
   conventional UBI scan mode.

   The reason for these pool blocks is to reduce the fastmap
   updates to the necessary minimum to avoid accelerated device
   wearout in scenarios where data changes rapidly. The fastmap
   data is updated whenever a working pool runs out of blocks.

So the fastmap scan consists of the following steps:

   1) Find the fastmap super block block by scanning the start of the
      device.

   2) Read the real fastmap data and construct the UBI device info
      structures.

   3) Scan the pool blocks.

The fastmap functionality is fully compatible with existing UBI
deployments. If no fastmap blocks can be found then the device is
scanned and the fastmap blocks are created from the scanned
information.

Changes since v17:

   - UBI reserves now PEBs to hold two fastmaps. It is guaranteed that
     each LEB has a corresponding PEB which can be used by an user.

   - Fastmap is automatically disabled if the FLASH devices has less than 64 PEBs

   - Fastmap is only available if CONFIG_MTD_UBI_FASTMAP is enabled.
     It is per default N. If fastmap has proven stable over some time we can
     remove CONFIG_MTD_UBI_FASTMAP and the corresponding #ifdefs.
     Even with CONFIG_MTD_UBI_FASTMAP=Y UBI will not automatically
     install a fastmap on existing images.
     This behavior is controlled by the fm_autoconvert UBI module parameter.
     Only if set to 1 UBI will install a fastmap automatically.
     By default it will use the fastmap only if one is found.

     So, if you want to test fastmap enable CONFIG_MTD_UBI_FASTMAP and
     set  fm_autoconvert to 1.
     If the device was attached by a fastmap you'll observe the following log
     message while attaching: "UBI: attached by fastmap".

State of fastmap:

We (linutronix gmbh) did numerous tests and are not aware of any issue or 
regression so far. The tests have been done on real hardware and simulators
(nandsim and mtdram). Of course with and without bitflip emulation enabled
and on NAND "bad" devices with bad blocks, bitflips, IO erros, ...
The tests consisted of mtd-util's ubi-tests, my fastmap torture script[1]
and real world use cases.

Each test run was done with the following configurations:
- CONFIG_MTD_UBI_FASTMAP=n
To verify that traditional UBI works fine.

- CONFIG_MTD_UBI_FASTMAP=y, fm_autoconvert=0
In this configuration the fastmap pool mechanism is active but
no fastmap is written to non-fastmap devices.

- CONFIG_MTD_UBI_FASTMAP=y, fm_autoconvert=1
Fastmap is enabled and non-fastmap devices get fastmap enabled.
Either at detach time or while writing.

I hope the MTD community do will also test fastmap in many different situations.
Bug reports are welcome!

Future work:

- Currently fastmap's powercut policy is that it will fall back to scanning mode if
  a power cut happened while writing the fastmap. If users really need fast attaching
  also after a power cut we could use the adjacent blocks mechanism for writing fastmap.
- Add fastmap support to ubinize
- If fastmap has proven stable, we can remove CONFIG_MTD_UBI_FASTMAP
  and enable it per default.

This patch set is based on artems ubi repository:
git://git.infradead.org/linux-ubi.git
You can find fastmap v18 also in my git repo on kernel.org:
git://git.kernel.org/pub/scm/linux/kernel/git/rw/ubi2.git ubi2/v18

Thanks to the folks at CELF who sponsored this work!

Thanks,
//richard

[1]
http://lists.infradead.org/pipermail/linux-mtd/2012-June/042347.html

[PATCH 01/10] UBI: Add fastmap on-flash data structures
[PATCH 02/10] UBI: Add fastmap stuff to ubi.h
[PATCH 03/10] UBI: Export next_sqnum()
[PATCH 04/10] UBI: Add self_check_eba()
[PATCH 05/10] UBI: Add fastmap bits to build.c
[PATCH 06/10] UBI: Wire-up ->fm_sem
[PATCH 07/10] UBI: Add fastmap stuff to attach.c
[PATCH 08/10] UBI: Add fastmap support to the WL sub-system
[PATCH 09/10] UBI: Add fastmap core
[PATCH 10/10] UBI: Wire-up fastmap

---
 MAINTAINERS                 |    6 +
 drivers/mtd/ubi/Kconfig     |   20 +
 drivers/mtd/ubi/Makefile    |    1 +
 drivers/mtd/ubi/attach.c    |  387 +++++++----
 drivers/mtd/ubi/build.c     |   71 ++-
 drivers/mtd/ubi/eba.c       |  126 ++++-
 drivers/mtd/ubi/fastmap.c   | 1560 +++++++++++++++++++++++++++++++++++++++++++
 drivers/mtd/ubi/ubi-media.h |  137 ++++
 drivers/mtd/ubi/ubi.h       |  119 ++++-
 drivers/mtd/ubi/wl.c        |  600 +++++++++++++++--
 10 files changed, 2814 insertions(+), 213 deletions(-)



From richard at nod.at  Mon Sep 24 14:31:24 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:24 +0200
Subject: [PATCH 02/10] UBI: Add fastmap stuff to ubi.h
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-3-git-send-email-richard@nod.at>

This patch adds fastmap specific data structures to ubi.h.
It moves also struct ubi_work to ubi.h as it is now needed
for more than one c file.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/ubi.h |  119 +++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/mtd/ubi/wl.c  |   24 ----------
 2 files changed, 116 insertions(+), 27 deletions(-)

diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index 383ee43..5f9ee1c 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -133,6 +133,17 @@ enum {
 	MOVE_RETRY,
 };
 
+/*
+ * Return codes of the fastmap sub-system
+ *
+ * UBI_NO_FASTMAP: No fastmap super block was found
+ * UBI_BAD_FASTMAP: A fastmap was found but it's unusable
+ */
+enum {
+	UBI_NO_FASTMAP = 1,
+	UBI_BAD_FASTMAP,
+};
+
 /**
  * struct ubi_wl_entry - wear-leveling entry.
  * @u.rb: link in the corresponding (free/used) RB-tree
@@ -199,6 +210,41 @@ struct ubi_rename_entry {
 struct ubi_volume_desc;
 
 /**
+ * struct ubi_fastmap_layout - in-memory fastmap data structure.
+ * @e: PEBs used by the current fastmap
+ * @to_be_tortured: if non-zero tortured this PEB
+ * @used_blocks: number of used PEBs
+ * @max_pool_size: maximal size of the user pool
+ * @max_wl_pool_size: maximal size of the pool used by the WL sub-system
+ */
+struct ubi_fastmap_layout {
+	struct ubi_wl_entry *e[UBI_FM_MAX_BLOCKS];
+	int to_be_tortured[UBI_FM_MAX_BLOCKS];
+	int used_blocks;
+	int max_pool_size;
+	int max_wl_pool_size;
+};
+
+/**
+ * struct ubi_fm_pool - in-memory fastmap pool
+ * @pebs: PEBs in this pool
+ * @used: number of used PEBs
+ * @size: total number of PEBs in this pool
+ * @max_size: maximal size of the pool
+ *
+ * A pool gets filled with up to max_size.
+ * If all PEBs within the pool are used a new fastmap will be written
+ * to the flash and the pool gets refilled with empty PEBs.
+ *
+ */
+struct ubi_fm_pool {
+	int pebs[UBI_FM_MAX_POOL_SIZE];
+	int used;
+	int size;
+	int max_size;
+};
+
+/**
  * struct ubi_volume - UBI volume description data structure.
  * @dev: device object to make use of the the Linux device model
  * @cdev: character device object to create character device
@@ -333,9 +379,21 @@ struct ubi_wl_entry;
  * @ltree: the lock tree
  * @alc_mutex: serializes "atomic LEB change" operations
  *
+ * @fm_disabled: non-zero if fastmap is disabled (default)
+ * @fm: in-memory data structure of the currently used fastmap
+ * @fm_pool: in-memory data structure of the fastmap pool
+ * @fm_wl_pool: in-memory data structure of the fastmap pool used by the WL
+ *		sub-system
+ * @fm_mutex: serializes ubi_update_fastmap() and protects @fm_buf
+ * @fm_buf: vmalloc()'d buffer which holds the raw fastmap
+ * @fm_size: fastmap size in bytes
+ * @fm_sem: allows ubi_update_fastmap() to block EBA table changes
+ * @fm_work: fastmap work queue
+ *
  * @used: RB-tree of used physical eraseblocks
  * @erroneous: RB-tree of erroneous used physical eraseblocks
  * @free: RB-tree of free physical eraseblocks
+ * @free_count: Contains the number of elements in @free
  * @scrub: RB-tree of physical eraseblocks which need scrubbing
  * @pq: protection queue (contain physical eraseblocks which are temporarily
  *      protected from the wear-leveling worker)
@@ -426,10 +484,22 @@ struct ubi_device {
 	struct rb_root ltree;
 	struct mutex alc_mutex;
 
+	/* Fastmap stuff */
+	int fm_disabled;
+	struct ubi_fastmap_layout *fm;
+	struct ubi_fm_pool fm_pool;
+	struct ubi_fm_pool fm_wl_pool;
+	struct rw_semaphore fm_sem;
+	struct mutex fm_mutex;
+	void *fm_buf;
+	size_t fm_size;
+	struct work_struct fm_work;
+
 	/* Wear-leveling sub-system's stuff */
 	struct rb_root used;
 	struct rb_root erroneous;
 	struct rb_root free;
+	int free_count;
 	struct rb_root scrub;
 	struct list_head pq[UBI_PROT_QUEUE_LEN];
 	int pq_head;
@@ -596,6 +666,32 @@ struct ubi_attach_info {
 	struct kmem_cache *aeb_slab_cache;
 };
 
+/**
+ * struct ubi_work - UBI work description data structure.
+ * @list: a link in the list of pending works
+ * @func: worker function
+ * @e: physical eraseblock to erase
+ * @vol_id: the volume ID on which this erasure is being performed
+ * @lnum: the logical eraseblock number
+ * @torture: if the physical eraseblock has to be tortured
+ * @anchor: produce a anchor PEB to by used by fastmap
+ *
+ * The @func pointer points to the worker function. If the @cancel argument is
+ * not zero, the worker has to free the resources and exit immediately. The
+ * worker has to return zero in case of success and a negative error code in
+ * case of failure.
+ */
+struct ubi_work {
+	struct list_head list;
+	int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel);
+	/* The below fields are only relevant to erasure works */
+	struct ubi_wl_entry *e;
+	int vol_id;
+	int lnum;
+	int torture;
+	int anchor;
+};
+
 #include "debug.h"
 
 extern struct kmem_cache *ubi_wl_entry_slab;
@@ -606,7 +702,7 @@ extern struct class *ubi_class;
 extern struct mutex ubi_devices_mutex;
 extern struct blocking_notifier_head ubi_notifiers;
 
-/* scan.c */
+/* attach.c */
 int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		  int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips);
 struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai,
@@ -614,8 +710,7 @@ struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai,
 void ubi_remove_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av);
 struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi,
 				       struct ubi_attach_info *ai);
-int ubi_attach(struct ubi_device *ubi);
-void ubi_destroy_ai(struct ubi_attach_info *ai);
+int ubi_attach(struct ubi_device *ubi, int force_scan);
 
 /* vtbl.c */
 int ubi_change_vtbl_record(struct ubi_device *ubi, int idx,
@@ -664,6 +759,9 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol,
 int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 		     struct ubi_vid_hdr *vid_hdr);
 int ubi_eba_init(struct ubi_device *ubi, struct ubi_attach_info *ai);
+unsigned long long ubi_next_sqnum(struct ubi_device *ubi);
+int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap,
+		   struct ubi_attach_info *ai_scan);
 
 /* wl.c */
 int ubi_wl_get_peb(struct ubi_device *ubi);
@@ -674,6 +772,12 @@ int ubi_wl_scrub_peb(struct ubi_device *ubi, int pnum);
 int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai);
 void ubi_wl_close(struct ubi_device *ubi);
 int ubi_thread(void *u);
+struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor);
+int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *used_e,
+		      int lnum, int torture);
+int ubi_is_erase_work(struct ubi_work *wrk);
+void ubi_refill_pools(struct ubi_device *ubi);
+int ubi_ensure_anchor_pebs(struct ubi_device *ubi);
 
 /* io.c */
 int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset,
@@ -711,6 +815,15 @@ void ubi_free_internal_volumes(struct ubi_device *ubi);
 void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di);
 void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol,
 			    struct ubi_volume_info *vi);
+/* scan.c */
+int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
+		      int pnum, const struct ubi_vid_hdr *vid_hdr);
+
+/* fastmap.c */
+size_t ubi_calc_fm_size(struct ubi_device *ubi);
+int ubi_update_fastmap(struct ubi_device *ubi);
+int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int fm_anchor);
 
 /*
  * ubi_rb_for_each_entry - walk an RB-tree.
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 032fc57..f4d06db 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -135,30 +135,6 @@
  */
 #define WL_MAX_FAILURES 32
 
-/**
- * struct ubi_work - UBI work description data structure.
- * @list: a link in the list of pending works
- * @func: worker function
- * @e: physical eraseblock to erase
- * @vol_id: the volume ID on which this erasure is being performed
- * @lnum: the logical eraseblock number
- * @torture: if the physical eraseblock has to be tortured
- *
- * The @func pointer points to the worker function. If the @cancel argument is
- * not zero, the worker has to free the resources and exit immediately. The
- * worker has to return zero in case of success and a negative error code in
- * case of failure.
- */
-struct ubi_work {
-	struct list_head list;
-	int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel);
-	/* The below fields are only relevant to erasure works */
-	struct ubi_wl_entry *e;
-	int vol_id;
-	int lnum;
-	int torture;
-};
-
 static int self_check_ec(struct ubi_device *ubi, int pnum, int ec);
 static int self_check_in_wl_tree(const struct ubi_device *ubi,
 				 struct ubi_wl_entry *e, struct rb_root *root);
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:27 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:27 +0200
Subject: [PATCH 05/10] UBI: Add fastmap bits to build.c
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-6-git-send-email-richard@nod.at>

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/build.c |   71 ++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 67 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3497703..cc7c03c 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -76,7 +76,10 @@ static int __initdata mtd_devs;
 
 /* MTD devices specification parameters */
 static struct mtd_dev_param __initdata mtd_dev_param[UBI_MAX_DEVICES];
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/* UBI module parameter to enable fastmap automatically on non-fastmap images */
+static bool fm_autoconvert;
+#endif
 /* Root UBI "class" object (corresponds to '/<sysfs>/class/ubi/') */
 struct class *ubi_class;
 
@@ -153,6 +156,19 @@ int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol, int ntype)
 
 	ubi_do_get_device_info(ubi, &nt.di);
 	ubi_do_get_volume_info(ubi, vol, &nt.vi);
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	switch (ntype) {
+	case UBI_VOLUME_ADDED:
+	case UBI_VOLUME_REMOVED:
+	case UBI_VOLUME_RESIZED:
+	case UBI_VOLUME_RENAMED:
+		if (ubi_update_fastmap(ubi)) {
+			ubi_err("Unable to update fastmap!");
+			ubi_ro_mode(ubi);
+		}
+	}
+#endif
 	return blocking_notifier_call_chain(&ubi_notifiers, ntype, &nt);
 }
 
@@ -918,10 +934,40 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	ubi->vid_hdr_offset = vid_hdr_offset;
 	ubi->autoresize_vol_id = -1;
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	ubi->fm_pool.used = ubi->fm_pool.size = 0;
+	ubi->fm_wl_pool.used = ubi->fm_wl_pool.size = 0;
+
+	/*
+	 * fm_pool.max_size is 5% of the total number of PEBs but it's also
+	 * between UBI_FM_MAX_POOL_SIZE and UBI_FM_MIN_POOL_SIZE.
+	 */
+	ubi->fm_pool.max_size = min(((int)mtd_div_by_eb(ubi->mtd->size,
+		ubi->mtd) / 100) * 5, UBI_FM_MAX_POOL_SIZE);
+	if (ubi->fm_pool.max_size < UBI_FM_MIN_POOL_SIZE)
+		ubi->fm_pool.max_size = UBI_FM_MIN_POOL_SIZE;
+
+	ubi->fm_wl_pool.max_size = UBI_FM_WL_POOL_SIZE;
+	ubi->fm_disabled = !fm_autoconvert;
+
+	if (!ubi->fm_disabled && (int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd)
+	    <= UBI_FM_MAX_START) {
+		ubi_err("More than %i PEBs are needed for fastmap, sorry.",
+			UBI_FM_MAX_START);
+		ubi->fm_disabled = 1;
+	}
+
+	ubi_msg("default fastmap pool size: %d", ubi->fm_pool.max_size);
+	ubi_msg("default fastmap WL pool size: %d", ubi->fm_wl_pool.max_size);
+#else
+	ubi->fm_disabled = 1;
+#endif
 	mutex_init(&ubi->buf_mutex);
 	mutex_init(&ubi->ckvol_mutex);
 	mutex_init(&ubi->device_mutex);
 	spin_lock_init(&ubi->volumes_lock);
+	mutex_init(&ubi->fm_mutex);
+	init_rwsem(&ubi->fm_sem);
 
 	ubi_msg("attaching mtd%d to ubi%d", mtd->index, ubi_num);
 
@@ -934,11 +980,17 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	if (!ubi->peb_buf)
 		goto out_free;
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	ubi->fm_size = ubi_calc_fm_size(ubi);
+	ubi->fm_buf = vzalloc(ubi->fm_size);
+	if (!ubi->fm_buf)
+		goto out_free;
+#endif
 	err = ubi_debugging_init_dev(ubi);
 	if (err)
 		goto out_free;
 
-	err = ubi_attach(ubi);
+	err = ubi_attach(ubi, 0);
 	if (err) {
 		ubi_err("failed to attach mtd%d, error %d", mtd->index, err);
 		goto out_debugging;
@@ -1012,6 +1064,7 @@ out_debugging:
 	ubi_debugging_exit_dev(ubi);
 out_free:
 	vfree(ubi->peb_buf);
+	vfree(ubi->fm_buf);
 	if (ref)
 		put_device(&ubi->dev);
 	else
@@ -1061,7 +1114,11 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
 	ubi_assert(ubi_num == ubi->ubi_num);
 	ubi_notify_all(ubi, UBI_VOLUME_REMOVED, NULL);
 	ubi_msg("detaching mtd%d from ubi%d", ubi->mtd->index, ubi_num);
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* If we don't write a new fastmap at detach time we lose all
+	 * EC updates that have been made since the last written fastmap. */
+	ubi_update_fastmap(ubi);
+#endif
 	/*
 	 * Before freeing anything, we have to stop the background thread to
 	 * prevent it from doing anything on this device while we are freeing.
@@ -1077,12 +1134,14 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
 
 	ubi_debugfs_exit_dev(ubi);
 	uif_close(ubi);
+
 	ubi_wl_close(ubi);
 	ubi_free_internal_volumes(ubi);
 	vfree(ubi->vtbl);
 	put_mtd_device(ubi->mtd);
 	ubi_debugging_exit_dev(ubi);
 	vfree(ubi->peb_buf);
+	vfree(ubi->fm_buf);
 	ubi_msg("mtd%d is detached from ubi%d", ubi->mtd->index, ubi->ubi_num);
 	put_device(&ubi->dev);
 	return 0;
@@ -1404,7 +1463,11 @@ MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: mtd=<name|num|pa
 		      "Example 2: mtd=content,1984 mtd=4 - attach MTD device with name \"content\" using VID header offset 1984, and MTD device number 4 with default VID header offset.\n"
 		      "Example 3: mtd=/dev/mtd1,0,25 - attach MTD device /dev/mtd1 using default VID header offset and reserve 25*nand_size_in_blocks/1024 erase blocks for bad block handling.\n"
 		      "\t(e.g. if the NAND *chipset* has 4096 PEB, 100 will be reserved for this UBI device).");
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+module_param(fm_autoconvert, bool, 0644);
+MODULE_PARM_DESC(fm_autoconvert, "Set this parameter to enable fastmap "
+				 "automatically on images without a fastmap.");
+#endif
 MODULE_VERSION(__stringify(UBI_VERSION));
 MODULE_DESCRIPTION("UBI - Unsorted Block Images");
 MODULE_AUTHOR("Artem Bityutskiy");
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:32 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:32 +0200
Subject: [PATCH 10/10] UBI: Wire-up fastmap
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-11-git-send-email-richard@nod.at>

Make fastmap known to Kconfig, UBI Makefile and MAINTAINERS.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 MAINTAINERS              |    6 ++++++
 drivers/mtd/ubi/Kconfig  |   20 ++++++++++++++++++++
 drivers/mtd/ubi/Makefile |    1 +
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..7bcade0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7075,6 +7075,12 @@ F:	drivers/mtd/ubi/
 F:	include/linux/mtd/ubi.h
 F:	include/mtd/ubi-user.h
 
+UNSORTED BLOCK IMAGES (UBI) Fastmap
+M:	Richard Weinberger <richard at nod.at>
+L:	linux-mtd at lists.infradead.org
+S:	Maintained
+F:	drivers/mtd/ubi/fastmap.c
+
 USB ACM DRIVER
 M:	Oliver Neukum <oliver at neukum.org>
 L:	linux-usb at vger.kernel.org
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 271a842..3620f91 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -56,6 +56,26 @@ config MTD_UBI_BEB_LIMIT
 
 	  Leave the default value if unsure.
 
+config MTD_UBI_FASTMAP
+	bool "UBI Fastmap (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	default n
+	help
+	   Fastmap is a mechanism which allows attaching an UBI device
+	   in nearly constant time.
+	   Instead of scanning the whole MTD device it only has to locate
+	   a checkpoint (called fastmap) on the device.
+	   The on-flash fastmap contains all information needed to attach
+	   the device. Using fastmap makes only sense on large devices where
+	   attaching by scanning takes long. UBI will not automatically install
+	   a fastmap on old images, but you can set the UBI module parameter
+	   fm_autoconvert to 1 if you want so. Please note that fastmap-enabled
+	   images are still usable with UBI implementations without
+	   fastmap support. On typical flash devices the whole fastmap fits
+	   into one PEB. UBI will reserve PEBs to hold two fastmaps.
+
+	   If in doubt, say "N".
+
 config MTD_UBI_GLUEBI
 	tristate "MTD devices emulation driver (gluebi)"
 	help
diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile
index a0803ac..7ab19ac 100644
--- a/drivers/mtd/ubi/Makefile
+++ b/drivers/mtd/ubi/Makefile
@@ -4,3 +4,4 @@ ubi-y += vtbl.o vmt.o upd.o build.o cdev.o kapi.o eba.o io.o wl.o attach.o
 ubi-y += misc.o debug.o
 
 obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
+obj-$(CONFIG_MTD_UBI_FASTMAP) += fastmap.o
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:28 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:28 +0200
Subject: [PATCH 06/10] UBI: Wire-up ->fm_sem
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-7-git-send-email-richard@nod.at>

Fastmap uses ->fm_sem to stop EBA changes while writing
a new fastmap.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 8af2ebf..50b3045 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -340,7 +340,9 @@ int ubi_eba_unmap_leb(struct ubi_device *ubi, struct ubi_volume *vol,
 
 	dbg_eba("erase LEB %d:%d, PEB %d", vol_id, lnum, pnum);
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = UBI_LEB_UNMAPPED;
+	up_read(&ubi->fm_sem);
 	err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 0);
 
 out_unlock:
@@ -548,7 +550,9 @@ retry:
 	mutex_unlock(&ubi->buf_mutex);
 	ubi_free_vid_hdr(ubi, vid_hdr);
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = new_pnum;
+	up_read(&ubi->fm_sem);
 	ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1);
 
 	ubi_msg("data was successfully recovered");
@@ -665,7 +669,9 @@ retry:
 		}
 	}
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 	leb_write_unlock(ubi, vol_id, lnum);
 	ubi_free_vid_hdr(ubi, vid_hdr);
@@ -783,7 +789,9 @@ retry:
 	}
 
 	ubi_assert(vol->eba_tbl[lnum] < 0);
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 	leb_write_unlock(ubi, vol_id, lnum);
 	ubi_free_vid_hdr(ubi, vid_hdr);
@@ -904,7 +912,9 @@ retry:
 			goto out_leb_unlock;
 	}
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 out_leb_unlock:
 	leb_write_unlock(ubi, vol_id, lnum);
@@ -1151,7 +1161,9 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 	}
 
 	ubi_assert(vol->eba_tbl[lnum] == from);
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = to;
+	up_read(&ubi->fm_sem);
 
 out_unlock_buf:
 	mutex_unlock(&ubi->buf_mutex);
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:23 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:23 +0200
Subject: [PATCH 01/10] UBI: Add fastmap on-flash data structures
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-2-git-send-email-richard@nod.at>

Add the on-flash data structures neeed by fastmap
to ubi-media.h

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/ubi-media.h |  137 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 137 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h
index 468ffbc..ac2b24d 100644
--- a/drivers/mtd/ubi/ubi-media.h
+++ b/drivers/mtd/ubi/ubi-media.h
@@ -375,4 +375,141 @@ struct ubi_vtbl_record {
 	__be32  crc;
 } __packed;
 
+/* UBI fastmap on-flash data structures */
+
+#define UBI_FM_SB_VOLUME_ID	(UBI_LAYOUT_VOLUME_ID + 1)
+#define UBI_FM_DATA_VOLUME_ID	(UBI_LAYOUT_VOLUME_ID + 2)
+
+/* fastmap on-flash data structure format version */
+#define UBI_FM_FMT_VERSION	1
+
+#define UBI_FM_SB_MAGIC		0x7B11D69F
+#define UBI_FM_HDR_MAGIC	0xD4B82EF7
+#define UBI_FM_VHDR_MAGIC	0xFA370ED1
+#define UBI_FM_POOL_MAGIC	0x67AF4D08
+#define UBI_FM_EBA_MAGIC	0xf0c040a8
+
+/* A fastmap supber block can be located between PEB 0 and
+ * UBI_FM_MAX_START */
+#define UBI_FM_MAX_START	64
+
+/* A fastmap can use up to UBI_FM_MAX_BLOCKS PEBs */
+#define UBI_FM_MAX_BLOCKS	32
+
+/* 5% of the total number of PEBs have to be scanned while attaching
+ * from a fastmap.
+ * But the size of this pool is limited to be between UBI_FM_MIN_POOL_SIZE and
+ * UBI_FM_MAX_POOL_SIZE */
+#define UBI_FM_MIN_POOL_SIZE	8
+#define UBI_FM_MAX_POOL_SIZE	256
+
+#define UBI_FM_WL_POOL_SIZE	25
+
+/**
+ * struct ubi_fm_sb - UBI fastmap super block
+ * @magic: fastmap super block magic number (%UBI_FM_SB_MAGIC)
+ * @version: format version of this fastmap
+ * @data_crc: CRC over the fastmap data
+ * @used_blocks: number of PEBs used by this fastmap
+ * @block_loc: an array containing the location of all PEBs of the fastmap
+ * @block_ec: the erase counter of each used PEB
+ * @sqnum: highest sequence number value at the time while taking the fastmap
+ *
+ */
+struct ubi_fm_sb {
+	__be32 magic;
+	__u8 version;
+	__u8 padding1[3];
+	__be32 data_crc;
+	__be32 used_blocks;
+	__be32 block_loc[UBI_FM_MAX_BLOCKS];
+	__be32 block_ec[UBI_FM_MAX_BLOCKS];
+	__be64 sqnum;
+	__u8 padding2[32];
+} __packed;
+
+/**
+ * struct ubi_fm_hdr - header of the fastmap data set
+ * @magic: fastmap header magic number (%UBI_FM_HDR_MAGIC)
+ * @free_peb_count: number of free PEBs known by this fastmap
+ * @used_peb_count: number of used PEBs known by this fastmap
+ * @scrub_peb_count: number of to be scrubbed PEBs known by this fastmap
+ * @bad_peb_count: number of bad PEBs known by this fastmap
+ * @erase_peb_count: number of bad PEBs which have to be erased
+ * @vol_count: number of UBI volumes known by this fastmap
+ */
+struct ubi_fm_hdr {
+	__be32 magic;
+	__be32 free_peb_count;
+	__be32 used_peb_count;
+	__be32 scrub_peb_count;
+	__be32 bad_peb_count;
+	__be32 erase_peb_count;
+	__be32 vol_count;
+	__u8 padding[4];
+} __packed;
+
+/* struct ubi_fm_hdr is followed by two struct ubi_fm_scan_pool */
+
+/**
+ * struct ubi_fm_scan_pool - Fastmap pool PEBs to be scanned while attaching
+ * @magic: pool magic numer (%UBI_FM_POOL_MAGIC)
+ * @size: current pool size
+ * @max_size: maximal pool size
+ * @pebs: an array containing the location of all PEBs in this pool
+ */
+struct ubi_fm_scan_pool {
+	__be32 magic;
+	__be16 size;
+	__be16 max_size;
+	__be32 pebs[UBI_FM_MAX_POOL_SIZE];
+	__be32 padding[4];
+} __packed;
+
+/* ubi_fm_scan_pool is followed by nfree+nused struct ubi_fm_ec records */
+
+/**
+ * struct ubi_fm_ec - stores the erase counter of a PEB
+ * @pnum: PEB number
+ * @ec: ec of this PEB
+ */
+struct ubi_fm_ec {
+	__be32 pnum;
+	__be32 ec;
+} __packed;
+
+/**
+ * struct ubi_fm_volhdr - Fastmap volume header
+ * it identifies the start of an eba table
+ * @magic: Fastmap volume header magic number (%UBI_FM_VHDR_MAGIC)
+ * @vol_id: volume id of the fastmapped volume
+ * @vol_type: type of the fastmapped volume
+ * @data_pad: data_pad value of the fastmapped volume
+ * @used_ebs: number of used LEBs within this volume
+ * @last_eb_bytes: number of bytes used in the last LEB
+ */
+struct ubi_fm_volhdr {
+	__be32 magic;
+	__be32 vol_id;
+	__u8 vol_type;
+	__u8 padding1[3];
+	__be32 data_pad;
+	__be32 used_ebs;
+	__be32 last_eb_bytes;
+	__u8 padding2[8];
+} __packed;
+
+/* struct ubi_fm_volhdr is followed by one struct ubi_fm_eba records */
+
+/**
+ * struct ubi_fm_eba - denotes an association beween a PEB and LEB
+ * @magic: EBA table magic number
+ * @reserved_pebs: number of table entries
+ * @pnum: PEB number of LEB (LEB is the index)
+ */
+struct ubi_fm_eba {
+	__be32 magic;
+	__be32 reserved_pebs;
+	__be32 pnum[0];
+} __packed;
 #endif /* !__UBI_MEDIA_H__ */
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:30 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:30 +0200
Subject: [PATCH 08/10] UBI: Add fastmap support to the WL sub-system
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-9-git-send-email-richard@nod.at>

To make fastmap possible the WL sub-system needs some
changes.
Mostly to support fastmaps pools.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/wl.c |  576 ++++++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 531 insertions(+), 45 deletions(-)

diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index f4d06db..2439f69 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -141,6 +141,42 @@ static int self_check_in_wl_tree(const struct ubi_device *ubi,
 static int self_check_in_pq(const struct ubi_device *ubi,
 			    struct ubi_wl_entry *e);
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * update_fastmap_work_fn - calls ubi_update_fastmap from a work queue
+ * @wrk: the work description object
+ */
+static void update_fastmap_work_fn(struct work_struct *wrk)
+{
+	struct ubi_device *ubi = container_of(wrk, struct ubi_device, fm_work);
+	ubi_update_fastmap(ubi);
+}
+
+/**
+ *  ubi_ubi_is_fm_block - returns 1 if a PEB is currently used in a fastmap.
+ *  @ubi: UBI device description object
+ *  @pnum: the to be checked PEB
+ */
+static int ubi_is_fm_block(struct ubi_device *ubi, int pnum)
+{
+	int i;
+
+	if (!ubi->fm)
+		return 0;
+
+	for (i = 0; i < ubi->fm->used_blocks; i++)
+		if (ubi->fm->e[i]->pnum == pnum)
+			return 1;
+
+	return 0;
+}
+#else
+static int ubi_is_fm_block(struct ubi_device *ubi, int pnum)
+{
+	return 0;
+}
+#endif
+
 /**
  * wl_tree_add - add a wear-leveling entry to a WL RB-tree.
  * @e: the wear-leveling entry to add
@@ -237,18 +273,16 @@ static int produce_free_peb(struct ubi_device *ubi)
 {
 	int err;
 
-	spin_lock(&ubi->wl_lock);
 	while (!ubi->free.rb_node) {
 		spin_unlock(&ubi->wl_lock);
 
 		dbg_wl("do one work synchronously");
 		err = do_work(ubi);
-		if (err)
-			return err;
 
 		spin_lock(&ubi->wl_lock);
+		if (err)
+			return err;
 	}
-	spin_unlock(&ubi->wl_lock);
 
 	return 0;
 }
@@ -315,16 +349,18 @@ static void prot_queue_add(struct ubi_device *ubi, struct ubi_wl_entry *e)
 
 /**
  * find_wl_entry - find wear-leveling entry closest to certain erase counter.
+ * @ubi: UBI device description object
  * @root: the RB-tree where to look for
  * @diff: maximum possible difference from the smallest erase counter
  *
  * This function looks for a wear leveling entry with erase counter closest to
  * min + @diff, where min is the smallest erase counter.
  */
-static struct ubi_wl_entry *find_wl_entry(struct rb_root *root, int diff)
+static struct ubi_wl_entry *find_wl_entry(struct ubi_device *ubi,
+					  struct rb_root *root, int diff)
 {
 	struct rb_node *p;
-	struct ubi_wl_entry *e;
+	struct ubi_wl_entry *e, *prev_e = NULL;
 	int max;
 
 	e = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb);
@@ -339,35 +375,144 @@ static struct ubi_wl_entry *find_wl_entry(struct rb_root *root, int diff)
 			p = p->rb_left;
 		else {
 			p = p->rb_right;
+			prev_e = e;
 			e = e1;
 		}
 	}
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* If no fastmap has been written and this WL entry can be used
+	 * as anchor PEB, hold it back and return the second best WL entry
+	 * such that fastmap can use the anchor PEB later. */
+	if (prev_e && !ubi->fm_disabled &&
+	    !ubi->fm && e->pnum < UBI_FM_MAX_START)
+		return prev_e;
+#endif
 	return e;
 }
 
 /**
- * ubi_wl_get_peb - get a physical eraseblock.
+ * find_mean_wl_entry - find wear-leveling entry with medium erase counter.
+ * @ubi: UBI device description object
+ * @root: the RB-tree where to look for
+ *
+ * This function looks for a wear leveling entry with medium erase counter,
+ * but not greater or equivalent than the lowest erase counter plus
+ * %WL_FREE_MAX_DIFF/2.
+ */
+static struct ubi_wl_entry *find_mean_wl_entry(struct ubi_device *ubi,
+					       struct rb_root *root)
+{
+	struct ubi_wl_entry *e, *first, *last;
+
+	first = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb);
+	last = rb_entry(rb_last(root), struct ubi_wl_entry, u.rb);
+
+	if (last->ec - first->ec < WL_FREE_MAX_DIFF) {
+		e = rb_entry(root->rb_node, struct ubi_wl_entry, u.rb);
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+		/* If no fastmap has been written and this WL entry can be used
+		 * as anchor PEB, hold it back and return the second best
+		 * WL entry such that fastmap can use the anchor PEB later. */
+		if (e && !ubi->fm_disabled && !ubi->fm &&
+		    e->pnum < UBI_FM_MAX_START)
+			e = rb_entry(rb_next(root->rb_node),
+				     struct ubi_wl_entry, u.rb);
+#endif
+	} else
+		e = find_wl_entry(ubi, root, WL_FREE_MAX_DIFF/2);
+
+	return e;
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * find_anchor_wl_entry - find wear-leveling entry to used as anchor PEB.
+ * @root: the RB-tree where to look for
+ */
+static struct ubi_wl_entry *find_anchor_wl_entry(struct rb_root *root)
+{
+	struct rb_node *p;
+	struct ubi_wl_entry *e, *victim = NULL;
+	int max_ec = UBI_MAX_ERASECOUNTER;
+
+	ubi_rb_for_each_entry(p, e, root, u.rb) {
+		if (e->pnum < UBI_FM_MAX_START && e->ec < max_ec) {
+			victim = e;
+			max_ec = e->ec;
+		}
+	}
+
+	return victim;
+}
+
+static int anchor_pebs_avalible(struct rb_root *root)
+{
+	struct rb_node *p;
+	struct ubi_wl_entry *e;
+
+	ubi_rb_for_each_entry(p, e, root, u.rb)
+		if (e->pnum < UBI_FM_MAX_START)
+			return 1;
+
+	return 0;
+}
+
+/**
+ * ubi_wl_get_fm_peb - find a physical erase block with a given maximal number.
+ * @ubi: UBI device description object
+ * @anchor: This PEB will be used as anchor PEB by fastmap
+ *
+ * The function returns a physical erase block with a given maximal number
+ * and removes it from the wl subsystem.
+ * Must be called with wl_lock held!
+ */
+struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor)
+{
+	struct ubi_wl_entry *e = NULL;
+
+	if (!ubi->free.rb_node || (ubi->free_count - ubi->beb_rsvd_pebs < 1))
+		goto out;
+
+	if (anchor)
+		e = find_anchor_wl_entry(&ubi->free);
+	else
+		e = find_mean_wl_entry(ubi, &ubi->free);
+
+	if (!e)
+		goto out;
+
+	self_check_in_wl_tree(ubi, e, &ubi->free);
+
+	/* remove it from the free list,
+	 * the wl subsystem does no longer know this erase block */
+	rb_erase(&e->u.rb, &ubi->free);
+	ubi->free_count--;
+out:
+	return e;
+}
+#endif
+
+/**
+ * __wl_get_peb - get a physical eraseblock.
  * @ubi: UBI device description object
  *
  * This function returns a physical eraseblock in case of success and a
  * negative error code in case of failure. Might sleep.
  */
-int ubi_wl_get_peb(struct ubi_device *ubi)
+static int __wl_get_peb(struct ubi_device *ubi)
 {
 	int err;
-	struct ubi_wl_entry *e, *first, *last;
+	struct ubi_wl_entry *e;
 
 retry:
-	spin_lock(&ubi->wl_lock);
 	if (!ubi->free.rb_node) {
 		if (ubi->works_count == 0) {
-			ubi_assert(list_empty(&ubi->works));
 			ubi_err("no free eraseblocks");
-			spin_unlock(&ubi->wl_lock);
+			ubi_assert(list_empty(&ubi->works));
 			return -ENOSPC;
 		}
-		spin_unlock(&ubi->wl_lock);
 
 		err = produce_free_peb(ubi);
 		if (err < 0)
@@ -375,13 +520,11 @@ retry:
 		goto retry;
 	}
 
-	first = rb_entry(rb_first(&ubi->free), struct ubi_wl_entry, u.rb);
-	last = rb_entry(rb_last(&ubi->free), struct ubi_wl_entry, u.rb);
-
-	if (last->ec - first->ec < WL_FREE_MAX_DIFF)
-		e = rb_entry(ubi->free.rb_node, struct ubi_wl_entry, u.rb);
-	else
-		e = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF/2);
+	e = find_mean_wl_entry(ubi, &ubi->free);
+	if (!e) {
+		ubi_err("no free eraseblocks");
+		return -ENOSPC;
+	}
 
 	self_check_in_wl_tree(ubi, e, &ubi->free);
 
@@ -390,10 +533,14 @@ retry:
 	 * be protected from being moved for some time.
 	 */
 	rb_erase(&e->u.rb, &ubi->free);
+	ubi->free_count--;
 	dbg_wl("PEB %d EC %d", e->pnum, e->ec);
+#ifndef CONFIG_MTD_UBI_FASTMAP
+	/* We have to enqueue e only if fastmap is disabled,
+	 * is fastmap enabled prot_queue_add() will be called by
+	 * ubi_wl_get_peb() after removing e from the pool. */
 	prot_queue_add(ubi, e);
-	spin_unlock(&ubi->wl_lock);
-
+#endif
 	err = ubi_self_check_all_ff(ubi, e->pnum, ubi->vid_hdr_aloffset,
 				    ubi->peb_size - ubi->vid_hdr_aloffset);
 	if (err) {
@@ -404,6 +551,150 @@ retry:
 	return e->pnum;
 }
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * return_unused_pool_pebs - returns unused PEB to the free tree.
+ * @ubi: UBI device description object
+ * @pool: fastmap pool description object
+ */
+static void return_unused_pool_pebs(struct ubi_device *ubi,
+				    struct ubi_fm_pool *pool)
+{
+	int i;
+	struct ubi_wl_entry *e;
+
+	for (i = pool->used; i < pool->size; i++) {
+		e = ubi->lookuptbl[pool->pebs[i]];
+		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
+	}
+}
+
+/**
+ * refill_wl_pool - refills all the fastmap pool used by the
+ * WL sub-system.
+ * @ubi: UBI device description object
+ */
+static void refill_wl_pool(struct ubi_device *ubi)
+{
+	struct ubi_wl_entry *e;
+	struct ubi_fm_pool *pool = &ubi->fm_wl_pool;
+
+	return_unused_pool_pebs(ubi, pool);
+
+	for (pool->size = 0; pool->size < pool->max_size; pool->size++) {
+		if (!ubi->free.rb_node ||
+		   (ubi->free_count - ubi->beb_rsvd_pebs < 5))
+			break;
+
+		e = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
+		self_check_in_wl_tree(ubi, e, &ubi->free);
+		rb_erase(&e->u.rb, &ubi->free);
+		ubi->free_count--;
+
+		pool->pebs[pool->size] = e->pnum;
+	}
+	pool->used = 0;
+}
+
+/**
+ * refill_wl_user_pool - refills all the fastmap pool used by ubi_wl_get_peb.
+ * @ubi: UBI device description object
+ */
+static void refill_wl_user_pool(struct ubi_device *ubi)
+{
+	struct ubi_fm_pool *pool = &ubi->fm_pool;
+
+	return_unused_pool_pebs(ubi, pool);
+
+	for (pool->size = 0; pool->size < pool->max_size; pool->size++) {
+		if (!ubi->free.rb_node ||
+		   (ubi->free_count - ubi->beb_rsvd_pebs < 1))
+			break;
+
+		pool->pebs[pool->size] = __wl_get_peb(ubi);
+		if (pool->pebs[pool->size] < 0)
+			break;
+	}
+	pool->used = 0;
+}
+
+/**
+ * ubi_refill_pools - refills all fastmap PEB pools.
+ * @ubi: UBI device description object
+ */
+void ubi_refill_pools(struct ubi_device *ubi)
+{
+	spin_lock(&ubi->wl_lock);
+	refill_wl_pool(ubi);
+	refill_wl_user_pool(ubi);
+	spin_unlock(&ubi->wl_lock);
+}
+
+/* ubi_wl_get_peb - works exaclty like __wl_get_peb but keeps track of
+ * the fastmap pool.
+ */
+int ubi_wl_get_peb(struct ubi_device *ubi)
+{
+	int ret;
+	struct ubi_fm_pool *pool = &ubi->fm_pool;
+	struct ubi_fm_pool *wl_pool = &ubi->fm_wl_pool;
+
+	if (!pool->size || !wl_pool->size || pool->used == pool->size ||
+	    wl_pool->used == wl_pool->size)
+		ubi_update_fastmap(ubi);
+
+	/* we got not a single free PEB */
+	if (!pool->size)
+		ret = -ENOSPC;
+	else {
+		spin_lock(&ubi->wl_lock);
+		ret = pool->pebs[pool->used++];
+		prot_queue_add(ubi, ubi->lookuptbl[ret]);
+		spin_unlock(&ubi->wl_lock);
+	}
+
+	return ret;
+}
+
+/* get_peb_for_wl - returns a PEB to be used internally by the WL sub-system.
+ *
+ * @ubi: UBI device description object
+ */
+static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi)
+{
+	struct ubi_fm_pool *pool = &ubi->fm_wl_pool;
+	int pnum;
+
+	if (pool->used == pool->size || !pool->size) {
+		/* We cannot update the fastmap here because this
+		 * function is called in atomic context.
+		 * Let's fail here and refill/update it as soon as possible. */
+		schedule_work(&ubi->fm_work);
+		return NULL;
+	} else {
+		pnum = pool->pebs[pool->used++];
+		return ubi->lookuptbl[pnum];
+	}
+}
+#else
+static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi)
+{
+	return find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
+}
+
+int ubi_wl_get_peb(struct ubi_device *ubi)
+{
+	int peb;
+
+	spin_lock(&ubi->wl_lock);
+	peb = __wl_get_peb(ubi);
+	spin_unlock(&ubi->wl_lock);
+
+	return peb;
+}
+#endif
+
 /**
  * prot_queue_del - remove a physical eraseblock from the protection queue.
  * @ubi: UBI device description object
@@ -534,14 +825,14 @@ repeat:
 }
 
 /**
- * schedule_ubi_work - schedule a work.
+ * __schedule_ubi_work - schedule a work.
  * @ubi: UBI device description object
  * @wrk: the work to schedule
  *
  * This function adds a work defined by @wrk to the tail of the pending works
- * list.
+ * list. Can only be used of ubi->work_sem is already held in read mode!
  */
-static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
+static void __schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
 {
 	spin_lock(&ubi->wl_lock);
 	list_add_tail(&wrk->list, &ubi->works);
@@ -552,9 +843,35 @@ static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
 	spin_unlock(&ubi->wl_lock);
 }
 
+/**
+ * schedule_ubi_work - schedule a work.
+ * @ubi: UBI device description object
+ * @wrk: the work to schedule
+ *
+ * This function adds a work defined by @wrk to the tail of the pending works
+ * list.
+ */
+static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
+{
+	down_read(&ubi->work_sem);
+	__schedule_ubi_work(ubi, wrk);
+	up_read(&ubi->work_sem);
+}
+
 static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 			int cancel);
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_is_erase_work - checks whether a work is erase work.
+ * @wrk: The work object to be checked
+ */
+int ubi_is_erase_work(struct ubi_work *wrk)
+{
+	return wrk->func == erase_worker;
+}
+#endif
+
 /**
  * schedule_erase - schedule an erase work.
  * @ubi: UBI device description object
@@ -571,6 +888,9 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
 {
 	struct ubi_work *wl_wrk;
 
+	ubi_assert(e);
+	ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 	dbg_wl("schedule erasure of PEB %d, EC %d, torture %d",
 	       e->pnum, e->ec, torture);
 
@@ -589,6 +909,79 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
 }
 
 /**
+ * do_sync_erase - run the erase worker synchronously.
+ * @ubi: UBI device description object
+ * @e: the WL entry of the physical eraseblock to erase
+ * @vol_id: the volume ID that last used this PEB
+ * @lnum: the last used logical eraseblock number for the PEB
+ * @torture: if the physical eraseblock has to be tortured
+ *
+ */
+static int do_sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
+			 int vol_id, int lnum, int torture)
+{
+	struct ubi_work *wl_wrk;
+
+	dbg_wl("sync erase of PEB %i", e->pnum);
+
+	wl_wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS);
+	if (!wl_wrk)
+		return -ENOMEM;
+
+	wl_wrk->e = e;
+	wl_wrk->vol_id = vol_id;
+	wl_wrk->lnum = lnum;
+	wl_wrk->torture = torture;
+
+	return erase_worker(ubi, wl_wrk, 0);
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_wl_put_fm_peb - returns a PEB used in a fastmap to the wear-leveling
+ * sub-system.
+ * see: ubi_wl_put_peb()
+ *
+ * @ubi: UBI device description object
+ * @fm_e: physical eraseblock to return
+ * @lnum: the last used logical eraseblock number for the PEB
+ * @torture: if this physical eraseblock has to be tortured
+ */
+int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *fm_e,
+		      int lnum, int torture)
+{
+	struct ubi_wl_entry *e;
+	int vol_id, pnum = fm_e->pnum;
+
+	dbg_wl("PEB %d", pnum);
+
+	ubi_assert(pnum >= 0);
+	ubi_assert(pnum < ubi->peb_count);
+
+	spin_lock(&ubi->wl_lock);
+	e = ubi->lookuptbl[pnum];
+
+	/* This can happen if we recovered from a fastmap the very
+	 * first time and writing now a new one. In this case the wl system
+	 * has never seen any PEB used by the original fastmap.
+	 */
+	if (!e) {
+		e = fm_e;
+		ubi_assert(e->ec >= 0);
+		ubi->lookuptbl[pnum] = e;
+	} else {
+		e->ec = fm_e->ec;
+		kfree(fm_e);
+	}
+
+	spin_unlock(&ubi->wl_lock);
+
+	vol_id = lnum ? UBI_FM_DATA_VOLUME_ID : UBI_FM_SB_VOLUME_ID;
+	return schedule_erase(ubi, e, vol_id, lnum, torture);
+}
+#endif
+
+/**
  * wear_leveling_worker - wear-leveling worker function.
  * @ubi: UBI device description object
  * @wrk: the work object
@@ -602,10 +995,11 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 				int cancel)
 {
 	int err, scrubbing = 0, torture = 0, protect = 0, erroneous = 0;
-	int vol_id = -1, uninitialized_var(lnum);
+	int anchor, vol_id = -1, uninitialized_var(lnum);
 	struct ubi_wl_entry *e1, *e2;
 	struct ubi_vid_hdr *vid_hdr;
 
+	anchor = wrk->anchor;
 	kfree(wrk);
 	if (cancel)
 		return 0;
@@ -636,14 +1030,35 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		goto out_cancel;
 	}
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* Check whether we need to produce an anchor PEB */
+	if (!anchor)
+		anchor = !anchor_pebs_avalible(&ubi->free);
+
+	if (anchor) {
+		e1 = find_anchor_wl_entry(&ubi->used);
+		if (!e1)
+			goto out_cancel;
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
+
+		self_check_in_wl_tree(ubi, e1, &ubi->used);
+		rb_erase(&e1->u.rb, &ubi->used);
+		dbg_wl("anchor-move PEB %d to PEB %d", e1->pnum, e2->pnum);
+	} else if (!ubi->scrub.rb_node) {
+#else
 	if (!ubi->scrub.rb_node) {
+#endif
 		/*
 		 * Now pick the least worn-out used physical eraseblock and a
 		 * highly worn-out free physical eraseblock. If the erase
 		 * counters differ much enough, start wear-leveling.
 		 */
 		e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
 
 		if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD)) {
 			dbg_wl("no WL needed: min used EC %d, max free EC %d",
@@ -658,14 +1073,15 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		/* Perform scrubbing */
 		scrubbing = 1;
 		e1 = rb_entry(rb_first(&ubi->scrub), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
+
 		self_check_in_wl_tree(ubi, e1, &ubi->scrub);
 		rb_erase(&e1->u.rb, &ubi->scrub);
 		dbg_wl("scrub PEB %d to PEB %d", e1->pnum, e2->pnum);
 	}
 
-	self_check_in_wl_tree(ubi, e2, &ubi->free);
-	rb_erase(&e2->u.rb, &ubi->free);
 	ubi->move_from = e1;
 	ubi->move_to = e2;
 	spin_unlock(&ubi->wl_lock);
@@ -782,7 +1198,7 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 	ubi->move_to_put = ubi->wl_scheduled = 0;
 	spin_unlock(&ubi->wl_lock);
 
-	err = schedule_erase(ubi, e1, vol_id, lnum, 0);
+	err = do_sync_erase(ubi, e1, vol_id, lnum, 0);
 	if (err) {
 		kmem_cache_free(ubi_wl_entry_slab, e1);
 		if (e2)
@@ -797,7 +1213,7 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		 */
 		dbg_wl("PEB %d (LEB %d:%d) was put meanwhile, erase",
 		       e2->pnum, vol_id, lnum);
-		err = schedule_erase(ubi, e2, vol_id, lnum, 0);
+		err = do_sync_erase(ubi, e2, vol_id, lnum, 0);
 		if (err) {
 			kmem_cache_free(ubi_wl_entry_slab, e2);
 			goto out_ro;
@@ -836,7 +1252,7 @@ out_not_moved:
 	spin_unlock(&ubi->wl_lock);
 
 	ubi_free_vid_hdr(ubi, vid_hdr);
-	err = schedule_erase(ubi, e2, vol_id, lnum, torture);
+	err = do_sync_erase(ubi, e2, vol_id, lnum, torture);
 	if (err) {
 		kmem_cache_free(ubi_wl_entry_slab, e2);
 		goto out_ro;
@@ -877,12 +1293,13 @@ out_cancel:
 /**
  * ensure_wear_leveling - schedule wear-leveling if it is needed.
  * @ubi: UBI device description object
+ * @nested: set to non-zero if this function is called from UBI worker
  *
  * This function checks if it is time to start wear-leveling and schedules it
  * if yes. This function returns zero in case of success and a negative error
  * code in case of failure.
  */
-static int ensure_wear_leveling(struct ubi_device *ubi)
+static int ensure_wear_leveling(struct ubi_device *ubi, int nested)
 {
 	int err = 0;
 	struct ubi_wl_entry *e1;
@@ -910,7 +1327,7 @@ static int ensure_wear_leveling(struct ubi_device *ubi)
 		 * %UBI_WL_THRESHOLD.
 		 */
 		e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
 
 		if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD))
 			goto out_unlock;
@@ -927,8 +1344,12 @@ static int ensure_wear_leveling(struct ubi_device *ubi)
 		goto out_cancel;
 	}
 
+	wrk->anchor = 0;
 	wrk->func = &wear_leveling_worker;
-	schedule_ubi_work(ubi, wrk);
+	if (nested)
+		__schedule_ubi_work(ubi, wrk);
+	else
+		schedule_ubi_work(ubi, wrk);
 	return err;
 
 out_cancel:
@@ -939,6 +1360,38 @@ out_unlock:
 	return err;
 }
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_ensure_anchor_pebs - schedule wear-leveling to produce an anchor PEB.
+ * @ubi: UBI device description object
+ */
+int ubi_ensure_anchor_pebs(struct ubi_device *ubi)
+{
+	struct ubi_work *wrk;
+
+	spin_lock(&ubi->wl_lock);
+	if (ubi->wl_scheduled) {
+		spin_unlock(&ubi->wl_lock);
+		return 0;
+	}
+	ubi->wl_scheduled = 1;
+	spin_unlock(&ubi->wl_lock);
+
+	wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS);
+	if (!wrk) {
+		spin_lock(&ubi->wl_lock);
+		ubi->wl_scheduled = 0;
+		spin_unlock(&ubi->wl_lock);
+		return -ENOMEM;
+	}
+
+	wrk->anchor = 1;
+	wrk->func = &wear_leveling_worker;
+	schedule_ubi_work(ubi, wrk);
+	return 0;
+}
+#endif
+
 /**
  * erase_worker - physical eraseblock erase worker function.
  * @ubi: UBI device description object
@@ -969,6 +1422,8 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 	dbg_wl("erase PEB %d EC %d LEB %d:%d",
 	       pnum, e->ec, wl_wrk->vol_id, wl_wrk->lnum);
 
+	ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 	err = sync_erase(ubi, e, wl_wrk->torture);
 	if (!err) {
 		/* Fine, we've erased it successfully */
@@ -976,6 +1431,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 
 		spin_lock(&ubi->wl_lock);
 		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
 		spin_unlock(&ubi->wl_lock);
 
 		/*
@@ -985,7 +1441,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 		serve_prot_queue(ubi);
 
 		/* And take care about wear-leveling */
-		err = ensure_wear_leveling(ubi);
+		err = ensure_wear_leveling(ubi, 1);
 		return err;
 	}
 
@@ -1223,7 +1679,7 @@ retry:
 	 * Technically scrubbing is the same as wear-leveling, so it is done
 	 * by the WL worker.
 	 */
-	return ensure_wear_leveling(ubi);
+	return ensure_wear_leveling(ubi, 0);
 }
 
 /**
@@ -1404,7 +1860,7 @@ static void cancel_pending(struct ubi_device *ubi)
  */
 int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 {
-	int err, i;
+	int err, i, reserved_pebs, found_pebs = 0;
 	struct rb_node *rb1, *rb2;
 	struct ubi_ainf_volume *av;
 	struct ubi_ainf_peb *aeb, *tmp;
@@ -1416,6 +1872,9 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 	init_rwsem(&ubi->work_sem);
 	ubi->max_ec = ai->max_ec;
 	INIT_LIST_HEAD(&ubi->works);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	INIT_WORK(&ubi->fm_work, update_fastmap_work_fn);
+#endif
 
 	sprintf(ubi->bgt_name, UBI_BGT_NAME_PATTERN, ubi->ubi_num);
 
@@ -1437,13 +1896,17 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 
 		e->pnum = aeb->pnum;
 		e->ec = aeb->ec;
+		ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
 		ubi->lookuptbl[e->pnum] = e;
 		if (schedule_erase(ubi, e, aeb->vol_id, aeb->lnum, 0)) {
 			kmem_cache_free(ubi_wl_entry_slab, e);
 			goto out_free;
 		}
+
+		found_pebs++;
 	}
 
+	ubi->free_count = 0;
 	list_for_each_entry(aeb, &ai->free, u.list) {
 		cond_resched();
 
@@ -1454,8 +1917,14 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 		e->pnum = aeb->pnum;
 		e->ec = aeb->ec;
 		ubi_assert(e->ec >= 0);
+		ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
+
 		ubi->lookuptbl[e->pnum] = e;
+
+		found_pebs++;
 	}
 
 	ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) {
@@ -1469,6 +1938,7 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 			e->pnum = aeb->pnum;
 			e->ec = aeb->ec;
 			ubi->lookuptbl[e->pnum] = e;
+
 			if (!aeb->scrub) {
 				dbg_wl("add PEB %d EC %d to the used tree",
 				       e->pnum, e->ec);
@@ -1478,22 +1948,38 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 				       e->pnum, e->ec);
 				wl_tree_add(e, &ubi->scrub);
 			}
+
+			found_pebs++;
 		}
 	}
 
-	if (ubi->avail_pebs < WL_RESERVED_PEBS) {
+	dbg_wl("found %i PEBs", found_pebs);
+
+	if (ubi->fm)
+		ubi_assert(ubi->good_peb_count == \
+			   found_pebs + ubi->fm->used_blocks);
+	else
+		ubi_assert(ubi->good_peb_count == found_pebs);
+
+	reserved_pebs = WL_RESERVED_PEBS;
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* Reserve enough LEBs to store two fastmaps. */
+	reserved_pebs += (ubi->fm_size / ubi->leb_size) * 2;
+#endif
+
+	if (ubi->avail_pebs < reserved_pebs) {
 		ubi_err("no enough physical eraseblocks (%d, need %d)",
-			ubi->avail_pebs, WL_RESERVED_PEBS);
+			ubi->avail_pebs, reserved_pebs);
 		if (ubi->corr_peb_count)
 			ubi_err("%d PEBs are corrupted and not used",
 				ubi->corr_peb_count);
 		goto out_free;
 	}
-	ubi->avail_pebs -= WL_RESERVED_PEBS;
-	ubi->rsvd_pebs += WL_RESERVED_PEBS;
+	ubi->avail_pebs -= reserved_pebs;
+	ubi->rsvd_pebs += reserved_pebs;
 
 	/* Schedule wear-leveling if needed */
-	err = ensure_wear_leveling(ubi);
+	err = ensure_wear_leveling(ubi, 0);
 	if (err)
 		goto out_free;
 
@@ -1572,7 +2058,7 @@ static int self_check_ec(struct ubi_device *ubi, int pnum, int ec)
 	}
 
 	read_ec = be64_to_cpu(ec_hdr->ec);
-	if (ec != read_ec) {
+	if (ec != read_ec && read_ec - ec > 1) {
 		ubi_err("self-check failed for PEB %d", pnum);
 		ubi_err("read EC is %lld, should be %d", read_ec, ec);
 		dump_stack();
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:29 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:29 +0200
Subject: [PATCH 07/10] UBI: Add fastmap stuff to attach.c
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-8-git-send-email-richard@nod.at>

- Export compare_lebs() as fastmap needs this function.
- Implement fastmap scan logic.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/attach.c |  387 +++++++++++++++++++++++++++++++---------------
 1 files changed, 259 insertions(+), 128 deletions(-)

diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c
index da13215..8dfc436 100644
--- a/drivers/mtd/ubi/attach.c
+++ b/drivers/mtd/ubi/attach.c
@@ -300,7 +300,7 @@ static struct ubi_ainf_volume *add_volume(struct ubi_attach_info *ai,
 }
 
 /**
- * compare_lebs - find out which logical eraseblock is newer.
+ * ubi_compare_lebs - find out which logical eraseblock is newer.
  * @ubi: UBI device description object
  * @aeb: first logical eraseblock to compare
  * @pnum: physical eraseblock number of the second logical eraseblock to
@@ -319,7 +319,7 @@ static struct ubi_ainf_volume *add_volume(struct ubi_attach_info *ai,
  *     o bit 2 is cleared: the older LEB is not corrupted;
  *     o bit 2 is set: the older LEB is corrupted.
  */
-static int compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
+int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
 			int pnum, const struct ubi_vid_hdr *vid_hdr)
 {
 	void *buf;
@@ -337,7 +337,7 @@ static int compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
 		 * support these images anymore. Well, those images still work,
 		 * but only if no unclean reboots happened.
 		 */
-		ubi_err("unsupported on-flash UBI format\n");
+		ubi_err("unsupported on-flash UBI format");
 		return -EINVAL;
 	}
 
@@ -507,7 +507,7 @@ int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		 * sequence numbers. We still can attach these images, unless
 		 * there is a need to distinguish between old and new
 		 * eraseblocks, in which case we'll refuse the image in
-		 * 'compare_lebs()'. In other words, we attach old clean
+		 * 'ubi_compare_lebs()'. In other words, we attach old clean
 		 * images, but refuse attaching old images with duplicated
 		 * logical eraseblocks because there was an unclean reboot.
 		 */
@@ -523,7 +523,7 @@ int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		 * Now we have to drop the older one and preserve the newer
 		 * one.
 		 */
-		cmp_res = compare_lebs(ubi, aeb, pnum, vid_hdr);
+		cmp_res = ubi_compare_lebs(ubi, aeb, pnum, vid_hdr);
 		if (cmp_res < 0)
 			return cmp_res;
 
@@ -748,7 +748,7 @@ struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi,
 /**
  * check_corruption - check the data area of PEB.
  * @ubi: UBI device description object
- * @vid_hrd: the (corrupted) VID header of this PEB
+ * @vid_hdr: the (corrupted) VID header of this PEB
  * @pnum: the physical eraseblock number to check
  *
  * This is a helper function which is used to distinguish between VID header
@@ -810,6 +810,8 @@ out_unlock:
  * @ubi: UBI device description object
  * @ai: attaching information
  * @pnum: the physical eraseblock number
+ * @vid: The volume ID of the found volume will be stored in this pointer
+ * @sqnum: The sqnum of the found volume will be stored in this pointer
  *
  * This function reads UBI headers of PEB @pnum, checks them, and adds
  * information about this PEB to the corresponding list or RB-tree in the
@@ -817,10 +819,10 @@ out_unlock:
  * successfully handled and a negative error code in case of failure.
  */
 static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai,
-		    int pnum)
+		    int pnum, int *vid, unsigned long long *sqnum)
 {
 	long long uninitialized_var(ec);
-	int err, bitflips = 0, vol_id, ec_err = 0;
+	int err, bitflips = 0, vol_id = -1, ec_err = 0;
 
 	dbg_bld("scan PEB %d", pnum);
 
@@ -991,14 +993,22 @@ static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai,
 	}
 
 	vol_id = be32_to_cpu(vidh->vol_id);
+	if (vid)
+		*vid = vol_id;
+	if (sqnum)
+		*sqnum = be64_to_cpu(vidh->sqnum);
 	if (vol_id > UBI_MAX_VOLUMES && vol_id != UBI_LAYOUT_VOLUME_ID) {
 		int lnum = be32_to_cpu(vidh->lnum);
 
 		/* Unsupported internal volume */
 		switch (vidh->compat) {
 		case UBI_COMPAT_DELETE:
-			ubi_msg("\"delete\" compatible internal volume %d:%d found, will remove it",
-				vol_id, lnum);
+			if (vol_id != UBI_FM_SB_VOLUME_ID
+			    && vol_id != UBI_FM_DATA_VOLUME_ID) {
+				ubi_msg("\"delete\" compatible internal volume"
+					" %d:%d found, will remove it",
+					vol_id, lnum);
+			}
 			err = add_to_list(ai, pnum, vol_id, lnum,
 					  ec, 1, &ai->erase);
 			if (err)
@@ -1121,51 +1131,126 @@ static int late_analysis(struct ubi_device *ubi, struct ubi_attach_info *ai)
 }
 
 /**
+ * destroy_av - free volume attaching information.
+ * @av: volume attaching information
+ * @ai: attaching information
+ *
+ * This function destroys the volume attaching information.
+ */
+static void destroy_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av)
+{
+	struct ubi_ainf_peb *aeb;
+	struct rb_node *this = av->root.rb_node;
+
+	while (this) {
+		if (this->rb_left)
+			this = this->rb_left;
+		else if (this->rb_right)
+			this = this->rb_right;
+		else {
+			aeb = rb_entry(this, struct ubi_ainf_peb, u.rb);
+			this = rb_parent(this);
+			if (this) {
+				if (this->rb_left == &aeb->u.rb)
+					this->rb_left = NULL;
+				else
+					this->rb_right = NULL;
+			}
+
+			kmem_cache_free(ai->aeb_slab_cache, aeb);
+		}
+	}
+	kfree(av);
+}
+
+/**
+ * destroy_ai - destroy attaching information.
+ * @ai: attaching information
+ */
+static void destroy_ai(struct ubi_attach_info *ai)
+{
+	struct ubi_ainf_peb *aeb, *aeb_tmp;
+	struct ubi_ainf_volume *av;
+	struct rb_node *rb;
+
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->alien, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->erase, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->corr, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->free, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+
+	/* Destroy the volume RB-tree */
+	rb = ai->volumes.rb_node;
+	while (rb) {
+		if (rb->rb_left)
+			rb = rb->rb_left;
+		else if (rb->rb_right)
+			rb = rb->rb_right;
+		else {
+			av = rb_entry(rb, struct ubi_ainf_volume, rb);
+
+			rb = rb_parent(rb);
+			if (rb) {
+				if (rb->rb_left == &av->rb)
+					rb->rb_left = NULL;
+				else
+					rb->rb_right = NULL;
+			}
+
+			destroy_av(ai, av);
+		}
+	}
+
+	if (ai->aeb_slab_cache)
+		kmem_cache_destroy(ai->aeb_slab_cache);
+
+	kfree(ai);
+}
+
+/**
  * scan_all - scan entire MTD device.
  * @ubi: UBI device description object
+ * @ai: attach info object
+ * @start: start scanning at this PEB
  *
  * This function does full scanning of an MTD device and returns complete
  * information about it in form of a "struct ubi_attach_info" object. In case
  * of failure, an error code is returned.
  */
-static struct ubi_attach_info *scan_all(struct ubi_device *ubi)
+static int scan_all(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		    int start)
 {
 	int err, pnum;
 	struct rb_node *rb1, *rb2;
 	struct ubi_ainf_volume *av;
 	struct ubi_ainf_peb *aeb;
-	struct ubi_attach_info *ai;
-
-	ai = kzalloc(sizeof(struct ubi_attach_info), GFP_KERNEL);
-	if (!ai)
-		return ERR_PTR(-ENOMEM);
-
-	INIT_LIST_HEAD(&ai->corr);
-	INIT_LIST_HEAD(&ai->free);
-	INIT_LIST_HEAD(&ai->erase);
-	INIT_LIST_HEAD(&ai->alien);
-	ai->volumes = RB_ROOT;
 
 	err = -ENOMEM;
-	ai->aeb_slab_cache = kmem_cache_create("ubi_aeb_slab_cache",
-					       sizeof(struct ubi_ainf_peb),
-					       0, 0, NULL);
-	if (!ai->aeb_slab_cache)
-		goto out_ai;
 
 	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
 	if (!ech)
-		goto out_ai;
+		return err;
 
 	vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
 	if (!vidh)
 		goto out_ech;
 
-	for (pnum = 0; pnum < ubi->peb_count; pnum++) {
+	for (pnum = start; pnum < ubi->peb_count; pnum++) {
 		cond_resched();
 
 		dbg_gen("process PEB %d", pnum);
-		err = scan_peb(ubi, ai, pnum);
+		err = scan_peb(ubi, ai, pnum, NULL, NULL);
 		if (err < 0)
 			goto out_vidh;
 	}
@@ -1210,32 +1295,144 @@ static struct ubi_attach_info *scan_all(struct ubi_device *ubi)
 	ubi_free_vid_hdr(ubi, vidh);
 	kfree(ech);
 
-	return ai;
+	return 0;
 
 out_vidh:
 	ubi_free_vid_hdr(ubi, vidh);
 out_ech:
 	kfree(ech);
-out_ai:
-	ubi_destroy_ai(ai);
-	return ERR_PTR(err);
+	return err;
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+
+/**
+ * scan_fastmap - try to find a fastmap and attach from it.
+ * @ubi: UBI device description object
+ * @ai: attach info object
+ *
+ * Returns 0 on success, negative return values indicate an internal
+ * error.
+ * UBI_NO_FASTMAP denotes that no fastmap was found.
+ * UBI_BAD_FASTMAP denotes that the found fastmap was invalid.
+ */
+static int scan_fast(struct ubi_device *ubi, struct ubi_attach_info *ai)
+{
+	int err, pnum, fm_anchor = -1;
+	unsigned long long max_sqnum = 0;
+
+	err = -ENOMEM;
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech)
+		goto out;
+
+	vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vidh)
+		goto out_ech;
+
+	for (pnum = 0; pnum < UBI_FM_MAX_START; pnum++) {
+		int vol_id = -1;
+		unsigned long long sqnum = -1;
+		cond_resched();
+
+		dbg_gen("process PEB %d", pnum);
+		err = scan_peb(ubi, ai, pnum, &vol_id, &sqnum);
+		if (err < 0)
+			goto out_vidh;
+
+		if (vol_id == UBI_FM_SB_VOLUME_ID && sqnum > max_sqnum) {
+			max_sqnum = sqnum;
+			fm_anchor = pnum;
+		}
+	}
+
+	ubi_free_vid_hdr(ubi, vidh);
+	kfree(ech);
+
+	if (fm_anchor < 0)
+		return UBI_NO_FASTMAP;
+
+	return ubi_scan_fastmap(ubi, ai, fm_anchor);
+
+out_vidh:
+	ubi_free_vid_hdr(ubi, vidh);
+out_ech:
+	kfree(ech);
+out:
+	return err;
+}
+
+#endif
+
+static struct ubi_attach_info *alloc_ai(const char *slab_name)
+{
+	struct ubi_attach_info *ai;
+
+	ai = kzalloc(sizeof(struct ubi_attach_info), GFP_KERNEL);
+	if (!ai)
+		return ai;
+
+	INIT_LIST_HEAD(&ai->corr);
+	INIT_LIST_HEAD(&ai->free);
+	INIT_LIST_HEAD(&ai->erase);
+	INIT_LIST_HEAD(&ai->alien);
+	ai->volumes = RB_ROOT;
+	ai->aeb_slab_cache = kmem_cache_create(slab_name,
+					       sizeof(struct ubi_ainf_peb),
+					       0, 0, NULL);
+	if (!ai->aeb_slab_cache) {
+		kfree(ai);
+		ai = NULL;
+	}
+
+	return ai;
 }
 
 /**
  * ubi_attach - attach an MTD device.
  * @ubi: UBI device descriptor
+ * @force_scan: if set to non-zero attach by scanning
  *
  * This function returns zero in case of success and a negative error code in
  * case of failure.
  */
-int ubi_attach(struct ubi_device *ubi)
+int ubi_attach(struct ubi_device *ubi, int force_scan)
 {
 	int err;
 	struct ubi_attach_info *ai;
 
-	ai = scan_all(ubi);
-	if (IS_ERR(ai))
-		return PTR_ERR(ai);
+	ai = alloc_ai("ubi_aeb_slab_cache");
+	if (!ai)
+		return -ENOMEM;
+
+	/* On small flash devices we disable fastmap in any case. */
+	if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {
+		ubi->fm_disabled = 1;
+		force_scan = 1;
+	}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	if (force_scan)
+		err = scan_all(ubi, ai, 0);
+	else {
+		err = scan_fast(ubi, ai);
+		if (err > 0) {
+			if (err != UBI_NO_FASTMAP) {
+				destroy_ai(ai);
+				ai = alloc_ai("ubi_aeb_slab_cache2");
+				if (!ai)
+					return -ENOMEM;
+			}
+
+			err = scan_all(ubi, ai, UBI_FM_MAX_START);
+		}
+	}
+#else
+	err = scan_all(ubi, ai, 0);
+#endif
+	if (err)
+		goto out_ai;
 
 	ubi->bad_peb_count = ai->bad_peb_count;
 	ubi->good_peb_count = ubi->peb_count - ubi->bad_peb_count;
@@ -1256,7 +1453,29 @@ int ubi_attach(struct ubi_device *ubi)
 	if (err)
 		goto out_wl;
 
-	ubi_destroy_ai(ai);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	if (ubi->fm && ubi->dbg->chk_gen) {
+		struct ubi_attach_info *scan_ai;
+
+		scan_ai = alloc_ai("ubi_ckh_aeb_slab_cache");
+		if (!scan_ai)
+			goto out_wl;
+
+		err = scan_all(ubi, scan_ai, 0);
+		if (err) {
+			destroy_ai(scan_ai);
+			goto out_wl;
+		}
+
+		err = self_check_eba(ubi, ai, scan_ai);
+		destroy_ai(scan_ai);
+
+		if (err)
+			goto out_wl;
+	}
+#endif
+
+	destroy_ai(ai);
 	return 0;
 
 out_wl:
@@ -1265,99 +1484,11 @@ out_vtbl:
 	ubi_free_internal_volumes(ubi);
 	vfree(ubi->vtbl);
 out_ai:
-	ubi_destroy_ai(ai);
+	destroy_ai(ai);
 	return err;
 }
 
 /**
- * destroy_av - free volume attaching information.
- * @av: volume attaching information
- * @ai: attaching information
- *
- * This function destroys the volume attaching information.
- */
-static void destroy_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av)
-{
-	struct ubi_ainf_peb *aeb;
-	struct rb_node *this = av->root.rb_node;
-
-	while (this) {
-		if (this->rb_left)
-			this = this->rb_left;
-		else if (this->rb_right)
-			this = this->rb_right;
-		else {
-			aeb = rb_entry(this, struct ubi_ainf_peb, u.rb);
-			this = rb_parent(this);
-			if (this) {
-				if (this->rb_left == &aeb->u.rb)
-					this->rb_left = NULL;
-				else
-					this->rb_right = NULL;
-			}
-
-			kmem_cache_free(ai->aeb_slab_cache, aeb);
-		}
-	}
-	kfree(av);
-}
-
-/**
- * ubi_destroy_ai - destroy attaching information.
- * @ai: attaching information
- */
-void ubi_destroy_ai(struct ubi_attach_info *ai)
-{
-	struct ubi_ainf_peb *aeb, *aeb_tmp;
-	struct ubi_ainf_volume *av;
-	struct rb_node *rb;
-
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->alien, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->erase, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->corr, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->free, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-
-	/* Destroy the volume RB-tree */
-	rb = ai->volumes.rb_node;
-	while (rb) {
-		if (rb->rb_left)
-			rb = rb->rb_left;
-		else if (rb->rb_right)
-			rb = rb->rb_right;
-		else {
-			av = rb_entry(rb, struct ubi_ainf_volume, rb);
-
-			rb = rb_parent(rb);
-			if (rb) {
-				if (rb->rb_left == &av->rb)
-					rb->rb_left = NULL;
-				else
-					rb->rb_right = NULL;
-			}
-
-			destroy_av(ai, av);
-		}
-	}
-
-	if (ai->aeb_slab_cache)
-		kmem_cache_destroy(ai->aeb_slab_cache);
-
-	kfree(ai);
-}
-
-/**
  * self_check_ai - check the attaching information.
  * @ubi: UBI device description object
  * @ai: attaching information
-- 
1.7.6.5



From richard at nod.at  Mon Sep 24 14:31:31 2012
From: richard at nod.at (Richard Weinberger)
Date: Mon, 24 Sep 2012 20:31:31 +0200
Subject: [PATCH 09/10] UBI: Add fastmap core
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348511492-91606-10-git-send-email-richard@nod.at>

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/fastmap.c | 1560 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 1560 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/ubi/fastmap.c

diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c
new file mode 100644
index 0000000..be73a1d
--- /dev/null
+++ b/drivers/mtd/ubi/fastmap.c
@@ -0,0 +1,1560 @@
+/*
+ * Copyright (c) 2012 Linutronix GmbH
+ * Author: Richard Weinberger <richard at nod.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ */
+
+#include <linux/crc32.h>
+#include "ubi.h"
+
+/**
+ * ubi_calc_fm_size - calculates the fastmap size in bytes for an UBI device.
+ * @ubi: UBI device description object
+ */
+size_t ubi_calc_fm_size(struct ubi_device *ubi)
+{
+	size_t size;
+
+	size = sizeof(struct ubi_fm_hdr) + \
+		sizeof(struct ubi_fm_scan_pool) + \
+		sizeof(struct ubi_fm_scan_pool) + \
+		(ubi->peb_count * sizeof(struct ubi_fm_ec)) + \
+		(sizeof(struct ubi_fm_eba) + \
+		(ubi->peb_count * sizeof(__be32))) + \
+		sizeof(struct ubi_fm_volhdr) * UBI_MAX_VOLUMES;
+	return roundup(size, ubi->leb_size);
+}
+
+
+/**
+ * new_fm_vhdr - allocate a new volume header for fastmap usage.
+ * @ubi: UBI device description object
+ * @vol_id: the VID of the new header
+ *
+ * Returns a new struct ubi_vid_hdr on success.
+ * NULL indicates out of memory.
+ */
+static struct ubi_vid_hdr *new_fm_vhdr(struct ubi_device *ubi, int vol_id)
+{
+	struct ubi_vid_hdr *new;
+
+	new = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!new)
+		goto out;
+
+	new->vol_type = UBI_VID_DYNAMIC;
+	new->vol_id = cpu_to_be32(vol_id);
+
+	/* UBI implementations without fastmap support have to delete the
+	 * fastmap.
+	 */
+	new->compat = UBI_COMPAT_DELETE;
+
+out:
+	return new;
+}
+
+/**
+ * add_aeb - create and add a attach erase block to a given list.
+ * @ai: UBI attach info object
+ * @list: the target list
+ * @pnum: PEB number of the new attach erase block
+ * @ec: erease counter of the new LEB
+ * @scrub: scrub this PEB after attaching
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int add_aeb(struct ubi_attach_info *ai, struct list_head *list,
+		   int pnum, int ec, int scrub)
+{
+	struct ubi_ainf_peb *aeb;
+
+	aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL);
+	if (!aeb)
+		return -ENOMEM;
+
+	aeb->pnum = pnum;
+	aeb->ec = ec;
+	aeb->lnum = -1;
+	aeb->scrub = scrub;
+	aeb->copy_flag = aeb->sqnum = 0;
+
+	ai->ec_sum += aeb->ec;
+	ai->ec_count++;
+
+	if (ai->max_ec < aeb->ec)
+		ai->max_ec = aeb->ec;
+
+	if (ai->min_ec > aeb->ec)
+		ai->min_ec = aeb->ec;
+
+	list_add_tail(&aeb->u.list, list);
+
+	return 0;
+}
+
+/**
+ * add_vol - create and add a new volume to ubi_attach_info.
+ * @ai: ubi_attach_info object
+ * @vol_id: VID of the new volume
+ * @used_ebs: number of used EBS
+ * @data_pad: data padding value of the new volume
+ * @vol_type: volume type
+ * @last_eb_bytes: number of bytes in the last LEB
+ *
+ * Returns the new struct ubi_ainf_volume on success.
+ * NULL indicates an error.
+ */
+static struct ubi_ainf_volume *add_vol(struct ubi_attach_info *ai, int vol_id,
+				       int used_ebs, int data_pad, u8 vol_type,
+				       int last_eb_bytes)
+{
+	struct ubi_ainf_volume *av;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+
+	while (*p) {
+		parent = *p;
+		av = rb_entry(parent, struct ubi_ainf_volume, rb);
+
+		if (vol_id > av->vol_id)
+			p = &(*p)->rb_left;
+		else if (vol_id > av->vol_id)
+			p = &(*p)->rb_right;
+	}
+
+	av = kmalloc(sizeof(struct ubi_ainf_volume), GFP_KERNEL);
+	if (!av)
+		goto out;
+
+	av->highest_lnum = av->leb_count = 0;
+	av->vol_id = vol_id;
+	av->used_ebs = used_ebs;
+	av->data_pad = data_pad;
+	av->last_data_size = last_eb_bytes;
+	av->compat = 0;
+	av->vol_type = vol_type;
+	av->root = RB_ROOT;
+
+	dbg_bld("found volume (ID %i)", vol_id);
+
+	rb_link_node(&av->rb, parent, p);
+	rb_insert_color(&av->rb, &ai->volumes);
+
+out:
+	return av;
+}
+
+/**
+ * assign_aeb_to_av - assigns a SEB to a given ainf_volume and removes it
+ * from it's original list.
+ * @ai: ubi_attach_info object
+ * @aeb: the to be assigned SEB
+ * @av: target scan volume
+ */
+static void assign_aeb_to_av(struct ubi_attach_info *ai,
+			     struct ubi_ainf_peb *aeb,
+			     struct ubi_ainf_volume *av)
+{
+	struct ubi_ainf_peb *tmp_aeb;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+
+	p = &av->root.rb_node;
+	while (*p) {
+		parent = *p;
+
+		tmp_aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb);
+		if (aeb->lnum != tmp_aeb->lnum) {
+			if (aeb->lnum < tmp_aeb->lnum)
+				p = &(*p)->rb_left;
+			else
+				p = &(*p)->rb_right;
+
+			continue;
+		} else
+			break;
+	}
+
+	list_del(&aeb->u.list);
+	av->leb_count++;
+
+	rb_link_node(&aeb->u.rb, parent, p);
+	rb_insert_color(&aeb->u.rb, &av->root);
+}
+
+/**
+ * update_vol - inserts or updates a LEB which was found a pool.
+ * @ubi: the UBI device object
+ * @ai: attach info object
+ * @av: the volume this LEB belongs to
+ * @new_vh: the volume header derived from new_aeb
+ * @new_aeb: the AEB to be examined
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int update_vol(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		      struct ubi_ainf_volume *av, struct ubi_vid_hdr *new_vh,
+		      struct ubi_ainf_peb *new_aeb)
+{
+	struct rb_node **p = &av->root.rb_node, *parent = NULL;
+	struct ubi_ainf_peb *aeb, *victim;
+	int cmp_res;
+
+	while (*p) {
+		parent = *p;
+		aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb);
+
+		if (be32_to_cpu(new_vh->lnum) != aeb->lnum) {
+			if (be32_to_cpu(new_vh->lnum) < aeb->lnum)
+				p = &(*p)->rb_left;
+			else
+				p = &(*p)->rb_right;
+
+			continue;
+		}
+
+		/* This case can happen if the fastmap gets written
+		 * because of a volume change (creation, deletion, ..).
+		 * Then a PEB can be within the persistent EBA and the pool.
+		 */
+		if (aeb->pnum == new_aeb->pnum) {
+			ubi_assert(aeb->lnum == new_aeb->lnum);
+			kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+			return 0;
+		}
+
+		cmp_res = ubi_compare_lebs(ubi, aeb, new_aeb->pnum, new_vh);
+		if (cmp_res < 0)
+			return cmp_res;
+
+		/* new_aeb is newer */
+		if (cmp_res & 1) {
+			victim = kmem_cache_alloc(ai->aeb_slab_cache,
+				GFP_KERNEL);
+			if (!victim)
+				return -ENOMEM;
+
+			victim->ec = aeb->ec;
+			victim->pnum = aeb->pnum;
+			list_add_tail(&victim->u.list, &ai->erase);
+
+			if (av->highest_lnum == be32_to_cpu(new_vh->lnum))
+				av->last_data_size = \
+					be32_to_cpu(new_vh->data_size);
+
+			dbg_bld("vol %i: AEB %i's PEB %i is the newer",
+				av->vol_id, aeb->lnum, new_aeb->pnum);
+
+			aeb->ec = new_aeb->ec;
+			aeb->pnum = new_aeb->pnum;
+			aeb->copy_flag = new_vh->copy_flag;
+			aeb->scrub = new_aeb->scrub;
+			kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+		/* new_aeb is older */
+		} else {
+			dbg_bld("vol %i: AEB %i's PEB %i is old, dropping it",
+				av->vol_id, aeb->lnum, new_aeb->pnum);
+			list_add_tail(&new_aeb->u.list, &ai->erase);
+		}
+
+		return 0;
+	}
+	/* This LEB is new, let's add it to the volume */
+
+	if (av->highest_lnum <= be32_to_cpu(new_vh->lnum)) {
+		av->highest_lnum = be32_to_cpu(new_vh->lnum);
+		av->last_data_size = be32_to_cpu(new_vh->data_size);
+	}
+
+	if (av->vol_type == UBI_STATIC_VOLUME)
+		av->used_ebs = be32_to_cpu(new_vh->used_ebs);
+
+	av->leb_count++;
+
+	rb_link_node(&new_aeb->u.rb, parent, p);
+	rb_insert_color(&new_aeb->u.rb, &av->root);
+
+	return 0;
+}
+
+/**
+ * process_pool_aeb - we found a non-empty PEB in a pool.
+ * @ubi: UBI device object
+ * @ai: attach info object
+ * @new_vh: the volume header derived from new_aeb
+ * @new_aeb: the AEB to be examined
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int process_pool_aeb(struct ubi_device *ubi, struct ubi_attach_info *ai,
+			    struct ubi_vid_hdr *new_vh,
+			    struct ubi_ainf_peb *new_aeb)
+{
+	struct ubi_ainf_volume *av, *tmp_av = NULL;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+	int found = 0;
+
+	if (be32_to_cpu(new_vh->vol_id) == UBI_FM_SB_VOLUME_ID ||
+		be32_to_cpu(new_vh->vol_id) == UBI_FM_DATA_VOLUME_ID) {
+		kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+		return 0;
+	}
+
+	/* Find the volume this SEB belongs to */
+	while (*p) {
+		parent = *p;
+		tmp_av = rb_entry(parent, struct ubi_ainf_volume, rb);
+
+		if (be32_to_cpu(new_vh->vol_id) > tmp_av->vol_id)
+			p = &(*p)->rb_left;
+		else if (be32_to_cpu(new_vh->vol_id) < tmp_av->vol_id)
+			p = &(*p)->rb_right;
+		else {
+			found = 1;
+			break;
+		}
+	}
+
+	if (found)
+		av = tmp_av;
+	else {
+		ubi_err("orphaned volume in fastmap pool!");
+		return UBI_BAD_FASTMAP;
+	}
+
+	ubi_assert(be32_to_cpu(new_vh->vol_id) == av->vol_id);
+
+	return update_vol(ubi, ai, av, new_vh, new_aeb);
+}
+
+/**
+ * unmap_peb - unmap a PEB.
+ * If fastmap detects a free PEB in the pool it has to check whether
+ * this PEB has been unmapped after writing the fastmap.
+ *
+ * @ai: UBI attach info object
+ * @pnum: The PEB to be unmapped
+ */
+static void unmap_peb(struct ubi_attach_info *ai, int pnum)
+{
+	struct ubi_ainf_volume *av;
+	struct rb_node *node, *node2;
+	struct ubi_ainf_peb *aeb;
+
+	for (node = rb_first(&ai->volumes); node; node = rb_next(node)) {
+		av = rb_entry(node, struct ubi_ainf_volume, rb);
+
+		for (node2 = rb_first(&av->root); node2;
+		     node2 = rb_next(node2)) {
+			aeb = rb_entry(node2, struct ubi_ainf_peb, u.rb);
+			if (aeb->pnum == pnum) {
+				rb_erase(&aeb->u.rb, &av->root);
+				kmem_cache_free(ai->aeb_slab_cache, aeb);
+				return;
+			}
+		}
+	}
+}
+
+/**
+ * scan_pool - scans a pool for changed (no longer empty PEBs).
+ * @ubi: UBI device object
+ * @ai: attach info object
+ * @pebs: an array of all PEB numbers in the to be scanned pool
+ * @pool_size: size of the pool (number of entries in @pebs)
+ * @max_sqnum: pointer to the maximal sequence number
+ * @eba_orphans: list of PEBs which need to be scanned
+ * @free: list of PEBs which are most likely free (and go into @ai->free)
+ *
+ * Returns 0 on success, if the pool is unusable UBI_BAD_FASTMAP is returned.
+ * < 0 indicates an internal error.
+ */
+static int scan_pool(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int *pebs, int pool_size, unsigned long long *max_sqnum,
+		     struct list_head *eba_orphans, struct list_head *free)
+{
+	struct ubi_vid_hdr *vh;
+	struct ubi_ec_hdr *ech;
+	struct ubi_ainf_peb *new_aeb, *tmp_aeb;
+	int i, pnum, err, found_orphan, ret = 0;
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech)
+		return -ENOMEM;
+
+	vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vh) {
+		kfree(ech);
+		return -ENOMEM;
+	}
+
+	dbg_bld("scanning fastmap pool: size = %i", pool_size);
+
+	/*
+	 * Now scan all PEBs in the pool to find changes which have been made
+	 * after the creation of the fastmap
+	 */
+	for (i = 0; i < pool_size; i++) {
+		int scrub = 0;
+
+		pnum = be32_to_cpu(pebs[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ubi_err("bad PEB in fastmap pool!");
+			ret = UBI_BAD_FASTMAP;
+			goto out;
+		}
+
+		err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+		if (err && err != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read EC header! PEB:%i err:%i",
+				pnum, err);
+			ret = err > 0 ? UBI_BAD_FASTMAP : err;
+			goto out;
+		} else if (ret == UBI_IO_BITFLIPS)
+			scrub = 1;
+
+		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+			ubi_err("bad image seq: 0x%x, expected: 0x%x",
+				be32_to_cpu(ech->image_seq), ubi->image_seq);
+			err = UBI_BAD_FASTMAP;
+			goto out;
+		}
+
+		err = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+		if (err == UBI_IO_FF || err == UBI_IO_FF_BITFLIPS) {
+			unsigned long long ec = be64_to_cpu(ech->ec);
+			unmap_peb(ai, pnum);
+			dbg_bld("Adding PEB to free: %i", pnum);
+			if (err == UBI_IO_FF_BITFLIPS)
+				add_aeb(ai, free, pnum, ec, 1);
+			else
+				add_aeb(ai, free, pnum, ec, 0);
+			continue;
+		} else if (err == 0 || err == UBI_IO_BITFLIPS) {
+			dbg_bld("Found non empty PEB:%i in pool", pnum);
+
+			if (err == UBI_IO_BITFLIPS)
+				scrub = 1;
+
+			found_orphan = 0;
+			list_for_each_entry(tmp_aeb, eba_orphans, u.list) {
+				if (tmp_aeb->pnum == pnum) {
+					found_orphan = 1;
+					break;
+				}
+			}
+			if (found_orphan) {
+				kmem_cache_free(ai->aeb_slab_cache, tmp_aeb);
+				list_del(&tmp_aeb->u.list);
+			}
+
+			new_aeb = kmem_cache_alloc(ai->aeb_slab_cache,
+						   GFP_KERNEL);
+			if (!new_aeb) {
+				ret = -ENOMEM;
+				goto out;
+			}
+
+			new_aeb->ec = be64_to_cpu(ech->ec);
+			new_aeb->pnum = pnum;
+			new_aeb->lnum = be32_to_cpu(vh->lnum);
+			new_aeb->sqnum = be64_to_cpu(vh->sqnum);
+			new_aeb->copy_flag = vh->copy_flag;
+			new_aeb->scrub = scrub;
+
+			if (*max_sqnum < new_aeb->sqnum)
+				*max_sqnum = new_aeb->sqnum;
+
+			err = process_pool_aeb(ubi, ai, vh, new_aeb);
+			if (err) {
+				ret = err > 0 ? UBI_BAD_FASTMAP : err;
+				goto out;
+			}
+		} else {
+			/* We are paranoid and fall back to scanning mode */
+			ubi_err("fastmap pool PEBs contains damaged PEBs!");
+			ret = err > 0 ? UBI_BAD_FASTMAP : err;
+			goto out;
+		}
+
+	}
+
+out:
+	ubi_free_vid_hdr(ubi, vh);
+	kfree(ech);
+	return ret;
+}
+
+/**
+ * count_fastmap_pebs - Counts the PEBs found by fastmap.
+ * @ai: The UBI attach info object
+ */
+static int count_fastmap_pebs(struct ubi_attach_info *ai)
+{
+	struct ubi_ainf_peb *aeb;
+	struct ubi_ainf_volume *av;
+	struct rb_node *rb1, *rb2;
+	int n = 0;
+
+	list_for_each_entry(aeb, &ai->erase, u.list)
+		n++;
+
+	list_for_each_entry(aeb, &ai->free, u.list)
+		n++;
+
+	 ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb)
+		ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb)
+			n++;
+
+	return n;
+}
+
+/**
+ * ubi_attach_fastmap - creates ubi_attach_info from a fastmap.
+ * @ubi: UBI device object
+ * @ai: UBI attach info object
+ * @fm: the fastmap to be attached
+ *
+ * Returns 0 on success, UBI_BAD_FASTMAP if the found fastmap was unusable.
+ * < 0 indicates an internal error.
+ */
+static int ubi_attach_fastmap(struct ubi_device *ubi,
+			      struct ubi_attach_info *ai,
+			      struct ubi_fastmap_layout *fm)
+{
+	struct list_head used, eba_orphans, free;
+	struct ubi_ainf_volume *av;
+	struct ubi_ainf_peb *aeb, *tmp_aeb, *_tmp_aeb;
+	struct ubi_ec_hdr *ech;
+	struct ubi_fm_sb *fmsb;
+	struct ubi_fm_hdr *fmhdr;
+	struct ubi_fm_scan_pool *fmpl1, *fmpl2;
+	struct ubi_fm_ec *fmec;
+	struct ubi_fm_volhdr *fmvhdr;
+	struct ubi_fm_eba *fm_eba;
+	int ret, i, j, pool_size, wl_pool_size;
+	size_t fm_pos = 0, fm_size = ubi->fm_size;
+	unsigned long long max_sqnum = 0;
+	void *fm_raw = ubi->fm_buf;
+
+	INIT_LIST_HEAD(&used);
+	INIT_LIST_HEAD(&free);
+	INIT_LIST_HEAD(&eba_orphans);
+	INIT_LIST_HEAD(&ai->corr);
+	INIT_LIST_HEAD(&ai->free);
+	INIT_LIST_HEAD(&ai->erase);
+	INIT_LIST_HEAD(&ai->alien);
+	ai->volumes = RB_ROOT;
+	ai->min_ec = UBI_MAX_ERASECOUNTER;
+
+	ai->aeb_slab_cache = kmem_cache_create("ubi_ainf_peb_slab",
+					       sizeof(struct ubi_ainf_peb),
+					       0, 0, NULL);
+	if (!ai->aeb_slab_cache) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	fmsb = (struct ubi_fm_sb *)(fm_raw);
+	ai->max_sqnum = fmsb->sqnum;
+	fm_pos += sizeof(struct ubi_fm_sb);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	fmhdr = (struct ubi_fm_hdr *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmhdr);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	if (be32_to_cpu(fmhdr->magic) != UBI_FM_HDR_MAGIC) {
+		ubi_err("bad fastmap header magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmhdr->magic), UBI_FM_HDR_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl1);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl1->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl1->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl2);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl2->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl2->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	pool_size = be16_to_cpu(fmpl1->size);
+	wl_pool_size = be16_to_cpu(fmpl2->size);
+	fm->max_pool_size = be16_to_cpu(fmpl1->max_size);
+	fm->max_wl_pool_size = be16_to_cpu(fmpl2->max_size);
+
+	if (pool_size > UBI_FM_MAX_POOL_SIZE || pool_size < 0) {
+		ubi_err("bad pool size: %i", pool_size);
+		goto fail_bad;
+	}
+
+	if (wl_pool_size > UBI_FM_MAX_POOL_SIZE || wl_pool_size < 0) {
+		ubi_err("bad WL pool size: %i", wl_pool_size);
+		goto fail_bad;
+	}
+
+
+	if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_pool_size < 0) {
+		ubi_err("bad maximal pool size: %i", fm->max_pool_size);
+		goto fail_bad;
+	}
+
+	if (fm->max_wl_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_wl_pool_size < 0) {
+		ubi_err("bad maximal WL pool size: %i", fm->max_wl_pool_size);
+		goto fail_bad;
+	}
+
+	/* read EC values from free list */
+	for (i = 0; i < be32_to_cpu(fmhdr->free_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &ai->free, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 0);
+	}
+
+	/* read EC values from used list */
+	for (i = 0; i < be32_to_cpu(fmhdr->used_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &used, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 0);
+	}
+
+	/* read EC values from scrub list */
+	for (i = 0; i < be32_to_cpu(fmhdr->scrub_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &used, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 1);
+	}
+
+	/* read EC values from erase list */
+	for (i = 0; i < be32_to_cpu(fmhdr->erase_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &ai->erase, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 1);
+	}
+
+	ai->mean_ec = div_u64(ai->ec_sum, ai->ec_count);
+	ai->bad_peb_count = be32_to_cpu(fmhdr->bad_peb_count);
+
+	/* Iterate over all volumes and read their EBA table */
+	for (i = 0; i < be32_to_cpu(fmhdr->vol_count); i++) {
+		fmvhdr = (struct ubi_fm_volhdr *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmvhdr);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fmvhdr->magic) != UBI_FM_VHDR_MAGIC) {
+			ubi_err("bad fastmap vol header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fmvhdr->magic), UBI_FM_VHDR_MAGIC);
+			goto fail_bad;
+		}
+
+		av = add_vol(ai, be32_to_cpu(fmvhdr->vol_id),
+			     be32_to_cpu(fmvhdr->used_ebs),
+			     be32_to_cpu(fmvhdr->data_pad),
+			     fmvhdr->vol_type,
+			     be32_to_cpu(fmvhdr->last_eb_bytes));
+
+		if (!av)
+			goto fail_bad;
+
+		ai->vols_found++;
+		if (ai->highest_vol_id < be32_to_cpu(fmvhdr->vol_id))
+			ai->highest_vol_id = be32_to_cpu(fmvhdr->vol_id);
+
+		fm_eba = (struct ubi_fm_eba *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fm_eba);
+		fm_pos += (sizeof(__be32) * be32_to_cpu(fm_eba->reserved_pebs));
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fm_eba->magic) != UBI_FM_EBA_MAGIC) {
+			ubi_err("bad fastmap EBA header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fm_eba->magic), UBI_FM_EBA_MAGIC);
+			goto fail_bad;
+		}
+
+		for (j = 0; j < be32_to_cpu(fm_eba->reserved_pebs); j++) {
+			int pnum = be32_to_cpu(fm_eba->pnum[j]);
+
+			if ((int)be32_to_cpu(fm_eba->pnum[j]) < 0)
+				continue;
+
+			aeb = NULL;
+			list_for_each_entry(tmp_aeb, &used, u.list) {
+				if (tmp_aeb->pnum == pnum)
+					aeb = tmp_aeb;
+			}
+
+			/* This can happen if a PEB is already in an EBA known
+			 * by this fastmap but the PEB itself is not in the used
+			 * list.
+			 * In this case the PEB can be within the fastmap pool
+			 * or while writing the fastmap it was in the protection
+			 * queue.
+			 */
+			if (!aeb) {
+				aeb = kmem_cache_alloc(ai->aeb_slab_cache,
+						       GFP_KERNEL);
+				if (!aeb) {
+					ret = -ENOMEM;
+
+					goto fail;
+				}
+
+				aeb->lnum = j;
+				aeb->pnum = be32_to_cpu(fm_eba->pnum[j]);
+				aeb->ec = -1;
+				aeb->scrub = aeb->copy_flag = aeb->sqnum = 0;
+				list_add_tail(&aeb->u.list, &eba_orphans);
+				continue;
+			}
+
+			aeb->lnum = j;
+
+			if (av->highest_lnum <= aeb->lnum)
+				av->highest_lnum = aeb->lnum;
+
+			assign_aeb_to_av(ai, aeb, av);
+
+			dbg_bld("inserting PEB:%i (LEB %i) to vol %i",
+				aeb->pnum, aeb->lnum, av->vol_id);
+		}
+
+		ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+		if (!ech) {
+			ret = -ENOMEM;
+			goto fail;
+		}
+
+		list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &eba_orphans,
+					 u.list) {
+			int err;
+
+			if (ubi_io_is_bad(ubi, tmp_aeb->pnum)) {
+				ubi_err("bad PEB in fastmap EBA orphan list");
+				ret = UBI_BAD_FASTMAP;
+				kfree(ech);
+				goto fail;
+			}
+
+			err = ubi_io_read_ec_hdr(ubi, tmp_aeb->pnum, ech, 0);
+			if (err && err != UBI_IO_BITFLIPS) {
+				ubi_err("unable to read EC header! PEB:%i " \
+					"err:%i", tmp_aeb->pnum, err);
+				ret = err > 0 ? UBI_BAD_FASTMAP : err;
+				kfree(ech);
+
+				goto fail;
+			} else if (err == UBI_IO_BITFLIPS)
+				tmp_aeb->scrub = 1;
+
+			tmp_aeb->ec = be64_to_cpu(ech->ec);
+			assign_aeb_to_av(ai, tmp_aeb, av);
+		}
+
+		kfree(ech);
+	}
+
+	ret = scan_pool(ubi, ai, fmpl1->pebs, pool_size, &max_sqnum,
+			&eba_orphans, &free);
+	if (ret)
+		goto fail;
+
+	ret = scan_pool(ubi, ai, fmpl2->pebs, wl_pool_size, &max_sqnum,
+			&eba_orphans, &free);
+	if (ret)
+		goto fail;
+
+	if (max_sqnum > ai->max_sqnum)
+		ai->max_sqnum = max_sqnum;
+
+	list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &free, u.list) {
+		list_del(&tmp_aeb->u.list);
+		list_add_tail(&tmp_aeb->u.list, &ai->free);
+	}
+
+	/*
+	 * If fastmap is leaking PEBs (must not happen), raise a
+	 * fat warning and fall back to scanning mode.
+	 * We do this here because in ubi_wl_init() it's too late
+	 * and we cannot fall back to scanning.
+	 */
+	if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count -
+		    ai->bad_peb_count - fm->used_blocks))
+		goto fail_bad;
+
+	return 0;
+
+fail_bad:
+	ret = UBI_BAD_FASTMAP;
+fail:
+	return ret;
+}
+
+/**
+ * ubi_scan_fastmap - scan the fastmap.
+ * @ubi: UBI device object
+ * @ai: UBI attach info to be filled
+ * @fm_anchor: The fastmap starts at this PEB
+ *
+ * Returns 0 on success, UBI_NO_FASTMAP if no fastmap was found,
+ * UBI_BAD_FASTMAP if one was found but is not usable.
+ * < 0 indicates an internal error.
+ */
+int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int fm_anchor)
+{
+	struct ubi_fm_sb *fmsb;
+	struct ubi_vid_hdr *vh;
+	struct ubi_ec_hdr *ech;
+	struct ubi_fastmap_layout *fm;
+	int i, used_blocks, pnum, ret = 0;
+	size_t fm_size;
+	__be32 crc, tmp_crc;
+	unsigned long long sqnum = 0;
+
+	mutex_lock(&ubi->fm_mutex);
+	memset(ubi->fm_buf, 0, ubi->fm_size);
+
+	fmsb = kmalloc(sizeof(*fmsb), GFP_KERNEL);
+	if (!fmsb) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	fm = kzalloc(sizeof(*fm), GFP_KERNEL);
+	if (!fm) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		goto out;
+	}
+
+	ret = ubi_io_read(ubi, fmsb, fm_anchor, ubi->leb_start, sizeof(*fmsb));
+	if (ret && ret != UBI_IO_BITFLIPS) {
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	} else if (ret == UBI_IO_BITFLIPS)
+		fm->to_be_tortured[0] = 1;
+
+	if (be32_to_cpu(fmsb->magic) != UBI_FM_SB_MAGIC) {
+		ubi_err("bad super block magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmsb->magic), UBI_FM_SB_MAGIC);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	if (fmsb->version != UBI_FM_FMT_VERSION) {
+		ubi_err("bad fastmap version: %i, expected: %i",
+			fmsb->version, UBI_FM_FMT_VERSION);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	used_blocks = be32_to_cpu(fmsb->used_blocks);
+	if (used_blocks > UBI_FM_MAX_BLOCKS || used_blocks < 1) {
+		ubi_err("number of fastmap blocks is invalid: %i", used_blocks);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	fm_size = ubi->leb_size * used_blocks;
+	if (fm_size != ubi->fm_size) {
+		ubi_err("bad fastmap size: %zi, expected: %zi", fm_size,
+			ubi->fm_size);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+	}
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vh) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		kfree(fm);
+		kfree(ech);
+		goto out;
+	}
+
+	for (i = 0; i < used_blocks; i++) {
+		pnum = be32_to_cpu(fmsb->block_loc[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ret = UBI_BAD_FASTMAP;
+			kfree(fm);
+			kfree(fmsb);
+			goto free_hdr;
+		}
+
+		ret = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i EC (PEB: %i)",
+				i, pnum);
+			if (ret > 0)
+				ret = UBI_BAD_FASTMAP;
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		} else if (ret == UBI_IO_BITFLIPS)
+			fm->to_be_tortured[i] = 1;
+
+		if (!ubi->image_seq)
+			ubi->image_seq = be32_to_cpu(ech->image_seq);
+
+		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+			ret = UBI_BAD_FASTMAP;
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+
+		ret = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i)",
+				i, pnum);
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+
+		if (i == 0) {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_SB_VOLUME_ID) {
+				ubi_err("bad fastmap anchor vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_SB_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				kfree(fmsb);
+				kfree(fm);
+				goto free_hdr;
+			}
+		} else {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_DATA_VOLUME_ID) {
+				ubi_err("bad fastmap data vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_DATA_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				kfree(fmsb);
+				goto free_hdr;
+			}
+		}
+
+		if (sqnum < be64_to_cpu(vh->sqnum))
+			sqnum = be64_to_cpu(vh->sqnum);
+
+		ret = ubi_io_read(ubi, ubi->fm_buf + (ubi->leb_size * i), pnum,
+				  ubi->leb_start, ubi->leb_size);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i, " \
+				"err: %i)", i, pnum, ret);
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+	}
+
+	kfree(fmsb);
+
+	fmsb = (struct ubi_fm_sb *)(ubi->fm_buf);
+	tmp_crc = be32_to_cpu(fmsb->data_crc);
+	fmsb->data_crc = 0;
+	crc = crc32(UBI_CRC32_INIT, ubi->fm_buf, fm_size);
+	if (crc != tmp_crc) {
+		ubi_err("fastmap data CRC is invalid");
+		ubi_err("CRC should be: 0x%x, calc: 0x%x", tmp_crc, crc);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fm);
+		goto free_hdr;
+	}
+
+	fmsb->sqnum = sqnum;
+
+	fm->used_blocks = used_blocks;
+
+	ret = ubi_attach_fastmap(ubi, ai, fm);
+	if (ret) {
+		if (ret > 0)
+			ret = UBI_BAD_FASTMAP;
+		kfree(fm);
+		goto free_hdr;
+	}
+
+	for (i = 0; i < used_blocks; i++) {
+		struct ubi_wl_entry *e;
+
+		e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL);
+		if (!e) {
+			while (i--)
+				kfree(fm->e[i]);
+
+			kfree(fm);
+			fm = NULL;
+			ret = -ENOMEM;
+			goto free_hdr;
+		}
+
+		e->pnum = be32_to_cpu(fmsb->block_loc[i]);
+		e->ec = be32_to_cpu(fmsb->block_ec[i]);
+		fm->e[i] = e;
+	}
+
+	ubi->fm = fm;
+	ubi->fm_pool.max_size = ubi->fm->max_pool_size;
+	ubi->fm_wl_pool.max_size = ubi->fm->max_wl_pool_size;
+	ubi_msg("attached by fastmap");
+	ubi_msg("fastmap pool size: %d", ubi->fm_pool.max_size);
+	ubi_msg("fastmap WL pool size: %d", ubi->fm_wl_pool.max_size);
+	ubi->fm_disabled = 0;
+
+free_hdr:
+	ubi_free_vid_hdr(ubi, vh);
+	kfree(ech);
+out:
+	mutex_unlock(&ubi->fm_mutex);
+	if (ret == UBI_BAD_FASTMAP)
+		ubi_err("Attach by fastmap failed, doing a full scan!");
+	return ret;
+}
+
+/**
+ * ubi_write_fastmap - writes a fastmap.
+ * @ubi: UBI device object
+ * @new_fm: the to be written fastmap
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int ubi_write_fastmap(struct ubi_device *ubi,
+			     struct ubi_fastmap_layout *new_fm)
+{
+	size_t fm_pos = 0;
+	void *fm_raw;
+	struct ubi_fm_sb *fmsb;
+	struct ubi_fm_hdr *fmh;
+	struct ubi_fm_scan_pool *fmpl1, *fmpl2;
+	struct ubi_fm_ec *fec;
+	struct ubi_fm_volhdr *fvh;
+	struct ubi_fm_eba *feba;
+	struct rb_node *node;
+	struct ubi_wl_entry *wl_e;
+	struct ubi_volume *vol;
+	struct ubi_vid_hdr *avhdr, *dvhdr;
+	struct ubi_work *ubi_wrk;
+	int ret, i, j, free_peb_count, used_peb_count, vol_count;
+	int scrub_peb_count, erase_peb_count;
+
+	fm_raw = ubi->fm_buf;
+	memset(ubi->fm_buf, 0, ubi->fm_size);
+
+	avhdr = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID);
+	if (!avhdr) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	dvhdr = new_fm_vhdr(ubi, UBI_FM_DATA_VOLUME_ID);
+	if (!dvhdr) {
+		ret = -ENOMEM;
+		goto out_kfree;
+	}
+
+	spin_lock(&ubi->volumes_lock);
+	spin_lock(&ubi->wl_lock);
+
+	fmsb = (struct ubi_fm_sb *)fm_raw;
+	fm_pos += sizeof(*fmsb);
+	ubi_assert(fm_pos <= ubi->fm_size);
+
+	fmh = (struct ubi_fm_hdr *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmh);
+	ubi_assert(fm_pos <= ubi->fm_size);
+
+	fmsb->magic = cpu_to_be32(UBI_FM_SB_MAGIC);
+	fmsb->version = UBI_FM_FMT_VERSION;
+	fmsb->used_blocks = cpu_to_be32(new_fm->used_blocks);
+	/* the max sqnum will be filled in while *reading* the fastmap */
+	fmsb->sqnum = 0;
+
+	fmh->magic = cpu_to_be32(UBI_FM_HDR_MAGIC);
+	free_peb_count = 0;
+	used_peb_count = 0;
+	scrub_peb_count = 0;
+	erase_peb_count = 0;
+	vol_count = 0;
+
+	fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl1);
+	fmpl1->magic = cpu_to_be32(UBI_FM_POOL_MAGIC);
+	fmpl1->size = cpu_to_be16(ubi->fm_pool.size);
+	fmpl1->max_size = cpu_to_be16(ubi->fm_pool.max_size);
+
+	for (i = 0; i < ubi->fm_pool.size; i++)
+		fmpl1->pebs[i] = cpu_to_be32(ubi->fm_pool.pebs[i]);
+
+	fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl2);
+	fmpl2->magic = cpu_to_be32(UBI_FM_POOL_MAGIC);
+	fmpl2->size = cpu_to_be16(ubi->fm_wl_pool.size);
+	fmpl2->max_size = cpu_to_be16(ubi->fm_wl_pool.max_size);
+
+	for (i = 0; i < ubi->fm_wl_pool.size; i++)
+		fmpl2->pebs[i] = cpu_to_be32(ubi->fm_wl_pool.pebs[i]);
+
+	for (node = rb_first(&ubi->free); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		free_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->free_peb_count = cpu_to_be32(free_peb_count);
+
+	for (node = rb_first(&ubi->used); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		used_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->used_peb_count = cpu_to_be32(used_peb_count);
+
+	for (node = rb_first(&ubi->scrub); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		scrub_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->scrub_peb_count = cpu_to_be32(scrub_peb_count);
+
+
+	list_for_each_entry(ubi_wrk, &ubi->works, list) {
+		if (ubi_is_erase_work(ubi_wrk)) {
+			wl_e = ubi_wrk->e;
+			ubi_assert(wl_e);
+
+			fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+			fec->pnum = cpu_to_be32(wl_e->pnum);
+			fec->ec = cpu_to_be32(wl_e->ec);
+
+			erase_peb_count++;
+			fm_pos += sizeof(*fec);
+			ubi_assert(fm_pos <= ubi->fm_size);
+		}
+	}
+	fmh->erase_peb_count = cpu_to_be32(erase_peb_count);
+
+	for (i = 0; i < UBI_MAX_VOLUMES + UBI_INT_VOL_COUNT; i++) {
+		vol = ubi->volumes[i];
+
+		if (!vol)
+			continue;
+
+		vol_count++;
+
+		fvh = (struct ubi_fm_volhdr *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fvh);
+		ubi_assert(fm_pos <= ubi->fm_size);
+
+		fvh->magic = cpu_to_be32(UBI_FM_VHDR_MAGIC);
+		fvh->vol_id = cpu_to_be32(vol->vol_id);
+		fvh->vol_type = vol->vol_type;
+		fvh->used_ebs = cpu_to_be32(vol->used_ebs);
+		fvh->data_pad = cpu_to_be32(vol->data_pad);
+		fvh->last_eb_bytes = cpu_to_be32(vol->last_eb_bytes);
+
+		ubi_assert(vol->vol_type == UBI_DYNAMIC_VOLUME ||
+			vol->vol_type == UBI_STATIC_VOLUME);
+
+		feba = (struct ubi_fm_eba *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*feba) + (sizeof(__be32) * vol->reserved_pebs);
+		ubi_assert(fm_pos <= ubi->fm_size);
+
+		for (j = 0; j < vol->reserved_pebs; j++)
+			feba->pnum[j] = cpu_to_be32(vol->eba_tbl[j]);
+
+		feba->reserved_pebs = cpu_to_be32(j);
+		feba->magic = cpu_to_be32(UBI_FM_EBA_MAGIC);
+	}
+	fmh->vol_count = cpu_to_be32(vol_count);
+	fmh->bad_peb_count = cpu_to_be32(ubi->bad_peb_count);
+
+	avhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+	avhdr->lnum = 0;
+
+	spin_unlock(&ubi->wl_lock);
+	spin_unlock(&ubi->volumes_lock);
+
+	dbg_bld("writing fastmap SB to PEB %i", new_fm->e[0]->pnum);
+	ret = ubi_io_write_vid_hdr(ubi, new_fm->e[0]->pnum, avhdr);
+	if (ret) {
+		ubi_err("unable to write vid_hdr to fastmap SB!");
+		goto out_kfree;
+	}
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		fmsb->block_loc[i] = cpu_to_be32(new_fm->e[i]->pnum);
+		fmsb->block_ec[i] = cpu_to_be32(new_fm->e[i]->ec);
+	}
+
+	fmsb->data_crc = 0;
+	fmsb->data_crc = cpu_to_be32(crc32(UBI_CRC32_INIT, fm_raw,
+					   ubi->fm_size));
+
+	for (i = 1; i < new_fm->used_blocks; i++) {
+		dvhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+		dvhdr->lnum = cpu_to_be32(i);
+		dbg_bld("writing fastmap data to PEB %i sqnum %llu",
+			new_fm->e[i]->pnum, be64_to_cpu(dvhdr->sqnum));
+		ret = ubi_io_write_vid_hdr(ubi, new_fm->e[i]->pnum, dvhdr);
+		if (ret) {
+			ubi_err("unable to write vid_hdr to PEB %i!",
+				new_fm->e[i]->pnum);
+			goto out_kfree;
+		}
+	}
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		ret = ubi_io_write(ubi, fm_raw + (i * ubi->leb_size),
+			new_fm->e[i]->pnum, ubi->leb_start, ubi->leb_size);
+		if (ret) {
+			ubi_err("unable to write fastmap to PEB %i!",
+				new_fm->e[i]->pnum);
+			goto out_kfree;
+		}
+	}
+
+	ubi_assert(new_fm);
+	ubi->fm = new_fm;
+
+	dbg_bld("fastmap written!");
+
+out_kfree:
+	ubi_free_vid_hdr(ubi, avhdr);
+	ubi_free_vid_hdr(ubi, dvhdr);
+out:
+	return ret;
+}
+
+/**
+ * erase_block - Manually erase a PEB.
+ * @ubi: UBI device object
+ * @pnum: PEB to be erased
+ *
+ * Returns the new EC value on success, < 0 indicates an internal error.
+ */
+static int erase_block(struct ubi_device *ubi, int pnum)
+{
+	int ret;
+	struct ubi_ec_hdr *ec_hdr;
+	long long ec;
+
+	ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ec_hdr)
+		return -ENOMEM;
+
+	ret = ubi_io_read_ec_hdr(ubi, pnum, ec_hdr, 0);
+	if (ret < 0)
+		goto out;
+	else if (ret && ret != UBI_IO_BITFLIPS) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = ubi_io_sync_erase(ubi, pnum, 0);
+	if (ret < 0)
+		goto out;
+
+	ec = be64_to_cpu(ec_hdr->ec);
+	ec += ret;
+	if (ec > UBI_MAX_ERASECOUNTER) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ec_hdr->ec = cpu_to_be64(ec);
+	ret = ubi_io_write_ec_hdr(ubi, pnum, ec_hdr);
+	if (ret < 0)
+		goto out;
+
+	ret = ec;
+out:
+	kfree(ec_hdr);
+	return ret;
+}
+
+/**
+ * invalidate_fastmap - destroys a fastmap.
+ * @ubi: UBI device object
+ * @fm: the fastmap to be destroyed
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int invalidate_fastmap(struct ubi_device *ubi,
+			      struct ubi_fastmap_layout *fm)
+{
+	int ret, i;
+	struct ubi_vid_hdr *vh;
+
+	ret = erase_block(ubi, fm->e[0]->pnum);
+	if (ret < 0)
+		return ret;
+
+	vh = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID);
+	if (!vh)
+		return -ENOMEM;
+
+	/* deleting the current fastmap SB is not enough, an old SB may exist,
+	 * so create a (corrupted) SB such that fastmap will find it and fall
+	 * back to scanning mode in any case */
+	vh->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+	ret = ubi_io_write_vid_hdr(ubi, fm->e[0]->pnum, vh);
+
+	for (i = 0; i < fm->used_blocks; i++)
+		ubi_wl_put_fm_peb(ubi, fm->e[i], i, fm->to_be_tortured[i]);
+
+	return ret;
+}
+
+/**
+ * ubi_update_fastmap - will be called by UBI if a volume changes or
+ * a fastmap pool becomes full.
+ * @ubi: UBI device object
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+int ubi_update_fastmap(struct ubi_device *ubi)
+{
+	int ret, i;
+	struct ubi_fastmap_layout *new_fm, *old_fm;
+	struct ubi_wl_entry *tmp_e;
+
+	mutex_lock(&ubi->fm_mutex);
+
+	ubi_refill_pools(ubi);
+
+	if (ubi->ro_mode || ubi->fm_disabled) {
+		mutex_unlock(&ubi->fm_mutex);
+		return 0;
+	}
+
+	ret = ubi_ensure_anchor_pebs(ubi);
+	if (ret) {
+		mutex_unlock(&ubi->fm_mutex);
+		return ret;
+	}
+
+	new_fm = kzalloc(sizeof(*new_fm), GFP_KERNEL);
+	if (!new_fm) {
+		mutex_unlock(&ubi->fm_mutex);
+		return -ENOMEM;
+	}
+
+	new_fm->used_blocks = ubi->fm_size / ubi->leb_size;
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		new_fm->e[i] = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL);
+		if (!new_fm->e[i]) {
+			while (i--)
+				kfree(new_fm->e[i]);
+
+			kfree(new_fm);
+			mutex_unlock(&ubi->fm_mutex);
+			return -ENOMEM;
+		}
+	}
+
+	old_fm = ubi->fm;
+	ubi->fm = NULL;
+
+	if (new_fm->used_blocks > UBI_FM_MAX_BLOCKS) {
+		ubi_err("fastmap too large");
+		ret = -ENOSPC;
+		goto err;
+	}
+
+	for (i = 1; i < new_fm->used_blocks; i++) {
+		spin_lock(&ubi->wl_lock);
+		tmp_e = ubi_wl_get_fm_peb(ubi, 0);
+		spin_unlock(&ubi->wl_lock);
+
+		if (!tmp_e && !old_fm) {
+			int j;
+			ubi_err("could not get any free erase block");
+
+			for (j = 1; j < i; j++)
+				ubi_wl_put_fm_peb(ubi, new_fm->e[j], j, 0);
+
+			ret = -ENOSPC;
+			goto err;
+		} else if (!tmp_e && old_fm) {
+			ret = erase_block(ubi, old_fm->e[i]->pnum);
+			if (ret < 0) {
+				int j;
+
+				for (j = 1; j < i; j++)
+					ubi_wl_put_fm_peb(ubi, new_fm->e[j],
+							  j, 0);
+
+				ubi_err("could not erase old fastmap PEB");
+				goto err;
+			}
+
+			new_fm->e[i]->pnum = old_fm->e[i]->pnum;
+			new_fm->e[i]->ec = old_fm->e[i]->ec;
+		} else {
+			new_fm->e[i]->pnum = tmp_e->pnum;
+			new_fm->e[i]->ec = tmp_e->ec;
+
+			if (old_fm)
+				ubi_wl_put_fm_peb(ubi, old_fm->e[i], i,
+						  old_fm->to_be_tortured[i]);
+		}
+	}
+
+	spin_lock(&ubi->wl_lock);
+	tmp_e = ubi_wl_get_fm_peb(ubi, 1);
+	spin_unlock(&ubi->wl_lock);
+
+	if (old_fm) {
+		/* no fresh anchor PEB was found, reuse the old one */
+		if (!tmp_e) {
+			ret = erase_block(ubi, old_fm->e[0]->pnum);
+			if (ret < 0) {
+				int i;
+				ubi_err("could not erase old anchor PEB");
+
+				for (i = 1; i < new_fm->used_blocks; i++)
+					ubi_wl_put_fm_peb(ubi, new_fm->e[i],
+							  i, 0);
+				goto err;
+			}
+
+			new_fm->e[0]->pnum = old_fm->e[0]->pnum;
+			new_fm->e[0]->ec = ret;
+		} else {
+			/* we've got a new anchor PEB, return the old one */
+			ubi_wl_put_fm_peb(ubi, old_fm->e[0], 0,
+					  old_fm->to_be_tortured[0]);
+
+			new_fm->e[0]->pnum = tmp_e->pnum;
+			new_fm->e[0]->ec = tmp_e->ec;
+		}
+	} else {
+		if (!tmp_e) {
+			int i;
+			ubi_err("could not find any anchor PEB");
+
+			for (i = 1; i < new_fm->used_blocks; i++)
+				ubi_wl_put_fm_peb(ubi, new_fm->e[i], i, 0);
+
+			ret = -ENOSPC;
+			goto err;
+		}
+
+		new_fm->e[0]->pnum = tmp_e->pnum;
+		new_fm->e[0]->ec = tmp_e->ec;
+	}
+
+	down_write(&ubi->work_sem);
+	down_write(&ubi->fm_sem);
+	ret = ubi_write_fastmap(ubi, new_fm);
+	up_write(&ubi->fm_sem);
+	up_write(&ubi->work_sem);
+
+	if (ret)
+		goto err;
+
+out_unlock:
+	mutex_unlock(&ubi->fm_mutex);
+	kfree(old_fm);
+	return ret;
+
+err:
+	kfree(new_fm);
+
+	ubi_warn("Unable to write new fastmap, err=%i", ret);
+
+	ret = 0;
+	if (old_fm) {
+		ret = invalidate_fastmap(ubi, old_fm);
+		if (ret < 0)
+			ubi_err("Unable to invalidiate current fastmap!");
+		else if (ret)
+			ret = 0;
+	}
+	goto out_unlock;
+}
-- 
1.7.6.5



From computersforpeace at gmail.com  Mon Sep 24 23:40:47 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:47 -0700
Subject: [PATCH 1/9] mtd: nand: remove unnecessary variable
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-2-git-send-email-computersforpeace@gmail.com>

We don't actually use the 'ret' variable; we set it, test it, and then it dies.

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 88f671c..30588eb 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2872,7 +2872,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 {
 	int i, maf_idx;
 	u8 id_data[8];
-	int ret;
 
 	/* Select the device */
 	chip->select_chip(mtd, 0);
@@ -2919,8 +2918,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 	chip->onfi_version = 0;
 	if (!type->name || !type->pagesize) {
 		/* Check is chip is ONFI compliant */
-		ret = nand_flash_detect_onfi(mtd, chip, &busw);
-		if (ret)
+		if (nand_flash_detect_onfi(mtd, chip, &busw))
 			goto ident_done;
 	}
 
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:46 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:46 -0700
Subject: [PATCH 0/9] mtd: nand: improve NAND ID detection
Message-ID: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>

Hi all,

I've been working on some changes to nand_base.c's nand_get_flash_type()
routine for improving its structure and readability as well as to detect some
new chips. Generally, this patch series does the following:

(1) split several of the big blocks of detection code into separate functions,
    each designated with different tasks
(2) add support for several "new" Hynix and Samsung NAND, which have new
    decoding tables
(3) provide a better baseline on which I or others can make future changes
    (esp., the "generic READ ID length calculation" is useful for detecting
    other patterns that will determine BB marker options)

I have tested this patch series for regressions against a few chips:

  Samsung K9GAG08U0D
  Samsung K9LBG08U0E
  Hynix H27U8G8G5D
  Micron MT29F32G08CBACA

Additionally, I used a test harness for nand_get_flash_type() provided Angus
Clark to test for both regressions and proper fixes (contact Angus if you need
the suite; I'm not sure I have permission to redistribute). The test uses some
data from:

  http://www.linux-mtd.infradead.org/nand-data/nanddata.html

I do not have actual samples of most of the new Samsung and Hynix but have
largely relied on datasheets and support from others who have these chips. Any
testing -- with either old or new chips -- is appreciated.

Thanks,
Brian

Brian Norris (9):
  mtd: nand: remove unnecessary variable
  mtd: nand: remove redundant ID read
  mtd: nand: split BB marker options decoding into its own function
  mtd: nand: split extended ID decoding into its own function
  mtd: nand: split simple ID decode into its own function
  mtd: nand: add generic READ ID length calculation functions
  mtd: nand: increase max OOB size to 640
  mtd: nand: decode Hynix MLC, 6-byte ID length
  mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID

 drivers/mtd/nand/nand_base.c | 360 +++++++++++++++++++++++++++++--------------
 include/linux/mtd/nand.h     |   2 +-
 2 files changed, 248 insertions(+), 114 deletions(-)

-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:48 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:48 -0700
Subject: [PATCH 2/9] mtd: nand: remove redundant ID read
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-3-git-send-email-computersforpeace@gmail.com>

Instead of reading 2 bytes then later 8 bytes, we can simply read all 8
bytes from the start.

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 30588eb..f725247 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2898,7 +2898,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
 
-	for (i = 0; i < 2; i++)
+	/* Read entire ID string */
+	for (i = 0; i < 8; i++)
 		id_data[i] = chip->read_byte(mtd);
 
 	if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
@@ -2922,13 +2923,6 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 			goto ident_done;
 	}
 
-	chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-
-	/* Read entire ID string */
-
-	for (i = 0; i < 8; i++)
-		id_data[i] = chip->read_byte(mtd);
-
 	if (!type->name)
 		return ERR_PTR(-ENODEV);
 
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:49 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:49 -0700
Subject: [PATCH 3/9] mtd: nand: split BB marker options decoding into its own
 function
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-4-git-send-email-computersforpeace@gmail.com>

When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.

This patch splits the bad block marker options detection into its own function,
away from the other parameters (e.g., chip size, page size, etc.).

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 66 ++++++++++++++++++++++++++------------------
 1 file changed, 39 insertions(+), 27 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index f725247..c7fc330 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2862,6 +2862,43 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /*
+ * Set the bad block marker/indicator (BBM/BBI) patterns according to some
+ * heuristic patterns using various detected parameters (e.g., manufacturer,
+ * page size, cell-type information).
+ */
+static void nand_decode_bbm_options(struct mtd_info *mtd,
+				    struct nand_chip *chip, u8 id_data[8])
+{
+	int maf_id = id_data[0];
+
+	/* Set the bad block position */
+	if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
+		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
+	else
+		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
+
+	/*
+	 * Bad block marker is stored in the last page of each block on Samsung
+	 * and Hynix MLC devices; stored in first two pages of each block on
+	 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
+	 * AMD/Spansion, and Macronix.  All others scan only the first page.
+	 */
+	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			(maf_id == NAND_MFR_SAMSUNG ||
+			 maf_id == NAND_MFR_HYNIX))
+		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
+	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+				(maf_id == NAND_MFR_SAMSUNG ||
+				 maf_id == NAND_MFR_HYNIX ||
+				 maf_id == NAND_MFR_TOSHIBA ||
+				 maf_id == NAND_MFR_AMD ||
+				 maf_id == NAND_MFR_MACRONIX)) ||
+			(mtd->writesize == 2048 &&
+			 maf_id == NAND_MFR_MICRON))
+		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
+}
+
+/*
  * Get the flash and manufacturer id and lookup if the type is supported.
  */
 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
@@ -3043,6 +3080,8 @@ ident_done:
 		return ERR_PTR(-EINVAL);
 	}
 
+	nand_decode_bbm_options(mtd, chip, id_data);
+
 	/* Calculate the address shift from the page size */
 	chip->page_shift = ffs(mtd->writesize) - 1;
 	/* Convert chipsize to number of pages per chip -1 */
@@ -3059,33 +3098,6 @@ ident_done:
 
 	chip->badblockbits = 8;
 
-	/* Set the bad block position */
-	if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
-		chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
-	else
-		chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
-
-	/*
-	 * Bad block marker is stored in the last page of each block
-	 * on Samsung and Hynix MLC devices; stored in first two pages
-	 * of each block on Micron devices with 2KiB pages and on
-	 * SLC Samsung, Hynix, Toshiba, AMD/Spansion, and Macronix.
-	 * All others scan only the first page.
-	 */
-	if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-			(*maf_id == NAND_MFR_SAMSUNG ||
-			 *maf_id == NAND_MFR_HYNIX))
-		chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
-	else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				(*maf_id == NAND_MFR_SAMSUNG ||
-				 *maf_id == NAND_MFR_HYNIX ||
-				 *maf_id == NAND_MFR_TOSHIBA ||
-				 *maf_id == NAND_MFR_AMD ||
-				 *maf_id == NAND_MFR_MACRONIX)) ||
-			(mtd->writesize == 2048 &&
-			 *maf_id == NAND_MFR_MICRON))
-		chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
-
 	/* Check for AND chips with 4 page planes */
 	if (chip->options & NAND_4PAGE_ARRAY)
 		chip->erase_cmd = multi_erase_cmd;
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:50 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:50 -0700
Subject: [PATCH 4/9] mtd: nand: split extended ID decoding into its own
 function
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-5-git-send-email-computersforpeace@gmail.com>

When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.

This patch splits out the extended ID decode functionality, which handles
decoding the 3rd-8th ID bytes to determine NAND device parameters.

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 122 ++++++++++++++++++++++++-------------------
 1 file changed, 67 insertions(+), 55 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index c7fc330..afbe1ce 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2862,6 +2862,71 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /*
+ * Many new NAND share similar device ID codes, which represent the size of the
+ * chip. The rest of the parameters must be decoded according to generic or
+ * manufacturer-specific "extended ID" decoding patterns.
+ */
+static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
+				u8 id_data[8], int *busw)
+{
+	int extid;
+	/* The 3rd id byte holds MLC / multichip data */
+	chip->cellinfo = id_data[2];
+	/* The 4th id byte is the important one */
+	extid = id_data[3];
+
+	/*
+	 * Field definitions are in the following datasheets:
+	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
+	 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
+	 *
+	 * Check for wraparound + Samsung ID + nonzero 6th byte
+	 * to decide what to do.
+	 */
+	if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
+			id_data[0] == NAND_MFR_SAMSUNG &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
+			id_data[5] != 0x00) {
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (extid & 0x03) {
+		case 1:
+			mtd->oobsize = 128;
+			break;
+		case 2:
+			mtd->oobsize = 218;
+			break;
+		case 3:
+			mtd->oobsize = 400;
+			break;
+		default:
+			mtd->oobsize = 436;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		mtd->erasesize = (128 * 1024) <<
+			(((extid >> 1) & 0x04) | (extid & 0x03));
+		*busw = 0;
+	} else {
+		/* Calc pagesize */
+		mtd->writesize = 1024 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		mtd->oobsize = (8 << (extid & 0x01)) *
+			(mtd->writesize >> 9);
+		extid >>= 2;
+		/* Calc blocksize. Blocksize is multiples of 64KiB */
+		mtd->erasesize = (64 * 1024) << (extid & 0x03);
+		extid >>= 2;
+		/* Get buswidth information */
+		*busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+	}
+}
+
+/*
  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  * heuristic patterns using various detected parameters (e.g., manufacturer,
  * page size, cell-type information).
@@ -2972,61 +3037,8 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		/* Set the pagesize, oobsize, erasesize by the driver */
 		busw = chip->init_size(mtd, chip, id_data);
 	} else if (!type->pagesize) {
-		int extid;
-		/* The 3rd id byte holds MLC / multichip data */
-		chip->cellinfo = id_data[2];
-		/* The 4th id byte is the important one */
-		extid = id_data[3];
-
-		/*
-		 * Field definitions are in the following datasheets:
-		 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
-		 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
-		 *
-		 * Check for wraparound + Samsung ID + nonzero 6th byte
-		 * to decide what to do.
-		 */
-		if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
-				id_data[0] == NAND_MFR_SAMSUNG &&
-				(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-				id_data[5] != 0x00) {
-			/* Calc pagesize */
-			mtd->writesize = 2048 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			switch (extid & 0x03) {
-			case 1:
-				mtd->oobsize = 128;
-				break;
-			case 2:
-				mtd->oobsize = 218;
-				break;
-			case 3:
-				mtd->oobsize = 400;
-				break;
-			default:
-				mtd->oobsize = 436;
-				break;
-			}
-			extid >>= 2;
-			/* Calc blocksize */
-			mtd->erasesize = (128 * 1024) <<
-				(((extid >> 1) & 0x04) | (extid & 0x03));
-			busw = 0;
-		} else {
-			/* Calc pagesize */
-			mtd->writesize = 1024 << (extid & 0x03);
-			extid >>= 2;
-			/* Calc oobsize */
-			mtd->oobsize = (8 << (extid & 0x01)) *
-				(mtd->writesize >> 9);
-			extid >>= 2;
-			/* Calc blocksize. Blocksize is multiples of 64KiB */
-			mtd->erasesize = (64 * 1024) << (extid & 0x03);
-			extid >>= 2;
-			/* Get buswidth information */
-			busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-		}
+		/* Decode parameters from extended ID */
+		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
 		/*
 		 * Old devices have chip data hardcoded in the device id table.
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:51 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:51 -0700
Subject: [PATCH 5/9] mtd: nand: split simple ID decode into its own function
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-6-git-send-email-computersforpeace@gmail.com>

When detecting NAND parameters, the code gets a little ugly so that the
logic is obscured. Try to remedy that by moving code to separate functions
that have well-defined purposes.

This patch splits out the simple ID decode functionality, where all the
information regarding NAND size/blocksize/pagesize/oobsize/busw is encoded in
the first two bytes of the ID string.

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 51 +++++++++++++++++++++++++++-----------------
 1 file changed, 31 insertions(+), 20 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index afbe1ce..380f783 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2927,6 +2927,36 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /*
+ * Old devices have chip data hardcoded in the device ID table. nand_decode_id
+ * decodes a matching ID table entry and assigns the MTD size parameters for
+ * the chip.
+ */
+static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
+				struct nand_flash_dev *type, u8 id_data[8],
+				int *busw)
+{
+	int maf_id = id_data[0];
+
+	mtd->erasesize = type->erasesize;
+	mtd->writesize = type->pagesize;
+	mtd->oobsize = mtd->writesize / 32;
+	*busw = type->options & NAND_BUSWIDTH_16;
+
+	/*
+	 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
+	 * some Spansion chips have erasesize that conflicts with size
+	 * listed in nand_ids table.
+	 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
+	 */
+	if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
+			&& id_data[6] == 0x00 && id_data[7] == 0x00
+			&& mtd->writesize == 512) {
+		mtd->erasesize = 128 * 1024;
+		mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
+	}
+}
+
+/*
  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  * heuristic patterns using various detected parameters (e.g., manufacturer,
  * page size, cell-type information).
@@ -3040,26 +3070,7 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 		/* Decode parameters from extended ID */
 		nand_decode_ext_id(mtd, chip, id_data, &busw);
 	} else {
-		/*
-		 * Old devices have chip data hardcoded in the device id table.
-		 */
-		mtd->erasesize = type->erasesize;
-		mtd->writesize = type->pagesize;
-		mtd->oobsize = mtd->writesize / 32;
-		busw = type->options & NAND_BUSWIDTH_16;
-
-		/*
-		 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
-		 * some Spansion chips have erasesize that conflicts with size
-		 * listed in nand_ids table.
-		 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
-		 */
-		if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
-				id_data[5] == 0x00 && id_data[6] == 0x00 &&
-				id_data[7] == 0x00 && mtd->writesize == 512) {
-			mtd->erasesize = 128 * 1024;
-			mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
-		}
+		nand_decode_id(mtd, chip, type, id_data, &busw);
 	}
 	/* Get chip options */
 	chip->options |= type->options;
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:52 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:52 -0700
Subject: [PATCH 6/9] mtd: nand: add generic READ ID length calculation
 functions
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-7-git-send-email-computersforpeace@gmail.com>

When decoding the extended ID bytes of a NAND chip, we have to calculate the ID
length according to some heuristic patterns (e.g., Does the ID wrap around?
Does it end in trailing zeros?). Currently, these heuristics are built into
complicated if/else blocks that can be hard to understand.

Now, these checks can be done generically in a function, making them more
robust and reusable. In fact, this sort of calculation is needed in future
additions to nand_base.c. And with this advancement, we get the added benefit
of a more readable "extended ID decode".

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 72 +++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 65 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 380f783..fd5c307 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2862,6 +2862,65 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 }
 
 /*
+ * nand_id_has_period - Check if an ID string has a given wraparound period
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+ * @period: the period of repitition
+ *
+ * Check if an ID string is repeated within a given sequence of bytes at
+ * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
+ * period of 2). This is a helper function for nand_id_len(). Returns non-zero
+ * if the repetition has a period of @period; otherwise, returns zero.
+ */
+static int nand_id_has_period(u8 *id_data, int arrlen, int period)
+{
+	int i, j;
+	for (i = 0; i < period; i++)
+		for (j = i + period; j < arrlen; j += period)
+			if (id_data[i] != id_data[j])
+				return 0;
+	return 1;
+}
+
+/*
+ * nand_id_len - Get the length of an ID string returned by CMD_READID
+ * @id_data: the ID string
+ * @arrlen: the length of the @id_data array
+
+ * Returns the length of the ID string, according to known wraparound/trailing
+ * zero patterns. If no pattern exists, returns the length of the array.
+ */
+static int nand_id_len(u8 *id_data, int arrlen)
+{
+	int last_nonzero, period;
+
+	/* Find last non-zero byte */
+	for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
+		if (id_data[last_nonzero])
+			break;
+
+	/* All zeros */
+	if (last_nonzero < 0)
+		return 0;
+
+	/* Calculate wraparound period */
+	for (period = 1; period < arrlen; period++)
+		if (nand_id_has_period(id_data, arrlen, period))
+			break;
+
+	/* There's a repeated pattern */
+	if (period < arrlen)
+		return period;
+
+	/* There are trailing zeros */
+	if (last_nonzero < arrlen - 1)
+		return last_nonzero + 1;
+
+	/* No pattern detected */
+	return arrlen;
+}
+
+/*
  * Many new NAND share similar device ID codes, which represent the size of the
  * chip. The rest of the parameters must be decoded according to generic or
  * manufacturer-specific "extended ID" decoding patterns.
@@ -2869,24 +2928,23 @@ static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 				u8 id_data[8], int *busw)
 {
-	int extid;
+	int extid, id_len;
 	/* The 3rd id byte holds MLC / multichip data */
 	chip->cellinfo = id_data[2];
 	/* The 4th id byte is the important one */
 	extid = id_data[3];
 
+	id_len = nand_id_len(id_data, 8);
+
 	/*
 	 * Field definitions are in the following datasheets:
 	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
 	 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
 	 *
-	 * Check for wraparound + Samsung ID + nonzero 6th byte
-	 * to decide what to do.
+	 * Check for ID length + Samsung ID to decide what to do.
 	 */
-	if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
-			id_data[0] == NAND_MFR_SAMSUNG &&
-			(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
-			id_data[5] != 0x00) {
+	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
 		/* Calc pagesize */
 		mtd->writesize = 2048 << (extid & 0x03);
 		extid >>= 2;
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:53 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:53 -0700
Subject: [PATCH 7/9] mtd: nand: increase max OOB size to 640
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-8-git-send-email-computersforpeace@gmail.com>

Some Hynix and Samsung MLC NAND have 640B OOB size. Sooner or later, we should
dynamically allocate the buffers that use these macros.

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 include/linux/mtd/nand.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index ce22824..817ff5a 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -56,7 +56,7 @@ extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  * is supported now. If you add a chip with bigger oobsize/page
  * adjust this accordingly.
  */
-#define NAND_MAX_OOBSIZE	576
+#define NAND_MAX_OOBSIZE	640
 #define NAND_MAX_PAGESIZE	8192
 
 /*
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:54 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:54 -0700
Subject: [PATCH 8/9] mtd: nand: decode Hynix MLC, 6-byte ID length
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-9-git-send-email-computersforpeace@gmail.com>

Hynix has introduced a new ID decoding scheme for their newer MLC, some of
which don't support ONFI. The following devices all follow the pattern given in
the datasheet for Hynix H27UBG8T2B, p.22:

Hynix H27UAG8T2A
Hynix H27UBG8T2A
Hynix H27UBG8T2B

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 45 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index fd5c307..7e93d0d 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2940,8 +2940,10 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 	 * Field definitions are in the following datasheets:
 	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
 	 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
+	 * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
 	 *
-	 * Check for ID length + Samsung ID to decide what to do.
+	 * Check for ID length, cell type, and Hynix/Samsung ID to decide what
+	 * to do.
 	 */
 	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
 			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
@@ -2968,6 +2970,47 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 		mtd->erasesize = (128 * 1024) <<
 			(((extid >> 1) & 0x04) | (extid & 0x03));
 		*busw = 0;
+	} else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
+			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+		unsigned int tmp;
+
+		/* Calc pagesize */
+		mtd->writesize = 2048 << (extid & 0x03);
+		extid >>= 2;
+		/* Calc oobsize */
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
+		case 0:
+			mtd->oobsize = 128;
+			break;
+		case 1:
+			mtd->oobsize = 224;
+			break;
+		case 2:
+			mtd->oobsize = 448;
+			break;
+		case 3:
+			mtd->oobsize = 64;
+			break;
+		case 4:
+			mtd->oobsize = 32;
+			break;
+		case 5:
+			mtd->oobsize = 16;
+			break;
+		default:
+			mtd->oobsize = 640;
+			break;
+		}
+		extid >>= 2;
+		/* Calc blocksize */
+		tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
+		if (tmp < 0x03)
+			mtd->erasesize = (128 * 1024) << tmp;
+		else if (tmp == 0x03)
+			mtd->erasesize = 768 * 1024;
+		else
+			mtd->erasesize = (64 * 1024) << tmp;
+		*busw = 0;
 	} else {
 		/* Calc pagesize */
 		mtd->writesize = 1024 << (extid & 0x03);
-- 
1.7.11.3



From computersforpeace at gmail.com  Mon Sep 24 23:40:55 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Mon, 24 Sep 2012 20:40:55 -0700
Subject: [PATCH 9/9] mtd: nand: detect Samsung K9GBG08U0A, K9GAG08U0F ID
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348544455-17656-10-git-send-email-computersforpeace@gmail.com>

Datasheets for the following Samsung NAND parts (both MLC and SLC) describe
extensions to the Samsung 6-byte extended ID decoding table:

K9GBG08U0A (MLC, 6-byte ID)
K9GAG08U0F (MLC, 6-byte ID)
K9FAG08U0M (SLC, 6-byte ID)

The table found in K9GAG08U0F, p.44, contains a superset of the information
found in other previous datasheets.

This patch adds support for all of these chips, with 512B and 640B OOB sizes.
It also changes the detection pattern such that this table applies to all
Samsung 6-byte ID NAND, not just MLC. This is safe, according to the NAND
parameter data I have collected:

Note that nand_base.c does not yet support the bad block marker scheme defined
for these chips (i.e., scan 1st and last page for BB markers).

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
 drivers/mtd/nand/nand_base.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 7e93d0d..bcb58ce 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2939,19 +2939,18 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 	/*
 	 * Field definitions are in the following datasheets:
 	 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
-	 * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
+	 * New style   (6 byte ID): Samsung K9GAG08U0F (p.44)
 	 * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
 	 *
 	 * Check for ID length, cell type, and Hynix/Samsung ID to decide what
 	 * to do.
 	 */
-	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
-			(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
+	if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG) {
 		/* Calc pagesize */
 		mtd->writesize = 2048 << (extid & 0x03);
 		extid >>= 2;
 		/* Calc oobsize */
-		switch (extid & 0x03) {
+		switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
 		case 1:
 			mtd->oobsize = 128;
 			break;
@@ -2961,9 +2960,16 @@ static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
 		case 3:
 			mtd->oobsize = 400;
 			break;
-		default:
+		case 4:
 			mtd->oobsize = 436;
 			break;
+		case 5:
+			mtd->oobsize = 512;
+			break;
+		case 6:
+		default: /* Other cases are "reserved" (unknown) */
+			mtd->oobsize = 640;
+			break;
 		}
 		extid >>= 2;
 		/* Calc blocksize */
-- 
1.7.11.3



From matthieu.castet at parrot.com  Tue Sep 25 05:05:27 2012
From: matthieu.castet at parrot.com (Matthieu CASTET)
Date: Tue, 25 Sep 2012 11:05:27 +0200
Subject: [PATCH] mtd: m25p80: add support for the windbond w25q256 chip
Message-ID: <1348563927-9131-1-git-send-email-matthieu.castet@parrot.com>

Signed-off-by: Matthieu CASTET <matthieu.castet at parrot.com>
---
 drivers/mtd/devices/m25p80.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 5257345..4eb99c6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -168,6 +168,7 @@ static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
 {
 	switch (JEDEC_MFR(jedec_id)) {
 	case CFI_MFR_MACRONIX:
+	case 0xEF /* winbond */:
 		flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
 		return spi_write(flash->spi, flash->command, 1);
 	default:
@@ -739,6 +740,7 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
 	{ "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
+	{ "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
 
 	/* Catalyst / On Semiconductor -- non-JEDEC */
 	{ "cat25c11", CAT25_INFO(  16, 8, 16, 1) },
-- 
1.7.10.4



From zajec5 at gmail.com  Tue Sep 25 05:33:35 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Tue, 25 Sep 2012 11:33:35 +0200
Subject: Problem with verify-ing patch (error: arch/m68k/Kconfig.cpu:
 patch does not apply)
In-Reply-To: <1348499094.4880.65.camel@sauron.fi.intel.com>
References: <CACna6rwju0g+sq+vBAfCqFJm=EBLg79G2XoGEKs5n1Y=PcmKBg@mail.gmail.com>
 <1348499094.4880.65.camel@sauron.fi.intel.com>
Message-ID: <CACna6ryu06qsgX99kdkeDaB+XJv4XwC0-O+5ysNFa1iOMEgNow@mail.gmail.com>

2012/9/24 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Mon, 2012-09-24 at 13:14 +0200, Rafa? Mi?ecki wrote:
>> I wanted to verify my patch before sending it.
>>
>> TRY[0]:
>> > ./verify ../wireless-testing/ mips-bcm47xx_defconfig < ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
>> error: patch failed: arch/m68k/Kconfig.cpu:28
>> error: arch/m68k/Kconfig.cpu: patch does not apply
>>
>> Weird. My patch doesn't touch m68k and applies cleanly to the
>> ../wireless-testing tree:
>>
>> > cd ../wireless-testing/
>> > git am ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
>> Applying: mtd: prepare place for BCMA NAND flash driver(s)
>>
>> Help? :|
>
> It tries to apply quick fixes - I carry them because the kernel gets
> broken in various places all the time. So you need to fix the quick
> fixes patch - probably a fix was applied in upstream already.
>
> Obviously, quick fixes are in maintaining.git, not in the generic aiaiai
> tools. They are in 'quick_fixes.mbox'.
>
> In this case it easy - the m68k patch get merged upstream and just can
> be dropped from quick_fixes.mbox. Just done that and pushed out.

Thanks. Unfortunately I'm still having problems with verify/aiaiai :|

After your change I started verify again and it took 3 minutes to let
me know it needs mips-linux-gcc. I had to install it (OpenWRT is using
it's own toolchain).

Then I started again and after 3 minutes: lacking sparse

3 minutes later: lacking smatch

3 minutes later: lacking cppcheck

3 minutes later: lacking spatch

I'm not sure what's going to be next. I'm sure that things are obvious
for you, but beginner can really get irritated before he manages to
setup everything... ;/

-- 
Rafa?


From sachin.kamat at linaro.org  Tue Sep 25 05:57:13 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Tue, 25 Sep 2012 15:27:13 +0530
Subject: [PATCH] mtd: ofpart: Fix incorrect NULL check in
 parse_ofoldpart_partitions()
Message-ID: <1348567033-5418-1-git-send-email-sachin.kamat@linaro.org>

The pointer returned by kzalloc should be tested for NULL
to avoid potential NULL pointer dereference later. Incorrect
pointer was being tested for NULL. Bug introduced by commit fbcf62a3
(mtd: physmap_of: move parse_obsolete_partitions to become separate
parser).
This patch fixes this bug.

Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
Cc: Artem Bityutskiy <artem.bityutskiy at intel.com>
Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
---
 drivers/mtd/ofpart.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/ofpart.c b/drivers/mtd/ofpart.c
index 64be8f0..d9127e2 100644
--- a/drivers/mtd/ofpart.c
+++ b/drivers/mtd/ofpart.c
@@ -121,7 +121,7 @@ static int parse_ofoldpart_partitions(struct mtd_info *master,
 	nr_parts = plen / sizeof(part[0]);
 
 	*pparts = kzalloc(nr_parts * sizeof(*(*pparts)), GFP_KERNEL);
-	if (!pparts)
+	if (!*pparts)
 		return -ENOMEM;
 
 	names = of_get_property(dp, "partition-names", &plen);
-- 
1.7.4.1



From dedekind1 at gmail.com  Tue Sep 25 08:06:25 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 15:06:25 +0300
Subject: Problem with verify-ing patch (error: arch/m68k/Kconfig.cpu:
 patch does not apply)
In-Reply-To: <CACna6ryu06qsgX99kdkeDaB+XJv4XwC0-O+5ysNFa1iOMEgNow@mail.gmail.com>
References: <CACna6rwju0g+sq+vBAfCqFJm=EBLg79G2XoGEKs5n1Y=PcmKBg@mail.gmail.com>
 <1348499094.4880.65.camel@sauron.fi.intel.com>
 <CACna6ryu06qsgX99kdkeDaB+XJv4XwC0-O+5ysNFa1iOMEgNow@mail.gmail.com>
Message-ID: <1348574785.20474.15.camel@sauron.fi.intel.com>

On Tue, 2012-09-25 at 11:33 +0200, Rafa? Mi?ecki wrote:
> 2012/9/24 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Mon, 2012-09-24 at 13:14 +0200, Rafa? Mi?ecki wrote:
> >> I wanted to verify my patch before sending it.
> >>
> >> TRY[0]:
> >> > ./verify ../wireless-testing/ mips-bcm47xx_defconfig < ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
> >> error: patch failed: arch/m68k/Kconfig.cpu:28
> >> error: arch/m68k/Kconfig.cpu: patch does not apply
> >>
> >> Weird. My patch doesn't touch m68k and applies cleanly to the
> >> ../wireless-testing tree:
> >>
> >> > cd ../wireless-testing/
> >> > git am ../nand4/0001-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch
> >> Applying: mtd: prepare place for BCMA NAND flash driver(s)
> >>
> >> Help? :|
> >
> > It tries to apply quick fixes - I carry them because the kernel gets
> > broken in various places all the time. So you need to fix the quick
> > fixes patch - probably a fix was applied in upstream already.
> >
> > Obviously, quick fixes are in maintaining.git, not in the generic aiaiai
> > tools. They are in 'quick_fixes.mbox'.
> >
> > In this case it easy - the m68k patch get merged upstream and just can
> > be dropped from quick_fixes.mbox. Just done that and pushed out.
> 
> Thanks. Unfortunately I'm still having problems with verify/aiaiai :|
> 
> After your change I started verify again and it took 3 minutes to let
> me know it needs mips-linux-gcc. I had to install it (OpenWRT is using
> it's own toolchain).
> 
> Then I started again and after 3 minutes: lacking sparse
> 
> 3 minutes later: lacking smatch
> 
> 3 minutes later: lacking cppcheck
> 
> 3 minutes later: lacking spatch
> 
> I'm not sure what's going to be next. I'm sure that things are obvious
> for you, but beginner can really get irritated before he manages to
> setup everything... ;/

Rafal, your complaints are fair, thanks. This needs some more work. I'll
add checks for all the required tools in the scripts so that they will
fail right away with a user-friendly messages.

But one thing is obvious for me - you did not read the docs in aiaiai
projects. Well, fair enough, typical users do not read docs :-) The docs
tell where to get tools, how to compile, etc. I think they also tell
where to download pre-build compilers even, but I should check this
part :-)

I'll do the fixes as soon as I have some time, please, keep bugging me
and thanks for your feed-back!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/d39df875/attachment.sig>

From dedekind1 at gmail.com  Tue Sep 25 09:56:03 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 16:56:03 +0300
Subject: UBI : Pairing up PEB
In-Reply-To: <CACVe6y2vgiypjvzMYdjBf+SBu9qiWcJrDst-UKe-jS3b=m8GVg@mail.gmail.com>
References: <CACVe6y2vgiypjvzMYdjBf+SBu9qiWcJrDst-UKe-jS3b=m8GVg@mail.gmail.com>
Message-ID: <1348581363.24309.2.camel@sauron.fi.intel.com>

On Tue, 2012-09-11 at 13:44 +0530, VenuGopaL A wrote:
> Hi All,
> 
> I am trying to speed up UBI. In FAQ section, they have mentioned about
> merging two or more PEB's and treating them as one composite PEB .
> I am not able to find any documentation over the net.
> 
> I tried changing the PEB size and LEB size during ubinizing the image
> but the file system did not mount and the target crashed.
> 
> Please put some light on the pairing up of PEBs.
> Target has 512MB OneNAND chip.

Hi, I meant pairing on the driver level, not in UBI. The driver would
need to report 2x larger PEB size to UBI.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/117d0f43/attachment.sig>

From artem.bityutskiy at linux.intel.com  Tue Sep 25 10:05:31 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 17:05:31 +0300
Subject: [PATCH] MTD: nandsim: BUG: Fail if overridesize is too big
In-Reply-To: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>
References: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348581931.24309.3.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 14:26 +0200, Richard Genoud wrote:
> If override size is too big, the module was actually loaded instead of
> failing, because retval was not set.
> 
> This lead to memory corruption with the use of the freed structs nandsim
> and nand_chip.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Pushed to l2-mtd.git, CCed -stable.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/54c9999c/attachment.sig>

From dedekind1 at gmail.com  Tue Sep 25 10:05:50 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 17:05:50 +0300
Subject: [MTD-UTILS] BUG: ubiformat fails on big partitions (>4Gio)
In-Reply-To: <1347460639-3241-1-git-send-email-richard.genoud@gmail.com>
References: <1347460639-3241-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348581950.24309.4.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 16:37 +0200, Richard Genoud wrote:
> The offset (which is 64bits when mtd-utils are not compile with
> WITHOUT_LARGEFILE) is calculated like that:
> offset = nb * size;
> But nb and size are int, so on 32bits platforms, there's a possible
> overflow.

Pushed to mtd-utils.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/ad6b0ce3/attachment.sig>

From dedekind1 at gmail.com  Tue Sep 25 10:05:59 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 17:05:59 +0300
Subject: [MTD-UTILS] io_update test: correct lseek parameters order
In-Reply-To: <1347460674-3536-1-git-send-email-richard.genoud@gmail.com>
References: <1347460674-3536-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348581959.24309.5.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 16:37 +0200, Richard Genoud wrote:
> There's a typo in lseek parameters order.
> 
> But, due to the value of SEEK_SET, this commit doesn't introduce a
> change.
> 
> Signed-off-by: Richard Genoud <richard.genoud at gmail.com>

Pushed to mtd-utils.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/e8dfa20c/attachment.sig>

From dedekind1 at gmail.com  Tue Sep 25 11:07:37 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 25 Sep 2012 18:07:37 +0300
Subject: [MTD-UTILS 0/3] fix off_t use in lseek
In-Reply-To: <1347460715-3951-1-git-send-email-richard.genoud@gmail.com>
References: <1347460715-3951-1-git-send-email-richard.genoud@gmail.com>
Message-ID: <1348585657.24309.13.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 16:38 +0200, Richard Genoud wrote:
> In lseek call, sometimes off_t is used, sometime u_int32_t or
> off64_t (with lseek64).
> This patchset corrects those inconsistencies in respect with the
> WITHOUT_LARGEFILE compilation option.

Could be a bit nicer (commit messages are not perfect, the second patch
is rather big), but not big deal, pushed to mtd-utils.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120925/80dbf0eb/attachment-0001.sig>

From prabhakar at freescale.com  Wed Sep 26 00:45:21 2012
From: prabhakar at freescale.com (Prabhakar Kushwaha)
Date: Wed, 26 Sep 2012 10:15:21 +0530
Subject: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any
 write
In-Reply-To: <68738277-B1F2-4455-B8FD-67F2DD9E1310@kernel.crashing.org>
References: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
 <68738277-B1F2-4455-B8FD-67F2DD9E1310@kernel.crashing.org>
Message-ID: <50628861.7050206@freescale.com>

On 09/13/2012 06:23 PM, Kumar Gala wrote:
> On Sep 13, 2012, at 3:54 AM, Prabhakar Kushwaha wrote:
>
>> IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
>> SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
>> implemented in IFC for any "system side write" into sram buffer. Reading an
>> uninitialized memory results in ECC Error from sram wrapper.
>>
>> Hence we must initialize/prefill SRAM buffer by any data before writing
>> anything in SRAM from system side. To initialize SRAM user can use "READID"
>> NAND command with read bytes equal to SRAM size. It will be a one time
>> activity post boot.
>>
>> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
>> ---
>> Based upon git://git.infradead.org/linux-mtd.git branch master
>> The compilation of this patch depends upon following patch.
>> http://patchwork.ozlabs.org/patch/177893/
>> This patch is currently applied on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git
>> branch next and status is "Awaiting Upstream"
>>
>>
>> drivers/mtd/nand/fsl_ifc_nand.c |   56 ++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 55 insertions(+), 1 deletion(-)
> If MTD maintainers ack, I'm happy to pull this in via PPC tree.

Hi  Artem,

Can you please ACK this patch so that it can be pulled via PPC tree.

Regards,
Prabhakar





From jayakumar.lkml at gmail.com  Wed Sep 26 01:42:15 2012
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Wed, 26 Sep 2012 13:42:15 +0800
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <1346751620.12610.35.camel@sauron.fi.intel.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
Message-ID: <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>

On Tue, Sep 4, 2012 at 5:40 PM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> Another approach people use is that they have "mirror" UBI volume of the
> same size, like "ubifs-reserve". Then the update image is put to
> ubifs-reserve, and after this you use the UBI volume rename feature and
> rename "ubifs-reserve into" "ubifs". This will kill the old "ubifs"
> volume. After this you may resize "ubifs" to something larger, and
> create a new "ubifs-reserve" volume.

Thanks Artem. I like above method. But one thing which I did not expect is that

I setup my single mtd partition with 2 volumes, rootfs and
rootfs_reserve. My system is running from volume 0 (rootfs), ie:
firmware upgrade is from there.

root at localhost:/# ubinfo -a
UBI version:                    1
Count of UBI devices:           1
UBI control device major/minor: 10:61
Present UBI devices:            ubi0

ubi0
Volumes count:                           2
Logical eraseblock size:                 129024 bytes, 126.0 KiB
Total amount of logical eraseblocks:     4036 (520740864 bytes, 496.6 MiB)
Amount of available logical eraseblocks: 0 (0 bytes)
Maximum count of volumes                 128
Count of bad physical eraseblocks:       0
Count of reserved physical eraseblocks:  80
Current maximum erase counter value:     2
Minimum input/output unit size:          2048 bytes
Character device major/minor:            252:0
Present volumes:                         0, 1

Volume ID:   0 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        1829 LEBs (235984896 bytes, 225.1 MiB)
State:       OK
Name:        rootfs
Character device major/minor: 252:1
-----------------------------------
Volume ID:   1 (on ubi0)
Type:        dynamic
Alignment:   1
Size:        2123 LEBs (273917952 bytes, 261.2 MiB)
State:       OK
Name:        rootfs_reserve
Character device major/minor: 252:2

I'm then able to use ubiupdatevol to write the firmware (containing
new rootfs) update to the rootfs_reserve volume.

root at localhost:/# ubiupdatevol /dev/ubi0_1 /mnt/microsd/newfw/ubifs.img

But then when I go to rename rootfs_reserve to rootfs and rootfs to
rootfs_reserve, I get:

root at localhost:/# ubirename /dev/ubi0 rootfs rootfs_reserve
rootfs_reserve rootfs
UBI error: ubi_open_volume: cannot open device 0, volume 0, error -16
UBI error: rename_volumes: cannot open volume 0, error -16
ubirename: error!: cannot rename volumes
           error 16 (Device or resource busy)

It looks like I cannot perform the rename of the running volume, rootfs.

root at localhost:/# ubirename /dev/ubi0 rootfs oldrootfs
UBI error: ubi_open_volume: cannot open device 0, volume 0, error -16
UBI error: rename_volumes: cannot open volume 0, error -16
ubirename: error!: cannot rename volumes
           error 16 (Device or resource busy)

I can rename the reserve fine.
root at localhost:/# ubirename /dev/ubi0 rootfs_reserve somenewname

But I can't kill the name of the running volume.
root at localhost:/# ubirename /dev/ubi0 somenewname rootfs
UBI error: ubi_open_volume: cannot open device 0, volume 0, error -16
UBI error: rename_volumes: cannot open volume "rootfs", error -16
ubirename: error!: cannot rename volumes
           error 16 (Device or resource busy)

I think what this means is that after doing the rootfs upgrade using
ubiupdatevol, I must reboot into a 3rd partition running a minimal OS
to perform the ubirename of roofs_reserve and then reboot again. This
step seems expensive to have to boot into a 3rd partition to do the
rename operation.

I see someone else also has encountered this,
http://comments.gmane.org/gmane.linux.drivers.mtd/39415 and solved by
having a initramfs. I guess I could do that. But still seems messy.

Thanks,
jayakumar


From dedekind1 at gmail.com  Wed Sep 26 03:39:31 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 10:39:31 +0300
Subject: [PATCH 1/4] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1347481275-995-1-git-send-email-zajec5@gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348645171.24309.21.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 22:21 +0200, Rafa? Mi?ecki wrote:
> +config MTD_NAND_BCM47XXNFLASH
> +	tristate "Support for NAND flash on BCMA bus"
> +	depends on BCMA_NFLASH && BROKEN
> +	help
> +	  BCMA bus can have various flash memories attached, they are
> +	  registered by bcma as platform devices. This enables driver for
> +	  NAND flash memories.

Could we please merge only non-broken stuff upstream. I understand your
intentions to merge something non-working first with a promise to make
it working later, but I do not think this is an acceptable approach.

Why exactly you mark this one as broken? If it is R/O so far, and
reading works, and you tested it (how?), we can merge it I guess, just
make it clear that it is R/O in Kconfig help text.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/805ddd45/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 03:41:10 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 10:41:10 +0300
Subject: [PATCH 1/4] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1347481275-995-1-git-send-email-zajec5@gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348645270.24309.22.camel@sauron.fi.intel.com>

On Wed, 2012-09-12 at 22:21 +0200, Rafa? Mi?ecki wrote:
> BCMA bus can contain NAND flash memory, it's registered in system as
> platform device. This adds required hooks and place for controler
> specific drivers.
> At this point it doesn't work yet, so it's marked as BROKEN.
> 
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>

If you send the next version of this, would you please base it on
l2-mtd.git tree, to make my job simpler, because otherwise I have to
solve small conflicts.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/c4c3320d/attachment.sig>

From zajec5 at gmail.com  Wed Sep 26 03:41:09 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Wed, 26 Sep 2012 09:41:09 +0200
Subject: [PATCH 1/4] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1348645171.24309.21.camel@sauron.fi.intel.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
 <1348645171.24309.21.camel@sauron.fi.intel.com>
Message-ID: <CACna6ryBwu3BFH=4PrmqnvL1qQdk5xcVCKb2=7UrCSpsvmpK5Q@mail.gmail.com>

2012/9/26 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Wed, 2012-09-12 at 22:21 +0200, Rafa? Mi?ecki wrote:
>> +config MTD_NAND_BCM47XXNFLASH
>> +     tristate "Support for NAND flash on BCMA bus"
>> +     depends on BCMA_NFLASH && BROKEN
>> +     help
>> +       BCMA bus can have various flash memories attached, they are
>> +       registered by bcma as platform devices. This enables driver for
>> +       NAND flash memories.
>
> Could we please merge only non-broken stuff upstream. I understand your
> intentions to merge something non-working first with a promise to make
> it working later, but I do not think this is an acceptable approach.
>
> Why exactly you mark this one as broken? If it is R/O so far, and
> reading works, and you tested it (how?), we can merge it I guess, just
> make it clear that it is R/O in Kconfig help text.

Yes, BROKEN can be dropped from this. I'll resend correct patchset
after checking it with verify/aiaiai (i'm almost done! :) )

-- 
Rafa?


From dedekind1 at gmail.com  Wed Sep 26 03:42:25 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 10:42:25 +0300
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348645345.24309.24.camel@sauron.fi.intel.com>

On Mon, 2012-09-17 at 11:50 +0200, Rafa? Mi?ecki wrote:
> This registers MTD driver for serial flash platform device. Right now it
> supports reading only, writing still has to be implemented.
> 
> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>

Can you please confirm that you tested this and the driver works in R/O
mode just fine. If yes, I would also like to add a note that this is R/O
to the Kconfig text. If it does not even work, I am willing to drop it.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/4ee9cac5/attachment-0001.sig>

From dedekind1 at gmail.com  Wed Sep 26 03:43:30 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 10:43:30 +0300
Subject: [PATCH 1/4] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <CACna6ryBwu3BFH=4PrmqnvL1qQdk5xcVCKb2=7UrCSpsvmpK5Q@mail.gmail.com>
References: <1347481275-995-1-git-send-email-zajec5@gmail.com>
 <1348645171.24309.21.camel@sauron.fi.intel.com>
 <CACna6ryBwu3BFH=4PrmqnvL1qQdk5xcVCKb2=7UrCSpsvmpK5Q@mail.gmail.com>
Message-ID: <1348645410.24309.25.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 09:41 +0200, Rafa? Mi?ecki wrote:
> 2012/9/26 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Wed, 2012-09-12 at 22:21 +0200, Rafa? Mi?ecki wrote:
> >> +config MTD_NAND_BCM47XXNFLASH
> >> +     tristate "Support for NAND flash on BCMA bus"
> >> +     depends on BCMA_NFLASH && BROKEN
> >> +     help
> >> +       BCMA bus can have various flash memories attached, they are
> >> +       registered by bcma as platform devices. This enables driver for
> >> +       NAND flash memories.
> >
> > Could we please merge only non-broken stuff upstream. I understand your
> > intentions to merge something non-working first with a promise to make
> > it working later, but I do not think this is an acceptable approach.
> >
> > Why exactly you mark this one as broken? If it is R/O so far, and
> > reading works, and you tested it (how?), we can merge it I guess, just
> > make it clear that it is R/O in Kconfig help text.
> 
> Yes, BROKEN can be dropped from this. I'll resend correct patchset
> after checking it with verify/aiaiai (i'm almost done! :) )

Great, thanks. Do not forget to tell about R/O in the Kconfig text
please!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/f3554dcf/attachment.sig>

From zajec5 at gmail.com  Wed Sep 26 03:55:14 2012
From: zajec5 at gmail.com (=?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?=)
Date: Wed, 26 Sep 2012 09:55:14 +0200
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <1348645345.24309.24.camel@sauron.fi.intel.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
 <1348645345.24309.24.camel@sauron.fi.intel.com>
Message-ID: <CACna6rwPVzgQ1NA_yN5wdmW=TMw9ZpOLyf69ZSj2yYdK0gsZ1g@mail.gmail.com>

2012/9/26 Artem Bityutskiy <dedekind1 at gmail.com>:
> On Mon, 2012-09-17 at 11:50 +0200, Rafa? Mi?ecki wrote:
>> This registers MTD driver for serial flash platform device. Right now it
>> supports reading only, writing still has to be implemented.
>>
>> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
>
> Can you please confirm that you tested this and the driver works in R/O
> mode just fine. If yes, I would also like to add a note that this is R/O
> to the Kconfig text. If it does not even work, I am willing to drop it.

OFC it works! :) It nicely cooperates with bcm47xxpart (partitions are
detected) and I can read mtd content (bootloader, nvram, etc.).

You're right, we miss info about R/O in Kconfig, I didn't think about this.

-- 
Rafa?


From dedekind1 at gmail.com  Wed Sep 26 04:08:07 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 11:08:07 +0300
Subject: [PATCH] mtd: fsl_ifc_nand: fix cast removes address space of
 expression warnings
In-Reply-To: <20120913185607.af76965cb973dfb1059c842f@freescale.com>
References: <20120913185607.af76965cb973dfb1059c842f@freescale.com>
Message-ID: <1348646887.24309.32.camel@sauron.fi.intel.com>

On Thu, 2012-09-13 at 18:56 -0500, Kim Phillips wrote:
> found by sparse.
> 
> Signed-off-by: Kim Phillips <kim.phillips at freescale.com>

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/acad4a49/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 04:10:58 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 11:10:58 +0300
Subject: [PATCH V3] mtd: basic (read only) driver for BCMA serial flash
In-Reply-To: <CACna6rwPVzgQ1NA_yN5wdmW=TMw9ZpOLyf69ZSj2yYdK0gsZ1g@mail.gmail.com>
References: <1347875449-19318-1-git-send-email-zajec5@gmail.com>
 <1348645345.24309.24.camel@sauron.fi.intel.com>
 <CACna6rwPVzgQ1NA_yN5wdmW=TMw9ZpOLyf69ZSj2yYdK0gsZ1g@mail.gmail.com>
Message-ID: <1348647058.24309.33.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 09:55 +0200, Rafa? Mi?ecki wrote:
> 2012/9/26 Artem Bityutskiy <dedekind1 at gmail.com>:
> > On Mon, 2012-09-17 at 11:50 +0200, Rafa? Mi?ecki wrote:
> >> This registers MTD driver for serial flash platform device. Right now it
> >> supports reading only, writing still has to be implemented.
> >>
> >> Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
> >
> > Can you please confirm that you tested this and the driver works in R/O
> > mode just fine. If yes, I would also like to add a note that this is R/O
> > to the Kconfig text. If it does not even work, I am willing to drop it.
> 
> OFC it works! :) It nicely cooperates with bcm47xxpart (partitions are
> detected) and I can read mtd content (bootloader, nvram, etc.).
> 
> You're right, we miss info about R/O in Kconfig, I didn't think about this.

I've just folded the following changes in:

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index ce6e3d4..27f80cd 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -121,12 +121,12 @@ config MTD_SST25L
          if you want to specify device partitioning.
 
 config MTD_BCM47XXSFLASH
-       tristate "Support for serial flash on BCMA bus"
+       tristate "R/O support for serial flash on BCMA bus"
        depends on BCMA_SFLASH
        help
          BCMA bus can have various flash memories attached, they are
          registered by bcma as platform devices. This enables driver for
-         serial flash memories.
+         serial flash memories (only read-only mode is implemented).
 
 config MTD_SLRAM
        tristate "Uncached system RAM"


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/81d13b0e/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 04:17:52 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 11:17:52 +0300
Subject: [PATCH v2 0/9] add EDO feature for gpmi-nand driver
In-Reply-To: <1347519480-31106-1-git-send-email-b32955@freescale.com>
References: <1347519480-31106-1-git-send-email-b32955@freescale.com>
Message-ID: <1348647472.24309.34.camel@sauron.fi.intel.com>

On Thu, 2012-09-13 at 14:57 +0800, Huang Shijie wrote:
> The ONFI nand supports the EDO (extended data out) feature in 
> asynchronous mode when the host controller(such as gpmi-nand)
> uses a tRC of less then 30ns.
> 
> The gpmi can supports this EDO feature.
> This patch set adds the EDO support the gpmi-nand driver.

I did not review this deeply, but the speed improvements are impressive
and patches look good, so pushed to l2-mtd.git, thanks!


-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/02e85c15/attachment.sig>

From artem.bityutskiy at linux.intel.com  Wed Sep 26 04:24:44 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 11:24:44 +0300
Subject: [GIT PULL] ARM: LPC32xx: core update
In-Reply-To: <5052FE40.2030305@antcom.de>
References: <50488FD6.4080402@antcom.de> <201209131155.16756.arnd@arndb.de>
 <5052FE40.2030305@antcom.de>
Message-ID: <1348647884.24309.35.camel@sauron.fi.intel.com>

On Fri, 2012-09-14 at 11:52 +0200, Roland Stigge wrote:
> Hi Arnd,
> 
> On 13/09/12 13:55, Arnd Bergmann wrote:
> > On Thursday 06 September 2012, Roland Stigge wrote:
> >>       ARM: LPC32xx: Provide DMA filter callbacks via platform data
> > 
> > This patch results in build errors in the for-next branch with lpc32xx_defconfig:
> > 
> > arch/arm/mach-lpc32xx/phy3250.c:40:35: fatal error: linux/mtd/lpc32xx_slc.h: No such file or directory
> > arch/arm/mach-lpc32xx/phy3250.c:41:35: fatal error: linux/mtd/lpc32xx_mlc.h: No such file or directory
> > arch/arm/mach-lpc32xx/phy3250.c:226:15: error: variable 'lpc32xx_slc_data' has initializer but incomplete type
> > arch/arm/mach-lpc32xx/phy3250.c:227:2: error: unknown field 'dma_filter' specified in initializer
> > arch/arm/mach-lpc32xx/phy3250.c:227:2: error: excess elements in struct initializer [-Werror]
> > arch/arm/mach-lpc32xx/phy3250.c:227:2: error: (near initialization for 'lpc32xx_slc_data') [-Werror]
> > arch/arm/mach-lpc32xx/phy3250.c:230:15: error: variable 'lpc32xx_mlc_data' has initializer but incomplete type
> > arch/arm/mach-lpc32xx/phy3250.c:231:2: error: unknown field 'dma_filter' specified in initializer
> > arch/arm/mach-lpc32xx/phy3250.c:231:2: error: excess elements in struct initializer [-Werror]
> > arch/arm/mach-lpc32xx/phy3250.c:231:2: error: (near initialization for 'lpc32xx_mlc_data') [-Werror]
> > 
> > It seems that we're missing a dependency. Which tree did the patch to add
> > these go through? Can we add that to the same branch in arm-soc?
> 
> Right - there is a dependency on l2-mtd.git here.
> 
> Since they didn't request pull for 3.6, there is quite some stuff
> pending in their tree (but I wonder why it isn't already part of
> linux-next, so the above error at least shouldn't occur in linux-next).

It is in linux-next:

[dedekind at sauron linux-next (master)]$ git log --format='%h %an %s' drivers/mtd/ | grep Stigge
562dec8 Roland Stigge mtd: lpc32xx_mlc: Cleanup after DT-only conversion
ad978ee Roland Stigge mtd: lpc32xx_slc: Cleanup after DT-only conversion
7359e4c Roland Stigge mtd: lpc32xx_mlc: Make driver independent of AMBA DMA engine driver
fa5eae7 Roland Stigge mtd: lpc32xx_slc: Make driver independent of AMBA DMA engine driver
79f9df7 Roland Stigge mtd: lpc32xx_mlc: Adjust to pl08x DMA interface changes
314a156 Roland Stigge mtd: lpc32xx_slc: Adjust to pl08x DMA interface changes
70f7cb7 Roland Stigge mtd: add LPC32xx MLC NAND driver
d5842ab Roland Stigge mtd: lpc32xx_slc: Make probe() return -EPROBE_DEFER if necessary
21535ab Roland Stigge mtd: lpc32xx_slc: Use of_get_named_gpio()
2944a44 Roland Stigge mtd: add LPC32xx SLC NAND driver
9d7b4b5 Roland Stigge [MTD] [NAND] Fix refactoring of EDB7312 hwcontrol function.
4a32cfa Roland Stigge [MTD] [NAND] Fix refactoring of EDB7312 hwcontrol function.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/56636377/attachment-0001.sig>

From stigge at antcom.de  Wed Sep 26 04:52:31 2012
From: stigge at antcom.de (Roland Stigge)
Date: Wed, 26 Sep 2012 10:52:31 +0200
Subject: [GIT PULL] ARM: LPC32xx: core update
In-Reply-To: <1348647884.24309.35.camel@sauron.fi.intel.com>
References: <50488FD6.4080402@antcom.de> <201209131155.16756.arnd@arndb.de>
 <5052FE40.2030305@antcom.de> <1348647884.24309.35.camel@sauron.fi.intel.com>
Message-ID: <5062C24F.4090603@antcom.de>

On 09/26/2012 10:24 AM, Artem Bityutskiy wrote:
>> On 13/09/12 13:55, Arnd Bergmann wrote:
>>> On Thursday 06 September 2012, Roland Stigge wrote:
>>>> ARM: LPC32xx: Provide DMA filter callbacks via platform data
>>> 
>>> This patch results in build errors in the for-next branch with
>>> lpc32xx_defconfig:
>>> 
>>> arch/arm/mach-lpc32xx/phy3250.c:40:35: fatal error:
>>> linux/mtd/lpc32xx_slc.h: No such file or directory 
>>> arch/arm/mach-lpc32xx/phy3250.c:41:35: fatal error:
>>> linux/mtd/lpc32xx_mlc.h: No such file or directory 
>>> arch/arm/mach-lpc32xx/phy3250.c:226:15: error: variable
>>> 'lpc32xx_slc_data' has initializer but incomplete type 
>>> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: unknown field
>>> 'dma_filter' specified in initializer 
>>> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: excess elements
>>> in struct initializer [-Werror] 
>>> arch/arm/mach-lpc32xx/phy3250.c:227:2: error: (near
>>> initialization for 'lpc32xx_slc_data') [-Werror] 
>>> arch/arm/mach-lpc32xx/phy3250.c:230:15: error: variable
>>> 'lpc32xx_mlc_data' has initializer but incomplete type 
>>> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: unknown field
>>> 'dma_filter' specified in initializer 
>>> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: excess elements
>>> in struct initializer [-Werror] 
>>> arch/arm/mach-lpc32xx/phy3250.c:231:2: error: (near
>>> initialization for 'lpc32xx_mlc_data') [-Werror]
>>> 
>>> It seems that we're missing a dependency. Which tree did the
>>> patch to add these go through? Can we add that to the same
>>> branch in arm-soc?
>> 
>> Right - there is a dependency on l2-mtd.git here.
>> 
>> Since they didn't request pull for 3.6, there is quite some
>> stuff pending in their tree (but I wonder why it isn't already
>> part of linux-next, so the above error at least shouldn't occur
>> in linux-next).
> 
> It is in linux-next:
> 
> [dedekind at sauron linux-next (master)]$ git log --format='%h %an %s'
> drivers/mtd/ | grep Stigge 562dec8 Roland Stigge mtd: lpc32xx_mlc:
> Cleanup after DT-only conversion ad978ee Roland Stigge mtd:
> lpc32xx_slc: Cleanup after DT-only conversion 7359e4c Roland Stigge
> mtd: lpc32xx_mlc: Make driver independent of AMBA DMA engine
> driver fa5eae7 Roland Stigge mtd: lpc32xx_slc: Make driver
> independent of AMBA DMA engine driver 79f9df7 Roland Stigge mtd:
> lpc32xx_mlc: Adjust to pl08x DMA interface changes 314a156 Roland
> Stigge mtd: lpc32xx_slc: Adjust to pl08x DMA interface changes 
> 70f7cb7 Roland Stigge mtd: add LPC32xx MLC NAND driver d5842ab
> Roland Stigge mtd: lpc32xx_slc: Make probe() return -EPROBE_DEFER
> if necessary 21535ab Roland Stigge mtd: lpc32xx_slc: Use
> of_get_named_gpio() 2944a44 Roland Stigge mtd: add LPC32xx SLC NAND
> driver 9d7b4b5 Roland Stigge [MTD] [NAND] Fix refactoring of
> EDB7312 hwcontrol function. 4a32cfa Roland Stigge [MTD] [NAND] Fix
> refactoring of EDB7312 hwcontrol function.

Good, thanks! Then, the above issue should be gone now.

Please note that there is still the dependency of mtd on mach-lpc32xx.

Roland


From hechtb at googlemail.com  Wed Sep 26 05:05:04 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Wed, 26 Sep 2012 11:05:04 +0200
Subject: [PATCH 1/3] mtd: sh_flctl: Probe SNAND_E flag from NAND chip
Message-ID: <1348650306-15492-1-git-send-email-hechtb@gmail.com>

SNAND_E indicates whether we deal with 512kB or 2048kB page sizes. We
can probe this from the NAND chip itself and don't need to specify it in
the platform data anymore.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe
and the 2 patches posted 3 days ago (09/23)
mtd: sh_flctl: Setup and release DMA channels
and
mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when available

 drivers/mtd/nand/sh_flctl.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 0d90af8..8f0bed1 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -970,6 +970,7 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
 		}
 	} else {
 		flctl->page_size = 1;
+		flctl->flcmncr_base |= SNAND_E;
 		if (chip->chipsize > (128 << 20)) {
 			/* big than 128MB */
 			flctl->rw_ADRCNT = ADRCNT2_E;
-- 
1.7.5.4



From hechtb at googlemail.com  Wed Sep 26 05:05:06 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Wed, 26 Sep 2012 11:05:06 +0200
Subject: [PATCH 3/3] mtd: sh_flctl: Add sh7372 device tree config
In-Reply-To: <1348650306-15492-1-git-send-email-hechtb@gmail.com>
References: <1348650306-15492-1-git-send-email-hechtb@gmail.com>
Message-ID: <1348650306-15492-3-git-send-email-hechtb@gmail.com>

Include the configuration data to set up FLCTL via device tree probing
for the SoC sh7372.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
 drivers/mtd/nand/sh_flctl.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 472c27e..b8b1d52 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -1030,7 +1030,15 @@ struct flctl_soc_config {
 	unsigned use_holden:1;
 };
 
+static struct flctl_soc_config flctl_sh7372_config = {
+	.flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET | SHBUSSEL,
+	.has_hwecc = 1,
+	.use_holden = 1,
+};
+
 static const struct of_device_id of_flctl_match[] = {
+	{ .compatible = "renesas,shmobile-flctl-sh7372",
+				.data = &flctl_sh7372_config },
 	{},
 };
 MODULE_DEVICE_TABLE(of, of_flctl_match);
-- 
1.7.5.4



From hechtb at googlemail.com  Wed Sep 26 05:05:05 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Wed, 26 Sep 2012 11:05:05 +0200
Subject: [PATCH 2/3] mtd: sh_flctl: Add device tree support
In-Reply-To: <1348650306-15492-1-git-send-email-hechtb@gmail.com>
References: <1348650306-15492-1-git-send-email-hechtb@gmail.com>
Message-ID: <1348650306-15492-2-git-send-email-hechtb@gmail.com>

The flctl can now be probed via device tree setup in addition to the
existing platform data way.

SoC specific setup data is set in the .data member of the OF match, so
kept within the driver itself, while board/user specific setup - like
partitioning - is taken from the device tree.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
 drivers/mtd/nand/sh_flctl.c |   84 +++++++++++++++++++++++++++++++++++++++----
 1 files changed, 77 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 8f0bed1..472c27e 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -28,6 +28,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_mtd.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/slab.h>
@@ -1020,6 +1023,65 @@ static irqreturn_t flctl_handle_flste(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+#ifdef CONFIG_OF
+struct flctl_soc_config {
+	unsigned long flcmncr_val;
+	unsigned has_hwecc:1;
+	unsigned use_holden:1;
+};
+
+static const struct of_device_id of_flctl_match[] = {
+	{},
+};
+MODULE_DEVICE_TABLE(of, of_flctl_match);
+
+static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
+{
+	const struct of_device_id *match;
+	struct flctl_soc_config *config;
+	struct sh_flctl_platform_data *pdata;
+	struct device_node *dn = dev->of_node;
+	int ret;
+
+	match = of_match_device(of_flctl_match, dev);
+	if (match)
+		config = (struct flctl_soc_config *)match->data;
+	else {
+		dev_err(dev, "%s: no OF configuration attached\n", __func__);
+		return NULL;
+	}
+
+	pdata = devm_kzalloc(dev, sizeof(struct sh_flctl_platform_data),
+								GFP_KERNEL);
+	if (!pdata) {
+		dev_err(dev, "%s: failed to allocate config data\n", __func__);
+		return NULL;
+	}
+
+	/* set SoC specific options */
+	pdata->flcmncr_val = config->flcmncr_val;
+	pdata->has_hwecc = config->has_hwecc;
+	pdata->use_holden = config->use_holden;
+
+	/* parse user defined options */
+	ret = of_get_nand_bus_width(dn);
+	if (ret == 16)
+		pdata->flcmncr_val |= SEL_16BIT;
+	else if (ret != 8) {
+		dev_err(dev, "%s: invalid bus width\n", __func__);
+		return NULL;
+	}
+
+	return pdata;
+}
+#else /* CONFIG_OF */
+#define of_flctl_match NULL
+static struct sh_flctl_platform_data *flctl_parse_dt(struct device *dev)
+{
+	return NULL;
+}
+#endif /* CONFIG_OF */
+
 static int __devinit flctl_probe(struct platform_device *pdev)
 {
 	struct resource *res;
@@ -1029,12 +1091,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	struct sh_flctl_platform_data *pdata;
 	int ret = -ENXIO;
 	int irq;
-
-	pdata = pdev->dev.platform_data;
-	if (pdata == NULL) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -EINVAL;
-	}
+	struct mtd_part_parser_data ppdata = {};
 
 	flctl = kzalloc(sizeof(struct sh_flctl), GFP_KERNEL);
 	if (!flctl) {
@@ -1066,6 +1123,16 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 		goto err_flste;
 	}
 
+	if (pdev->dev.of_node)
+		pdata = flctl_parse_dt(&pdev->dev);
+	else
+		pdata = pdev->dev.platform_data;
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "no setup data defined\n");
+		return -EINVAL;
+	}
+
 	platform_set_drvdata(pdev, flctl);
 	flctl_mtd = &flctl->mtd;
 	nand = &flctl->chip;
@@ -1108,7 +1175,9 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_chip;
 
-	mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
+	ppdata.of_node = pdev->dev.of_node;
+	ret = mtd_device_parse_register(flctl_mtd, NULL, &ppdata, pdata->parts,
+			pdata->nr_parts);
 
 	return 0;
 
@@ -1142,6 +1211,7 @@ static struct platform_driver flctl_driver = {
 	.driver = {
 		.name	= "sh_flctl",
 		.owner	= THIS_MODULE,
+		.of_match_table = of_flctl_match,
 	},
 };
 
-- 
1.7.5.4



From dedekind1 at gmail.com  Wed Sep 26 05:16:03 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:16:03 +0300
Subject: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any
 write
In-Reply-To: <68738277-B1F2-4455-B8FD-67F2DD9E1310@kernel.crashing.org>
References: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
 <68738277-B1F2-4455-B8FD-67F2DD9E1310@kernel.crashing.org>
Message-ID: <1348650963.24309.38.camel@sauron.fi.intel.com>

On Thu, 2012-09-13 at 07:53 -0500, Kumar Gala wrote:
> > drivers/mtd/nand/fsl_ifc_nand.c |   56 ++++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 55 insertions(+), 1 deletion(-)
> 
> If MTD maintainers ack, I'm happy to pull this in via PPC tree.

Acked-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/13f8970f/attachment.sig>

From Daniel.MONDON at lpgsystems.com  Wed Sep 26 05:16:00 2012
From: Daniel.MONDON at lpgsystems.com (MONDON Daniel)
Date: Wed, 26 Sep 2012 11:16:00 +0200
Subject: ubinize.cfg for NAND with multi ubi devices and multi volume inside
Message-ID: <D604D5FB4D200642AA2FAAE94E39258601AFFFCE@CARAMBAR.lpg.priv>

Hi,

I don't find how to generate my .cfg for the ubinize command.
Perhaps impossible ?

I'v got 1GB NAND with 4 UBI devices.
I want to ubinize some volumes in some UBI devices.

For example : (i've got ubi1_0 to ubi1_3 and ubi4_0 to ubi4_4)
Ubi1_0 (80MiB)
Ubi1_3 (300MiB)
Ubi4_0 (30MiB)
Ubi4_4 (30MiB)

What have i to write in the .cfg file.

With the result, i will use ubiupdatevol to write fs images.

I've got ubinize V1.4.9.

Thanks
Daniel.

   
 



From dedekind1 at gmail.com  Wed Sep 26 05:29:55 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:29:55 +0300
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
Message-ID: <1348651795.24309.49.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 13:42 +0800, Jaya Kumar wrote:
> I think what this means is that after doing the rootfs upgrade using
> ubiupdatevol, I must reboot into a 3rd partition running a minimal OS
> to perform the ubirename of roofs_reserve and then reboot again. This
> step seems expensive to have to boot into a 3rd partition to do the
> rename operation.
> 
> I see someone else also has encountered this,
> http://comments.gmane.org/gmane.linux.drivers.mtd/39415 and solved by
> having a initramfs. I guess I could do that. But still seems messy.

Yes, the way it is currently implemented is:

1. ubirename /dev/ubi0 rootfs rootfs_reserve
2. UBI figures out that old 'rootfs' should be removed.
3. UBI changes the volume table and wipes old rootfs from there,
   and changes name 'rootfs_reserve' to 'rootfs'.

   Now if you have a power cut, you will no longer see the old rootfs
   vloume, only the new one.
4. Then UBI actually deletes the old volume from all the in-memory
   data structures. Obviously, you cannot use this volume at the same
   time.

But this can be improved, I did not think a lot about this, but I guess
if you just skip step 4, it should work. The rename will succeed, but
you will still see the old layout. And only when you reboot, you'll have
the old rootfs deleted and the new one being in place.

Or not even reboot - detach and attach back should be enough. I guess
you can hack this.

Also, I guess the rename path should not open the volume in the
exclusive mode.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/a3798dee/attachment-0001.sig>

From dedekind1 at gmail.com  Wed Sep 26 05:44:30 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:44:30 +0300
Subject: [PATCH] mtd: nand: omap2: Fix the nand-disk led trigger
In-Reply-To: <CANOLnOOfwe1EvG1VHAZbtaC2xAD7_Rc6PqCWrs2cwEqauun8KA@mail.gmail.com>
References: <20120913150614.GC22993@renkinjitsu.usine.8d.com>
 <CANOLnOOfwe1EvG1VHAZbtaC2xAD7_Rc6PqCWrs2cwEqauun8KA@mail.gmail.com>
Message-ID: <1348652670.24309.52.camel@sauron.fi.intel.com>

On Mon, 2012-09-17 at 13:52 +0300, Grazvydas Ignotas wrote:
> On Thu, Sep 13, 2012 at 6:06 PM, Raphael Assenat <raph at 8d.com> wrote:
> > When the omap2 nand flash driver is used, the nand-disk led trigger does not
> > work due to nand_wait_ready not being called.
> 
> I think better solution is just to delete omap_wait() function, which
> is just a copy of nand_wait() without LED and oops handling. If
> waitfunc is not set by the driver, default nand_wait is used by the
> core.

Or if it does really need own wait function, we can re-work the internal
api similarly to what we did to MTD api. Instead of calling
'chip->waitfunc()' directly from everywhere, have a wrapper
'nand_wati()' function, which can do things common to all drivers, and
then actually call the underlying '->waitfunc()'. So in this case, it
can do the LED stuff.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/324ae9d0/attachment.sig>

From artem.bityutskiy at linux.intel.com  Wed Sep 26 05:49:22 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:49:22 +0300
Subject: [PATCH] mtd/nand/docg4: Add missing HAS_IOMEM dependency
In-Reply-To: <1347662469-1604-1-git-send-email-peterhuewe@gmx.de>
References: <1347662469-1604-1-git-send-email-peterhuewe@gmx.de>
Message-ID: <1348652962.24309.53.camel@sauron.fi.intel.com>

On Sat, 2012-09-15 at 00:41 +0200, Peter Huewe wrote:
> While building an allyesconfig for UML I received this error message(s):
>  drivers/mtd/nand/docg4.c: In function 'probe_docg4':
>  drivers/mtd/nand/docg4.c:1272:2: error: implicit declaration of function
>  'ioremap' [-Werror=implicit-function-declaration]
>  drivers/mtd/nand/docg4.c:1272:10: warning: assignment makes pointer from
>  integer without a cast [enabled by default]
>  drivers/mtd/nand/docg4.c:1327:2: error: implicit declaration of function
>  'iounmap' [-Werror=implicit-function-declaration]

Pushed to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/f67a0de6/attachment.sig>

From artem.bityutskiy at linux.intel.com  Wed Sep 26 05:52:38 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:52:38 +0300
Subject: [PATCH] MTD: nandsim: BUG: Fail if overridesize is too big
In-Reply-To: <CACQ1gAg7Kb7v1HZVdF1N2CtmUSGEYJwB+Un2GUJFDX+==6yO8g@mail.gmail.com>
References: <1347452786-10208-1-git-send-email-richard.genoud@gmail.com>
 <CACQ1gAg7Kb7v1HZVdF1N2CtmUSGEYJwB+Un2GUJFDX+==6yO8g@mail.gmail.com>
Message-ID: <1348653158.24309.54.camel@sauron.fi.intel.com>

On Tue, 2012-09-18 at 10:27 +0200, Richard Genoud wrote:
> As this is a bug fix, it should be pushed to 3.6-rc7, shouldn't it ?

Well, it is a fix for an ancient bug, so it is enough to CC the stable
tree and merge this patch normally, I think.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/62a40bc8/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 05:54:08 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 12:54:08 +0300
Subject: [PATCH] mtd: cmdlineparts.c: Codingstyle cleanup
In-Reply-To: <1348043427-5165-1-git-send-email-sr@denx.de>
References: <1348043427-5165-1-git-send-email-sr@denx.de>
Message-ID: <1348653248.24309.55.camel@sauron.fi.intel.com>

On Wed, 2012-09-19 at 10:30 +0200, Stefan Roese wrote:
> The codingstyle of cmdlineparts.c was really ugly. I've run this
> file through Lindent and made some manual tweaks.
> 
> Signed-off-by: Stefan Roese <sr at denx.de>

But it is cleaned-up in the l2-mtd.git tree. Remember to base your
patches on this tree :-)

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/c5db0a75/attachment.sig>

From artem.bityutskiy at linux.intel.com  Wed Sep 26 06:33:11 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 13:33:11 +0300
Subject: [PATCH 01/10] UBI: Add fastmap on-flash data structures
In-Reply-To: <1348511492-91606-2-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
 <1348511492-91606-2-git-send-email-richard@nod.at>
Message-ID: <1348655591.24309.64.camel@sauron.fi.intel.com>

On Mon, 2012-09-24 at 20:31 +0200, Richard Weinberger wrote:
> Add the on-flash data structures neeed by fastmap
> to ubi-media.h
> 
> Signed-off-by: Richard Weinberger <richard at nod.at>

Richard, thanks, here is the deal I suggest

1. I do not really have time to review this in details.
2. I do not want to block this either
3. I want to merge this to 3.7 with come pre-conditions (see below)
   as "Experimental" with a claim that the on-flash format can
   be changed. Something like Linus did for btrfs. Then let people
   play with fastmap. I am sure it'll need changes when people
   try to use it in production.
   
   a. Aiaiai is happy
   b. You provide a section for the mtd web site describing fastmap
   c. It does not break anything when it is disabled
   d. When it is enabled, it also passes the UBI tests

Actually, I want to expose it to linux-next already after step a.
Despite a lot of testing you have already done, I am willing to do some
testing myself as well, so I'll do c. and d. and let you know if there
are issues.

Could you please do b. ?

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/1e3e0999/attachment.sig>

From sachin.kamat at linaro.org  Wed Sep 26 06:46:55 2012
From: sachin.kamat at linaro.org (Sachin Kamat)
Date: Wed, 26 Sep 2012 16:16:55 +0530
Subject: [PATCH] mtd: ofpart: Fix incorrect NULL check in
 parse_ofoldpart_partitions()
In-Reply-To: <1348567033-5418-1-git-send-email-sachin.kamat@linaro.org>
References: <1348567033-5418-1-git-send-email-sachin.kamat@linaro.org>
Message-ID: <CAK9yfHwh466FeAefBUsXGck-wnVrYh9=RUT8bRGMZP0DWs8Ayg@mail.gmail.com>

Hi Artem,

I was hoping if we can have this fix for the 3.6 release.

On 25 September 2012 15:27, Sachin Kamat <sachin.kamat at linaro.org> wrote:
> The pointer returned by kzalloc should be tested for NULL
> to avoid potential NULL pointer dereference later. Incorrect
> pointer was being tested for NULL. Bug introduced by commit fbcf62a3
> (mtd: physmap_of: move parse_obsolete_partitions to become separate
> parser).
> This patch fixes this bug.
>
> Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> Cc: Artem Bityutskiy <artem.bityutskiy at intel.com>
> Signed-off-by: Sachin Kamat <sachin.kamat at linaro.org>
> ---
>  drivers/mtd/ofpart.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mtd/ofpart.c b/drivers/mtd/ofpart.c
> index 64be8f0..d9127e2 100644
> --- a/drivers/mtd/ofpart.c
> +++ b/drivers/mtd/ofpart.c
> @@ -121,7 +121,7 @@ static int parse_ofoldpart_partitions(struct mtd_info *master,
>         nr_parts = plen / sizeof(part[0]);
>
>         *pparts = kzalloc(nr_parts * sizeof(*(*pparts)), GFP_KERNEL);
> -       if (!pparts)
> +       if (!*pparts)
>                 return -ENOMEM;
>
>         names = of_get_property(dp, "partition-names", &plen);
> --
> 1.7.4.1
>



-- 
With warm regards,
Sachin


From ricard.wanderlof at axis.com  Wed Sep 26 06:53:15 2012
From: ricard.wanderlof at axis.com (Ricard Wanderlof)
Date: Wed, 26 Sep 2012 12:53:15 +0200
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <1348651795.24309.49.camel@sauron.fi.intel.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
 <1348651795.24309.49.camel@sauron.fi.intel.com>
Message-ID: <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>


On Wed, 26 Sep 2012, Artem Bityutskiy wrote:

> On Wed, 2012-09-26 at 13:42 +0800, Jaya Kumar wrote:
>> I think what this means is that after doing the rootfs upgrade using
>> ubiupdatevol, I must reboot into a 3rd partition running a minimal OS
>> to perform the ubirename of roofs_reserve and then reboot again. This
>> step seems expensive to have to boot into a 3rd partition to do the
>> rename operation.
>>
>> I see someone else also has encountered this,
>> http://comments.gmane.org/gmane.linux.drivers.mtd/39415 and solved by
>> having a initramfs. I guess I could do that. But still seems messy.
>
> Yes, the way it is currently implemented is:
>
> 1. ubirename /dev/ubi0 rootfs rootfs_reserve
> 2. UBI figures out that old 'rootfs' should be removed.
> 3. UBI changes the volume table and wipes old rootfs from there,
>   and changes name 'rootfs_reserve' to 'rootfs'.
>
>   Now if you have a power cut, you will no longer see the old rootfs
>   vloume, only the new one.
> 4. Then UBI actually deletes the old volume from all the in-memory
>   data structures. Obviously, you cannot use this volume at the same
>   time.
>
> But this can be improved, I did not think a lot about this, but I guess
> if you just skip step 4, it should work. The rename will succeed, but
> you will still see the old layout. And only when you reboot, you'll have
> the old rootfs deleted and the new one being in place.

But the problem is that the first step fails as the system is still 
running, and you can't unmount / while it is up.

> Also, I guess the rename path should not open the volume in the
> exclusive mode.

Yes, that would be a workable solution, if there weren't any other 
disadvantages (e.g. something getting confused by the volume name 
changing, like df).

/Ricard
-- 
Ricard Wolf Wanderl?f                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30


From ricard.wanderlof at axis.com  Wed Sep 26 07:09:29 2012
From: ricard.wanderlof at axis.com (Ricard Wanderlof)
Date: Wed, 26 Sep 2012 13:09:29 +0200
Subject: ubinize.cfg for NAND with multi ubi devices and multi volume
 inside
In-Reply-To: <D604D5FB4D200642AA2FAAE94E39258601AFFFCE@CARAMBAR.lpg.priv>
References: <D604D5FB4D200642AA2FAAE94E39258601AFFFCE@CARAMBAR.lpg.priv>
Message-ID: <alpine.DEB.2.00.1209261307230.19047@lnxricardw.se.axis.com>


On Wed, 26 Sep 2012, MONDON Daniel wrote:

> I don't find how to generate my .cfg for the ubinize command.
> Perhaps impossible ?
>
> I'v got 1GB NAND with 4 UBI devices.
> I want to ubinize some volumes in some UBI devices.
>
> For example : (i've got ubi1_0 to ubi1_3 and ubi4_0 to ubi4_4)
> Ubi1_0 (80MiB)
> Ubi1_3 (300MiB)
> Ubi4_0 (30MiB)
> Ubi4_4 (30MiB)
>
> What have i to write in the .cfg file.
>
> With the result, i will use ubiupdatevol to write fs images.

Ubinize is not intended for use by ubiupdatevol, rather it is intended 
when you need an image to write to raw flash, for instance during 
production. With ubiupdatevol you simply supply the volume images that you 
get from mkfs.ubifs (or the binary blobs if that's what you want to store 
there).

Or do you mean that you already have data in your volumes, and you want to 
create a file system image which you can then write to another device 
using ubiupdatevol? In that case you would use mkfs.ubifs to create a file 
system image from the file system.

/Ricard
-- 
Ricard Wolf Wanderl?f                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30


From dedekind1 at gmail.com  Wed Sep 26 07:11:13 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 14:11:13 +0300
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
 <1348651795.24309.49.camel@sauron.fi.intel.com>
 <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
Message-ID: <1348657873.24309.68.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 12:53 +0200, Ricard Wanderlof wrote:
> On Wed, 26 Sep 2012, Artem Bityutskiy wrote:
> 
> > On Wed, 2012-09-26 at 13:42 +0800, Jaya Kumar wrote:
> >> I think what this means is that after doing the rootfs upgrade using
> >> ubiupdatevol, I must reboot into a 3rd partition running a minimal OS
> >> to perform the ubirename of roofs_reserve and then reboot again. This
> >> step seems expensive to have to boot into a 3rd partition to do the
> >> rename operation.
> >>
> >> I see someone else also has encountered this,
> >> http://comments.gmane.org/gmane.linux.drivers.mtd/39415 and solved by
> >> having a initramfs. I guess I could do that. But still seems messy.
> >
> > Yes, the way it is currently implemented is:
> >
> > 1. ubirename /dev/ubi0 rootfs rootfs_reserve
> > 2. UBI figures out that old 'rootfs' should be removed.
> > 3. UBI changes the volume table and wipes old rootfs from there,
> >   and changes name 'rootfs_reserve' to 'rootfs'.
> >
> >   Now if you have a power cut, you will no longer see the old rootfs
> >   vloume, only the new one.
> > 4. Then UBI actually deletes the old volume from all the in-memory
> >   data structures. Obviously, you cannot use this volume at the same
> >   time.
> >
> > But this can be improved, I did not think a lot about this, but I guess
> > if you just skip step 4, it should work. The rename will succeed, but
> > you will still see the old layout. And only when you reboot, you'll have
> > the old rootfs deleted and the new one being in place.
> 
> But the problem is that the first step fails as the system is still 
> running, and you can't unmount / while it is up.
> 
> > Also, I guess the rename path should not open the volume in the
> > exclusive mode.
> 
> Yes, that would be a workable solution, if there weren't any other 
> disadvantages (e.g. something getting confused by the volume name 
> changing, like df).

Well, what I say is that we only do the changes in the on-flash volume
table. The in-memory data structures are not changed. So nothing should
be confused in theory, except the user :-) Something like I'll send in
the follow-up e-mail, which Jaya can probably try.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/3a5cfa2a/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 07:11:32 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 14:11:32 +0300
Subject: [PATCH] mtd: ofpart: Fix incorrect NULL check in
 parse_ofoldpart_partitions()
In-Reply-To: <CAK9yfHwh466FeAefBUsXGck-wnVrYh9=RUT8bRGMZP0DWs8Ayg@mail.gmail.com>
References: <1348567033-5418-1-git-send-email-sachin.kamat@linaro.org>
 <CAK9yfHwh466FeAefBUsXGck-wnVrYh9=RUT8bRGMZP0DWs8Ayg@mail.gmail.com>
Message-ID: <1348657892.24309.69.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 16:16 +0530, Sachin Kamat wrote:
> Hi Artem,
> 
> I was hoping if we can have this fix for the 3.6 release.

Please, bug dwmw2.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/6a385818/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 07:13:23 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 14:13:23 +0300
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
 <1348651795.24309.49.camel@sauron.fi.intel.com>
 <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
Message-ID: <1348658003.24309.70.camel@sauron.fi.intel.com>

From df2a498002498e52025acf51e0b43064d766aa0a Mon Sep 17 00:00:00 2001
From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
Date: Wed, 26 Sep 2012 14:12:28 +0300
Subject: [PATCH] UBI: allow for delayed rename

Just an experimental patch.

Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
---
 drivers/mtd/ubi/vmt.c |   19 -------------------
 1 file changed, 19 deletions(-)

diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c
index 9169e58..6d7bcd9 100644
--- a/drivers/mtd/ubi/vmt.c
+++ b/drivers/mtd/ubi/vmt.c
@@ -597,25 +597,6 @@ int ubi_rename_volumes(struct ubi_device *ubi, struct list_head *rename_list)
 	struct ubi_rename_entry *re;
 
 	err = ubi_vtbl_rename_volumes(ubi, rename_list);
-	if (err)
-		return err;
-
-	list_for_each_entry(re, rename_list, list) {
-		if (re->remove) {
-			err = ubi_remove_volume(re->desc, 1);
-			if (err)
-				break;
-		} else {
-			struct ubi_volume *vol = re->desc->vol;
-
-			spin_lock(&ubi->volumes_lock);
-			vol->name_len = re->new_name_len;
-			memcpy(vol->name, re->new_name, re->new_name_len + 1);
-			spin_unlock(&ubi->volumes_lock);
-			ubi_volume_notify(ubi, vol, UBI_VOLUME_RENAMED);
-		}
-	}
-
 	if (!err)
 		self_check_volumes(ubi);
 	return err;
-- 
1.7.10.4


-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/669ac9e4/attachment.sig>

From dedekind1 at gmail.com  Wed Sep 26 07:17:54 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 14:17:54 +0300
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <1348658003.24309.70.camel@sauron.fi.intel.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
 <1348651795.24309.49.camel@sauron.fi.intel.com>
 <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
 <1348658003.24309.70.camel@sauron.fi.intel.com>
Message-ID: <1348658274.24309.72.camel@sauron.fi.intel.com>

On Wed, 2012-09-26 at 14:13 +0300, Artem Bityutskiy wrote:
> From df2a498002498e52025acf51e0b43064d766aa0a Mon Sep 17 00:00:00 2001
> From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Date: Wed, 26 Sep 2012 14:12:28 +0300
> Subject: [PATCH] UBI: allow for delayed rename
> 
> Just an experimental patch.
> 
> Signed-off-by: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>

This have a lot of chances to work. If we do this, it would need to be
an extention to the existing ioctl, to preserve the original behaviour.
Something like a "delayed" flag, and then we can implement this in
ubirename as a --delayed option. Surely there may be better names for
this.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/84408e61/attachment.sig>

From artem.bityutskiy at linux.intel.com  Wed Sep 26 08:22:11 2012
From: artem.bityutskiy at linux.intel.com (Artem Bityutskiy)
Date: Wed, 26 Sep 2012 15:22:11 +0300
Subject: UBI: Fastmap request for inclusion (v18)
In-Reply-To: <1348511492-91606-1-git-send-email-richard@nod.at>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
Message-ID: <1348662131.24309.74.camel@sauron.fi.intel.com>

On Mon, 2012-09-24 at 20:31 +0200, Richard Weinberger wrote:
> UBI Fastmap is an optional feature which stores the physical to
> logical eraseblock relations in a checkpoint (called fastmap) to reduce
> the initialization time of UBI. The current init time of UBI is
> proportional to the number of physical erase blocks on the FLASH
> device. With fastmap enabled the scan time is limited to a fixed
> number of blocks.

Aiaiai!

Please, take a look at Aiaiai's complaints below. I did not go through
them myself.

dedekind at blue:~/git/maintaining$ ../aiaiai/aiaiai-concat-mboxes ~/tmp/richard* | ./verify ../linux-ubi gen
Tested the patch(es) on top of the following commits:
311a256 Quick fixes - applied by aiaiai
55393ba UBI: fix trivial typo 'it' => 'is'
cf38aca UBI: load after mtd device drivers
719bb84 UBI: print less

--------------------------------------------------------------------------------

Bisectability test results for configuration "arm-omap2plus_defconfig,arm,arm-unknown-linux-gnueabi-"

Failed to build the following commit for configuration "arm-omap2plus_defconfig"":

cabfa2b UBI: Add fastmap stuff to ubi.h


drivers/mtd/ubi/attach.c: In function 'scan_all':
drivers/mtd/ubi/attach.c:1220:2: error: implicit declaration of function 'ubi_destroy_ai' [-Werror=implicit-function-declaration]
drivers/mtd/ubi/attach.c: At top level:
drivers/mtd/ubi/attach.c:1231:5: error: conflicting types for 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: previous declaration of 'ubi_attach' was here
drivers/mtd/ubi/attach.c:1309:6: warning: no previous prototype for 'ubi_destroy_ai' [-Wmissing-prototypes]
drivers/mtd/ubi/attach.c:1309:6: warning: conflicting types for 'ubi_destroy_ai' [enabled by default]
drivers/mtd/ubi/attach.c:1220:2: note: previous implicit declaration of 'ubi_destroy_ai' was here
cc1: some warnings being treated as errors
make[4]: *** [drivers/mtd/ubi/attach.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "arm-omap2plus_defconfig,arm,arm-unknown-linux-gnueabi-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "i386_defconfig,i386,"

Failed to build the following commit for configuration "i386_defconfig"":

258cfe8 UBI: Add fastmap stuff to ubi.h


drivers/mtd/ubi/build.c: In function ?ubi_attach_mtd_dev?:
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function ?ubi_attach?
In file included from drivers/mtd/ubi/build.c:44:0:
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "i386_defconfig,i386,", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function ?ubi_attach?:
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter ?force_scan? set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function ?find_wl_entry?:
+drivers/mtd/ubi/wl.c:363:27: warning: variable ?prev_e? set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function ?wear_leveling_worker?:
+drivers/mtd/ubi/wl.c:998:6: warning: variable ?anchor? set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "ia64_defconfig,ia64,ia64-linux-"

Failed to build the following commit for configuration "ia64_defconfig"":

f1b826b UBI: Add fastmap stuff to ubi.h


warning: (IA64) selects PM which has unmet direct dependencies (PM_SLEEP || PM_RUNTIME)
warning: (IA64) selects PM which has unmet direct dependencies (PM_SLEEP || PM_RUNTIME)
warning: (IA64) selects PM which has unmet direct dependencies (PM_SLEEP || PM_RUNTIME)
kernel/sys.c: In function 'sys_prctl':
kernel/sys.c:2026:4: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
kernel/module.c: In function 'add_usage_links':
kernel/module.c:1484:6: warning: variable 'nowarn' set but not used [-Wunused-but-set-variable]
kernel/module.c: At top level:
kernel/module.c:3531:6: warning: no previous prototype for 'module_layout' [-Wmissing-prototypes]
drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "ia64_defconfig,ia64,ia64-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "m68k-m5208evb_defconfig,m68k,m68k-linux-"

Failed to build the following commit for configuration "m68k-m5208evb_defconfig"":

638c620 UBI: Add fastmap stuff to ubi.h


kernel/sys.c: In function 'sys_prctl':
kernel/sys.c:2026:4: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "m68k-m5208evb_defconfig,m68k,m68k-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "mips64_defconfig,mips,mips64-linux-"

Failed to build the following commit for configuration "mips64_defconfig"":

d5665b7 UBI: Add fastmap stuff to ubi.h

kernel/sys.c:1365:1: warning: no previous prototype for 'SyS_sethostname' [-Wmissing-prototypes]
kernel/sys.c:1391:1: warning: no previous prototype for 'SyS_gethostname' [-Wmissing-prototypes]
kernel/sys.c:1416:1: warning: no previous prototype for 'SyS_setdomainname' [-Wmissing-prototypes]
kernel/sys.c:1440:1: warning: no previous prototype for 'SyS_getrlimit' [-Wmissing-prototypes]
kernel/sys.c:1459:1: warning: no previous prototype for 'SyS_old_getrlimit' [-Wmissing-prototypes]
kernel/sys.c:1601:1: warning: no previous prototype for 'SyS_prlimit64' [-Wmissing-prototypes]
kernel/sys.c:1641:1: warning: no previous prototype for 'SyS_setrlimit' [-Wmissing-prototypes]
kernel/sys.c:1774:1: warning: no previous prototype for 'SyS_getrusage' [-Wmissing-prototypes]
kernel/sys.c:1782:1: warning: no previous prototype for 'SyS_umask' [-Wmissing-prototypes]
kernel/sys.c:2000:1: warning: no previous prototype for 'SyS_prctl' [-Wmissing-prototypes]
kernel/sys.c: In function 'SYSC_prctl':
kernel/sys.c:2026:4: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
kernel/sys.c: At top level:
kernel/sys.c:2171:1: warning: no previous prototype for 'SyS_getcpu' [-Wmissing-prototypes]
kernel/module.c:769:1: warning: no previous prototype for 'SyS_delete_module' [-Wmissing-prototypes]
kernel/module.c: In function 'add_usage_links':
kernel/module.c:1484:6: warning: variable 'nowarn' set but not used [-Wunused-but-set-variable]
kernel/module.c: At top level:
kernel/module.c:3011:1: warning: no previous prototype for 'SyS_init_module' [-Wmissing-prototypes]
kernel/module.c:3531:6: warning: no previous prototype for 'module_layout' [-Wmissing-prototypes]
drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "mips64_defconfig,mips,mips64-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "mips-bcm63xx_defconfig,mips,mips-linux-"

Failed to build the following commit for configuration "mips-bcm63xx_defconfig"":

aef58e8 UBI: Add fastmap stuff to ubi.h


drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "mips-bcm63xx_defconfig,mips,mips-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "ppc32_defconfig,powerpc,powerpc-linux-"

Failed to build the following commit for configuration "ppc32_defconfig"":

18ae4d4 UBI: Add fastmap stuff to ubi.h


warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "ppc32_defconfig,powerpc,powerpc-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "ppc64_defconfig,powerpc,powerpc64-linux-"

Failed to build the following commit for configuration "ppc64_defconfig"":

d1ad70b UBI: Add fastmap stuff to ubi.h


warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC)
drivers/mtd/ubi/build.c: In function 'ubi_attach_mtd_dev':
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function 'ubi_attach'
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "ppc64_defconfig,powerpc,powerpc64-linux-", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function 'ubi_attach':
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter 'force_scan' set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function 'find_wl_entry':
+drivers/mtd/ubi/wl.c:363:27: warning: variable 'prev_e' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function 'wear_leveling_worker':
+drivers/mtd/ubi/wl.c:998:6: warning: variable 'anchor' set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

Bisectability test results for configuration "x86_64_defconfig,x86_64,"

Failed to build the following commit for configuration "x86_64_defconfig"":

9d3e659 UBI: Add fastmap stuff to ubi.h


drivers/mtd/ubi/build.c: In function ?ubi_attach_mtd_dev?:
drivers/mtd/ubi/build.c:941:2: error: too few arguments to function ?ubi_attach?
In file included from drivers/mtd/ubi/build.c:44:0:
drivers/mtd/ubi/ubi.h:713:5: note: declared here
make[4]: *** [drivers/mtd/ubi/build.o] Error 1

--------------------------------------------------------------------------------

Successfully built configuration "x86_64_defconfig,x86_64,", results:

--- before_patching.log
+++ after_patching.log
@@ @@
+drivers/mtd/ubi/attach.c: In function ?ubi_attach?:
+drivers/mtd/ubi/attach.c:1400:44: warning: parameter ?force_scan? set but not used [-Wunused-but-set-parameter]
@@ @@
+drivers/mtd/ubi/eba.c:1260:2-11: alloc with no test, possible model on line 1270 [coccinelle]
@@ @@
+drivers/mtd/ubi/wl.c: In function ?find_wl_entry?:
+drivers/mtd/ubi/wl.c:363:27: warning: variable ?prev_e? set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c: In function ?wear_leveling_worker?:
+drivers/mtd/ubi/wl.c:998:6: warning: variable ?anchor? set but not used [-Wunused-but-set-variable]
+drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]

--------------------------------------------------------------------------------

checkpatch.pl has some complaints:

--------------------------------------------------------------------------------

checkpatch.pl results for patch "[PATCH 05/10] UBI: Add fastmap bits to build.c"

WARNING:SPLIT_STRING: quoted string split across lines
#151: FILE: drivers/mtd/ubi/build.c:1469:
+MODULE_PARM_DESC(fm_autoconvert, "Set this parameter to enable fastmap "
+                                "automatically on images without a fastmap.");

total: 0 errors, 1 warnings, 133 lines checked

--------------------------------------------------------------------------------

checkpatch.pl results for patch "[PATCH 07/10] UBI: Add fastmap stuff to attach.c"

WARNING:SPLIT_STRING: quoted string split across lines
#113: FILE: drivers/mtd/ubi/attach.c:1009:
+                               ubi_msg("\"delete\" compatible internal volume"
+                                       " %d:%d found, will remove it",

total: 0 errors, 1 warnings, 535 lines checked

--------------------------------------------------------------------------------

checkpatch.pl results for the entire squashed patch-set

WARNING:SPLIT_STRING: quoted string split across lines
#794: FILE: drivers/mtd/ubi/build.c:1469:
+MODULE_PARM_DESC(fm_autoconvert, "Set this parameter to enable fastmap "
+                                "automatically on images without a fastmap.");

WARNING:SPLIT_STRING: quoted string split across lines
#996: FILE: drivers/mtd/ubi/attach.c:1009:
+                               ubi_msg("\"delete\" compatible internal volume"
+                                       " %d:%d found, will remove it",

total: 0 errors, 2 warnings, 3712 lines checked

--------------------------------------------------------------------------------

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120926/43b5dd3c/attachment-0001.sig>

From jayakumar.lkml at gmail.com  Wed Sep 26 08:38:44 2012
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Wed, 26 Sep 2012 20:38:44 +0800
Subject: Offtopic: ubifs and best practice for supporting browser based
 firmware upgrades
In-Reply-To: <1348658003.24309.70.camel@sauron.fi.intel.com>
References: <CADqH6VzVhsGvCCbokjW8TAJSq5Sj33GiHt4gZxOFZaeHtJ4JeQ@mail.gmail.com>
 <1346751620.12610.35.camel@sauron.fi.intel.com>
 <CADqH6Vw0kY=U-jymgpj_JpzLkqLb0JjK7J1C1V6qF_uo-jDFng@mail.gmail.com>
 <1348651795.24309.49.camel@sauron.fi.intel.com>
 <alpine.DEB.2.00.1209261251200.19047@lnxricardw.se.axis.com>
 <1348658003.24309.70.camel@sauron.fi.intel.com>
Message-ID: <CADqH6VxNTns60J6tc5a6SwdoGcetSK5sYF=a5Sf2HxDR+igCLg@mail.gmail.com>

On Wed, Sep 26, 2012 at 7:13 PM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
> From df2a498002498e52025acf51e0b43064d766aa0a Mon Sep 17 00:00:00 2001
> From: Artem Bityutskiy <artem.bityutskiy at linux.intel.com>
> Date: Wed, 26 Sep 2012 14:12:28 +0300
> Subject: [PATCH] UBI: allow for delayed rename
>
> Just an experimental patch.

Thanks Artem. I gave it a quick try.

I applied the patch, flashed new kernel and then attempted to rename
the rootfs-reserve volume to rootfs while running from the rootfs
volume.

root at localhost:/# ubirename /dev/ubi0 rootfs-reserve rootfs
UBI error: ubi_open_volume: cannot open device 0, volume 1, error -16
UBI error: rename_volumes: cannot open volume "rootfs", error -16
ubirename: error!: cannot rename volumes
           error 16 (Device or resource busy)

UBI DBG (pid 1786): ubi_cdev_ioctl: re-name volumes
UBI DBG (pid 1786): rename_volumes: will rename volume 0 from
"rootfs-reserve" to "rootfs"
UBI error: ubi_open_volume: cannot open device 0, volume 1, error -16
UBI error: rename_volumes: cannot open volume "rootfs", error -16

I also tried the reverse, renaming the running rootfs volume to something else.

root at localhost:/# ubirename /dev/ubi0 rootfs rootfsold
UBI error: ubi_open_volume: cannot open device 0, volume 1, error -16
UBI error: rename_volumes: cannot open volume 1, error -16
ubirename: error!: cannot rename volumes
           error 16 (Device or resource busy)
UBI DBG (pid 2600): ubi_cdev_ioctl: re-name volumes
UBI error: ubi_open_volume: cannot open device 0, volume 1, error -16
UBI error: rename_volumes: cannot open volume 1, error -16

I'm guessing I also need to hack the following in rename_volumes:
desc = ubi_open_volume_nm(ubi->ubi_num, re->new_name, UBI_EXCLUSIVE);

I'll try looking at it further tomorrow.

Thanks,
jayakumar


From richard at nod.at  Wed Sep 26 11:51:41 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:41 +0200
Subject: [PATCH 01/10] UBI: Add fastmap on-flash data structures
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-2-git-send-email-richard@nod.at>

Add the on-flash data structures neeed by fastmap
to ubi-media.h

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/ubi-media.h |  137 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 137 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h
index 468ffbc..ac2b24d 100644
--- a/drivers/mtd/ubi/ubi-media.h
+++ b/drivers/mtd/ubi/ubi-media.h
@@ -375,4 +375,141 @@ struct ubi_vtbl_record {
 	__be32  crc;
 } __packed;
 
+/* UBI fastmap on-flash data structures */
+
+#define UBI_FM_SB_VOLUME_ID	(UBI_LAYOUT_VOLUME_ID + 1)
+#define UBI_FM_DATA_VOLUME_ID	(UBI_LAYOUT_VOLUME_ID + 2)
+
+/* fastmap on-flash data structure format version */
+#define UBI_FM_FMT_VERSION	1
+
+#define UBI_FM_SB_MAGIC		0x7B11D69F
+#define UBI_FM_HDR_MAGIC	0xD4B82EF7
+#define UBI_FM_VHDR_MAGIC	0xFA370ED1
+#define UBI_FM_POOL_MAGIC	0x67AF4D08
+#define UBI_FM_EBA_MAGIC	0xf0c040a8
+
+/* A fastmap supber block can be located between PEB 0 and
+ * UBI_FM_MAX_START */
+#define UBI_FM_MAX_START	64
+
+/* A fastmap can use up to UBI_FM_MAX_BLOCKS PEBs */
+#define UBI_FM_MAX_BLOCKS	32
+
+/* 5% of the total number of PEBs have to be scanned while attaching
+ * from a fastmap.
+ * But the size of this pool is limited to be between UBI_FM_MIN_POOL_SIZE and
+ * UBI_FM_MAX_POOL_SIZE */
+#define UBI_FM_MIN_POOL_SIZE	8
+#define UBI_FM_MAX_POOL_SIZE	256
+
+#define UBI_FM_WL_POOL_SIZE	25
+
+/**
+ * struct ubi_fm_sb - UBI fastmap super block
+ * @magic: fastmap super block magic number (%UBI_FM_SB_MAGIC)
+ * @version: format version of this fastmap
+ * @data_crc: CRC over the fastmap data
+ * @used_blocks: number of PEBs used by this fastmap
+ * @block_loc: an array containing the location of all PEBs of the fastmap
+ * @block_ec: the erase counter of each used PEB
+ * @sqnum: highest sequence number value at the time while taking the fastmap
+ *
+ */
+struct ubi_fm_sb {
+	__be32 magic;
+	__u8 version;
+	__u8 padding1[3];
+	__be32 data_crc;
+	__be32 used_blocks;
+	__be32 block_loc[UBI_FM_MAX_BLOCKS];
+	__be32 block_ec[UBI_FM_MAX_BLOCKS];
+	__be64 sqnum;
+	__u8 padding2[32];
+} __packed;
+
+/**
+ * struct ubi_fm_hdr - header of the fastmap data set
+ * @magic: fastmap header magic number (%UBI_FM_HDR_MAGIC)
+ * @free_peb_count: number of free PEBs known by this fastmap
+ * @used_peb_count: number of used PEBs known by this fastmap
+ * @scrub_peb_count: number of to be scrubbed PEBs known by this fastmap
+ * @bad_peb_count: number of bad PEBs known by this fastmap
+ * @erase_peb_count: number of bad PEBs which have to be erased
+ * @vol_count: number of UBI volumes known by this fastmap
+ */
+struct ubi_fm_hdr {
+	__be32 magic;
+	__be32 free_peb_count;
+	__be32 used_peb_count;
+	__be32 scrub_peb_count;
+	__be32 bad_peb_count;
+	__be32 erase_peb_count;
+	__be32 vol_count;
+	__u8 padding[4];
+} __packed;
+
+/* struct ubi_fm_hdr is followed by two struct ubi_fm_scan_pool */
+
+/**
+ * struct ubi_fm_scan_pool - Fastmap pool PEBs to be scanned while attaching
+ * @magic: pool magic numer (%UBI_FM_POOL_MAGIC)
+ * @size: current pool size
+ * @max_size: maximal pool size
+ * @pebs: an array containing the location of all PEBs in this pool
+ */
+struct ubi_fm_scan_pool {
+	__be32 magic;
+	__be16 size;
+	__be16 max_size;
+	__be32 pebs[UBI_FM_MAX_POOL_SIZE];
+	__be32 padding[4];
+} __packed;
+
+/* ubi_fm_scan_pool is followed by nfree+nused struct ubi_fm_ec records */
+
+/**
+ * struct ubi_fm_ec - stores the erase counter of a PEB
+ * @pnum: PEB number
+ * @ec: ec of this PEB
+ */
+struct ubi_fm_ec {
+	__be32 pnum;
+	__be32 ec;
+} __packed;
+
+/**
+ * struct ubi_fm_volhdr - Fastmap volume header
+ * it identifies the start of an eba table
+ * @magic: Fastmap volume header magic number (%UBI_FM_VHDR_MAGIC)
+ * @vol_id: volume id of the fastmapped volume
+ * @vol_type: type of the fastmapped volume
+ * @data_pad: data_pad value of the fastmapped volume
+ * @used_ebs: number of used LEBs within this volume
+ * @last_eb_bytes: number of bytes used in the last LEB
+ */
+struct ubi_fm_volhdr {
+	__be32 magic;
+	__be32 vol_id;
+	__u8 vol_type;
+	__u8 padding1[3];
+	__be32 data_pad;
+	__be32 used_ebs;
+	__be32 last_eb_bytes;
+	__u8 padding2[8];
+} __packed;
+
+/* struct ubi_fm_volhdr is followed by one struct ubi_fm_eba records */
+
+/**
+ * struct ubi_fm_eba - denotes an association beween a PEB and LEB
+ * @magic: EBA table magic number
+ * @reserved_pebs: number of table entries
+ * @pnum: PEB number of LEB (LEB is the index)
+ */
+struct ubi_fm_eba {
+	__be32 magic;
+	__be32 reserved_pebs;
+	__be32 pnum[0];
+} __packed;
 #endif /* !__UBI_MEDIA_H__ */
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:40 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:40 +0200
Subject: UBI: Fastmap request for inclusion (v19)
Message-ID: <1348674710-102885-1-git-send-email-richard@nod.at>

UBI Fastmap is an optional feature which stores the physical to
logical eraseblock relations in a checkpoint (called fastmap) to reduce
the initialization time of UBI. The current init time of UBI is
proportional to the number of physical erase blocks on the FLASH
device. With fastmap enabled the scan time is limited to a fixed
number of blocks.

Fastmap does not affect any of the existing UBI robustness
features and in fact the fastmap code falls back to scanning
mode when the found fastmap is corrupted.

A fastmap consists of two elements:

1) A primary super block, which contains merrily a pointer to the
   erase block(s) which hold the real fastmap data.

   This super block is guaranteed to be held within the first 64
   eraseblocks of a device.

2) The secondary fastmap blocks, which contain the real
   fastmap data (physical to logical eraseblock relations,
   erase counts, sequence numbers ...)

   Aside of that the fastmap data contains a list of blocks
   which belong to the active working pool. The active working pool is
   a fixed number of blocks to be used by the WL sub-system itself and the
   layer on top of UBI, which can be modified before the next fastmap
   is written to FLASH. These blocks need to be scanned in the
   conventional UBI scan mode.

   The reason for these pool blocks is to reduce the fastmap
   updates to the necessary minimum to avoid accelerated device
   wearout in scenarios where data changes rapidly. The fastmap
   data is updated whenever a working pool runs out of blocks.

So the fastmap scan consists of the following steps:

   1) Find the fastmap super block block by scanning the start of the
      device.

   2) Read the real fastmap data and construct the UBI device info
      structures.

   3) Scan the pool blocks.

The fastmap functionality is fully compatible with existing UBI
deployments. If no fastmap blocks can be found then the device is
scanned and the fastmap blocks are created from the scanned
information.

Changes sinze v18:
   - Aiaiai uncovered some issues, now the patch set is fully bisectable,
     all compiler warnings have been fixed (set but unused variable),
     coccinelle found a missing check for kmalloc()'s return value.
     
     "drivers/mtd/ubi/wl.c:284:3-9: preceding lock on line 282 [coccinelle]"
     is a false positive.

Changes since v17:

   - UBI reserves now PEBs to hold two fastmaps. It is guaranteed that
     each LEB has a corresponding PEB which can be used by an user.

   - Fastmap is automatically disabled if the FLASH devices has less than 64 PEBs

   - Fastmap is only available if CONFIG_MTD_UBI_FASTMAP is enabled.
     It is per default N. If fastmap has proven stable over some time we can
     remove CONFIG_MTD_UBI_FASTMAP and the corresponding #ifdefs.
     Even with CONFIG_MTD_UBI_FASTMAP=Y UBI will not automatically
     install a fastmap on existing images.
     This behavior is controlled by the fm_autoconvert UBI module parameter.
     Only if set to 1 UBI will install a fastmap automatically.
     By default it will use the fastmap only if one is found.

     So, if you want to test fastmap enable CONFIG_MTD_UBI_FASTMAP and
     set  fm_autoconvert to 1.
     If the device was attached by a fastmap you'll observe the following log
     message while attaching: "UBI: attached by fastmap".

State of fastmap:

We (linutronix gmbh) did numerous tests and are not aware of any issue or
regression so far. The tests have been done on real hardware and simulators
(nandsim and mtdram). Of course with and without bitflip emulation enabled
and on NAND "bad" devices with bad blocks, bitflips, IO erros, ...
The tests consisted of mtd-util's ubi-tests, my fastmap torture script[1]
and real world use cases.

Each test run was done with the following configurations:
- CONFIG_MTD_UBI_FASTMAP=n
To verify that traditional UBI works fine.

- CONFIG_MTD_UBI_FASTMAP=y, fm_autoconvert=0
In this configuration the fastmap pool mechanism is active but
no fastmap is written to non-fastmap devices.

- CONFIG_MTD_UBI_FASTMAP=y, fm_autoconvert=1
Fastmap is enabled and non-fastmap devices get fastmap enabled.
Either at detach time or while writing.

I hope the MTD community do will also test fastmap in many different situations.
Bug reports are welcome!

Future work:

- Currently fastmap's powercut policy is that it will fall back to scanning mode if
  a power cut happened while writing the fastmap. If users really need fast attaching
  also after a power cut we could use the adjacent blocks mechanism for writing fastmap.
- Add fastmap support to ubinize
- If fastmap has proven stable, we can remove CONFIG_MTD_UBI_FASTMAP
  and enable it per default.

This patch set is based on artems ubi repository:
git://git.infradead.org/linux-ubi.git

Thanks to the folks at CELF who sponsored this work!

Thanks,
//richard

[1]
http://lists.infradead.org/pipermail/linux-mtd/2012-June/042347.html

 MAINTAINERS                 |    6 +
 drivers/mtd/ubi/Kconfig     |   20 ++
 drivers/mtd/ubi/Makefile    |    1 +
 drivers/mtd/ubi/attach.c    |  386 +++++++++++++++++++---------
 drivers/mtd/ubi/build.c     |   70 +++++-
 drivers/mtd/ubi/eba.c       |  126 +++++++++-
 drivers/mtd/ubi/ubi-media.h |  137 ++++++++++
 drivers/mtd/ubi/ubi.h       |  118 +++++++++-
 drivers/mtd/ubi/wl.c        |  599 ++++++++++++++++++++++++++++++++++++++-----
 9 files changed, 1252 insertions(+), 211 deletions(-)

[PATCH 01/10] UBI: Add fastmap on-flash data structures
[PATCH 02/10] UBI: Add fastmap stuff to ubi.h
[PATCH 03/10] UBI: Export next_sqnum()
[PATCH 04/10] UBI: Add self_check_eba()
[PATCH 05/10] UBI: Add fastmap bits to build.c
[PATCH 06/10] UBI: Wire-up ->fm_sem
[PATCH 07/10] UBI: Add fastmap stuff to attach.c
[PATCH 08/10] UBI: Add fastmap support to the WL sub-system
[PATCH 09/10] UBI: Add fastmap core
[PATCH 10/10] UBI: Wire-up fastmap


From richard at nod.at  Wed Sep 26 11:51:46 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:46 +0200
Subject: [PATCH 06/10] UBI: Wire-up ->fm_sem
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-7-git-send-email-richard@nod.at>

Fastmap uses ->fm_sem to stop EBA changes while writing
a new fastmap.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index d56ae1c..0e11671 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -340,7 +340,9 @@ int ubi_eba_unmap_leb(struct ubi_device *ubi, struct ubi_volume *vol,
 
 	dbg_eba("erase LEB %d:%d, PEB %d", vol_id, lnum, pnum);
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = UBI_LEB_UNMAPPED;
+	up_read(&ubi->fm_sem);
 	err = ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 0);
 
 out_unlock:
@@ -548,7 +550,9 @@ retry:
 	mutex_unlock(&ubi->buf_mutex);
 	ubi_free_vid_hdr(ubi, vid_hdr);
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = new_pnum;
+	up_read(&ubi->fm_sem);
 	ubi_wl_put_peb(ubi, vol_id, lnum, pnum, 1);
 
 	ubi_msg("data was successfully recovered");
@@ -665,7 +669,9 @@ retry:
 		}
 	}
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 	leb_write_unlock(ubi, vol_id, lnum);
 	ubi_free_vid_hdr(ubi, vid_hdr);
@@ -783,7 +789,9 @@ retry:
 	}
 
 	ubi_assert(vol->eba_tbl[lnum] < 0);
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 	leb_write_unlock(ubi, vol_id, lnum);
 	ubi_free_vid_hdr(ubi, vid_hdr);
@@ -904,7 +912,9 @@ retry:
 			goto out_leb_unlock;
 	}
 
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = pnum;
+	up_read(&ubi->fm_sem);
 
 out_leb_unlock:
 	leb_write_unlock(ubi, vol_id, lnum);
@@ -1151,7 +1161,9 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 	}
 
 	ubi_assert(vol->eba_tbl[lnum] == from);
+	down_read(&ubi->fm_sem);
 	vol->eba_tbl[lnum] = to;
+	up_read(&ubi->fm_sem);
 
 out_unlock_buf:
 	mutex_unlock(&ubi->buf_mutex);
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:43 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:43 +0200
Subject: [PATCH 03/10] UBI: Export next_sqnum()
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-4-git-send-email-richard@nod.at>

Fastmap needs next_sqnum(), rename it to ubi_next_sqnum()
and make it non-static.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index a26d7d2..0910c2c 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -57,7 +57,7 @@
  * global sequence counter value. It also increases the global sequence
  * counter.
  */
-static unsigned long long next_sqnum(struct ubi_device *ubi)
+unsigned long long ubi_next_sqnum(struct ubi_device *ubi)
 {
 	unsigned long long sqnum;
 
@@ -521,7 +521,7 @@ retry:
 		goto out_put;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	err = ubi_io_write_vid_hdr(ubi, new_pnum, vid_hdr);
 	if (err)
 		goto write_error;
@@ -632,7 +632,7 @@ int ubi_eba_write_leb(struct ubi_device *ubi, struct ubi_volume *vol, int lnum,
 	}
 
 	vid_hdr->vol_type = UBI_VID_DYNAMIC;
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -692,7 +692,7 @@ write_error:
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -745,7 +745,7 @@ int ubi_eba_write_leb_st(struct ubi_device *ubi, struct ubi_volume *vol,
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -810,7 +810,7 @@ write_error:
 		return err;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -862,7 +862,7 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol,
 	if (err)
 		goto out_mutex;
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	vid_hdr->vol_id = cpu_to_be32(vol_id);
 	vid_hdr->lnum = cpu_to_be32(lnum);
 	vid_hdr->compat = ubi_get_compat(ubi, vol_id);
@@ -930,7 +930,7 @@ write_error:
 		goto out_leb_unlock;
 	}
 
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 	ubi_msg("try another PEB");
 	goto retry;
 }
@@ -1089,7 +1089,7 @@ int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 		vid_hdr->data_size = cpu_to_be32(data_size);
 		vid_hdr->data_crc = cpu_to_be32(crc);
 	}
-	vid_hdr->sqnum = cpu_to_be64(next_sqnum(ubi));
+	vid_hdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
 
 	err = ubi_io_write_vid_hdr(ubi, to, vid_hdr);
 	if (err) {
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:44 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:44 +0200
Subject: [PATCH 04/10] UBI: Add self_check_eba()
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-5-git-send-email-richard@nod.at>

self_check_eba() compares two ubi_attach_info objects.
Fastmap uses this function for self checks.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/eba.c |   96 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c
index 0910c2c..d56ae1c 100644
--- a/drivers/mtd/ubi/eba.c
+++ b/drivers/mtd/ubi/eba.c
@@ -1202,6 +1202,102 @@ static void print_rsvd_warning(struct ubi_device *ubi,
 }
 
 /**
+ * self_check_eba - run a self check on the EBA table constructed by fastmap.
+ * @ubi: UBI device description object
+ * @ai_fastmap: UBI attach info object created by fastmap
+ * @ai_scan: UBI attach info object created by scanning
+ *
+ * Returns < 0 in case of an internal error, 0 otherwise.
+ * If a bad EBA table entry was found it will be printed out and
+ * ubi_assert() triggers.
+ */
+int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap,
+		   struct ubi_attach_info *ai_scan)
+{
+	int i, j, num_volumes, ret = 0;
+	int **scan_eba, **fm_eba;
+	struct ubi_ainf_volume *av;
+	struct ubi_volume *vol;
+	struct ubi_ainf_peb *aeb;
+	struct rb_node *rb;
+
+	num_volumes = ubi->vtbl_slots + UBI_INT_VOL_COUNT;
+
+	scan_eba = kmalloc(sizeof(*scan_eba) * num_volumes, GFP_KERNEL);
+	if (!scan_eba)
+		return -ENOMEM;
+
+	fm_eba = kmalloc(sizeof(*fm_eba) * num_volumes, GFP_KERNEL);
+	if (!fm_eba) {
+		kfree(scan_eba);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < num_volumes; i++) {
+		vol = ubi->volumes[i];
+		if (!vol)
+			continue;
+
+		scan_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**scan_eba),
+				      GFP_KERNEL);
+		if (!scan_eba[i]) {
+			ret = -ENOMEM;
+			goto out_free;
+		}
+
+		fm_eba[i] = kmalloc(vol->reserved_pebs * sizeof(**fm_eba),
+				    GFP_KERNEL);
+		if (!fm_eba[i]) {
+			ret = -ENOMEM;
+			goto out_free;
+		}
+
+		for (j = 0; j < vol->reserved_pebs; j++)
+			scan_eba[i][j] = fm_eba[i][j] = UBI_LEB_UNMAPPED;
+
+		av = ubi_find_av(ai_scan, idx2vol_id(ubi, i));
+		if (!av)
+			continue;
+
+		ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb)
+			scan_eba[i][aeb->lnum] = aeb->pnum;
+
+		av = ubi_find_av(ai_fastmap, idx2vol_id(ubi, i));
+		if (!av)
+			continue;
+
+		ubi_rb_for_each_entry(rb, aeb, &av->root, u.rb)
+			fm_eba[i][aeb->lnum] = aeb->pnum;
+
+		for (j = 0; j < vol->reserved_pebs; j++) {
+			if (scan_eba[i][j] != fm_eba[i][j]) {
+				if (scan_eba[i][j] == UBI_LEB_UNMAPPED ||
+					fm_eba[i][j] == UBI_LEB_UNMAPPED)
+					continue;
+
+				ubi_err("LEB:%i:%i is PEB:%i instead of %i!",
+					vol->vol_id, i, fm_eba[i][j],
+					scan_eba[i][j]);
+				ubi_assert(0);
+			}
+		}
+	}
+
+out_free:
+	for (i = 0; i < num_volumes; i++) {
+		if (!ubi->volumes[i])
+			continue;
+
+		kfree(scan_eba[i]);
+		kfree(fm_eba[i]);
+	}
+
+	kfree(scan_eba);
+	kfree(fm_eba);
+	return ret;
+}
+
+/**
  * ubi_eba_init - initialize the EBA sub-system using attaching information.
  * @ubi: UBI device description object
  * @ai: attaching information
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:45 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:45 +0200
Subject: [PATCH 05/10] UBI: Add fastmap bits to build.c
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-6-git-send-email-richard@nod.at>

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/build.c |   68 ++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 65 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index 3497703..c9b99be 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -76,7 +76,10 @@ static int __initdata mtd_devs;
 
 /* MTD devices specification parameters */
 static struct mtd_dev_param __initdata mtd_dev_param[UBI_MAX_DEVICES];
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/* UBI module parameter to enable fastmap automatically on non-fastmap images */
+static bool fm_autoconvert;
+#endif
 /* Root UBI "class" object (corresponds to '/<sysfs>/class/ubi/') */
 struct class *ubi_class;
 
@@ -153,6 +156,19 @@ int ubi_volume_notify(struct ubi_device *ubi, struct ubi_volume *vol, int ntype)
 
 	ubi_do_get_device_info(ubi, &nt.di);
 	ubi_do_get_volume_info(ubi, vol, &nt.vi);
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	switch (ntype) {
+	case UBI_VOLUME_ADDED:
+	case UBI_VOLUME_REMOVED:
+	case UBI_VOLUME_RESIZED:
+	case UBI_VOLUME_RENAMED:
+		if (ubi_update_fastmap(ubi)) {
+			ubi_err("Unable to update fastmap!");
+			ubi_ro_mode(ubi);
+		}
+	}
+#endif
 	return blocking_notifier_call_chain(&ubi_notifiers, ntype, &nt);
 }
 
@@ -918,10 +934,40 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	ubi->vid_hdr_offset = vid_hdr_offset;
 	ubi->autoresize_vol_id = -1;
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	ubi->fm_pool.used = ubi->fm_pool.size = 0;
+	ubi->fm_wl_pool.used = ubi->fm_wl_pool.size = 0;
+
+	/*
+	 * fm_pool.max_size is 5% of the total number of PEBs but it's also
+	 * between UBI_FM_MAX_POOL_SIZE and UBI_FM_MIN_POOL_SIZE.
+	 */
+	ubi->fm_pool.max_size = min(((int)mtd_div_by_eb(ubi->mtd->size,
+		ubi->mtd) / 100) * 5, UBI_FM_MAX_POOL_SIZE);
+	if (ubi->fm_pool.max_size < UBI_FM_MIN_POOL_SIZE)
+		ubi->fm_pool.max_size = UBI_FM_MIN_POOL_SIZE;
+
+	ubi->fm_wl_pool.max_size = UBI_FM_WL_POOL_SIZE;
+	ubi->fm_disabled = !fm_autoconvert;
+
+	if (!ubi->fm_disabled && (int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd)
+	    <= UBI_FM_MAX_START) {
+		ubi_err("More than %i PEBs are needed for fastmap, sorry.",
+			UBI_FM_MAX_START);
+		ubi->fm_disabled = 1;
+	}
+
+	ubi_msg("default fastmap pool size: %d", ubi->fm_pool.max_size);
+	ubi_msg("default fastmap WL pool size: %d", ubi->fm_wl_pool.max_size);
+#else
+	ubi->fm_disabled = 1;
+#endif
 	mutex_init(&ubi->buf_mutex);
 	mutex_init(&ubi->ckvol_mutex);
 	mutex_init(&ubi->device_mutex);
 	spin_lock_init(&ubi->volumes_lock);
+	mutex_init(&ubi->fm_mutex);
+	init_rwsem(&ubi->fm_sem);
 
 	ubi_msg("attaching mtd%d to ubi%d", mtd->index, ubi_num);
 
@@ -934,6 +980,12 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	if (!ubi->peb_buf)
 		goto out_free;
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	ubi->fm_size = ubi_calc_fm_size(ubi);
+	ubi->fm_buf = vzalloc(ubi->fm_size);
+	if (!ubi->fm_buf)
+		goto out_free;
+#endif
 	err = ubi_debugging_init_dev(ubi);
 	if (err)
 		goto out_free;
@@ -1012,6 +1064,7 @@ out_debugging:
 	ubi_debugging_exit_dev(ubi);
 out_free:
 	vfree(ubi->peb_buf);
+	vfree(ubi->fm_buf);
 	if (ref)
 		put_device(&ubi->dev);
 	else
@@ -1061,7 +1114,11 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
 	ubi_assert(ubi_num == ubi->ubi_num);
 	ubi_notify_all(ubi, UBI_VOLUME_REMOVED, NULL);
 	ubi_msg("detaching mtd%d from ubi%d", ubi->mtd->index, ubi_num);
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* If we don't write a new fastmap at detach time we lose all
+	 * EC updates that have been made since the last written fastmap. */
+	ubi_update_fastmap(ubi);
+#endif
 	/*
 	 * Before freeing anything, we have to stop the background thread to
 	 * prevent it from doing anything on this device while we are freeing.
@@ -1077,12 +1134,14 @@ int ubi_detach_mtd_dev(int ubi_num, int anyway)
 
 	ubi_debugfs_exit_dev(ubi);
 	uif_close(ubi);
+
 	ubi_wl_close(ubi);
 	ubi_free_internal_volumes(ubi);
 	vfree(ubi->vtbl);
 	put_mtd_device(ubi->mtd);
 	ubi_debugging_exit_dev(ubi);
 	vfree(ubi->peb_buf);
+	vfree(ubi->fm_buf);
 	ubi_msg("mtd%d is detached from ubi%d", ubi->mtd->index, ubi->ubi_num);
 	put_device(&ubi->dev);
 	return 0;
@@ -1404,7 +1463,10 @@ MODULE_PARM_DESC(mtd, "MTD devices to attach. Parameter format: mtd=<name|num|pa
 		      "Example 2: mtd=content,1984 mtd=4 - attach MTD device with name \"content\" using VID header offset 1984, and MTD device number 4 with default VID header offset.\n"
 		      "Example 3: mtd=/dev/mtd1,0,25 - attach MTD device /dev/mtd1 using default VID header offset and reserve 25*nand_size_in_blocks/1024 erase blocks for bad block handling.\n"
 		      "\t(e.g. if the NAND *chipset* has 4096 PEB, 100 will be reserved for this UBI device).");
-
+#ifdef CONFIG_MTD_UBI_FASTMAP
+module_param(fm_autoconvert, bool, 0644);
+MODULE_PARM_DESC(fm_autoconvert, "Set this parameter to enable fastmap automatically on images without a fastmap.");
+#endif
 MODULE_VERSION(__stringify(UBI_VERSION));
 MODULE_DESCRIPTION("UBI - Unsorted Block Images");
 MODULE_AUTHOR("Artem Bityutskiy");
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:42 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:42 +0200
Subject: [PATCH 02/10] UBI: Add fastmap stuff to ubi.h
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-3-git-send-email-richard@nod.at>

This patch adds fastmap specific data structures to ubi.h.
It moves also struct ubi_work to ubi.h as it is now needed
for more than one c file.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/ubi.h |  116 ++++++++++++++++++++++++++++++++++++++++++++++++-
 drivers/mtd/ubi/wl.c  |   24 ----------
 2 files changed, 115 insertions(+), 25 deletions(-)

diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index 383ee43..b0d3ba2 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -133,6 +133,17 @@ enum {
 	MOVE_RETRY,
 };
 
+/*
+ * Return codes of the fastmap sub-system
+ *
+ * UBI_NO_FASTMAP: No fastmap super block was found
+ * UBI_BAD_FASTMAP: A fastmap was found but it's unusable
+ */
+enum {
+	UBI_NO_FASTMAP = 1,
+	UBI_BAD_FASTMAP,
+};
+
 /**
  * struct ubi_wl_entry - wear-leveling entry.
  * @u.rb: link in the corresponding (free/used) RB-tree
@@ -199,6 +210,41 @@ struct ubi_rename_entry {
 struct ubi_volume_desc;
 
 /**
+ * struct ubi_fastmap_layout - in-memory fastmap data structure.
+ * @e: PEBs used by the current fastmap
+ * @to_be_tortured: if non-zero tortured this PEB
+ * @used_blocks: number of used PEBs
+ * @max_pool_size: maximal size of the user pool
+ * @max_wl_pool_size: maximal size of the pool used by the WL sub-system
+ */
+struct ubi_fastmap_layout {
+	struct ubi_wl_entry *e[UBI_FM_MAX_BLOCKS];
+	int to_be_tortured[UBI_FM_MAX_BLOCKS];
+	int used_blocks;
+	int max_pool_size;
+	int max_wl_pool_size;
+};
+
+/**
+ * struct ubi_fm_pool - in-memory fastmap pool
+ * @pebs: PEBs in this pool
+ * @used: number of used PEBs
+ * @size: total number of PEBs in this pool
+ * @max_size: maximal size of the pool
+ *
+ * A pool gets filled with up to max_size.
+ * If all PEBs within the pool are used a new fastmap will be written
+ * to the flash and the pool gets refilled with empty PEBs.
+ *
+ */
+struct ubi_fm_pool {
+	int pebs[UBI_FM_MAX_POOL_SIZE];
+	int used;
+	int size;
+	int max_size;
+};
+
+/**
  * struct ubi_volume - UBI volume description data structure.
  * @dev: device object to make use of the the Linux device model
  * @cdev: character device object to create character device
@@ -333,9 +379,21 @@ struct ubi_wl_entry;
  * @ltree: the lock tree
  * @alc_mutex: serializes "atomic LEB change" operations
  *
+ * @fm_disabled: non-zero if fastmap is disabled (default)
+ * @fm: in-memory data structure of the currently used fastmap
+ * @fm_pool: in-memory data structure of the fastmap pool
+ * @fm_wl_pool: in-memory data structure of the fastmap pool used by the WL
+ *		sub-system
+ * @fm_mutex: serializes ubi_update_fastmap() and protects @fm_buf
+ * @fm_buf: vmalloc()'d buffer which holds the raw fastmap
+ * @fm_size: fastmap size in bytes
+ * @fm_sem: allows ubi_update_fastmap() to block EBA table changes
+ * @fm_work: fastmap work queue
+ *
  * @used: RB-tree of used physical eraseblocks
  * @erroneous: RB-tree of erroneous used physical eraseblocks
  * @free: RB-tree of free physical eraseblocks
+ * @free_count: Contains the number of elements in @free
  * @scrub: RB-tree of physical eraseblocks which need scrubbing
  * @pq: protection queue (contain physical eraseblocks which are temporarily
  *      protected from the wear-leveling worker)
@@ -426,10 +484,22 @@ struct ubi_device {
 	struct rb_root ltree;
 	struct mutex alc_mutex;
 
+	/* Fastmap stuff */
+	int fm_disabled;
+	struct ubi_fastmap_layout *fm;
+	struct ubi_fm_pool fm_pool;
+	struct ubi_fm_pool fm_wl_pool;
+	struct rw_semaphore fm_sem;
+	struct mutex fm_mutex;
+	void *fm_buf;
+	size_t fm_size;
+	struct work_struct fm_work;
+
 	/* Wear-leveling sub-system's stuff */
 	struct rb_root used;
 	struct rb_root erroneous;
 	struct rb_root free;
+	int free_count;
 	struct rb_root scrub;
 	struct list_head pq[UBI_PROT_QUEUE_LEN];
 	int pq_head;
@@ -596,6 +666,32 @@ struct ubi_attach_info {
 	struct kmem_cache *aeb_slab_cache;
 };
 
+/**
+ * struct ubi_work - UBI work description data structure.
+ * @list: a link in the list of pending works
+ * @func: worker function
+ * @e: physical eraseblock to erase
+ * @vol_id: the volume ID on which this erasure is being performed
+ * @lnum: the logical eraseblock number
+ * @torture: if the physical eraseblock has to be tortured
+ * @anchor: produce a anchor PEB to by used by fastmap
+ *
+ * The @func pointer points to the worker function. If the @cancel argument is
+ * not zero, the worker has to free the resources and exit immediately. The
+ * worker has to return zero in case of success and a negative error code in
+ * case of failure.
+ */
+struct ubi_work {
+	struct list_head list;
+	int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel);
+	/* The below fields are only relevant to erasure works */
+	struct ubi_wl_entry *e;
+	int vol_id;
+	int lnum;
+	int torture;
+	int anchor;
+};
+
 #include "debug.h"
 
 extern struct kmem_cache *ubi_wl_entry_slab;
@@ -606,7 +702,7 @@ extern struct class *ubi_class;
 extern struct mutex ubi_devices_mutex;
 extern struct blocking_notifier_head ubi_notifiers;
 
-/* scan.c */
+/* attach.c */
 int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		  int ec, const struct ubi_vid_hdr *vid_hdr, int bitflips);
 struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai,
@@ -664,6 +760,9 @@ int ubi_eba_atomic_leb_change(struct ubi_device *ubi, struct ubi_volume *vol,
 int ubi_eba_copy_leb(struct ubi_device *ubi, int from, int to,
 		     struct ubi_vid_hdr *vid_hdr);
 int ubi_eba_init(struct ubi_device *ubi, struct ubi_attach_info *ai);
+unsigned long long ubi_next_sqnum(struct ubi_device *ubi);
+int self_check_eba(struct ubi_device *ubi, struct ubi_attach_info *ai_fastmap,
+		   struct ubi_attach_info *ai_scan);
 
 /* wl.c */
 int ubi_wl_get_peb(struct ubi_device *ubi);
@@ -674,6 +773,12 @@ int ubi_wl_scrub_peb(struct ubi_device *ubi, int pnum);
 int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai);
 void ubi_wl_close(struct ubi_device *ubi);
 int ubi_thread(void *u);
+struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor);
+int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *used_e,
+		      int lnum, int torture);
+int ubi_is_erase_work(struct ubi_work *wrk);
+void ubi_refill_pools(struct ubi_device *ubi);
+int ubi_ensure_anchor_pebs(struct ubi_device *ubi);
 
 /* io.c */
 int ubi_io_read(const struct ubi_device *ubi, void *buf, int pnum, int offset,
@@ -711,6 +816,15 @@ void ubi_free_internal_volumes(struct ubi_device *ubi);
 void ubi_do_get_device_info(struct ubi_device *ubi, struct ubi_device_info *di);
 void ubi_do_get_volume_info(struct ubi_device *ubi, struct ubi_volume *vol,
 			    struct ubi_volume_info *vi);
+/* scan.c */
+int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
+		      int pnum, const struct ubi_vid_hdr *vid_hdr);
+
+/* fastmap.c */
+size_t ubi_calc_fm_size(struct ubi_device *ubi);
+int ubi_update_fastmap(struct ubi_device *ubi);
+int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int fm_anchor);
 
 /*
  * ubi_rb_for_each_entry - walk an RB-tree.
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index 032fc57..f4d06db 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -135,30 +135,6 @@
  */
 #define WL_MAX_FAILURES 32
 
-/**
- * struct ubi_work - UBI work description data structure.
- * @list: a link in the list of pending works
- * @func: worker function
- * @e: physical eraseblock to erase
- * @vol_id: the volume ID on which this erasure is being performed
- * @lnum: the logical eraseblock number
- * @torture: if the physical eraseblock has to be tortured
- *
- * The @func pointer points to the worker function. If the @cancel argument is
- * not zero, the worker has to free the resources and exit immediately. The
- * worker has to return zero in case of success and a negative error code in
- * case of failure.
- */
-struct ubi_work {
-	struct list_head list;
-	int (*func)(struct ubi_device *ubi, struct ubi_work *wrk, int cancel);
-	/* The below fields are only relevant to erasure works */
-	struct ubi_wl_entry *e;
-	int vol_id;
-	int lnum;
-	int torture;
-};
-
 static int self_check_ec(struct ubi_device *ubi, int pnum, int ec);
 static int self_check_in_wl_tree(const struct ubi_device *ubi,
 				 struct ubi_wl_entry *e, struct rb_root *root);
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:50 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:50 +0200
Subject: [PATCH 10/10] UBI: Wire-up fastmap
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-11-git-send-email-richard@nod.at>

Make fastmap known to Kconfig, UBI Makefile and MAINTAINERS.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 MAINTAINERS              |    6 ++++++
 drivers/mtd/ubi/Kconfig  |   20 ++++++++++++++++++++
 drivers/mtd/ubi/Makefile |    1 +
 3 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..7bcade0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7075,6 +7075,12 @@ F:	drivers/mtd/ubi/
 F:	include/linux/mtd/ubi.h
 F:	include/mtd/ubi-user.h
 
+UNSORTED BLOCK IMAGES (UBI) Fastmap
+M:	Richard Weinberger <richard at nod.at>
+L:	linux-mtd at lists.infradead.org
+S:	Maintained
+F:	drivers/mtd/ubi/fastmap.c
+
 USB ACM DRIVER
 M:	Oliver Neukum <oliver at neukum.org>
 L:	linux-usb at vger.kernel.org
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 271a842..3620f91 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -56,6 +56,26 @@ config MTD_UBI_BEB_LIMIT
 
 	  Leave the default value if unsure.
 
+config MTD_UBI_FASTMAP
+	bool "UBI Fastmap (EXPERIMENTAL)"
+	depends on EXPERIMENTAL
+	default n
+	help
+	   Fastmap is a mechanism which allows attaching an UBI device
+	   in nearly constant time.
+	   Instead of scanning the whole MTD device it only has to locate
+	   a checkpoint (called fastmap) on the device.
+	   The on-flash fastmap contains all information needed to attach
+	   the device. Using fastmap makes only sense on large devices where
+	   attaching by scanning takes long. UBI will not automatically install
+	   a fastmap on old images, but you can set the UBI module parameter
+	   fm_autoconvert to 1 if you want so. Please note that fastmap-enabled
+	   images are still usable with UBI implementations without
+	   fastmap support. On typical flash devices the whole fastmap fits
+	   into one PEB. UBI will reserve PEBs to hold two fastmaps.
+
+	   If in doubt, say "N".
+
 config MTD_UBI_GLUEBI
 	tristate "MTD devices emulation driver (gluebi)"
 	help
diff --git a/drivers/mtd/ubi/Makefile b/drivers/mtd/ubi/Makefile
index a0803ac..7ab19ac 100644
--- a/drivers/mtd/ubi/Makefile
+++ b/drivers/mtd/ubi/Makefile
@@ -4,3 +4,4 @@ ubi-y += vtbl.o vmt.o upd.o build.o cdev.o kapi.o eba.o io.o wl.o attach.o
 ubi-y += misc.o debug.o
 
 obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
+obj-$(CONFIG_MTD_UBI_FASTMAP) += fastmap.o
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:47 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:47 +0200
Subject: [PATCH 07/10] UBI: Add fastmap stuff to attach.c
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-8-git-send-email-richard@nod.at>

- Export compare_lebs() as fastmap needs this function.
- Implement fastmap scan logic.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/attach.c |  386 +++++++++++++++++++++++++++++++---------------
 drivers/mtd/ubi/build.c  |    2 +-
 drivers/mtd/ubi/ubi.h    |    2 +-
 3 files changed, 260 insertions(+), 130 deletions(-)

diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c
index da13215..e106e59 100644
--- a/drivers/mtd/ubi/attach.c
+++ b/drivers/mtd/ubi/attach.c
@@ -300,7 +300,7 @@ static struct ubi_ainf_volume *add_volume(struct ubi_attach_info *ai,
 }
 
 /**
- * compare_lebs - find out which logical eraseblock is newer.
+ * ubi_compare_lebs - find out which logical eraseblock is newer.
  * @ubi: UBI device description object
  * @aeb: first logical eraseblock to compare
  * @pnum: physical eraseblock number of the second logical eraseblock to
@@ -319,7 +319,7 @@ static struct ubi_ainf_volume *add_volume(struct ubi_attach_info *ai,
  *     o bit 2 is cleared: the older LEB is not corrupted;
  *     o bit 2 is set: the older LEB is corrupted.
  */
-static int compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
+int ubi_compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
 			int pnum, const struct ubi_vid_hdr *vid_hdr)
 {
 	void *buf;
@@ -337,7 +337,7 @@ static int compare_lebs(struct ubi_device *ubi, const struct ubi_ainf_peb *aeb,
 		 * support these images anymore. Well, those images still work,
 		 * but only if no unclean reboots happened.
 		 */
-		ubi_err("unsupported on-flash UBI format\n");
+		ubi_err("unsupported on-flash UBI format");
 		return -EINVAL;
 	}
 
@@ -507,7 +507,7 @@ int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		 * sequence numbers. We still can attach these images, unless
 		 * there is a need to distinguish between old and new
 		 * eraseblocks, in which case we'll refuse the image in
-		 * 'compare_lebs()'. In other words, we attach old clean
+		 * 'ubi_compare_lebs()'. In other words, we attach old clean
 		 * images, but refuse attaching old images with duplicated
 		 * logical eraseblocks because there was an unclean reboot.
 		 */
@@ -523,7 +523,7 @@ int ubi_add_to_av(struct ubi_device *ubi, struct ubi_attach_info *ai, int pnum,
 		 * Now we have to drop the older one and preserve the newer
 		 * one.
 		 */
-		cmp_res = compare_lebs(ubi, aeb, pnum, vid_hdr);
+		cmp_res = ubi_compare_lebs(ubi, aeb, pnum, vid_hdr);
 		if (cmp_res < 0)
 			return cmp_res;
 
@@ -748,7 +748,7 @@ struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi,
 /**
  * check_corruption - check the data area of PEB.
  * @ubi: UBI device description object
- * @vid_hrd: the (corrupted) VID header of this PEB
+ * @vid_hdr: the (corrupted) VID header of this PEB
  * @pnum: the physical eraseblock number to check
  *
  * This is a helper function which is used to distinguish between VID header
@@ -810,6 +810,8 @@ out_unlock:
  * @ubi: UBI device description object
  * @ai: attaching information
  * @pnum: the physical eraseblock number
+ * @vid: The volume ID of the found volume will be stored in this pointer
+ * @sqnum: The sqnum of the found volume will be stored in this pointer
  *
  * This function reads UBI headers of PEB @pnum, checks them, and adds
  * information about this PEB to the corresponding list or RB-tree in the
@@ -817,10 +819,10 @@ out_unlock:
  * successfully handled and a negative error code in case of failure.
  */
 static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai,
-		    int pnum)
+		    int pnum, int *vid, unsigned long long *sqnum)
 {
 	long long uninitialized_var(ec);
-	int err, bitflips = 0, vol_id, ec_err = 0;
+	int err, bitflips = 0, vol_id = -1, ec_err = 0;
 
 	dbg_bld("scan PEB %d", pnum);
 
@@ -991,14 +993,21 @@ static int scan_peb(struct ubi_device *ubi, struct ubi_attach_info *ai,
 	}
 
 	vol_id = be32_to_cpu(vidh->vol_id);
+	if (vid)
+		*vid = vol_id;
+	if (sqnum)
+		*sqnum = be64_to_cpu(vidh->sqnum);
 	if (vol_id > UBI_MAX_VOLUMES && vol_id != UBI_LAYOUT_VOLUME_ID) {
 		int lnum = be32_to_cpu(vidh->lnum);
 
 		/* Unsupported internal volume */
 		switch (vidh->compat) {
 		case UBI_COMPAT_DELETE:
-			ubi_msg("\"delete\" compatible internal volume %d:%d found, will remove it",
-				vol_id, lnum);
+			if (vol_id != UBI_FM_SB_VOLUME_ID
+			    && vol_id != UBI_FM_DATA_VOLUME_ID) {
+				ubi_msg("\"delete\" compatible internal volume %d:%d found, will remove it",
+					vol_id, lnum);
+			}
 			err = add_to_list(ai, pnum, vol_id, lnum,
 					  ec, 1, &ai->erase);
 			if (err)
@@ -1121,51 +1130,126 @@ static int late_analysis(struct ubi_device *ubi, struct ubi_attach_info *ai)
 }
 
 /**
+ * destroy_av - free volume attaching information.
+ * @av: volume attaching information
+ * @ai: attaching information
+ *
+ * This function destroys the volume attaching information.
+ */
+static void destroy_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av)
+{
+	struct ubi_ainf_peb *aeb;
+	struct rb_node *this = av->root.rb_node;
+
+	while (this) {
+		if (this->rb_left)
+			this = this->rb_left;
+		else if (this->rb_right)
+			this = this->rb_right;
+		else {
+			aeb = rb_entry(this, struct ubi_ainf_peb, u.rb);
+			this = rb_parent(this);
+			if (this) {
+				if (this->rb_left == &aeb->u.rb)
+					this->rb_left = NULL;
+				else
+					this->rb_right = NULL;
+			}
+
+			kmem_cache_free(ai->aeb_slab_cache, aeb);
+		}
+	}
+	kfree(av);
+}
+
+/**
+ * destroy_ai - destroy attaching information.
+ * @ai: attaching information
+ */
+static void destroy_ai(struct ubi_attach_info *ai)
+{
+	struct ubi_ainf_peb *aeb, *aeb_tmp;
+	struct ubi_ainf_volume *av;
+	struct rb_node *rb;
+
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->alien, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->erase, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->corr, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+	list_for_each_entry_safe(aeb, aeb_tmp, &ai->free, u.list) {
+		list_del(&aeb->u.list);
+		kmem_cache_free(ai->aeb_slab_cache, aeb);
+	}
+
+	/* Destroy the volume RB-tree */
+	rb = ai->volumes.rb_node;
+	while (rb) {
+		if (rb->rb_left)
+			rb = rb->rb_left;
+		else if (rb->rb_right)
+			rb = rb->rb_right;
+		else {
+			av = rb_entry(rb, struct ubi_ainf_volume, rb);
+
+			rb = rb_parent(rb);
+			if (rb) {
+				if (rb->rb_left == &av->rb)
+					rb->rb_left = NULL;
+				else
+					rb->rb_right = NULL;
+			}
+
+			destroy_av(ai, av);
+		}
+	}
+
+	if (ai->aeb_slab_cache)
+		kmem_cache_destroy(ai->aeb_slab_cache);
+
+	kfree(ai);
+}
+
+/**
  * scan_all - scan entire MTD device.
  * @ubi: UBI device description object
+ * @ai: attach info object
+ * @start: start scanning at this PEB
  *
  * This function does full scanning of an MTD device and returns complete
  * information about it in form of a "struct ubi_attach_info" object. In case
  * of failure, an error code is returned.
  */
-static struct ubi_attach_info *scan_all(struct ubi_device *ubi)
+static int scan_all(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		    int start)
 {
 	int err, pnum;
 	struct rb_node *rb1, *rb2;
 	struct ubi_ainf_volume *av;
 	struct ubi_ainf_peb *aeb;
-	struct ubi_attach_info *ai;
-
-	ai = kzalloc(sizeof(struct ubi_attach_info), GFP_KERNEL);
-	if (!ai)
-		return ERR_PTR(-ENOMEM);
-
-	INIT_LIST_HEAD(&ai->corr);
-	INIT_LIST_HEAD(&ai->free);
-	INIT_LIST_HEAD(&ai->erase);
-	INIT_LIST_HEAD(&ai->alien);
-	ai->volumes = RB_ROOT;
 
 	err = -ENOMEM;
-	ai->aeb_slab_cache = kmem_cache_create("ubi_aeb_slab_cache",
-					       sizeof(struct ubi_ainf_peb),
-					       0, 0, NULL);
-	if (!ai->aeb_slab_cache)
-		goto out_ai;
 
 	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
 	if (!ech)
-		goto out_ai;
+		return err;
 
 	vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
 	if (!vidh)
 		goto out_ech;
 
-	for (pnum = 0; pnum < ubi->peb_count; pnum++) {
+	for (pnum = start; pnum < ubi->peb_count; pnum++) {
 		cond_resched();
 
 		dbg_gen("process PEB %d", pnum);
-		err = scan_peb(ubi, ai, pnum);
+		err = scan_peb(ubi, ai, pnum, NULL, NULL);
 		if (err < 0)
 			goto out_vidh;
 	}
@@ -1210,32 +1294,144 @@ static struct ubi_attach_info *scan_all(struct ubi_device *ubi)
 	ubi_free_vid_hdr(ubi, vidh);
 	kfree(ech);
 
-	return ai;
+	return 0;
 
 out_vidh:
 	ubi_free_vid_hdr(ubi, vidh);
 out_ech:
 	kfree(ech);
-out_ai:
-	ubi_destroy_ai(ai);
-	return ERR_PTR(err);
+	return err;
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+
+/**
+ * scan_fastmap - try to find a fastmap and attach from it.
+ * @ubi: UBI device description object
+ * @ai: attach info object
+ *
+ * Returns 0 on success, negative return values indicate an internal
+ * error.
+ * UBI_NO_FASTMAP denotes that no fastmap was found.
+ * UBI_BAD_FASTMAP denotes that the found fastmap was invalid.
+ */
+static int scan_fast(struct ubi_device *ubi, struct ubi_attach_info *ai)
+{
+	int err, pnum, fm_anchor = -1;
+	unsigned long long max_sqnum = 0;
+
+	err = -ENOMEM;
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech)
+		goto out;
+
+	vidh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vidh)
+		goto out_ech;
+
+	for (pnum = 0; pnum < UBI_FM_MAX_START; pnum++) {
+		int vol_id = -1;
+		unsigned long long sqnum = -1;
+		cond_resched();
+
+		dbg_gen("process PEB %d", pnum);
+		err = scan_peb(ubi, ai, pnum, &vol_id, &sqnum);
+		if (err < 0)
+			goto out_vidh;
+
+		if (vol_id == UBI_FM_SB_VOLUME_ID && sqnum > max_sqnum) {
+			max_sqnum = sqnum;
+			fm_anchor = pnum;
+		}
+	}
+
+	ubi_free_vid_hdr(ubi, vidh);
+	kfree(ech);
+
+	if (fm_anchor < 0)
+		return UBI_NO_FASTMAP;
+
+	return ubi_scan_fastmap(ubi, ai, fm_anchor);
+
+out_vidh:
+	ubi_free_vid_hdr(ubi, vidh);
+out_ech:
+	kfree(ech);
+out:
+	return err;
+}
+
+#endif
+
+static struct ubi_attach_info *alloc_ai(const char *slab_name)
+{
+	struct ubi_attach_info *ai;
+
+	ai = kzalloc(sizeof(struct ubi_attach_info), GFP_KERNEL);
+	if (!ai)
+		return ai;
+
+	INIT_LIST_HEAD(&ai->corr);
+	INIT_LIST_HEAD(&ai->free);
+	INIT_LIST_HEAD(&ai->erase);
+	INIT_LIST_HEAD(&ai->alien);
+	ai->volumes = RB_ROOT;
+	ai->aeb_slab_cache = kmem_cache_create(slab_name,
+					       sizeof(struct ubi_ainf_peb),
+					       0, 0, NULL);
+	if (!ai->aeb_slab_cache) {
+		kfree(ai);
+		ai = NULL;
+	}
+
+	return ai;
 }
 
 /**
  * ubi_attach - attach an MTD device.
  * @ubi: UBI device descriptor
+ * @force_scan: if set to non-zero attach by scanning
  *
  * This function returns zero in case of success and a negative error code in
  * case of failure.
  */
-int ubi_attach(struct ubi_device *ubi)
+int ubi_attach(struct ubi_device *ubi, int force_scan)
 {
 	int err;
 	struct ubi_attach_info *ai;
 
-	ai = scan_all(ubi);
-	if (IS_ERR(ai))
-		return PTR_ERR(ai);
+	ai = alloc_ai("ubi_aeb_slab_cache");
+	if (!ai)
+		return -ENOMEM;
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* On small flash devices we disable fastmap in any case. */
+	if ((int)mtd_div_by_eb(ubi->mtd->size, ubi->mtd) <= UBI_FM_MAX_START) {
+		ubi->fm_disabled = 1;
+		force_scan = 1;
+	}
+
+	if (force_scan)
+		err = scan_all(ubi, ai, 0);
+	else {
+		err = scan_fast(ubi, ai);
+		if (err > 0) {
+			if (err != UBI_NO_FASTMAP) {
+				destroy_ai(ai);
+				ai = alloc_ai("ubi_aeb_slab_cache2");
+				if (!ai)
+					return -ENOMEM;
+			}
+
+			err = scan_all(ubi, ai, UBI_FM_MAX_START);
+		}
+	}
+#else
+	err = scan_all(ubi, ai, 0);
+#endif
+	if (err)
+		goto out_ai;
 
 	ubi->bad_peb_count = ai->bad_peb_count;
 	ubi->good_peb_count = ubi->peb_count - ubi->bad_peb_count;
@@ -1256,7 +1452,29 @@ int ubi_attach(struct ubi_device *ubi)
 	if (err)
 		goto out_wl;
 
-	ubi_destroy_ai(ai);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	if (ubi->fm && ubi->dbg->chk_gen) {
+		struct ubi_attach_info *scan_ai;
+
+		scan_ai = alloc_ai("ubi_ckh_aeb_slab_cache");
+		if (!scan_ai)
+			goto out_wl;
+
+		err = scan_all(ubi, scan_ai, 0);
+		if (err) {
+			destroy_ai(scan_ai);
+			goto out_wl;
+		}
+
+		err = self_check_eba(ubi, ai, scan_ai);
+		destroy_ai(scan_ai);
+
+		if (err)
+			goto out_wl;
+	}
+#endif
+
+	destroy_ai(ai);
 	return 0;
 
 out_wl:
@@ -1265,99 +1483,11 @@ out_vtbl:
 	ubi_free_internal_volumes(ubi);
 	vfree(ubi->vtbl);
 out_ai:
-	ubi_destroy_ai(ai);
+	destroy_ai(ai);
 	return err;
 }
 
 /**
- * destroy_av - free volume attaching information.
- * @av: volume attaching information
- * @ai: attaching information
- *
- * This function destroys the volume attaching information.
- */
-static void destroy_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av)
-{
-	struct ubi_ainf_peb *aeb;
-	struct rb_node *this = av->root.rb_node;
-
-	while (this) {
-		if (this->rb_left)
-			this = this->rb_left;
-		else if (this->rb_right)
-			this = this->rb_right;
-		else {
-			aeb = rb_entry(this, struct ubi_ainf_peb, u.rb);
-			this = rb_parent(this);
-			if (this) {
-				if (this->rb_left == &aeb->u.rb)
-					this->rb_left = NULL;
-				else
-					this->rb_right = NULL;
-			}
-
-			kmem_cache_free(ai->aeb_slab_cache, aeb);
-		}
-	}
-	kfree(av);
-}
-
-/**
- * ubi_destroy_ai - destroy attaching information.
- * @ai: attaching information
- */
-void ubi_destroy_ai(struct ubi_attach_info *ai)
-{
-	struct ubi_ainf_peb *aeb, *aeb_tmp;
-	struct ubi_ainf_volume *av;
-	struct rb_node *rb;
-
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->alien, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->erase, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->corr, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-	list_for_each_entry_safe(aeb, aeb_tmp, &ai->free, u.list) {
-		list_del(&aeb->u.list);
-		kmem_cache_free(ai->aeb_slab_cache, aeb);
-	}
-
-	/* Destroy the volume RB-tree */
-	rb = ai->volumes.rb_node;
-	while (rb) {
-		if (rb->rb_left)
-			rb = rb->rb_left;
-		else if (rb->rb_right)
-			rb = rb->rb_right;
-		else {
-			av = rb_entry(rb, struct ubi_ainf_volume, rb);
-
-			rb = rb_parent(rb);
-			if (rb) {
-				if (rb->rb_left == &av->rb)
-					rb->rb_left = NULL;
-				else
-					rb->rb_right = NULL;
-			}
-
-			destroy_av(ai, av);
-		}
-	}
-
-	if (ai->aeb_slab_cache)
-		kmem_cache_destroy(ai->aeb_slab_cache);
-
-	kfree(ai);
-}
-
-/**
  * self_check_ai - check the attaching information.
  * @ubi: UBI device description object
  * @ai: attaching information
diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c
index c9b99be..344b4cb 100644
--- a/drivers/mtd/ubi/build.c
+++ b/drivers/mtd/ubi/build.c
@@ -990,7 +990,7 @@ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
 	if (err)
 		goto out_free;
 
-	err = ubi_attach(ubi);
+	err = ubi_attach(ubi, 0);
 	if (err) {
 		ubi_err("failed to attach mtd%d, error %d", mtd->index, err);
 		goto out_debugging;
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index b0d3ba2..7d57469 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -710,7 +710,7 @@ struct ubi_ainf_volume *ubi_find_av(const struct ubi_attach_info *ai,
 void ubi_remove_av(struct ubi_attach_info *ai, struct ubi_ainf_volume *av);
 struct ubi_ainf_peb *ubi_early_get_peb(struct ubi_device *ubi,
 				       struct ubi_attach_info *ai);
-int ubi_attach(struct ubi_device *ubi);
+int ubi_attach(struct ubi_device *ubi, int force_scan);
 void ubi_destroy_ai(struct ubi_attach_info *ai);
 
 /* vtbl.c */
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:48 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:48 +0200
Subject: [PATCH 08/10] UBI: Add fastmap support to the WL sub-system
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-9-git-send-email-richard@nod.at>

To make fastmap possible the WL sub-system needs some
changes.
Mostly to support fastmaps pools.

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/wl.c |  575 ++++++++++++++++++++++++++++++++++++++++++++++----
 1 files changed, 531 insertions(+), 44 deletions(-)

diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index f4d06db..da7b449 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -141,6 +141,42 @@ static int self_check_in_wl_tree(const struct ubi_device *ubi,
 static int self_check_in_pq(const struct ubi_device *ubi,
 			    struct ubi_wl_entry *e);
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * update_fastmap_work_fn - calls ubi_update_fastmap from a work queue
+ * @wrk: the work description object
+ */
+static void update_fastmap_work_fn(struct work_struct *wrk)
+{
+	struct ubi_device *ubi = container_of(wrk, struct ubi_device, fm_work);
+	ubi_update_fastmap(ubi);
+}
+
+/**
+ *  ubi_ubi_is_fm_block - returns 1 if a PEB is currently used in a fastmap.
+ *  @ubi: UBI device description object
+ *  @pnum: the to be checked PEB
+ */
+static int ubi_is_fm_block(struct ubi_device *ubi, int pnum)
+{
+	int i;
+
+	if (!ubi->fm)
+		return 0;
+
+	for (i = 0; i < ubi->fm->used_blocks; i++)
+		if (ubi->fm->e[i]->pnum == pnum)
+			return 1;
+
+	return 0;
+}
+#else
+static int ubi_is_fm_block(struct ubi_device *ubi, int pnum)
+{
+	return 0;
+}
+#endif
+
 /**
  * wl_tree_add - add a wear-leveling entry to a WL RB-tree.
  * @e: the wear-leveling entry to add
@@ -237,18 +273,16 @@ static int produce_free_peb(struct ubi_device *ubi)
 {
 	int err;
 
-	spin_lock(&ubi->wl_lock);
 	while (!ubi->free.rb_node) {
 		spin_unlock(&ubi->wl_lock);
 
 		dbg_wl("do one work synchronously");
 		err = do_work(ubi);
-		if (err)
-			return err;
 
 		spin_lock(&ubi->wl_lock);
+		if (err)
+			return err;
 	}
-	spin_unlock(&ubi->wl_lock);
 
 	return 0;
 }
@@ -315,16 +349,18 @@ static void prot_queue_add(struct ubi_device *ubi, struct ubi_wl_entry *e)
 
 /**
  * find_wl_entry - find wear-leveling entry closest to certain erase counter.
+ * @ubi: UBI device description object
  * @root: the RB-tree where to look for
  * @diff: maximum possible difference from the smallest erase counter
  *
  * This function looks for a wear leveling entry with erase counter closest to
  * min + @diff, where min is the smallest erase counter.
  */
-static struct ubi_wl_entry *find_wl_entry(struct rb_root *root, int diff)
+static struct ubi_wl_entry *find_wl_entry(struct ubi_device *ubi,
+					  struct rb_root *root, int diff)
 {
 	struct rb_node *p;
-	struct ubi_wl_entry *e;
+	struct ubi_wl_entry *e, *prev_e = NULL;
 	int max;
 
 	e = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb);
@@ -339,35 +375,143 @@ static struct ubi_wl_entry *find_wl_entry(struct rb_root *root, int diff)
 			p = p->rb_left;
 		else {
 			p = p->rb_right;
+			prev_e = e;
 			e = e1;
 		}
 	}
 
+	/* If no fastmap has been written and this WL entry can be used
+	 * as anchor PEB, hold it back and return the second best WL entry
+	 * such that fastmap can use the anchor PEB later. */
+	if (prev_e && !ubi->fm_disabled &&
+	    !ubi->fm && e->pnum < UBI_FM_MAX_START)
+		return prev_e;
+
 	return e;
 }
 
 /**
- * ubi_wl_get_peb - get a physical eraseblock.
+ * find_mean_wl_entry - find wear-leveling entry with medium erase counter.
+ * @ubi: UBI device description object
+ * @root: the RB-tree where to look for
+ *
+ * This function looks for a wear leveling entry with medium erase counter,
+ * but not greater or equivalent than the lowest erase counter plus
+ * %WL_FREE_MAX_DIFF/2.
+ */
+static struct ubi_wl_entry *find_mean_wl_entry(struct ubi_device *ubi,
+					       struct rb_root *root)
+{
+	struct ubi_wl_entry *e, *first, *last;
+
+	first = rb_entry(rb_first(root), struct ubi_wl_entry, u.rb);
+	last = rb_entry(rb_last(root), struct ubi_wl_entry, u.rb);
+
+	if (last->ec - first->ec < WL_FREE_MAX_DIFF) {
+		e = rb_entry(root->rb_node, struct ubi_wl_entry, u.rb);
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+		/* If no fastmap has been written and this WL entry can be used
+		 * as anchor PEB, hold it back and return the second best
+		 * WL entry such that fastmap can use the anchor PEB later. */
+		if (e && !ubi->fm_disabled && !ubi->fm &&
+		    e->pnum < UBI_FM_MAX_START)
+			e = rb_entry(rb_next(root->rb_node),
+				     struct ubi_wl_entry, u.rb);
+#endif
+	} else
+		e = find_wl_entry(ubi, root, WL_FREE_MAX_DIFF/2);
+
+	return e;
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * find_anchor_wl_entry - find wear-leveling entry to used as anchor PEB.
+ * @root: the RB-tree where to look for
+ */
+static struct ubi_wl_entry *find_anchor_wl_entry(struct rb_root *root)
+{
+	struct rb_node *p;
+	struct ubi_wl_entry *e, *victim = NULL;
+	int max_ec = UBI_MAX_ERASECOUNTER;
+
+	ubi_rb_for_each_entry(p, e, root, u.rb) {
+		if (e->pnum < UBI_FM_MAX_START && e->ec < max_ec) {
+			victim = e;
+			max_ec = e->ec;
+		}
+	}
+
+	return victim;
+}
+
+static int anchor_pebs_avalible(struct rb_root *root)
+{
+	struct rb_node *p;
+	struct ubi_wl_entry *e;
+
+	ubi_rb_for_each_entry(p, e, root, u.rb)
+		if (e->pnum < UBI_FM_MAX_START)
+			return 1;
+
+	return 0;
+}
+
+/**
+ * ubi_wl_get_fm_peb - find a physical erase block with a given maximal number.
+ * @ubi: UBI device description object
+ * @anchor: This PEB will be used as anchor PEB by fastmap
+ *
+ * The function returns a physical erase block with a given maximal number
+ * and removes it from the wl subsystem.
+ * Must be called with wl_lock held!
+ */
+struct ubi_wl_entry *ubi_wl_get_fm_peb(struct ubi_device *ubi, int anchor)
+{
+	struct ubi_wl_entry *e = NULL;
+
+	if (!ubi->free.rb_node || (ubi->free_count - ubi->beb_rsvd_pebs < 1))
+		goto out;
+
+	if (anchor)
+		e = find_anchor_wl_entry(&ubi->free);
+	else
+		e = find_mean_wl_entry(ubi, &ubi->free);
+
+	if (!e)
+		goto out;
+
+	self_check_in_wl_tree(ubi, e, &ubi->free);
+
+	/* remove it from the free list,
+	 * the wl subsystem does no longer know this erase block */
+	rb_erase(&e->u.rb, &ubi->free);
+	ubi->free_count--;
+out:
+	return e;
+}
+#endif
+
+/**
+ * __wl_get_peb - get a physical eraseblock.
  * @ubi: UBI device description object
  *
  * This function returns a physical eraseblock in case of success and a
  * negative error code in case of failure. Might sleep.
  */
-int ubi_wl_get_peb(struct ubi_device *ubi)
+static int __wl_get_peb(struct ubi_device *ubi)
 {
 	int err;
-	struct ubi_wl_entry *e, *first, *last;
+	struct ubi_wl_entry *e;
 
 retry:
-	spin_lock(&ubi->wl_lock);
 	if (!ubi->free.rb_node) {
 		if (ubi->works_count == 0) {
-			ubi_assert(list_empty(&ubi->works));
 			ubi_err("no free eraseblocks");
-			spin_unlock(&ubi->wl_lock);
+			ubi_assert(list_empty(&ubi->works));
 			return -ENOSPC;
 		}
-		spin_unlock(&ubi->wl_lock);
 
 		err = produce_free_peb(ubi);
 		if (err < 0)
@@ -375,13 +519,11 @@ retry:
 		goto retry;
 	}
 
-	first = rb_entry(rb_first(&ubi->free), struct ubi_wl_entry, u.rb);
-	last = rb_entry(rb_last(&ubi->free), struct ubi_wl_entry, u.rb);
-
-	if (last->ec - first->ec < WL_FREE_MAX_DIFF)
-		e = rb_entry(ubi->free.rb_node, struct ubi_wl_entry, u.rb);
-	else
-		e = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF/2);
+	e = find_mean_wl_entry(ubi, &ubi->free);
+	if (!e) {
+		ubi_err("no free eraseblocks");
+		return -ENOSPC;
+	}
 
 	self_check_in_wl_tree(ubi, e, &ubi->free);
 
@@ -390,10 +532,14 @@ retry:
 	 * be protected from being moved for some time.
 	 */
 	rb_erase(&e->u.rb, &ubi->free);
+	ubi->free_count--;
 	dbg_wl("PEB %d EC %d", e->pnum, e->ec);
+#ifndef CONFIG_MTD_UBI_FASTMAP
+	/* We have to enqueue e only if fastmap is disabled,
+	 * is fastmap enabled prot_queue_add() will be called by
+	 * ubi_wl_get_peb() after removing e from the pool. */
 	prot_queue_add(ubi, e);
-	spin_unlock(&ubi->wl_lock);
-
+#endif
 	err = ubi_self_check_all_ff(ubi, e->pnum, ubi->vid_hdr_aloffset,
 				    ubi->peb_size - ubi->vid_hdr_aloffset);
 	if (err) {
@@ -404,6 +550,150 @@ retry:
 	return e->pnum;
 }
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * return_unused_pool_pebs - returns unused PEB to the free tree.
+ * @ubi: UBI device description object
+ * @pool: fastmap pool description object
+ */
+static void return_unused_pool_pebs(struct ubi_device *ubi,
+				    struct ubi_fm_pool *pool)
+{
+	int i;
+	struct ubi_wl_entry *e;
+
+	for (i = pool->used; i < pool->size; i++) {
+		e = ubi->lookuptbl[pool->pebs[i]];
+		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
+	}
+}
+
+/**
+ * refill_wl_pool - refills all the fastmap pool used by the
+ * WL sub-system.
+ * @ubi: UBI device description object
+ */
+static void refill_wl_pool(struct ubi_device *ubi)
+{
+	struct ubi_wl_entry *e;
+	struct ubi_fm_pool *pool = &ubi->fm_wl_pool;
+
+	return_unused_pool_pebs(ubi, pool);
+
+	for (pool->size = 0; pool->size < pool->max_size; pool->size++) {
+		if (!ubi->free.rb_node ||
+		   (ubi->free_count - ubi->beb_rsvd_pebs < 5))
+			break;
+
+		e = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
+		self_check_in_wl_tree(ubi, e, &ubi->free);
+		rb_erase(&e->u.rb, &ubi->free);
+		ubi->free_count--;
+
+		pool->pebs[pool->size] = e->pnum;
+	}
+	pool->used = 0;
+}
+
+/**
+ * refill_wl_user_pool - refills all the fastmap pool used by ubi_wl_get_peb.
+ * @ubi: UBI device description object
+ */
+static void refill_wl_user_pool(struct ubi_device *ubi)
+{
+	struct ubi_fm_pool *pool = &ubi->fm_pool;
+
+	return_unused_pool_pebs(ubi, pool);
+
+	for (pool->size = 0; pool->size < pool->max_size; pool->size++) {
+		if (!ubi->free.rb_node ||
+		   (ubi->free_count - ubi->beb_rsvd_pebs < 1))
+			break;
+
+		pool->pebs[pool->size] = __wl_get_peb(ubi);
+		if (pool->pebs[pool->size] < 0)
+			break;
+	}
+	pool->used = 0;
+}
+
+/**
+ * ubi_refill_pools - refills all fastmap PEB pools.
+ * @ubi: UBI device description object
+ */
+void ubi_refill_pools(struct ubi_device *ubi)
+{
+	spin_lock(&ubi->wl_lock);
+	refill_wl_pool(ubi);
+	refill_wl_user_pool(ubi);
+	spin_unlock(&ubi->wl_lock);
+}
+
+/* ubi_wl_get_peb - works exaclty like __wl_get_peb but keeps track of
+ * the fastmap pool.
+ */
+int ubi_wl_get_peb(struct ubi_device *ubi)
+{
+	int ret;
+	struct ubi_fm_pool *pool = &ubi->fm_pool;
+	struct ubi_fm_pool *wl_pool = &ubi->fm_wl_pool;
+
+	if (!pool->size || !wl_pool->size || pool->used == pool->size ||
+	    wl_pool->used == wl_pool->size)
+		ubi_update_fastmap(ubi);
+
+	/* we got not a single free PEB */
+	if (!pool->size)
+		ret = -ENOSPC;
+	else {
+		spin_lock(&ubi->wl_lock);
+		ret = pool->pebs[pool->used++];
+		prot_queue_add(ubi, ubi->lookuptbl[ret]);
+		spin_unlock(&ubi->wl_lock);
+	}
+
+	return ret;
+}
+
+/* get_peb_for_wl - returns a PEB to be used internally by the WL sub-system.
+ *
+ * @ubi: UBI device description object
+ */
+static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi)
+{
+	struct ubi_fm_pool *pool = &ubi->fm_wl_pool;
+	int pnum;
+
+	if (pool->used == pool->size || !pool->size) {
+		/* We cannot update the fastmap here because this
+		 * function is called in atomic context.
+		 * Let's fail here and refill/update it as soon as possible. */
+		schedule_work(&ubi->fm_work);
+		return NULL;
+	} else {
+		pnum = pool->pebs[pool->used++];
+		return ubi->lookuptbl[pnum];
+	}
+}
+#else
+static struct ubi_wl_entry *get_peb_for_wl(struct ubi_device *ubi)
+{
+	return find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
+}
+
+int ubi_wl_get_peb(struct ubi_device *ubi)
+{
+	int peb;
+
+	spin_lock(&ubi->wl_lock);
+	peb = __wl_get_peb(ubi);
+	spin_unlock(&ubi->wl_lock);
+
+	return peb;
+}
+#endif
+
 /**
  * prot_queue_del - remove a physical eraseblock from the protection queue.
  * @ubi: UBI device description object
@@ -534,14 +824,14 @@ repeat:
 }
 
 /**
- * schedule_ubi_work - schedule a work.
+ * __schedule_ubi_work - schedule a work.
  * @ubi: UBI device description object
  * @wrk: the work to schedule
  *
  * This function adds a work defined by @wrk to the tail of the pending works
- * list.
+ * list. Can only be used of ubi->work_sem is already held in read mode!
  */
-static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
+static void __schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
 {
 	spin_lock(&ubi->wl_lock);
 	list_add_tail(&wrk->list, &ubi->works);
@@ -552,9 +842,35 @@ static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
 	spin_unlock(&ubi->wl_lock);
 }
 
+/**
+ * schedule_ubi_work - schedule a work.
+ * @ubi: UBI device description object
+ * @wrk: the work to schedule
+ *
+ * This function adds a work defined by @wrk to the tail of the pending works
+ * list.
+ */
+static void schedule_ubi_work(struct ubi_device *ubi, struct ubi_work *wrk)
+{
+	down_read(&ubi->work_sem);
+	__schedule_ubi_work(ubi, wrk);
+	up_read(&ubi->work_sem);
+}
+
 static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 			int cancel);
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_is_erase_work - checks whether a work is erase work.
+ * @wrk: The work object to be checked
+ */
+int ubi_is_erase_work(struct ubi_work *wrk)
+{
+	return wrk->func == erase_worker;
+}
+#endif
+
 /**
  * schedule_erase - schedule an erase work.
  * @ubi: UBI device description object
@@ -571,6 +887,9 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
 {
 	struct ubi_work *wl_wrk;
 
+	ubi_assert(e);
+	ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 	dbg_wl("schedule erasure of PEB %d, EC %d, torture %d",
 	       e->pnum, e->ec, torture);
 
@@ -589,6 +908,79 @@ static int schedule_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
 }
 
 /**
+ * do_sync_erase - run the erase worker synchronously.
+ * @ubi: UBI device description object
+ * @e: the WL entry of the physical eraseblock to erase
+ * @vol_id: the volume ID that last used this PEB
+ * @lnum: the last used logical eraseblock number for the PEB
+ * @torture: if the physical eraseblock has to be tortured
+ *
+ */
+static int do_sync_erase(struct ubi_device *ubi, struct ubi_wl_entry *e,
+			 int vol_id, int lnum, int torture)
+{
+	struct ubi_work *wl_wrk;
+
+	dbg_wl("sync erase of PEB %i", e->pnum);
+
+	wl_wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS);
+	if (!wl_wrk)
+		return -ENOMEM;
+
+	wl_wrk->e = e;
+	wl_wrk->vol_id = vol_id;
+	wl_wrk->lnum = lnum;
+	wl_wrk->torture = torture;
+
+	return erase_worker(ubi, wl_wrk, 0);
+}
+
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_wl_put_fm_peb - returns a PEB used in a fastmap to the wear-leveling
+ * sub-system.
+ * see: ubi_wl_put_peb()
+ *
+ * @ubi: UBI device description object
+ * @fm_e: physical eraseblock to return
+ * @lnum: the last used logical eraseblock number for the PEB
+ * @torture: if this physical eraseblock has to be tortured
+ */
+int ubi_wl_put_fm_peb(struct ubi_device *ubi, struct ubi_wl_entry *fm_e,
+		      int lnum, int torture)
+{
+	struct ubi_wl_entry *e;
+	int vol_id, pnum = fm_e->pnum;
+
+	dbg_wl("PEB %d", pnum);
+
+	ubi_assert(pnum >= 0);
+	ubi_assert(pnum < ubi->peb_count);
+
+	spin_lock(&ubi->wl_lock);
+	e = ubi->lookuptbl[pnum];
+
+	/* This can happen if we recovered from a fastmap the very
+	 * first time and writing now a new one. In this case the wl system
+	 * has never seen any PEB used by the original fastmap.
+	 */
+	if (!e) {
+		e = fm_e;
+		ubi_assert(e->ec >= 0);
+		ubi->lookuptbl[pnum] = e;
+	} else {
+		e->ec = fm_e->ec;
+		kfree(fm_e);
+	}
+
+	spin_unlock(&ubi->wl_lock);
+
+	vol_id = lnum ? UBI_FM_DATA_VOLUME_ID : UBI_FM_SB_VOLUME_ID;
+	return schedule_erase(ubi, e, vol_id, lnum, torture);
+}
+#endif
+
+/**
  * wear_leveling_worker - wear-leveling worker function.
  * @ubi: UBI device description object
  * @wrk: the work object
@@ -603,6 +995,9 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 {
 	int err, scrubbing = 0, torture = 0, protect = 0, erroneous = 0;
 	int vol_id = -1, uninitialized_var(lnum);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	int anchor = wrk->anchor;
+#endif
 	struct ubi_wl_entry *e1, *e2;
 	struct ubi_vid_hdr *vid_hdr;
 
@@ -636,14 +1031,35 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		goto out_cancel;
 	}
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* Check whether we need to produce an anchor PEB */
+	if (!anchor)
+		anchor = !anchor_pebs_avalible(&ubi->free);
+
+	if (anchor) {
+		e1 = find_anchor_wl_entry(&ubi->used);
+		if (!e1)
+			goto out_cancel;
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
+
+		self_check_in_wl_tree(ubi, e1, &ubi->used);
+		rb_erase(&e1->u.rb, &ubi->used);
+		dbg_wl("anchor-move PEB %d to PEB %d", e1->pnum, e2->pnum);
+	} else if (!ubi->scrub.rb_node) {
+#else
 	if (!ubi->scrub.rb_node) {
+#endif
 		/*
 		 * Now pick the least worn-out used physical eraseblock and a
 		 * highly worn-out free physical eraseblock. If the erase
 		 * counters differ much enough, start wear-leveling.
 		 */
 		e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
 
 		if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD)) {
 			dbg_wl("no WL needed: min used EC %d, max free EC %d",
@@ -658,14 +1074,15 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		/* Perform scrubbing */
 		scrubbing = 1;
 		e1 = rb_entry(rb_first(&ubi->scrub), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = get_peb_for_wl(ubi);
+		if (!e2)
+			goto out_cancel;
+
 		self_check_in_wl_tree(ubi, e1, &ubi->scrub);
 		rb_erase(&e1->u.rb, &ubi->scrub);
 		dbg_wl("scrub PEB %d to PEB %d", e1->pnum, e2->pnum);
 	}
 
-	self_check_in_wl_tree(ubi, e2, &ubi->free);
-	rb_erase(&e2->u.rb, &ubi->free);
 	ubi->move_from = e1;
 	ubi->move_to = e2;
 	spin_unlock(&ubi->wl_lock);
@@ -782,7 +1199,7 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 	ubi->move_to_put = ubi->wl_scheduled = 0;
 	spin_unlock(&ubi->wl_lock);
 
-	err = schedule_erase(ubi, e1, vol_id, lnum, 0);
+	err = do_sync_erase(ubi, e1, vol_id, lnum, 0);
 	if (err) {
 		kmem_cache_free(ubi_wl_entry_slab, e1);
 		if (e2)
@@ -797,7 +1214,7 @@ static int wear_leveling_worker(struct ubi_device *ubi, struct ubi_work *wrk,
 		 */
 		dbg_wl("PEB %d (LEB %d:%d) was put meanwhile, erase",
 		       e2->pnum, vol_id, lnum);
-		err = schedule_erase(ubi, e2, vol_id, lnum, 0);
+		err = do_sync_erase(ubi, e2, vol_id, lnum, 0);
 		if (err) {
 			kmem_cache_free(ubi_wl_entry_slab, e2);
 			goto out_ro;
@@ -836,7 +1253,7 @@ out_not_moved:
 	spin_unlock(&ubi->wl_lock);
 
 	ubi_free_vid_hdr(ubi, vid_hdr);
-	err = schedule_erase(ubi, e2, vol_id, lnum, torture);
+	err = do_sync_erase(ubi, e2, vol_id, lnum, torture);
 	if (err) {
 		kmem_cache_free(ubi_wl_entry_slab, e2);
 		goto out_ro;
@@ -877,12 +1294,13 @@ out_cancel:
 /**
  * ensure_wear_leveling - schedule wear-leveling if it is needed.
  * @ubi: UBI device description object
+ * @nested: set to non-zero if this function is called from UBI worker
  *
  * This function checks if it is time to start wear-leveling and schedules it
  * if yes. This function returns zero in case of success and a negative error
  * code in case of failure.
  */
-static int ensure_wear_leveling(struct ubi_device *ubi)
+static int ensure_wear_leveling(struct ubi_device *ubi, int nested)
 {
 	int err = 0;
 	struct ubi_wl_entry *e1;
@@ -910,7 +1328,7 @@ static int ensure_wear_leveling(struct ubi_device *ubi)
 		 * %UBI_WL_THRESHOLD.
 		 */
 		e1 = rb_entry(rb_first(&ubi->used), struct ubi_wl_entry, u.rb);
-		e2 = find_wl_entry(&ubi->free, WL_FREE_MAX_DIFF);
+		e2 = find_wl_entry(ubi, &ubi->free, WL_FREE_MAX_DIFF);
 
 		if (!(e2->ec - e1->ec >= UBI_WL_THRESHOLD))
 			goto out_unlock;
@@ -927,8 +1345,12 @@ static int ensure_wear_leveling(struct ubi_device *ubi)
 		goto out_cancel;
 	}
 
+	wrk->anchor = 0;
 	wrk->func = &wear_leveling_worker;
-	schedule_ubi_work(ubi, wrk);
+	if (nested)
+		__schedule_ubi_work(ubi, wrk);
+	else
+		schedule_ubi_work(ubi, wrk);
 	return err;
 
 out_cancel:
@@ -939,6 +1361,38 @@ out_unlock:
 	return err;
 }
 
+#ifdef CONFIG_MTD_UBI_FASTMAP
+/**
+ * ubi_ensure_anchor_pebs - schedule wear-leveling to produce an anchor PEB.
+ * @ubi: UBI device description object
+ */
+int ubi_ensure_anchor_pebs(struct ubi_device *ubi)
+{
+	struct ubi_work *wrk;
+
+	spin_lock(&ubi->wl_lock);
+	if (ubi->wl_scheduled) {
+		spin_unlock(&ubi->wl_lock);
+		return 0;
+	}
+	ubi->wl_scheduled = 1;
+	spin_unlock(&ubi->wl_lock);
+
+	wrk = kmalloc(sizeof(struct ubi_work), GFP_NOFS);
+	if (!wrk) {
+		spin_lock(&ubi->wl_lock);
+		ubi->wl_scheduled = 0;
+		spin_unlock(&ubi->wl_lock);
+		return -ENOMEM;
+	}
+
+	wrk->anchor = 1;
+	wrk->func = &wear_leveling_worker;
+	schedule_ubi_work(ubi, wrk);
+	return 0;
+}
+#endif
+
 /**
  * erase_worker - physical eraseblock erase worker function.
  * @ubi: UBI device description object
@@ -969,6 +1423,8 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 	dbg_wl("erase PEB %d EC %d LEB %d:%d",
 	       pnum, e->ec, wl_wrk->vol_id, wl_wrk->lnum);
 
+	ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 	err = sync_erase(ubi, e, wl_wrk->torture);
 	if (!err) {
 		/* Fine, we've erased it successfully */
@@ -976,6 +1432,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 
 		spin_lock(&ubi->wl_lock);
 		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
 		spin_unlock(&ubi->wl_lock);
 
 		/*
@@ -985,7 +1442,7 @@ static int erase_worker(struct ubi_device *ubi, struct ubi_work *wl_wrk,
 		serve_prot_queue(ubi);
 
 		/* And take care about wear-leveling */
-		err = ensure_wear_leveling(ubi);
+		err = ensure_wear_leveling(ubi, 1);
 		return err;
 	}
 
@@ -1223,7 +1680,7 @@ retry:
 	 * Technically scrubbing is the same as wear-leveling, so it is done
 	 * by the WL worker.
 	 */
-	return ensure_wear_leveling(ubi);
+	return ensure_wear_leveling(ubi, 0);
 }
 
 /**
@@ -1404,7 +1861,7 @@ static void cancel_pending(struct ubi_device *ubi)
  */
 int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 {
-	int err, i;
+	int err, i, reserved_pebs, found_pebs = 0;
 	struct rb_node *rb1, *rb2;
 	struct ubi_ainf_volume *av;
 	struct ubi_ainf_peb *aeb, *tmp;
@@ -1416,6 +1873,9 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 	init_rwsem(&ubi->work_sem);
 	ubi->max_ec = ai->max_ec;
 	INIT_LIST_HEAD(&ubi->works);
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	INIT_WORK(&ubi->fm_work, update_fastmap_work_fn);
+#endif
 
 	sprintf(ubi->bgt_name, UBI_BGT_NAME_PATTERN, ubi->ubi_num);
 
@@ -1437,13 +1897,17 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 
 		e->pnum = aeb->pnum;
 		e->ec = aeb->ec;
+		ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
 		ubi->lookuptbl[e->pnum] = e;
 		if (schedule_erase(ubi, e, aeb->vol_id, aeb->lnum, 0)) {
 			kmem_cache_free(ubi_wl_entry_slab, e);
 			goto out_free;
 		}
+
+		found_pebs++;
 	}
 
+	ubi->free_count = 0;
 	list_for_each_entry(aeb, &ai->free, u.list) {
 		cond_resched();
 
@@ -1454,8 +1918,14 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 		e->pnum = aeb->pnum;
 		e->ec = aeb->ec;
 		ubi_assert(e->ec >= 0);
+		ubi_assert(!ubi_is_fm_block(ubi, e->pnum));
+
 		wl_tree_add(e, &ubi->free);
+		ubi->free_count++;
+
 		ubi->lookuptbl[e->pnum] = e;
+
+		found_pebs++;
 	}
 
 	ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb) {
@@ -1469,6 +1939,7 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 			e->pnum = aeb->pnum;
 			e->ec = aeb->ec;
 			ubi->lookuptbl[e->pnum] = e;
+
 			if (!aeb->scrub) {
 				dbg_wl("add PEB %d EC %d to the used tree",
 				       e->pnum, e->ec);
@@ -1478,22 +1949,38 @@ int ubi_wl_init(struct ubi_device *ubi, struct ubi_attach_info *ai)
 				       e->pnum, e->ec);
 				wl_tree_add(e, &ubi->scrub);
 			}
+
+			found_pebs++;
 		}
 	}
 
-	if (ubi->avail_pebs < WL_RESERVED_PEBS) {
+	dbg_wl("found %i PEBs", found_pebs);
+
+	if (ubi->fm)
+		ubi_assert(ubi->good_peb_count == \
+			   found_pebs + ubi->fm->used_blocks);
+	else
+		ubi_assert(ubi->good_peb_count == found_pebs);
+
+	reserved_pebs = WL_RESERVED_PEBS;
+#ifdef CONFIG_MTD_UBI_FASTMAP
+	/* Reserve enough LEBs to store two fastmaps. */
+	reserved_pebs += (ubi->fm_size / ubi->leb_size) * 2;
+#endif
+
+	if (ubi->avail_pebs < reserved_pebs) {
 		ubi_err("no enough physical eraseblocks (%d, need %d)",
-			ubi->avail_pebs, WL_RESERVED_PEBS);
+			ubi->avail_pebs, reserved_pebs);
 		if (ubi->corr_peb_count)
 			ubi_err("%d PEBs are corrupted and not used",
 				ubi->corr_peb_count);
 		goto out_free;
 	}
-	ubi->avail_pebs -= WL_RESERVED_PEBS;
-	ubi->rsvd_pebs += WL_RESERVED_PEBS;
+	ubi->avail_pebs -= reserved_pebs;
+	ubi->rsvd_pebs += reserved_pebs;
 
 	/* Schedule wear-leveling if needed */
-	err = ensure_wear_leveling(ubi);
+	err = ensure_wear_leveling(ubi, 0);
 	if (err)
 		goto out_free;
 
@@ -1572,7 +2059,7 @@ static int self_check_ec(struct ubi_device *ubi, int pnum, int ec)
 	}
 
 	read_ec = be64_to_cpu(ec_hdr->ec);
-	if (ec != read_ec) {
+	if (ec != read_ec && read_ec - ec > 1) {
 		ubi_err("self-check failed for PEB %d", pnum);
 		ubi_err("read EC is %lld, should be %d", read_ec, ec);
 		dump_stack();
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:51:49 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:51:49 +0200
Subject: [PATCH 09/10] UBI: Add fastmap core
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <1348674710-102885-10-git-send-email-richard@nod.at>

Signed-off-by: Richard Weinberger <richard at nod.at>
---
 drivers/mtd/ubi/fastmap.c | 1560 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 1560 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/ubi/fastmap.c

diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c
new file mode 100644
index 0000000..be73a1d
--- /dev/null
+++ b/drivers/mtd/ubi/fastmap.c
@@ -0,0 +1,1560 @@
+/*
+ * Copyright (c) 2012 Linutronix GmbH
+ * Author: Richard Weinberger <richard at nod.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
+ * the GNU General Public License for more details.
+ *
+ */
+
+#include <linux/crc32.h>
+#include "ubi.h"
+
+/**
+ * ubi_calc_fm_size - calculates the fastmap size in bytes for an UBI device.
+ * @ubi: UBI device description object
+ */
+size_t ubi_calc_fm_size(struct ubi_device *ubi)
+{
+	size_t size;
+
+	size = sizeof(struct ubi_fm_hdr) + \
+		sizeof(struct ubi_fm_scan_pool) + \
+		sizeof(struct ubi_fm_scan_pool) + \
+		(ubi->peb_count * sizeof(struct ubi_fm_ec)) + \
+		(sizeof(struct ubi_fm_eba) + \
+		(ubi->peb_count * sizeof(__be32))) + \
+		sizeof(struct ubi_fm_volhdr) * UBI_MAX_VOLUMES;
+	return roundup(size, ubi->leb_size);
+}
+
+
+/**
+ * new_fm_vhdr - allocate a new volume header for fastmap usage.
+ * @ubi: UBI device description object
+ * @vol_id: the VID of the new header
+ *
+ * Returns a new struct ubi_vid_hdr on success.
+ * NULL indicates out of memory.
+ */
+static struct ubi_vid_hdr *new_fm_vhdr(struct ubi_device *ubi, int vol_id)
+{
+	struct ubi_vid_hdr *new;
+
+	new = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!new)
+		goto out;
+
+	new->vol_type = UBI_VID_DYNAMIC;
+	new->vol_id = cpu_to_be32(vol_id);
+
+	/* UBI implementations without fastmap support have to delete the
+	 * fastmap.
+	 */
+	new->compat = UBI_COMPAT_DELETE;
+
+out:
+	return new;
+}
+
+/**
+ * add_aeb - create and add a attach erase block to a given list.
+ * @ai: UBI attach info object
+ * @list: the target list
+ * @pnum: PEB number of the new attach erase block
+ * @ec: erease counter of the new LEB
+ * @scrub: scrub this PEB after attaching
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int add_aeb(struct ubi_attach_info *ai, struct list_head *list,
+		   int pnum, int ec, int scrub)
+{
+	struct ubi_ainf_peb *aeb;
+
+	aeb = kmem_cache_alloc(ai->aeb_slab_cache, GFP_KERNEL);
+	if (!aeb)
+		return -ENOMEM;
+
+	aeb->pnum = pnum;
+	aeb->ec = ec;
+	aeb->lnum = -1;
+	aeb->scrub = scrub;
+	aeb->copy_flag = aeb->sqnum = 0;
+
+	ai->ec_sum += aeb->ec;
+	ai->ec_count++;
+
+	if (ai->max_ec < aeb->ec)
+		ai->max_ec = aeb->ec;
+
+	if (ai->min_ec > aeb->ec)
+		ai->min_ec = aeb->ec;
+
+	list_add_tail(&aeb->u.list, list);
+
+	return 0;
+}
+
+/**
+ * add_vol - create and add a new volume to ubi_attach_info.
+ * @ai: ubi_attach_info object
+ * @vol_id: VID of the new volume
+ * @used_ebs: number of used EBS
+ * @data_pad: data padding value of the new volume
+ * @vol_type: volume type
+ * @last_eb_bytes: number of bytes in the last LEB
+ *
+ * Returns the new struct ubi_ainf_volume on success.
+ * NULL indicates an error.
+ */
+static struct ubi_ainf_volume *add_vol(struct ubi_attach_info *ai, int vol_id,
+				       int used_ebs, int data_pad, u8 vol_type,
+				       int last_eb_bytes)
+{
+	struct ubi_ainf_volume *av;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+
+	while (*p) {
+		parent = *p;
+		av = rb_entry(parent, struct ubi_ainf_volume, rb);
+
+		if (vol_id > av->vol_id)
+			p = &(*p)->rb_left;
+		else if (vol_id > av->vol_id)
+			p = &(*p)->rb_right;
+	}
+
+	av = kmalloc(sizeof(struct ubi_ainf_volume), GFP_KERNEL);
+	if (!av)
+		goto out;
+
+	av->highest_lnum = av->leb_count = 0;
+	av->vol_id = vol_id;
+	av->used_ebs = used_ebs;
+	av->data_pad = data_pad;
+	av->last_data_size = last_eb_bytes;
+	av->compat = 0;
+	av->vol_type = vol_type;
+	av->root = RB_ROOT;
+
+	dbg_bld("found volume (ID %i)", vol_id);
+
+	rb_link_node(&av->rb, parent, p);
+	rb_insert_color(&av->rb, &ai->volumes);
+
+out:
+	return av;
+}
+
+/**
+ * assign_aeb_to_av - assigns a SEB to a given ainf_volume and removes it
+ * from it's original list.
+ * @ai: ubi_attach_info object
+ * @aeb: the to be assigned SEB
+ * @av: target scan volume
+ */
+static void assign_aeb_to_av(struct ubi_attach_info *ai,
+			     struct ubi_ainf_peb *aeb,
+			     struct ubi_ainf_volume *av)
+{
+	struct ubi_ainf_peb *tmp_aeb;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+
+	p = &av->root.rb_node;
+	while (*p) {
+		parent = *p;
+
+		tmp_aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb);
+		if (aeb->lnum != tmp_aeb->lnum) {
+			if (aeb->lnum < tmp_aeb->lnum)
+				p = &(*p)->rb_left;
+			else
+				p = &(*p)->rb_right;
+
+			continue;
+		} else
+			break;
+	}
+
+	list_del(&aeb->u.list);
+	av->leb_count++;
+
+	rb_link_node(&aeb->u.rb, parent, p);
+	rb_insert_color(&aeb->u.rb, &av->root);
+}
+
+/**
+ * update_vol - inserts or updates a LEB which was found a pool.
+ * @ubi: the UBI device object
+ * @ai: attach info object
+ * @av: the volume this LEB belongs to
+ * @new_vh: the volume header derived from new_aeb
+ * @new_aeb: the AEB to be examined
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int update_vol(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		      struct ubi_ainf_volume *av, struct ubi_vid_hdr *new_vh,
+		      struct ubi_ainf_peb *new_aeb)
+{
+	struct rb_node **p = &av->root.rb_node, *parent = NULL;
+	struct ubi_ainf_peb *aeb, *victim;
+	int cmp_res;
+
+	while (*p) {
+		parent = *p;
+		aeb = rb_entry(parent, struct ubi_ainf_peb, u.rb);
+
+		if (be32_to_cpu(new_vh->lnum) != aeb->lnum) {
+			if (be32_to_cpu(new_vh->lnum) < aeb->lnum)
+				p = &(*p)->rb_left;
+			else
+				p = &(*p)->rb_right;
+
+			continue;
+		}
+
+		/* This case can happen if the fastmap gets written
+		 * because of a volume change (creation, deletion, ..).
+		 * Then a PEB can be within the persistent EBA and the pool.
+		 */
+		if (aeb->pnum == new_aeb->pnum) {
+			ubi_assert(aeb->lnum == new_aeb->lnum);
+			kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+			return 0;
+		}
+
+		cmp_res = ubi_compare_lebs(ubi, aeb, new_aeb->pnum, new_vh);
+		if (cmp_res < 0)
+			return cmp_res;
+
+		/* new_aeb is newer */
+		if (cmp_res & 1) {
+			victim = kmem_cache_alloc(ai->aeb_slab_cache,
+				GFP_KERNEL);
+			if (!victim)
+				return -ENOMEM;
+
+			victim->ec = aeb->ec;
+			victim->pnum = aeb->pnum;
+			list_add_tail(&victim->u.list, &ai->erase);
+
+			if (av->highest_lnum == be32_to_cpu(new_vh->lnum))
+				av->last_data_size = \
+					be32_to_cpu(new_vh->data_size);
+
+			dbg_bld("vol %i: AEB %i's PEB %i is the newer",
+				av->vol_id, aeb->lnum, new_aeb->pnum);
+
+			aeb->ec = new_aeb->ec;
+			aeb->pnum = new_aeb->pnum;
+			aeb->copy_flag = new_vh->copy_flag;
+			aeb->scrub = new_aeb->scrub;
+			kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+		/* new_aeb is older */
+		} else {
+			dbg_bld("vol %i: AEB %i's PEB %i is old, dropping it",
+				av->vol_id, aeb->lnum, new_aeb->pnum);
+			list_add_tail(&new_aeb->u.list, &ai->erase);
+		}
+
+		return 0;
+	}
+	/* This LEB is new, let's add it to the volume */
+
+	if (av->highest_lnum <= be32_to_cpu(new_vh->lnum)) {
+		av->highest_lnum = be32_to_cpu(new_vh->lnum);
+		av->last_data_size = be32_to_cpu(new_vh->data_size);
+	}
+
+	if (av->vol_type == UBI_STATIC_VOLUME)
+		av->used_ebs = be32_to_cpu(new_vh->used_ebs);
+
+	av->leb_count++;
+
+	rb_link_node(&new_aeb->u.rb, parent, p);
+	rb_insert_color(&new_aeb->u.rb, &av->root);
+
+	return 0;
+}
+
+/**
+ * process_pool_aeb - we found a non-empty PEB in a pool.
+ * @ubi: UBI device object
+ * @ai: attach info object
+ * @new_vh: the volume header derived from new_aeb
+ * @new_aeb: the AEB to be examined
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int process_pool_aeb(struct ubi_device *ubi, struct ubi_attach_info *ai,
+			    struct ubi_vid_hdr *new_vh,
+			    struct ubi_ainf_peb *new_aeb)
+{
+	struct ubi_ainf_volume *av, *tmp_av = NULL;
+	struct rb_node **p = &ai->volumes.rb_node, *parent = NULL;
+	int found = 0;
+
+	if (be32_to_cpu(new_vh->vol_id) == UBI_FM_SB_VOLUME_ID ||
+		be32_to_cpu(new_vh->vol_id) == UBI_FM_DATA_VOLUME_ID) {
+		kmem_cache_free(ai->aeb_slab_cache, new_aeb);
+
+		return 0;
+	}
+
+	/* Find the volume this SEB belongs to */
+	while (*p) {
+		parent = *p;
+		tmp_av = rb_entry(parent, struct ubi_ainf_volume, rb);
+
+		if (be32_to_cpu(new_vh->vol_id) > tmp_av->vol_id)
+			p = &(*p)->rb_left;
+		else if (be32_to_cpu(new_vh->vol_id) < tmp_av->vol_id)
+			p = &(*p)->rb_right;
+		else {
+			found = 1;
+			break;
+		}
+	}
+
+	if (found)
+		av = tmp_av;
+	else {
+		ubi_err("orphaned volume in fastmap pool!");
+		return UBI_BAD_FASTMAP;
+	}
+
+	ubi_assert(be32_to_cpu(new_vh->vol_id) == av->vol_id);
+
+	return update_vol(ubi, ai, av, new_vh, new_aeb);
+}
+
+/**
+ * unmap_peb - unmap a PEB.
+ * If fastmap detects a free PEB in the pool it has to check whether
+ * this PEB has been unmapped after writing the fastmap.
+ *
+ * @ai: UBI attach info object
+ * @pnum: The PEB to be unmapped
+ */
+static void unmap_peb(struct ubi_attach_info *ai, int pnum)
+{
+	struct ubi_ainf_volume *av;
+	struct rb_node *node, *node2;
+	struct ubi_ainf_peb *aeb;
+
+	for (node = rb_first(&ai->volumes); node; node = rb_next(node)) {
+		av = rb_entry(node, struct ubi_ainf_volume, rb);
+
+		for (node2 = rb_first(&av->root); node2;
+		     node2 = rb_next(node2)) {
+			aeb = rb_entry(node2, struct ubi_ainf_peb, u.rb);
+			if (aeb->pnum == pnum) {
+				rb_erase(&aeb->u.rb, &av->root);
+				kmem_cache_free(ai->aeb_slab_cache, aeb);
+				return;
+			}
+		}
+	}
+}
+
+/**
+ * scan_pool - scans a pool for changed (no longer empty PEBs).
+ * @ubi: UBI device object
+ * @ai: attach info object
+ * @pebs: an array of all PEB numbers in the to be scanned pool
+ * @pool_size: size of the pool (number of entries in @pebs)
+ * @max_sqnum: pointer to the maximal sequence number
+ * @eba_orphans: list of PEBs which need to be scanned
+ * @free: list of PEBs which are most likely free (and go into @ai->free)
+ *
+ * Returns 0 on success, if the pool is unusable UBI_BAD_FASTMAP is returned.
+ * < 0 indicates an internal error.
+ */
+static int scan_pool(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int *pebs, int pool_size, unsigned long long *max_sqnum,
+		     struct list_head *eba_orphans, struct list_head *free)
+{
+	struct ubi_vid_hdr *vh;
+	struct ubi_ec_hdr *ech;
+	struct ubi_ainf_peb *new_aeb, *tmp_aeb;
+	int i, pnum, err, found_orphan, ret = 0;
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech)
+		return -ENOMEM;
+
+	vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vh) {
+		kfree(ech);
+		return -ENOMEM;
+	}
+
+	dbg_bld("scanning fastmap pool: size = %i", pool_size);
+
+	/*
+	 * Now scan all PEBs in the pool to find changes which have been made
+	 * after the creation of the fastmap
+	 */
+	for (i = 0; i < pool_size; i++) {
+		int scrub = 0;
+
+		pnum = be32_to_cpu(pebs[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ubi_err("bad PEB in fastmap pool!");
+			ret = UBI_BAD_FASTMAP;
+			goto out;
+		}
+
+		err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+		if (err && err != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read EC header! PEB:%i err:%i",
+				pnum, err);
+			ret = err > 0 ? UBI_BAD_FASTMAP : err;
+			goto out;
+		} else if (ret == UBI_IO_BITFLIPS)
+			scrub = 1;
+
+		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+			ubi_err("bad image seq: 0x%x, expected: 0x%x",
+				be32_to_cpu(ech->image_seq), ubi->image_seq);
+			err = UBI_BAD_FASTMAP;
+			goto out;
+		}
+
+		err = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+		if (err == UBI_IO_FF || err == UBI_IO_FF_BITFLIPS) {
+			unsigned long long ec = be64_to_cpu(ech->ec);
+			unmap_peb(ai, pnum);
+			dbg_bld("Adding PEB to free: %i", pnum);
+			if (err == UBI_IO_FF_BITFLIPS)
+				add_aeb(ai, free, pnum, ec, 1);
+			else
+				add_aeb(ai, free, pnum, ec, 0);
+			continue;
+		} else if (err == 0 || err == UBI_IO_BITFLIPS) {
+			dbg_bld("Found non empty PEB:%i in pool", pnum);
+
+			if (err == UBI_IO_BITFLIPS)
+				scrub = 1;
+
+			found_orphan = 0;
+			list_for_each_entry(tmp_aeb, eba_orphans, u.list) {
+				if (tmp_aeb->pnum == pnum) {
+					found_orphan = 1;
+					break;
+				}
+			}
+			if (found_orphan) {
+				kmem_cache_free(ai->aeb_slab_cache, tmp_aeb);
+				list_del(&tmp_aeb->u.list);
+			}
+
+			new_aeb = kmem_cache_alloc(ai->aeb_slab_cache,
+						   GFP_KERNEL);
+			if (!new_aeb) {
+				ret = -ENOMEM;
+				goto out;
+			}
+
+			new_aeb->ec = be64_to_cpu(ech->ec);
+			new_aeb->pnum = pnum;
+			new_aeb->lnum = be32_to_cpu(vh->lnum);
+			new_aeb->sqnum = be64_to_cpu(vh->sqnum);
+			new_aeb->copy_flag = vh->copy_flag;
+			new_aeb->scrub = scrub;
+
+			if (*max_sqnum < new_aeb->sqnum)
+				*max_sqnum = new_aeb->sqnum;
+
+			err = process_pool_aeb(ubi, ai, vh, new_aeb);
+			if (err) {
+				ret = err > 0 ? UBI_BAD_FASTMAP : err;
+				goto out;
+			}
+		} else {
+			/* We are paranoid and fall back to scanning mode */
+			ubi_err("fastmap pool PEBs contains damaged PEBs!");
+			ret = err > 0 ? UBI_BAD_FASTMAP : err;
+			goto out;
+		}
+
+	}
+
+out:
+	ubi_free_vid_hdr(ubi, vh);
+	kfree(ech);
+	return ret;
+}
+
+/**
+ * count_fastmap_pebs - Counts the PEBs found by fastmap.
+ * @ai: The UBI attach info object
+ */
+static int count_fastmap_pebs(struct ubi_attach_info *ai)
+{
+	struct ubi_ainf_peb *aeb;
+	struct ubi_ainf_volume *av;
+	struct rb_node *rb1, *rb2;
+	int n = 0;
+
+	list_for_each_entry(aeb, &ai->erase, u.list)
+		n++;
+
+	list_for_each_entry(aeb, &ai->free, u.list)
+		n++;
+
+	 ubi_rb_for_each_entry(rb1, av, &ai->volumes, rb)
+		ubi_rb_for_each_entry(rb2, aeb, &av->root, u.rb)
+			n++;
+
+	return n;
+}
+
+/**
+ * ubi_attach_fastmap - creates ubi_attach_info from a fastmap.
+ * @ubi: UBI device object
+ * @ai: UBI attach info object
+ * @fm: the fastmap to be attached
+ *
+ * Returns 0 on success, UBI_BAD_FASTMAP if the found fastmap was unusable.
+ * < 0 indicates an internal error.
+ */
+static int ubi_attach_fastmap(struct ubi_device *ubi,
+			      struct ubi_attach_info *ai,
+			      struct ubi_fastmap_layout *fm)
+{
+	struct list_head used, eba_orphans, free;
+	struct ubi_ainf_volume *av;
+	struct ubi_ainf_peb *aeb, *tmp_aeb, *_tmp_aeb;
+	struct ubi_ec_hdr *ech;
+	struct ubi_fm_sb *fmsb;
+	struct ubi_fm_hdr *fmhdr;
+	struct ubi_fm_scan_pool *fmpl1, *fmpl2;
+	struct ubi_fm_ec *fmec;
+	struct ubi_fm_volhdr *fmvhdr;
+	struct ubi_fm_eba *fm_eba;
+	int ret, i, j, pool_size, wl_pool_size;
+	size_t fm_pos = 0, fm_size = ubi->fm_size;
+	unsigned long long max_sqnum = 0;
+	void *fm_raw = ubi->fm_buf;
+
+	INIT_LIST_HEAD(&used);
+	INIT_LIST_HEAD(&free);
+	INIT_LIST_HEAD(&eba_orphans);
+	INIT_LIST_HEAD(&ai->corr);
+	INIT_LIST_HEAD(&ai->free);
+	INIT_LIST_HEAD(&ai->erase);
+	INIT_LIST_HEAD(&ai->alien);
+	ai->volumes = RB_ROOT;
+	ai->min_ec = UBI_MAX_ERASECOUNTER;
+
+	ai->aeb_slab_cache = kmem_cache_create("ubi_ainf_peb_slab",
+					       sizeof(struct ubi_ainf_peb),
+					       0, 0, NULL);
+	if (!ai->aeb_slab_cache) {
+		ret = -ENOMEM;
+		goto fail;
+	}
+
+	fmsb = (struct ubi_fm_sb *)(fm_raw);
+	ai->max_sqnum = fmsb->sqnum;
+	fm_pos += sizeof(struct ubi_fm_sb);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	fmhdr = (struct ubi_fm_hdr *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmhdr);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+
+	if (be32_to_cpu(fmhdr->magic) != UBI_FM_HDR_MAGIC) {
+		ubi_err("bad fastmap header magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmhdr->magic), UBI_FM_HDR_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl1);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl1->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl1->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl2);
+	if (fm_pos >= fm_size)
+		goto fail_bad;
+	if (be32_to_cpu(fmpl2->magic) != UBI_FM_POOL_MAGIC) {
+		ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmpl2->magic), UBI_FM_POOL_MAGIC);
+		goto fail_bad;
+	}
+
+	pool_size = be16_to_cpu(fmpl1->size);
+	wl_pool_size = be16_to_cpu(fmpl2->size);
+	fm->max_pool_size = be16_to_cpu(fmpl1->max_size);
+	fm->max_wl_pool_size = be16_to_cpu(fmpl2->max_size);
+
+	if (pool_size > UBI_FM_MAX_POOL_SIZE || pool_size < 0) {
+		ubi_err("bad pool size: %i", pool_size);
+		goto fail_bad;
+	}
+
+	if (wl_pool_size > UBI_FM_MAX_POOL_SIZE || wl_pool_size < 0) {
+		ubi_err("bad WL pool size: %i", wl_pool_size);
+		goto fail_bad;
+	}
+
+
+	if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_pool_size < 0) {
+		ubi_err("bad maximal pool size: %i", fm->max_pool_size);
+		goto fail_bad;
+	}
+
+	if (fm->max_wl_pool_size > UBI_FM_MAX_POOL_SIZE ||
+	    fm->max_wl_pool_size < 0) {
+		ubi_err("bad maximal WL pool size: %i", fm->max_wl_pool_size);
+		goto fail_bad;
+	}
+
+	/* read EC values from free list */
+	for (i = 0; i < be32_to_cpu(fmhdr->free_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &ai->free, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 0);
+	}
+
+	/* read EC values from used list */
+	for (i = 0; i < be32_to_cpu(fmhdr->used_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &used, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 0);
+	}
+
+	/* read EC values from scrub list */
+	for (i = 0; i < be32_to_cpu(fmhdr->scrub_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &used, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 1);
+	}
+
+	/* read EC values from erase list */
+	for (i = 0; i < be32_to_cpu(fmhdr->erase_peb_count); i++) {
+		fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmec);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		add_aeb(ai, &ai->erase, be32_to_cpu(fmec->pnum),
+			be32_to_cpu(fmec->ec), 1);
+	}
+
+	ai->mean_ec = div_u64(ai->ec_sum, ai->ec_count);
+	ai->bad_peb_count = be32_to_cpu(fmhdr->bad_peb_count);
+
+	/* Iterate over all volumes and read their EBA table */
+	for (i = 0; i < be32_to_cpu(fmhdr->vol_count); i++) {
+		fmvhdr = (struct ubi_fm_volhdr *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fmvhdr);
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fmvhdr->magic) != UBI_FM_VHDR_MAGIC) {
+			ubi_err("bad fastmap vol header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fmvhdr->magic), UBI_FM_VHDR_MAGIC);
+			goto fail_bad;
+		}
+
+		av = add_vol(ai, be32_to_cpu(fmvhdr->vol_id),
+			     be32_to_cpu(fmvhdr->used_ebs),
+			     be32_to_cpu(fmvhdr->data_pad),
+			     fmvhdr->vol_type,
+			     be32_to_cpu(fmvhdr->last_eb_bytes));
+
+		if (!av)
+			goto fail_bad;
+
+		ai->vols_found++;
+		if (ai->highest_vol_id < be32_to_cpu(fmvhdr->vol_id))
+			ai->highest_vol_id = be32_to_cpu(fmvhdr->vol_id);
+
+		fm_eba = (struct ubi_fm_eba *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fm_eba);
+		fm_pos += (sizeof(__be32) * be32_to_cpu(fm_eba->reserved_pebs));
+		if (fm_pos >= fm_size)
+			goto fail_bad;
+
+		if (be32_to_cpu(fm_eba->magic) != UBI_FM_EBA_MAGIC) {
+			ubi_err("bad fastmap EBA header magic: 0x%x, " \
+				"expected: 0x%x",
+				be32_to_cpu(fm_eba->magic), UBI_FM_EBA_MAGIC);
+			goto fail_bad;
+		}
+
+		for (j = 0; j < be32_to_cpu(fm_eba->reserved_pebs); j++) {
+			int pnum = be32_to_cpu(fm_eba->pnum[j]);
+
+			if ((int)be32_to_cpu(fm_eba->pnum[j]) < 0)
+				continue;
+
+			aeb = NULL;
+			list_for_each_entry(tmp_aeb, &used, u.list) {
+				if (tmp_aeb->pnum == pnum)
+					aeb = tmp_aeb;
+			}
+
+			/* This can happen if a PEB is already in an EBA known
+			 * by this fastmap but the PEB itself is not in the used
+			 * list.
+			 * In this case the PEB can be within the fastmap pool
+			 * or while writing the fastmap it was in the protection
+			 * queue.
+			 */
+			if (!aeb) {
+				aeb = kmem_cache_alloc(ai->aeb_slab_cache,
+						       GFP_KERNEL);
+				if (!aeb) {
+					ret = -ENOMEM;
+
+					goto fail;
+				}
+
+				aeb->lnum = j;
+				aeb->pnum = be32_to_cpu(fm_eba->pnum[j]);
+				aeb->ec = -1;
+				aeb->scrub = aeb->copy_flag = aeb->sqnum = 0;
+				list_add_tail(&aeb->u.list, &eba_orphans);
+				continue;
+			}
+
+			aeb->lnum = j;
+
+			if (av->highest_lnum <= aeb->lnum)
+				av->highest_lnum = aeb->lnum;
+
+			assign_aeb_to_av(ai, aeb, av);
+
+			dbg_bld("inserting PEB:%i (LEB %i) to vol %i",
+				aeb->pnum, aeb->lnum, av->vol_id);
+		}
+
+		ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+		if (!ech) {
+			ret = -ENOMEM;
+			goto fail;
+		}
+
+		list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &eba_orphans,
+					 u.list) {
+			int err;
+
+			if (ubi_io_is_bad(ubi, tmp_aeb->pnum)) {
+				ubi_err("bad PEB in fastmap EBA orphan list");
+				ret = UBI_BAD_FASTMAP;
+				kfree(ech);
+				goto fail;
+			}
+
+			err = ubi_io_read_ec_hdr(ubi, tmp_aeb->pnum, ech, 0);
+			if (err && err != UBI_IO_BITFLIPS) {
+				ubi_err("unable to read EC header! PEB:%i " \
+					"err:%i", tmp_aeb->pnum, err);
+				ret = err > 0 ? UBI_BAD_FASTMAP : err;
+				kfree(ech);
+
+				goto fail;
+			} else if (err == UBI_IO_BITFLIPS)
+				tmp_aeb->scrub = 1;
+
+			tmp_aeb->ec = be64_to_cpu(ech->ec);
+			assign_aeb_to_av(ai, tmp_aeb, av);
+		}
+
+		kfree(ech);
+	}
+
+	ret = scan_pool(ubi, ai, fmpl1->pebs, pool_size, &max_sqnum,
+			&eba_orphans, &free);
+	if (ret)
+		goto fail;
+
+	ret = scan_pool(ubi, ai, fmpl2->pebs, wl_pool_size, &max_sqnum,
+			&eba_orphans, &free);
+	if (ret)
+		goto fail;
+
+	if (max_sqnum > ai->max_sqnum)
+		ai->max_sqnum = max_sqnum;
+
+	list_for_each_entry_safe(tmp_aeb, _tmp_aeb, &free, u.list) {
+		list_del(&tmp_aeb->u.list);
+		list_add_tail(&tmp_aeb->u.list, &ai->free);
+	}
+
+	/*
+	 * If fastmap is leaking PEBs (must not happen), raise a
+	 * fat warning and fall back to scanning mode.
+	 * We do this here because in ubi_wl_init() it's too late
+	 * and we cannot fall back to scanning.
+	 */
+	if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count -
+		    ai->bad_peb_count - fm->used_blocks))
+		goto fail_bad;
+
+	return 0;
+
+fail_bad:
+	ret = UBI_BAD_FASTMAP;
+fail:
+	return ret;
+}
+
+/**
+ * ubi_scan_fastmap - scan the fastmap.
+ * @ubi: UBI device object
+ * @ai: UBI attach info to be filled
+ * @fm_anchor: The fastmap starts at this PEB
+ *
+ * Returns 0 on success, UBI_NO_FASTMAP if no fastmap was found,
+ * UBI_BAD_FASTMAP if one was found but is not usable.
+ * < 0 indicates an internal error.
+ */
+int ubi_scan_fastmap(struct ubi_device *ubi, struct ubi_attach_info *ai,
+		     int fm_anchor)
+{
+	struct ubi_fm_sb *fmsb;
+	struct ubi_vid_hdr *vh;
+	struct ubi_ec_hdr *ech;
+	struct ubi_fastmap_layout *fm;
+	int i, used_blocks, pnum, ret = 0;
+	size_t fm_size;
+	__be32 crc, tmp_crc;
+	unsigned long long sqnum = 0;
+
+	mutex_lock(&ubi->fm_mutex);
+	memset(ubi->fm_buf, 0, ubi->fm_size);
+
+	fmsb = kmalloc(sizeof(*fmsb), GFP_KERNEL);
+	if (!fmsb) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	fm = kzalloc(sizeof(*fm), GFP_KERNEL);
+	if (!fm) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		goto out;
+	}
+
+	ret = ubi_io_read(ubi, fmsb, fm_anchor, ubi->leb_start, sizeof(*fmsb));
+	if (ret && ret != UBI_IO_BITFLIPS) {
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	} else if (ret == UBI_IO_BITFLIPS)
+		fm->to_be_tortured[0] = 1;
+
+	if (be32_to_cpu(fmsb->magic) != UBI_FM_SB_MAGIC) {
+		ubi_err("bad super block magic: 0x%x, expected: 0x%x",
+			be32_to_cpu(fmsb->magic), UBI_FM_SB_MAGIC);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	if (fmsb->version != UBI_FM_FMT_VERSION) {
+		ubi_err("bad fastmap version: %i, expected: %i",
+			fmsb->version, UBI_FM_FMT_VERSION);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	used_blocks = be32_to_cpu(fmsb->used_blocks);
+	if (used_blocks > UBI_FM_MAX_BLOCKS || used_blocks < 1) {
+		ubi_err("number of fastmap blocks is invalid: %i", used_blocks);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	fm_size = ubi->leb_size * used_blocks;
+	if (fm_size != ubi->fm_size) {
+		ubi_err("bad fastmap size: %zi, expected: %zi", fm_size,
+			ubi->fm_size);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fmsb);
+		kfree(fm);
+	}
+
+	ech = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ech) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		kfree(fm);
+		goto out;
+	}
+
+	vh = ubi_zalloc_vid_hdr(ubi, GFP_KERNEL);
+	if (!vh) {
+		ret = -ENOMEM;
+		kfree(fmsb);
+		kfree(fm);
+		kfree(ech);
+		goto out;
+	}
+
+	for (i = 0; i < used_blocks; i++) {
+		pnum = be32_to_cpu(fmsb->block_loc[i]);
+
+		if (ubi_io_is_bad(ubi, pnum)) {
+			ret = UBI_BAD_FASTMAP;
+			kfree(fm);
+			kfree(fmsb);
+			goto free_hdr;
+		}
+
+		ret = ubi_io_read_ec_hdr(ubi, pnum, ech, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i EC (PEB: %i)",
+				i, pnum);
+			if (ret > 0)
+				ret = UBI_BAD_FASTMAP;
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		} else if (ret == UBI_IO_BITFLIPS)
+			fm->to_be_tortured[i] = 1;
+
+		if (!ubi->image_seq)
+			ubi->image_seq = be32_to_cpu(ech->image_seq);
+
+		if (be32_to_cpu(ech->image_seq) != ubi->image_seq) {
+			ret = UBI_BAD_FASTMAP;
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+
+		ret = ubi_io_read_vid_hdr(ubi, pnum, vh, 0);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i)",
+				i, pnum);
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+
+		if (i == 0) {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_SB_VOLUME_ID) {
+				ubi_err("bad fastmap anchor vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_SB_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				kfree(fmsb);
+				kfree(fm);
+				goto free_hdr;
+			}
+		} else {
+			if (be32_to_cpu(vh->vol_id) != UBI_FM_DATA_VOLUME_ID) {
+				ubi_err("bad fastmap data vol_id: 0x%x," \
+					" expected: 0x%x",
+					be32_to_cpu(vh->vol_id),
+					UBI_FM_DATA_VOLUME_ID);
+				ret = UBI_BAD_FASTMAP;
+				kfree(fmsb);
+				goto free_hdr;
+			}
+		}
+
+		if (sqnum < be64_to_cpu(vh->sqnum))
+			sqnum = be64_to_cpu(vh->sqnum);
+
+		ret = ubi_io_read(ubi, ubi->fm_buf + (ubi->leb_size * i), pnum,
+				  ubi->leb_start, ubi->leb_size);
+		if (ret && ret != UBI_IO_BITFLIPS) {
+			ubi_err("unable to read fastmap block# %i (PEB: %i, " \
+				"err: %i)", i, pnum, ret);
+			kfree(fmsb);
+			kfree(fm);
+			goto free_hdr;
+		}
+	}
+
+	kfree(fmsb);
+
+	fmsb = (struct ubi_fm_sb *)(ubi->fm_buf);
+	tmp_crc = be32_to_cpu(fmsb->data_crc);
+	fmsb->data_crc = 0;
+	crc = crc32(UBI_CRC32_INIT, ubi->fm_buf, fm_size);
+	if (crc != tmp_crc) {
+		ubi_err("fastmap data CRC is invalid");
+		ubi_err("CRC should be: 0x%x, calc: 0x%x", tmp_crc, crc);
+		ret = UBI_BAD_FASTMAP;
+		kfree(fm);
+		goto free_hdr;
+	}
+
+	fmsb->sqnum = sqnum;
+
+	fm->used_blocks = used_blocks;
+
+	ret = ubi_attach_fastmap(ubi, ai, fm);
+	if (ret) {
+		if (ret > 0)
+			ret = UBI_BAD_FASTMAP;
+		kfree(fm);
+		goto free_hdr;
+	}
+
+	for (i = 0; i < used_blocks; i++) {
+		struct ubi_wl_entry *e;
+
+		e = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL);
+		if (!e) {
+			while (i--)
+				kfree(fm->e[i]);
+
+			kfree(fm);
+			fm = NULL;
+			ret = -ENOMEM;
+			goto free_hdr;
+		}
+
+		e->pnum = be32_to_cpu(fmsb->block_loc[i]);
+		e->ec = be32_to_cpu(fmsb->block_ec[i]);
+		fm->e[i] = e;
+	}
+
+	ubi->fm = fm;
+	ubi->fm_pool.max_size = ubi->fm->max_pool_size;
+	ubi->fm_wl_pool.max_size = ubi->fm->max_wl_pool_size;
+	ubi_msg("attached by fastmap");
+	ubi_msg("fastmap pool size: %d", ubi->fm_pool.max_size);
+	ubi_msg("fastmap WL pool size: %d", ubi->fm_wl_pool.max_size);
+	ubi->fm_disabled = 0;
+
+free_hdr:
+	ubi_free_vid_hdr(ubi, vh);
+	kfree(ech);
+out:
+	mutex_unlock(&ubi->fm_mutex);
+	if (ret == UBI_BAD_FASTMAP)
+		ubi_err("Attach by fastmap failed, doing a full scan!");
+	return ret;
+}
+
+/**
+ * ubi_write_fastmap - writes a fastmap.
+ * @ubi: UBI device object
+ * @new_fm: the to be written fastmap
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int ubi_write_fastmap(struct ubi_device *ubi,
+			     struct ubi_fastmap_layout *new_fm)
+{
+	size_t fm_pos = 0;
+	void *fm_raw;
+	struct ubi_fm_sb *fmsb;
+	struct ubi_fm_hdr *fmh;
+	struct ubi_fm_scan_pool *fmpl1, *fmpl2;
+	struct ubi_fm_ec *fec;
+	struct ubi_fm_volhdr *fvh;
+	struct ubi_fm_eba *feba;
+	struct rb_node *node;
+	struct ubi_wl_entry *wl_e;
+	struct ubi_volume *vol;
+	struct ubi_vid_hdr *avhdr, *dvhdr;
+	struct ubi_work *ubi_wrk;
+	int ret, i, j, free_peb_count, used_peb_count, vol_count;
+	int scrub_peb_count, erase_peb_count;
+
+	fm_raw = ubi->fm_buf;
+	memset(ubi->fm_buf, 0, ubi->fm_size);
+
+	avhdr = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID);
+	if (!avhdr) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	dvhdr = new_fm_vhdr(ubi, UBI_FM_DATA_VOLUME_ID);
+	if (!dvhdr) {
+		ret = -ENOMEM;
+		goto out_kfree;
+	}
+
+	spin_lock(&ubi->volumes_lock);
+	spin_lock(&ubi->wl_lock);
+
+	fmsb = (struct ubi_fm_sb *)fm_raw;
+	fm_pos += sizeof(*fmsb);
+	ubi_assert(fm_pos <= ubi->fm_size);
+
+	fmh = (struct ubi_fm_hdr *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmh);
+	ubi_assert(fm_pos <= ubi->fm_size);
+
+	fmsb->magic = cpu_to_be32(UBI_FM_SB_MAGIC);
+	fmsb->version = UBI_FM_FMT_VERSION;
+	fmsb->used_blocks = cpu_to_be32(new_fm->used_blocks);
+	/* the max sqnum will be filled in while *reading* the fastmap */
+	fmsb->sqnum = 0;
+
+	fmh->magic = cpu_to_be32(UBI_FM_HDR_MAGIC);
+	free_peb_count = 0;
+	used_peb_count = 0;
+	scrub_peb_count = 0;
+	erase_peb_count = 0;
+	vol_count = 0;
+
+	fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl1);
+	fmpl1->magic = cpu_to_be32(UBI_FM_POOL_MAGIC);
+	fmpl1->size = cpu_to_be16(ubi->fm_pool.size);
+	fmpl1->max_size = cpu_to_be16(ubi->fm_pool.max_size);
+
+	for (i = 0; i < ubi->fm_pool.size; i++)
+		fmpl1->pebs[i] = cpu_to_be32(ubi->fm_pool.pebs[i]);
+
+	fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos);
+	fm_pos += sizeof(*fmpl2);
+	fmpl2->magic = cpu_to_be32(UBI_FM_POOL_MAGIC);
+	fmpl2->size = cpu_to_be16(ubi->fm_wl_pool.size);
+	fmpl2->max_size = cpu_to_be16(ubi->fm_wl_pool.max_size);
+
+	for (i = 0; i < ubi->fm_wl_pool.size; i++)
+		fmpl2->pebs[i] = cpu_to_be32(ubi->fm_wl_pool.pebs[i]);
+
+	for (node = rb_first(&ubi->free); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		free_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->free_peb_count = cpu_to_be32(free_peb_count);
+
+	for (node = rb_first(&ubi->used); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		used_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->used_peb_count = cpu_to_be32(used_peb_count);
+
+	for (node = rb_first(&ubi->scrub); node; node = rb_next(node)) {
+		wl_e = rb_entry(node, struct ubi_wl_entry, u.rb);
+		fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+		fec->pnum = cpu_to_be32(wl_e->pnum);
+		fec->ec = cpu_to_be32(wl_e->ec);
+
+		scrub_peb_count++;
+		fm_pos += sizeof(*fec);
+		ubi_assert(fm_pos <= ubi->fm_size);
+	}
+	fmh->scrub_peb_count = cpu_to_be32(scrub_peb_count);
+
+
+	list_for_each_entry(ubi_wrk, &ubi->works, list) {
+		if (ubi_is_erase_work(ubi_wrk)) {
+			wl_e = ubi_wrk->e;
+			ubi_assert(wl_e);
+
+			fec = (struct ubi_fm_ec *)(fm_raw + fm_pos);
+
+			fec->pnum = cpu_to_be32(wl_e->pnum);
+			fec->ec = cpu_to_be32(wl_e->ec);
+
+			erase_peb_count++;
+			fm_pos += sizeof(*fec);
+			ubi_assert(fm_pos <= ubi->fm_size);
+		}
+	}
+	fmh->erase_peb_count = cpu_to_be32(erase_peb_count);
+
+	for (i = 0; i < UBI_MAX_VOLUMES + UBI_INT_VOL_COUNT; i++) {
+		vol = ubi->volumes[i];
+
+		if (!vol)
+			continue;
+
+		vol_count++;
+
+		fvh = (struct ubi_fm_volhdr *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*fvh);
+		ubi_assert(fm_pos <= ubi->fm_size);
+
+		fvh->magic = cpu_to_be32(UBI_FM_VHDR_MAGIC);
+		fvh->vol_id = cpu_to_be32(vol->vol_id);
+		fvh->vol_type = vol->vol_type;
+		fvh->used_ebs = cpu_to_be32(vol->used_ebs);
+		fvh->data_pad = cpu_to_be32(vol->data_pad);
+		fvh->last_eb_bytes = cpu_to_be32(vol->last_eb_bytes);
+
+		ubi_assert(vol->vol_type == UBI_DYNAMIC_VOLUME ||
+			vol->vol_type == UBI_STATIC_VOLUME);
+
+		feba = (struct ubi_fm_eba *)(fm_raw + fm_pos);
+		fm_pos += sizeof(*feba) + (sizeof(__be32) * vol->reserved_pebs);
+		ubi_assert(fm_pos <= ubi->fm_size);
+
+		for (j = 0; j < vol->reserved_pebs; j++)
+			feba->pnum[j] = cpu_to_be32(vol->eba_tbl[j]);
+
+		feba->reserved_pebs = cpu_to_be32(j);
+		feba->magic = cpu_to_be32(UBI_FM_EBA_MAGIC);
+	}
+	fmh->vol_count = cpu_to_be32(vol_count);
+	fmh->bad_peb_count = cpu_to_be32(ubi->bad_peb_count);
+
+	avhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+	avhdr->lnum = 0;
+
+	spin_unlock(&ubi->wl_lock);
+	spin_unlock(&ubi->volumes_lock);
+
+	dbg_bld("writing fastmap SB to PEB %i", new_fm->e[0]->pnum);
+	ret = ubi_io_write_vid_hdr(ubi, new_fm->e[0]->pnum, avhdr);
+	if (ret) {
+		ubi_err("unable to write vid_hdr to fastmap SB!");
+		goto out_kfree;
+	}
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		fmsb->block_loc[i] = cpu_to_be32(new_fm->e[i]->pnum);
+		fmsb->block_ec[i] = cpu_to_be32(new_fm->e[i]->ec);
+	}
+
+	fmsb->data_crc = 0;
+	fmsb->data_crc = cpu_to_be32(crc32(UBI_CRC32_INIT, fm_raw,
+					   ubi->fm_size));
+
+	for (i = 1; i < new_fm->used_blocks; i++) {
+		dvhdr->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+		dvhdr->lnum = cpu_to_be32(i);
+		dbg_bld("writing fastmap data to PEB %i sqnum %llu",
+			new_fm->e[i]->pnum, be64_to_cpu(dvhdr->sqnum));
+		ret = ubi_io_write_vid_hdr(ubi, new_fm->e[i]->pnum, dvhdr);
+		if (ret) {
+			ubi_err("unable to write vid_hdr to PEB %i!",
+				new_fm->e[i]->pnum);
+			goto out_kfree;
+		}
+	}
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		ret = ubi_io_write(ubi, fm_raw + (i * ubi->leb_size),
+			new_fm->e[i]->pnum, ubi->leb_start, ubi->leb_size);
+		if (ret) {
+			ubi_err("unable to write fastmap to PEB %i!",
+				new_fm->e[i]->pnum);
+			goto out_kfree;
+		}
+	}
+
+	ubi_assert(new_fm);
+	ubi->fm = new_fm;
+
+	dbg_bld("fastmap written!");
+
+out_kfree:
+	ubi_free_vid_hdr(ubi, avhdr);
+	ubi_free_vid_hdr(ubi, dvhdr);
+out:
+	return ret;
+}
+
+/**
+ * erase_block - Manually erase a PEB.
+ * @ubi: UBI device object
+ * @pnum: PEB to be erased
+ *
+ * Returns the new EC value on success, < 0 indicates an internal error.
+ */
+static int erase_block(struct ubi_device *ubi, int pnum)
+{
+	int ret;
+	struct ubi_ec_hdr *ec_hdr;
+	long long ec;
+
+	ec_hdr = kzalloc(ubi->ec_hdr_alsize, GFP_KERNEL);
+	if (!ec_hdr)
+		return -ENOMEM;
+
+	ret = ubi_io_read_ec_hdr(ubi, pnum, ec_hdr, 0);
+	if (ret < 0)
+		goto out;
+	else if (ret && ret != UBI_IO_BITFLIPS) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ret = ubi_io_sync_erase(ubi, pnum, 0);
+	if (ret < 0)
+		goto out;
+
+	ec = be64_to_cpu(ec_hdr->ec);
+	ec += ret;
+	if (ec > UBI_MAX_ERASECOUNTER) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	ec_hdr->ec = cpu_to_be64(ec);
+	ret = ubi_io_write_ec_hdr(ubi, pnum, ec_hdr);
+	if (ret < 0)
+		goto out;
+
+	ret = ec;
+out:
+	kfree(ec_hdr);
+	return ret;
+}
+
+/**
+ * invalidate_fastmap - destroys a fastmap.
+ * @ubi: UBI device object
+ * @fm: the fastmap to be destroyed
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+static int invalidate_fastmap(struct ubi_device *ubi,
+			      struct ubi_fastmap_layout *fm)
+{
+	int ret, i;
+	struct ubi_vid_hdr *vh;
+
+	ret = erase_block(ubi, fm->e[0]->pnum);
+	if (ret < 0)
+		return ret;
+
+	vh = new_fm_vhdr(ubi, UBI_FM_SB_VOLUME_ID);
+	if (!vh)
+		return -ENOMEM;
+
+	/* deleting the current fastmap SB is not enough, an old SB may exist,
+	 * so create a (corrupted) SB such that fastmap will find it and fall
+	 * back to scanning mode in any case */
+	vh->sqnum = cpu_to_be64(ubi_next_sqnum(ubi));
+	ret = ubi_io_write_vid_hdr(ubi, fm->e[0]->pnum, vh);
+
+	for (i = 0; i < fm->used_blocks; i++)
+		ubi_wl_put_fm_peb(ubi, fm->e[i], i, fm->to_be_tortured[i]);
+
+	return ret;
+}
+
+/**
+ * ubi_update_fastmap - will be called by UBI if a volume changes or
+ * a fastmap pool becomes full.
+ * @ubi: UBI device object
+ *
+ * Returns 0 on success, < 0 indicates an internal error.
+ */
+int ubi_update_fastmap(struct ubi_device *ubi)
+{
+	int ret, i;
+	struct ubi_fastmap_layout *new_fm, *old_fm;
+	struct ubi_wl_entry *tmp_e;
+
+	mutex_lock(&ubi->fm_mutex);
+
+	ubi_refill_pools(ubi);
+
+	if (ubi->ro_mode || ubi->fm_disabled) {
+		mutex_unlock(&ubi->fm_mutex);
+		return 0;
+	}
+
+	ret = ubi_ensure_anchor_pebs(ubi);
+	if (ret) {
+		mutex_unlock(&ubi->fm_mutex);
+		return ret;
+	}
+
+	new_fm = kzalloc(sizeof(*new_fm), GFP_KERNEL);
+	if (!new_fm) {
+		mutex_unlock(&ubi->fm_mutex);
+		return -ENOMEM;
+	}
+
+	new_fm->used_blocks = ubi->fm_size / ubi->leb_size;
+
+	for (i = 0; i < new_fm->used_blocks; i++) {
+		new_fm->e[i] = kmem_cache_alloc(ubi_wl_entry_slab, GFP_KERNEL);
+		if (!new_fm->e[i]) {
+			while (i--)
+				kfree(new_fm->e[i]);
+
+			kfree(new_fm);
+			mutex_unlock(&ubi->fm_mutex);
+			return -ENOMEM;
+		}
+	}
+
+	old_fm = ubi->fm;
+	ubi->fm = NULL;
+
+	if (new_fm->used_blocks > UBI_FM_MAX_BLOCKS) {
+		ubi_err("fastmap too large");
+		ret = -ENOSPC;
+		goto err;
+	}
+
+	for (i = 1; i < new_fm->used_blocks; i++) {
+		spin_lock(&ubi->wl_lock);
+		tmp_e = ubi_wl_get_fm_peb(ubi, 0);
+		spin_unlock(&ubi->wl_lock);
+
+		if (!tmp_e && !old_fm) {
+			int j;
+			ubi_err("could not get any free erase block");
+
+			for (j = 1; j < i; j++)
+				ubi_wl_put_fm_peb(ubi, new_fm->e[j], j, 0);
+
+			ret = -ENOSPC;
+			goto err;
+		} else if (!tmp_e && old_fm) {
+			ret = erase_block(ubi, old_fm->e[i]->pnum);
+			if (ret < 0) {
+				int j;
+
+				for (j = 1; j < i; j++)
+					ubi_wl_put_fm_peb(ubi, new_fm->e[j],
+							  j, 0);
+
+				ubi_err("could not erase old fastmap PEB");
+				goto err;
+			}
+
+			new_fm->e[i]->pnum = old_fm->e[i]->pnum;
+			new_fm->e[i]->ec = old_fm->e[i]->ec;
+		} else {
+			new_fm->e[i]->pnum = tmp_e->pnum;
+			new_fm->e[i]->ec = tmp_e->ec;
+
+			if (old_fm)
+				ubi_wl_put_fm_peb(ubi, old_fm->e[i], i,
+						  old_fm->to_be_tortured[i]);
+		}
+	}
+
+	spin_lock(&ubi->wl_lock);
+	tmp_e = ubi_wl_get_fm_peb(ubi, 1);
+	spin_unlock(&ubi->wl_lock);
+
+	if (old_fm) {
+		/* no fresh anchor PEB was found, reuse the old one */
+		if (!tmp_e) {
+			ret = erase_block(ubi, old_fm->e[0]->pnum);
+			if (ret < 0) {
+				int i;
+				ubi_err("could not erase old anchor PEB");
+
+				for (i = 1; i < new_fm->used_blocks; i++)
+					ubi_wl_put_fm_peb(ubi, new_fm->e[i],
+							  i, 0);
+				goto err;
+			}
+
+			new_fm->e[0]->pnum = old_fm->e[0]->pnum;
+			new_fm->e[0]->ec = ret;
+		} else {
+			/* we've got a new anchor PEB, return the old one */
+			ubi_wl_put_fm_peb(ubi, old_fm->e[0], 0,
+					  old_fm->to_be_tortured[0]);
+
+			new_fm->e[0]->pnum = tmp_e->pnum;
+			new_fm->e[0]->ec = tmp_e->ec;
+		}
+	} else {
+		if (!tmp_e) {
+			int i;
+			ubi_err("could not find any anchor PEB");
+
+			for (i = 1; i < new_fm->used_blocks; i++)
+				ubi_wl_put_fm_peb(ubi, new_fm->e[i], i, 0);
+
+			ret = -ENOSPC;
+			goto err;
+		}
+
+		new_fm->e[0]->pnum = tmp_e->pnum;
+		new_fm->e[0]->ec = tmp_e->ec;
+	}
+
+	down_write(&ubi->work_sem);
+	down_write(&ubi->fm_sem);
+	ret = ubi_write_fastmap(ubi, new_fm);
+	up_write(&ubi->fm_sem);
+	up_write(&ubi->work_sem);
+
+	if (ret)
+		goto err;
+
+out_unlock:
+	mutex_unlock(&ubi->fm_mutex);
+	kfree(old_fm);
+	return ret;
+
+err:
+	kfree(new_fm);
+
+	ubi_warn("Unable to write new fastmap, err=%i", ret);
+
+	ret = 0;
+	if (old_fm) {
+		ret = invalidate_fastmap(ubi, old_fm);
+		if (ret < 0)
+			ubi_err("Unable to invalidiate current fastmap!");
+		else if (ret)
+			ret = 0;
+	}
+	goto out_unlock;
+}
-- 
1.7.6.5



From richard at nod.at  Wed Sep 26 11:54:13 2012
From: richard at nod.at (Richard Weinberger)
Date: Wed, 26 Sep 2012 17:54:13 +0200
Subject: [PATCH 01/10] UBI: Add fastmap on-flash data structures
In-Reply-To: <1348655591.24309.64.camel@sauron.fi.intel.com>
References: <1348511492-91606-1-git-send-email-richard@nod.at>
 <1348511492-91606-2-git-send-email-richard@nod.at>
 <1348655591.24309.64.camel@sauron.fi.intel.com>
Message-ID: <20120926175413.58a5c455@spider.haslach.nod.at>

Artem,

Am Wed, 26 Sep 2012 13:33:11 +0300
schrieb Artem Bityutskiy <artem.bityutskiy at linux.intel.com>:
> Richard, thanks, here is the deal I suggest
> 
> 1. I do not really have time to review this in details.
> 2. I do not want to block this either
> 3. I want to merge this to 3.7 with come pre-conditions (see below)
>    as "Experimental" with a claim that the on-flash format can
>    be changed. Something like Linus did for btrfs. Then let people
>    play with fastmap. I am sure it'll need changes when people
>    try to use it in production.
>    
>    a. Aiaiai is happy

sent you v19 where I've addresses all warnings from Aiaiai you mailed
me.

>    b. You provide a section for the mtd web site describing fastmap
>    c. It does not break anything when it is disabled
>    d. When it is enabled, it also passes the UBI tests
> 
> Actually, I want to expose it to linux-next already after step a.
> Despite a lot of testing you have already done, I am willing to do
> some testing myself as well, so I'll do c. and d. and let you know if
> there are issues.
> 
> Could you please do b. ?

Will do!
I'm fine with your plan.

Thanks,
//richard


From computersforpeace at gmail.com  Wed Sep 26 18:20:11 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 26 Sep 2012 15:20:11 -0700
Subject: [PATCH] mtd: m25p80: add support for the windbond w25q256 chip
In-Reply-To: <1348563927-9131-1-git-send-email-matthieu.castet@parrot.com>
References: <1348563927-9131-1-git-send-email-matthieu.castet@parrot.com>
Message-ID: <CAN8TOE-h1VrbNg6ZqwQdhLaQ18E4-=_Lw+biuhGONUS5HCx-4g@mail.gmail.com>

On Tue, Sep 25, 2012 at 2:05 AM, Matthieu CASTET
<matthieu.castet at parrot.com> wrote:
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
> index 5257345..4eb99c6 100644
> --- a/drivers/mtd/devices/m25p80.c
> +++ b/drivers/mtd/devices/m25p80.c
> @@ -168,6 +168,7 @@ static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
>  {
>         switch (JEDEC_MFR(jedec_id)) {
>         case CFI_MFR_MACRONIX:
> +       case 0xEF /* winbond */:
>                 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
>                 return spi_write(flash->spi, flash->command, 1);
>         default:

Just checking: Winbond didn't use their known manufacturer ID (0xDA)
for this chip? Do they have other chips that support/need 4-byte
addressing and use 0xDA?

Brian


From computersforpeace at gmail.com  Wed Sep 26 18:43:35 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 26 Sep 2012 15:43:35 -0700
Subject: [RFC] nand_btt : use nand chip->block_bad
In-Reply-To: <1347931697.19543.24@snotra>
References: <CAN8TOE9QCnq7AKT9t8VKc2iQE9VXT7USDQjJ7vR640FMweqJDQ@mail.gmail.com>
 <1347931697.19543.24@snotra>
Message-ID: <CAN8TOE_D=rHRqpdkrAvtKL2-6x7UB3exfP587D_MZwqP=a=arg@mail.gmail.com>

On Mon, Sep 17, 2012 at 6:28 PM, Scott Wood <scottwood at freescale.com> wrote:
> On 09/17/2012 08:06:54 PM, Brian Norris wrote:
>> On Mon, Aug 6, 2012 at 3:21 PM, Brian Norris <computersforpeace at gmail.com> wrote:
...
>> The following files use badblock_pattern to varying degrees. Some are
>> just duplicating some nand_base stuff, where we can replace the
>> badblock_pattern with something simple like "chip->badblockpos = 0" or
>> setting a few "chip->bbt_options |= NAND_BBT_SCAN*" options. But it's
>> not all so simple:
>>
>> arch/arm/mach-pxa/corgi.c
>> arch/arm/mach-pxa/eseries.c
>> arch/arm/mach-pxa/poodle.c
>> arch/arm/mach-pxa/spitz.c
>> arch/arm/mach-pxa/tosa.c
>> drivers/mtd/nand/bcm_umi_nand.c
>> drivers/mtd/nand/docg4.c
>> drivers/mtd/nand/fsl_elbc_nand.c
>> drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> drivers/mtd/nand/nand_base.c
>> drivers/mtd/nand/omap2.c
>> drivers/mtd/nand/sh_flctl.c
>> drivers/mtd/nand/sharpsl.c
>> drivers/mtd/nand/tmio_nand.c
>> drivers/mtd/onenand/onenand_bbt.c
>> include/linux/mfd/tmio.h
>> include/linux/mtd/sharpsl.h
>>
>> Any thoughts on how to tackle this? Or is it even worth doing
>> properly? Is there a policy for dealing with old/unmaintained drivers
>> here, if I can't get a response from driver authors?
>
> fsl_elbc_nand uses this for historical reasons, to retain compatibility with
> the original OOB layout which only reserved one byte for the bad block
> marker and let users write to the second byte.  This controller only
> supports 8-bit chips.

OK. Could this be fixed up by forcing nand_chip.badblockpos=0 in
fsl_elbc_nand? I think nand_base/nand_bbt are configured to read/write
only a single byte for 8-bit chips now.

Also, if done properly, this change could still support other legacy
layouts by allowing them to provide their own nand_chip.block_markbad
and nand_chip.block_bad implementations.

> See commit 97ae023648e764f794ffb9c52da109d6caf09c47

I can't find such a commit in upstream. Perhaps you're referring to a
private git tree?

Brian


From scottwood at freescale.com  Wed Sep 26 18:57:46 2012
From: scottwood at freescale.com (Scott Wood)
Date: Wed, 26 Sep 2012 17:57:46 -0500
Subject: [RFC] nand_btt : use nand chip->block_bad
In-Reply-To: <CAN8TOE_D=rHRqpdkrAvtKL2-6x7UB3exfP587D_MZwqP=a=arg@mail.gmail.com>
 (from computersforpeace@gmail.com on Wed Sep 26 17:43:35 2012)
Message-ID: <1348700266.9030.26@snotra>

On 09/26/2012 05:43:35 PM, Brian Norris wrote:
> On Mon, Sep 17, 2012 at 6:28 PM, Scott Wood <scottwood at freescale.com>  
> wrote:
> > On 09/17/2012 08:06:54 PM, Brian Norris wrote:
> >> On Mon, Aug 6, 2012 at 3:21 PM, Brian Norris  
> <computersforpeace at gmail.com> wrote:
> ...
> >> The following files use badblock_pattern to varying degrees. Some  
> are
> >> just duplicating some nand_base stuff, where we can replace the
> >> badblock_pattern with something simple like "chip->badblockpos =  
> 0" or
> >> setting a few "chip->bbt_options |= NAND_BBT_SCAN*" options. But  
> it's
> >> not all so simple:
> >>
> >> arch/arm/mach-pxa/corgi.c
> >> arch/arm/mach-pxa/eseries.c
> >> arch/arm/mach-pxa/poodle.c
> >> arch/arm/mach-pxa/spitz.c
> >> arch/arm/mach-pxa/tosa.c
> >> drivers/mtd/nand/bcm_umi_nand.c
> >> drivers/mtd/nand/docg4.c
> >> drivers/mtd/nand/fsl_elbc_nand.c
> >> drivers/mtd/nand/gpmi-nand/gpmi-nand.c
> >> drivers/mtd/nand/nand_base.c
> >> drivers/mtd/nand/omap2.c
> >> drivers/mtd/nand/sh_flctl.c
> >> drivers/mtd/nand/sharpsl.c
> >> drivers/mtd/nand/tmio_nand.c
> >> drivers/mtd/onenand/onenand_bbt.c
> >> include/linux/mfd/tmio.h
> >> include/linux/mtd/sharpsl.h
> >>
> >> Any thoughts on how to tackle this? Or is it even worth doing
> >> properly? Is there a policy for dealing with old/unmaintained  
> drivers
> >> here, if I can't get a response from driver authors?
> >
> > fsl_elbc_nand uses this for historical reasons, to retain  
> compatibility with
> > the original OOB layout which only reserved one byte for the bad  
> block
> > marker and let users write to the second byte.  This controller only
> > supports 8-bit chips.
> 
> OK. Could this be fixed up by forcing nand_chip.badblockpos=0 in
> fsl_elbc_nand? I think nand_base/nand_bbt are configured to read/write
> only a single byte for 8-bit chips now.

Good, in that case I think we can just drop it.  No need to override  
nand_chip.badblockpos; it's only the size that we were overriding.

> > See commit 97ae023648e764f794ffb9c52da109d6caf09c47
> 
> I can't find such a commit in upstream. Perhaps you're referring to a
> private git tree?

Oops, that was the U-Boot tree. :-P

The Linux commit is 452db2724351ff3d9416a183a7955e00ab4e6ab4

-Scott


From computersforpeace at gmail.com  Wed Sep 26 19:15:58 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 26 Sep 2012 16:15:58 -0700
Subject: [RFC] nand_btt : use nand chip->block_bad
In-Reply-To: <1348700266.9030.26@snotra>
References: <CAN8TOE_D=rHRqpdkrAvtKL2-6x7UB3exfP587D_MZwqP=a=arg@mail.gmail.com>
 <1348700266.9030.26@snotra>
Message-ID: <CAN8TOE9YgCB8bAuQyLNU_YZSvW2_GpA8EvYfT=CEQQyP5RQFZg@mail.gmail.com>

Hi Scott,

On Wed, Sep 26, 2012 at 3:57 PM, Scott Wood <scottwood at freescale.com> wrote:
> On 09/26/2012 05:43:35 PM, Brian Norris wrote:
>>
>> On Mon, Sep 17, 2012 at 6:28 PM, Scott Wood <scottwood at freescale.com>
>> wrote:
>> > On 09/17/2012 08:06:54 PM, Brian Norris wrote:
>> >> On Mon, Aug 6, 2012 at 3:21 PM, Brian Norris
>> >> <computersforpeace at gmail.com> wrote:
>> ...
>> >> The following files use badblock_pattern to varying degrees. Some are
>> >> just duplicating some nand_base stuff, where we can replace the
>> >> badblock_pattern with something simple like "chip->badblockpos = 0" or
>> >> setting a few "chip->bbt_options |= NAND_BBT_SCAN*" options. But it's
>> >> not all so simple:
>> >>
>> >> arch/arm/mach-pxa/corgi.c
>> >> arch/arm/mach-pxa/eseries.c
>> >> arch/arm/mach-pxa/poodle.c
>> >> arch/arm/mach-pxa/spitz.c
>> >> arch/arm/mach-pxa/tosa.c
>> >> drivers/mtd/nand/bcm_umi_nand.c
>> >> drivers/mtd/nand/docg4.c
>> >> drivers/mtd/nand/fsl_elbc_nand.c
>> >> drivers/mtd/nand/gpmi-nand/gpmi-nand.c
>> >> drivers/mtd/nand/nand_base.c
>> >> drivers/mtd/nand/omap2.c
>> >> drivers/mtd/nand/sh_flctl.c
>> >> drivers/mtd/nand/sharpsl.c
>> >> drivers/mtd/nand/tmio_nand.c
>> >> drivers/mtd/onenand/onenand_bbt.c
>> >> include/linux/mfd/tmio.h
>> >> include/linux/mtd/sharpsl.h
>> >>
>> >> Any thoughts on how to tackle this? Or is it even worth doing
>> >> properly? Is there a policy for dealing with old/unmaintained drivers
>> >> here, if I can't get a response from driver authors?
>> >
>> > fsl_elbc_nand uses this for historical reasons, to retain compatibility
>> > with
>> > the original OOB layout which only reserved one byte for the bad block
>> > marker and let users write to the second byte.  This controller only
>> > supports 8-bit chips.
>>
>> OK. Could this be fixed up by forcing nand_chip.badblockpos=0 in
>> fsl_elbc_nand? I think nand_base/nand_bbt are configured to read/write
>> only a single byte for 8-bit chips now.
>
>
> Good, in that case I think we can just drop it.  No need to override
> nand_chip.badblockpos; it's only the size that we were overriding.

Yep. I just figured that out myself.

>> > See commit 97ae023648e764f794ffb9c52da109d6caf09c47
>>
>> I can't find such a commit in upstream. Perhaps you're referring to a
>> private git tree?
>
>
> Oops, that was the U-Boot tree. :-P
>
> The Linux commit is 452db2724351ff3d9416a183a7955e00ab4e6ab4

Found that as well. I should just put a few minute delay on the "send"
button, then I'd have my answers :)

Thanks for the help, I'll send a patch shortly; your testing (if
possible) and Ack would be appreciated.

Brian


From computersforpeace at gmail.com  Wed Sep 26 19:15:27 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 26 Sep 2012 16:15:27 -0700
Subject: [PATCH] mtd: fsl_elbc_nand: remove unnecessary badblock_pattern
Message-ID: <1348701327-12226-1-git-send-email-computersforpeace@gmail.com>

Since the introduction of nand_create_default_bbt_descr() (now known as
nand_create_badblock_pattern()) in

  commit 58373ff0afff4cc8ac40608872995f4d87eb72ec

nand_chip.badblock_pattern will be dynamically calculated to the same
1-byte-length pattern that is required by fsl_elbc_nand. This custom
badblock_pattern is no longer needed, then, and its removal may help
facilitate further nand_bbt.c/nand_base.c cleanup in the future (one
down, many to go?)

Anyway, with nand_bbt.c fixed, this effectively reverts:

  commit 452db2724351ff3d9416a183a7955e00ab4e6ab4
  [MTD] [NAND] fsl_elbc_nand: fix OOB workability for large page NAND chips

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
Cc: Scott Wood <scottwood at freescale.com>
---

Not even compile-tested...

 drivers/mtd/nand/fsl_elbc_nand.c | 15 ---------------
 1 file changed, 15 deletions(-)

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index cc1480a..4c4d3e5 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -109,20 +109,6 @@ static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 };
 
 /*
- * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
- * 1, so we have to adjust bad block pattern. This pattern should be used for
- * x8 chips only. So far hardware does not support x16 chips anyway.
- */
-static u8 scan_ff_pattern[] = { 0xff, };
-
-static struct nand_bbt_descr largepage_memorybased = {
-	.options = 0,
-	.offs = 0,
-	.len = 1,
-	.pattern = scan_ff_pattern,
-};
-
-/*
  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
  * interfere with ECC positions, that's why we implement our own descriptors.
  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
@@ -699,7 +685,6 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 			chip->ecc.layout = (priv->fmr & FMR_ECCM) ?
 			                   &fsl_elbc_oob_lp_eccm1 :
 			                   &fsl_elbc_oob_lp_eccm0;
-			chip->badblock_pattern = &largepage_memorybased;
 		}
 	} else {
 		dev_err(priv->dev,
-- 
1.7.11.3



From computersforpeace at gmail.com  Wed Sep 26 22:37:02 2012
From: computersforpeace at gmail.com (Brian Norris)
Date: Wed, 26 Sep 2012 19:37:02 -0700
Subject: [PATCH] mtd: mtd_oobtest: printk -> pr_{info,err}
Message-ID: <1348713422-16626-1-git-send-email-computersforpeace@gmail.com>

Use pr_info() and pr_err() while defining pr_fmt(). This saves a few
characters, joins a few lines, and makes the code a little more readable
(and grep-able).

Signed-off-by: Brian Norris <computersforpeace at gmail.com>
---
Compile-tested and run once.

 drivers/mtd/tests/mtd_oobtest.c | 169 ++++++++++++++++++++--------------------
 1 file changed, 83 insertions(+), 86 deletions(-)

diff --git a/drivers/mtd/tests/mtd_oobtest.c b/drivers/mtd/tests/mtd_oobtest.c
index ed9b628..a1c059b 100644
--- a/drivers/mtd/tests/mtd_oobtest.c
+++ b/drivers/mtd/tests/mtd_oobtest.c
@@ -19,6 +19,8 @@
  * Author: Adrian Hunter <ext-adrian.hunter at nokia.com>
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <asm/div64.h>
 #include <linux/init.h>
 #include <linux/module.h>
@@ -28,8 +30,6 @@
 #include <linux/slab.h>
 #include <linux/sched.h>
 
-#define PRINT_PREF KERN_INFO "mtd_oobtest: "
-
 static int dev = -EINVAL;
 module_param(dev, int, S_IRUGO);
 MODULE_PARM_DESC(dev, "MTD device number to use");
@@ -80,13 +80,12 @@ static int erase_eraseblock(int ebnum)
 
 	err = mtd_erase(mtd, &ei);
 	if (err) {
-		printk(PRINT_PREF "error %d while erasing EB %d\n", err, ebnum);
+		pr_err("error %d while erasing EB %d\n", err, ebnum);
 		return err;
 	}
 
 	if (ei.state == MTD_ERASE_FAILED) {
-		printk(PRINT_PREF "some erase error occurred at EB %d\n",
-		       ebnum);
+		pr_err("some erase error occurred at EB %d\n", ebnum);
 		return -EIO;
 	}
 
@@ -98,7 +97,7 @@ static int erase_whole_device(void)
 	int err;
 	unsigned int i;
 
-	printk(PRINT_PREF "erasing whole device\n");
+	pr_info("erasing whole device\n");
 	for (i = 0; i < ebcnt; ++i) {
 		if (bbt[i])
 			continue;
@@ -107,7 +106,7 @@ static int erase_whole_device(void)
 			return err;
 		cond_resched();
 	}
-	printk(PRINT_PREF "erased %u eraseblocks\n", i);
+	pr_info("erased %u eraseblocks\n", i);
 	return 0;
 }
 
@@ -141,9 +140,9 @@ static int write_eraseblock(int ebnum)
 		ops.oobbuf    = writebuf;
 		err = mtd_write_oob(mtd, addr, &ops);
 		if (err || ops.oobretlen != use_len) {
-			printk(PRINT_PREF "error: writeoob failed at %#llx\n",
+			pr_err("error: writeoob failed at %#llx\n",
 			       (long long)addr);
-			printk(PRINT_PREF "error: use_len %d, use_offset %d\n",
+			pr_err("error: use_len %d, use_offset %d\n",
 			       use_len, use_offset);
 			errcnt += 1;
 			return err ? err : -1;
@@ -160,7 +159,7 @@ static int write_whole_device(void)
 	int err;
 	unsigned int i;
 
-	printk(PRINT_PREF "writing OOBs of whole device\n");
+	pr_info("writing OOBs of whole device\n");
 	for (i = 0; i < ebcnt; ++i) {
 		if (bbt[i])
 			continue;
@@ -168,10 +167,10 @@ static int write_whole_device(void)
 		if (err)
 			return err;
 		if (i % 256 == 0)
-			printk(PRINT_PREF "written up to eraseblock %u\n", i);
+			pr_info("written up to eraseblock %u\n", i);
 		cond_resched();
 	}
-	printk(PRINT_PREF "written %u eraseblocks\n", i);
+	pr_info("written %u eraseblocks\n", i);
 	return 0;
 }
 
@@ -194,17 +193,17 @@ static int verify_eraseblock(int ebnum)
 		ops.oobbuf    = readbuf;
 		err = mtd_read_oob(mtd, addr, &ops);
 		if (err || ops.oobretlen != use_len) {
-			printk(PRINT_PREF "error: readoob failed at %#llx\n",
+			pr_err("error: readoob failed at %#llx\n",
 			       (long long)addr);
 			errcnt += 1;
 			return err ? err : -1;
 		}
 		if (memcmp(readbuf, writebuf, use_len)) {
-			printk(PRINT_PREF "error: verify failed at %#llx\n",
+			pr_err("error: verify failed at %#llx\n",
 			       (long long)addr);
 			errcnt += 1;
 			if (errcnt > 1000) {
-				printk(PRINT_PREF "error: too many errors\n");
+				pr_err("error: too many errors\n");
 				return -1;
 			}
 		}
@@ -221,29 +220,28 @@ static int verify_eraseblock(int ebnum)
 			ops.oobbuf    = readbuf;
 			err = mtd_read_oob(mtd, addr, &ops);
 			if (err || ops.oobretlen != mtd->ecclayout->oobavail) {
-				printk(PRINT_PREF "error: readoob failed at "
-				       "%#llx\n", (long long)addr);
+				pr_err("error: readoob failed at %#llx\n",
+						(long long)addr);
 				errcnt += 1;
 				return err ? err : -1;
 			}
 			if (memcmp(readbuf + use_offset, writebuf, use_len)) {
-				printk(PRINT_PREF "error: verify failed at "
-				       "%#llx\n", (long long)addr);
+				pr_err("error: verify failed at %#llx\n",
+						(long long)addr);
 				errcnt += 1;
 				if (errcnt > 1000) {
-					printk(PRINT_PREF "error: too many "
-					       "errors\n");
+					pr_err("error: too many errors\n");
 					return -1;
 				}
 			}
 			for (k = 0; k < use_offset; ++k)
 				if (readbuf[k] != 0xff) {
-					printk(PRINT_PREF "error: verify 0xff "
+					pr_err("error: verify 0xff "
 					       "failed at %#llx\n",
 					       (long long)addr);
 					errcnt += 1;
 					if (errcnt > 1000) {
-						printk(PRINT_PREF "error: too "
+						pr_err("error: too "
 						       "many errors\n");
 						return -1;
 					}
@@ -251,12 +249,12 @@ static int verify_eraseblock(int ebnum)
 			for (k = use_offset + use_len;
 			     k < mtd->ecclayout->oobavail; ++k)
 				if (readbuf[k] != 0xff) {
-					printk(PRINT_PREF "error: verify 0xff "
+					pr_err("error: verify 0xff "
 					       "failed at %#llx\n",
 					       (long long)addr);
 					errcnt += 1;
 					if (errcnt > 1000) {
-						printk(PRINT_PREF "error: too "
+						pr_err("error: too "
 						       "many errors\n");
 						return -1;
 					}
@@ -286,17 +284,17 @@ static int verify_eraseblock_in_one_go(int ebnum)
 	ops.oobbuf    = readbuf;
 	err = mtd_read_oob(mtd, addr, &ops);
 	if (err || ops.oobretlen != len) {
-		printk(PRINT_PREF "error: readoob failed at %#llx\n",
+		pr_err("error: readoob failed at %#llx\n",
 		       (long long)addr);
 		errcnt += 1;
 		return err ? err : -1;
 	}
 	if (memcmp(readbuf, writebuf, len)) {
-		printk(PRINT_PREF "error: verify failed at %#llx\n",
+		pr_err("error: verify failed at %#llx\n",
 		       (long long)addr);
 		errcnt += 1;
 		if (errcnt > 1000) {
-			printk(PRINT_PREF "error: too many errors\n");
+			pr_err("error: too many errors\n");
 			return -1;
 		}
 	}
@@ -309,7 +307,7 @@ static int verify_all_eraseblocks(void)
 	int err;
 	unsigned int i;
 
-	printk(PRINT_PREF "verifying all eraseblocks\n");
+	pr_info("verifying all eraseblocks\n");
 	for (i = 0; i < ebcnt; ++i) {
 		if (bbt[i])
 			continue;
@@ -317,10 +315,10 @@ static int verify_all_eraseblocks(void)
 		if (err)
 			return err;
 		if (i % 256 == 0)
-			printk(PRINT_PREF "verified up to eraseblock %u\n", i);
+			pr_info("verified up to eraseblock %u\n", i);
 		cond_resched();
 	}
-	printk(PRINT_PREF "verified %u eraseblocks\n", i);
+	pr_info("verified %u eraseblocks\n", i);
 	return 0;
 }
 
@@ -331,7 +329,7 @@ static int is_block_bad(int ebnum)
 
 	ret = mtd_block_isbad(mtd, addr);
 	if (ret)
-		printk(PRINT_PREF "block %d is bad\n", ebnum);
+		pr_info("block %d is bad\n", ebnum);
 	return ret;
 }
 
@@ -341,18 +339,18 @@ static int scan_for_bad_eraseblocks(void)
 
 	bbt = kmalloc(ebcnt, GFP_KERNEL);
 	if (!bbt) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+		pr_err("error: cannot allocate memory\n");
 		return -ENOMEM;
 	}
 
-	printk(PRINT_PREF "scanning for bad eraseblocks\n");
+	pr_info("scanning for bad eraseblocks\n");
 	for (i = 0; i < ebcnt; ++i) {
 		bbt[i] = is_block_bad(i) ? 1 : 0;
 		if (bbt[i])
 			bad += 1;
 		cond_resched();
 	}
-	printk(PRINT_PREF "scanned %d eraseblocks, %d are bad\n", i, bad);
+	pr_info("scanned %d eraseblocks, %d are bad\n", i, bad);
 	return 0;
 }
 
@@ -368,22 +366,22 @@ static int __init mtd_oobtest_init(void)
 	printk(KERN_INFO "=================================================\n");
 
 	if (dev < 0) {
-		printk(PRINT_PREF "Please specify a valid mtd-device via module paramter\n");
+		pr_info("Please specify a valid mtd-device via module paramter\n");
 		printk(KERN_CRIT "CAREFUL: This test wipes all data on the specified MTD device!\n");
 		return -EINVAL;
 	}
 
-	printk(PRINT_PREF "MTD device: %d\n", dev);
+	pr_info("MTD device: %d\n", dev);
 
 	mtd = get_mtd_device(NULL, dev);
 	if (IS_ERR(mtd)) {
 		err = PTR_ERR(mtd);
-		printk(PRINT_PREF "error: cannot get MTD device\n");
+		pr_err("error: cannot get MTD device\n");
 		return err;
 	}
 
 	if (mtd->type != MTD_NANDFLASH) {
-		printk(PRINT_PREF "this test requires NAND flash\n");
+		pr_info("this test requires NAND flash\n");
 		goto out;
 	}
 
@@ -392,7 +390,7 @@ static int __init mtd_oobtest_init(void)
 	ebcnt = tmp;
 	pgcnt = mtd->erasesize / mtd->writesize;
 
-	printk(PRINT_PREF "MTD device size %llu, eraseblock size %u, "
+	pr_info("MTD device size %llu, eraseblock size %u, "
 	       "page size %u, count of eraseblocks %u, pages per "
 	       "eraseblock %u, OOB size %u\n",
 	       (unsigned long long)mtd->size, mtd->erasesize,
@@ -401,12 +399,12 @@ static int __init mtd_oobtest_init(void)
 	err = -ENOMEM;
 	readbuf = kmalloc(mtd->erasesize, GFP_KERNEL);
 	if (!readbuf) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+		pr_err("error: cannot allocate memory\n");
 		goto out;
 	}
 	writebuf = kmalloc(mtd->erasesize, GFP_KERNEL);
 	if (!writebuf) {
-		printk(PRINT_PREF "error: cannot allocate memory\n");
+		pr_err("error: cannot allocate memory\n");
 		goto out;
 	}
 
@@ -420,7 +418,7 @@ static int __init mtd_oobtest_init(void)
 	vary_offset = 0;
 
 	/* First test: write all OOB, read it back and verify */
-	printk(PRINT_PREF "test 1 of 5\n");
+	pr_info("test 1 of 5\n");
 
 	err = erase_whole_device();
 	if (err)
@@ -440,7 +438,7 @@ static int __init mtd_oobtest_init(void)
 	 * Second test: write all OOB, a block at a time, read it back and
 	 * verify.
 	 */
-	printk(PRINT_PREF "test 2 of 5\n");
+	pr_info("test 2 of 5\n");
 
 	err = erase_whole_device();
 	if (err)
@@ -453,7 +451,7 @@ static int __init mtd_oobtest_init(void)
 
 	/* Check all eraseblocks */
 	simple_srand(3);
-	printk(PRINT_PREF "verifying all eraseblocks\n");
+	pr_info("verifying all eraseblocks\n");
 	for (i = 0; i < ebcnt; ++i) {
 		if (bbt[i])
 			continue;
@@ -461,16 +459,16 @@ static int __init mtd_oobtest_init(void)
 		if (err)
 			goto out;
 		if (i % 256 == 0)
-			printk(PRINT_PREF "verified up to eraseblock %u\n", i);
+			pr_info("verified up to eraseblock %u\n", i);
 		cond_resched();
 	}
-	printk(PRINT_PREF "verified %u eraseblocks\n", i);
+	pr_info("verified %u eraseblocks\n", i);
 
 	/*
 	 * Third test: write OOB at varying offsets and lengths, read it back
 	 * and verify.
 	 */
-	printk(PRINT_PREF "test 3 of 5\n");
+	pr_info("test 3 of 5\n");
 
 	err = erase_whole_device();
 	if (err)
@@ -503,7 +501,7 @@ static int __init mtd_oobtest_init(void)
 	vary_offset = 0;
 
 	/* Fourth test: try to write off end of device */
-	printk(PRINT_PREF "test 4 of 5\n");
+	pr_info("test 4 of 5\n");
 
 	err = erase_whole_device();
 	if (err)
@@ -522,14 +520,14 @@ static int __init mtd_oobtest_init(void)
 	ops.ooboffs   = mtd->ecclayout->oobavail;
 	ops.datbuf    = NULL;
 	ops.oobbuf    = writebuf;
-	printk(PRINT_PREF "attempting to start write past end of OOB\n");
-	printk(PRINT_PREF "an error is expected...\n");
+	pr_info("attempting to start write past end of OOB\n");
+	pr_info("an error is expected...\n");
 	err = mtd_write_oob(mtd, addr0, &ops);
 	if (err) {
-		printk(PRINT_PREF "error occurred as expected\n");
+		pr_info("error occurred as expected\n");
 		err = 0;
 	} else {
-		printk(PRINT_PREF "error: can write past end of OOB\n");
+		pr_err("error: can write past end of OOB\n");
 		errcnt += 1;
 	}
 
@@ -542,19 +540,19 @@ static int __init mtd_oobtest_init(void)
 	ops.ooboffs   = mtd->ecclayout->oobavail;
 	ops.datbuf    = NULL;
 	ops.oobbuf    = readbuf;
-	printk(PRINT_PREF "attempting to start read past end of OOB\n");
-	printk(PRINT_PREF "an error is expected...\n");
+	pr_info("attempting to start read past end of OOB\n");
+	pr_info("an error is expected...\n");
 	err = mtd_read_oob(mtd, addr0, &ops);
 	if (err) {
-		printk(PRINT_PREF "error occurred as expected\n");
+		pr_info("error occurred as expected\n");
 		err = 0;
 	} else {
-		printk(PRINT_PREF "error: can read past end of OOB\n");
+		pr_err("error: can read past end of OOB\n");
 		errcnt += 1;
 	}
 
 	if (bbt[ebcnt - 1])
-		printk(PRINT_PREF "skipping end of device tests because last "
+		pr_info("skipping end of device tests because last "
 		       "block is bad\n");
 	else {
 		/* Attempt to write off end of device */
@@ -566,14 +564,14 @@ static int __init mtd_oobtest_init(void)
 		ops.ooboffs   = 0;
 		ops.datbuf    = NULL;
 		ops.oobbuf    = writebuf;
-		printk(PRINT_PREF "attempting to write past end of device\n");
-		printk(PRINT_PREF "an error is expected...\n");
+		pr_info("attempting to write past end of device\n");
+		pr_info("an error is expected...\n");
 		err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
 		if (err) {
-			printk(PRINT_PREF "error occurred as expected\n");
+			pr_info("error occurred as expected\n");
 			err = 0;
 		} else {
-			printk(PRINT_PREF "error: wrote past end of device\n");
+			pr_err("error: wrote past end of device\n");
 			errcnt += 1;
 		}
 
@@ -586,14 +584,14 @@ static int __init mtd_oobtest_init(void)
 		ops.ooboffs   = 0;
 		ops.datbuf    = NULL;
 		ops.oobbuf    = readbuf;
-		printk(PRINT_PREF "attempting to read past end of device\n");
-		printk(PRINT_PREF "an error is expected...\n");
+		pr_info("attempting to read past end of device\n");
+		pr_info("an error is expected...\n");
 		err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
 		if (err) {
-			printk(PRINT_PREF "error occurred as expected\n");
+			pr_info("error occurred as expected\n");
 			err = 0;
 		} else {
-			printk(PRINT_PREF "error: read past end of device\n");
+			pr_err("error: read past end of device\n");
 			errcnt += 1;
 		}
 
@@ -610,14 +608,14 @@ static int __init mtd_oobtest_init(void)
 		ops.ooboffs   = 1;
 		ops.datbuf    = NULL;
 		ops.oobbuf    = writebuf;
-		printk(PRINT_PREF "attempting to write past end of device\n");
-		printk(PRINT_PREF "an error is expected...\n");
+		pr_info("attempting to write past end of device\n");
+		pr_info("an error is expected...\n");
 		err = mtd_write_oob(mtd, mtd->size - mtd->writesize, &ops);
 		if (err) {
-			printk(PRINT_PREF "error occurred as expected\n");
+			pr_info("error occurred as expected\n");
 			err = 0;
 		} else {
-			printk(PRINT_PREF "error: wrote past end of device\n");
+			pr_err("error: wrote past end of device\n");
 			errcnt += 1;
 		}
 
@@ -630,20 +628,20 @@ static int __init mtd_oobtest_init(void)
 		ops.ooboffs   = 1;
 		ops.datbuf    = NULL;
 		ops.oobbuf    = readbuf;
-		printk(PRINT_PREF "attempting to read past end of device\n");
-		printk(PRINT_PREF "an error is expected...\n");
+		pr_info("attempting to read past end of device\n");
+		pr_info("an error is expected...\n");
 		err = mtd_read_oob(mtd, mtd->size - mtd->writesize, &ops);
 		if (err) {
-			printk(PRINT_PREF "error occurred as expected\n");
+			pr_info("error occurred as expected\n");
 			err = 0;
 		} else {
-			printk(PRINT_PREF "error: read past end of device\n");
+			pr_err("error: read past end of device\n");
 			errcnt += 1;
 		}
 	}
 
 	/* Fifth test: write / read across block boundaries */
-	printk(PRINT_PREF "test 5 of 5\n");
+	pr_info("test 5 of 5\n");
 
 	/* Erase all eraseblocks */
 	err = erase_whole_device();
@@ -652,7 +650,7 @@ static int __init mtd_oobtest_init(void)
 
 	/* Write all eraseblocks */
 	simple_srand(11);
-	printk(PRINT_PREF "writing OOBs of whole device\n");
+	pr_info("writing OOBs of whole device\n");
 	for (i = 0; i < ebcnt - 1; ++i) {
 		int cnt = 2;
 		int pg;
@@ -674,17 +672,16 @@ static int __init mtd_oobtest_init(void)
 			if (err)
 				goto out;
 			if (i % 256 == 0)
-				printk(PRINT_PREF "written up to eraseblock "
-				       "%u\n", i);
+				pr_info("written up to eraseblock %u\n", i);
 			cond_resched();
 			addr += mtd->writesize;
 		}
 	}
-	printk(PRINT_PREF "written %u eraseblocks\n", i);
+	pr_info("written %u eraseblocks\n", i);
 
 	/* Check all eraseblocks */
 	simple_srand(11);
-	printk(PRINT_PREF "verifying all eraseblocks\n");
+	pr_info("verifying all eraseblocks\n");
 	for (i = 0; i < ebcnt - 1; ++i) {
 		if (bbt[i] || bbt[i + 1])
 			continue;
@@ -702,28 +699,28 @@ static int __init mtd_oobtest_init(void)
 		if (err)
 			goto out;
 		if (memcmp(readbuf, writebuf, mtd->ecclayout->oobavail * 2)) {
-			printk(PRINT_PREF "error: verify failed at %#llx\n",
+			pr_err("error: verify failed at %#llx\n",
 			       (long long)addr);
 			errcnt += 1;
 			if (errcnt > 1000) {
-				printk(PRINT_PREF "error: too many errors\n");
+				pr_err("error: too many errors\n");
 				goto out;
 			}
 		}
 		if (i % 256 == 0)
-			printk(PRINT_PREF "verified up to eraseblock %u\n", i);
+			pr_info("verified up to eraseblock %u\n", i);
 		cond_resched();
 	}
-	printk(PRINT_PREF "verified %u eraseblocks\n", i);
+	pr_info("verified %u eraseblocks\n", i);
 
-	printk(PRINT_PREF "finished with %d errors\n", errcnt);
+	pr_info("finished with %d errors\n", errcnt);
 out:
 	kfree(bbt);
 	kfree(writebuf);
 	kfree(readbuf);
 	put_mtd_device(mtd);
 	if (err)
-		printk(PRINT_PREF "error %d occurred\n", err);
+		pr_info("error %d occurred\n", err);
 	printk(KERN_INFO "=================================================\n");
 	return err;
 }
-- 
1.7.11.3



From Daniel.MONDON at lpgsystems.com  Thu Sep 27 03:08:12 2012
From: Daniel.MONDON at lpgsystems.com (MONDON Daniel)
Date: Thu, 27 Sep 2012 09:08:12 +0200
Subject: ubinize.cfg for NAND with multi ubi devices and multi volume
 inside
In-Reply-To: <alpine.DEB.2.00.1209261307230.19047@lnxricardw.se.axis.com>
References: <D604D5FB4D200642AA2FAAE94E39258601AFFFCE@CARAMBAR.lpg.priv>
 <alpine.DEB.2.00.1209261307230.19047@lnxricardw.se.axis.com>
Message-ID: <D604D5FB4D200642AA2FAAE94E39258601B000FD@CARAMBAR.lpg.priv>

>On Wed, 26 Sep 2012, MONDON Daniel wrote:
>
>> I don't find how to generate my .cfg for the ubinize command.
>> Perhaps impossible ?
>>
>> I'v got 1GB NAND with 4 UBI devices.
>> I want to ubinize some volumes in some UBI devices.
>>
>> For example : (i've got ubi1_0 to ubi1_3 and ubi4_0 to ubi4_4)
>> Ubi1_0 (80MiB)
>> Ubi1_3 (300MiB)
>> Ubi4_0 (30MiB)
>> Ubi4_4 (30MiB)
>>
>> What have i to write in the .cfg file.
>>
>> With the result, i will use ubiupdatevol to write fs images.
>
>Ubinize is not intended for use by ubiupdatevol, rather it is intended when you need an image to write to raw flash, for >instance during production. With ubiupdatevol you simply supply the volume images that you get from mkfs.ubifs (or the binary >blobs if that's what you want to store there).
>
>Or do you mean that you already have data in your volumes, and you want to create a file system image which you can then >write to another device using ubiupdatevol? In that case you would use mkfs.ubifs to create a file system image from the file >system.

Yes. 
I want to take volumes data and create file system image to update another device.
I will have a look to mkfs.ubifs!
:)


>/Ricard
>-- 
>Ricard Wolf Wanderl?f                           ricardw(at)axis.com
>Axis Communications AB, Lund, Sweden            www.axis.com
>Phone +46 46 272 2016                           Fax +46 46 13 61 30


From matthieu.castet at parrot.com  Thu Sep 27 04:15:49 2012
From: matthieu.castet at parrot.com (Matthieu CASTET)
Date: Thu, 27 Sep 2012 10:15:49 +0200
Subject: [PATCH] mtd: m25p80: add support for the windbond w25q256 chip
In-Reply-To: <CAN8TOE-h1VrbNg6ZqwQdhLaQ18E4-=_Lw+biuhGONUS5HCx-4g@mail.gmail.com>
References: <1348563927-9131-1-git-send-email-matthieu.castet@parrot.com>
 <CAN8TOE-h1VrbNg6ZqwQdhLaQ18E4-=_Lw+biuhGONUS5HCx-4g@mail.gmail.com>
Message-ID: <50640B35.206@parrot.com>

Brian Norris a ?crit :
> On Tue, Sep 25, 2012 at 2:05 AM, Matthieu CASTET
> <matthieu.castet at parrot.com> wrote:
>> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
>> index 5257345..4eb99c6 100644
>> --- a/drivers/mtd/devices/m25p80.c
>> +++ b/drivers/mtd/devices/m25p80.c
>> @@ -168,6 +168,7 @@ static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
>>  {
>>         switch (JEDEC_MFR(jedec_id)) {
>>         case CFI_MFR_MACRONIX:
>> +       case 0xEF /* winbond */:
>>                 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
>>                 return spi_write(flash->spi, flash->command, 1);
>>         default:
> 
> Just checking: Winbond didn't use their known manufacturer ID (0xDA)
> for this chip? Do they have other chips that support/need 4-byte
> addressing and use 0xDA?
> 
I don't know, but if you look in m25p80 device list, all windbond flash start
(the jdec manuf code) with 0xEF [1].
May be MFR code are different for NOR flash and spi NOR ?

For info the datasheet is avaiable at :
http://www.winbond.com.tw/NR/rdonlyres/658E0D71-9AC3-48D6-B043-3702625A2CF5/0/W25Q256FV.pdf

Matthieu

[1]
    /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
    { "w25x10", INFO(0xef3011, 0, 64 * 1024,  2,  SECT_4K) },
    { "w25x20", INFO(0xef3012, 0, 64 * 1024,  4,  SECT_4K) },
    { "w25x40", INFO(0xef3013, 0, 64 * 1024,  8,  SECT_4K) },
    { "w25x80", INFO(0xef3014, 0, 64 * 1024,  16, SECT_4K) },
    { "w25x16", INFO(0xef3015, 0, 64 * 1024,  32, SECT_4K) },
    { "w25x32", INFO(0xef3016, 0, 64 * 1024,  64, SECT_4K) },
    { "w25q32", INFO(0xef4016, 0, 64 * 1024,  64, SECT_4K) },
    { "w25q32dw", INFO(0xef6016, 0, 64 * 1024,  64, SECT_4K) },
    { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
    { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
    { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
    { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },


From zajec5 at gmail.com  Thu Sep 27 07:55:42 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:42 +0200
Subject: [PATCH 1/6] bcma: export PLL reading function
Message-ID: <1348746947-2349-1-git-send-email-zajec5@gmail.com>

This is required by NAND flash driver for initializing wait counters.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0001-bcma-export-PLL-reading-function.patch                           
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues
---
 drivers/bcma/driver_chipcommon_pmu.c |    3 ++-
 include/linux/bcma/bcma.h            |    1 +
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
index 8b8f2f3..c7d94b47 100644
--- a/drivers/bcma/driver_chipcommon_pmu.c
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -13,12 +13,13 @@
 #include <linux/export.h>
 #include <linux/bcma/bcma.h>
 
-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
+u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
 {
 	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
 	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
 	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 }
+EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
 
 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
 {
diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index 1954a4e..b58fae0 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -345,6 +345,7 @@ extern void bcma_core_set_clockmode(struct bcma_device *core,
 				    enum bcma_clkmode clkmode);
 extern void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status,
 			      bool on);
+extern u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset);
 #define BCMA_DMA_TRANSLATION_MASK	0xC0000000
 #define  BCMA_DMA_TRANSLATION_NONE	0x00000000
 #define  BCMA_DMA_TRANSLATION_DMA32_CMT	0x40000000 /* Client Mode Translation for 32-bit DMA */
-- 
1.7.7



From zajec5 at gmail.com  Thu Sep 27 07:55:43 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:43 +0200
Subject: [PATCH 2/6] mtd: prepare place for BCMA NAND flash driver(s)
In-Reply-To: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
References: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348746947-2349-2-git-send-email-zajec5@gmail.com>

BCMA bus can contain NAND flash memory, it's registered in system as
platform device. This adds required hooks and place for controler
specific drivers.

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0002-mtd-prepare-place-for-BCMA-NAND-flash-driver-s.patch 
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues

WARNING:CONFIG_DESCRIPTION: please write a paragraph that describes the config symbol fully
#33: FILE: drivers/mtd/nand/Kconfig:492:
+config MTD_NAND_BCM47XXNFLASH

WARNING:STATIC_CONST_CHAR_ARRAY: static const char * array should probably be static const char * const
#113: FILE: drivers/mtd/nand/bcm47xxnflash/main.c:24:
+static const char *probes[] = { "bcm47xxpart", NULL };


I believe that Kconfig description is OK, and I don't anything wrong
with my probes. Other drivers define probes in the same way.
---
 drivers/mtd/nand/Kconfig                       |    8 ++
 drivers/mtd/nand/Makefile                      |    1 +
 drivers/mtd/nand/bcm47xxnflash/Makefile        |    3 +
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |   14 +++
 drivers/mtd/nand/bcm47xxnflash/main.c          |  108 ++++++++++++++++++++++++
 5 files changed, 134 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/Makefile
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/main.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 4883139..6ba1988 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -446,6 +446,14 @@ config MTD_NAND_GPMI_NAND
 	 block, such as SD card. So pay attention to it when you enable
 	 the GPMI.
 
+config MTD_NAND_BCM47XXNFLASH
+	tristate "R/O support for NAND flash on BCMA bus"
+	depends on BCMA_NFLASH
+	help
+	  BCMA bus can have various flash memories attached, they are
+	  registered by bcma as platform devices. This enables driver for
+	  NAND flash memories. For now only read mode is implemented.
+
 config MTD_NAND_PLATFORM
 	tristate "Support for generic platform NAND driver"
 	depends on HAS_IOMEM
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 2cbd091..01f39f87c 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_RICOH)		+= r852.o
 obj-$(CONFIG_MTD_NAND_JZ4740)		+= jz4740_nand.o
 obj-$(CONFIG_MTD_NAND_GPMI_NAND)	+= gpmi-nand/
 obj-$(CONFIG_MTD_NAND_XWAY)		+= xway_nand.o
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash/
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
new file mode 100644
index 0000000..1d0693a
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -0,0 +1,3 @@
+bcm47xxnflash-y				+= main.o
+
+obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
new file mode 100644
index 0000000..2e8864a
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -0,0 +1,14 @@
+#ifndef __BCM47XXNFLASH_H
+#define __BCM47XXNFLASH_H
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
+struct bcm47xxnflash {
+	struct bcma_drv_cc *cc;
+
+	struct nand_chip nand_chip;
+	struct mtd_info mtd;
+};
+
+#endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/main.c b/drivers/mtd/nand/bcm47xxnflash/main.c
new file mode 100644
index 0000000..fc9139d
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/main.c
@@ -0,0 +1,108 @@
+/*
+ * BCM47XX NAND flash driver
+ *
+ * Copyright (C) 2012 Rafa? Mi?ecki <zajec5 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/bcma/bcma.h>
+
+#include "bcm47xxnflash.h"
+
+MODULE_DESCRIPTION("NAND flash driver for BCMA bus");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Rafa? Mi?ecki");
+
+static const char *probes[] = { "bcm47xxpart", NULL };
+
+static int bcm47xxnflash_probe(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+	struct bcm47xxnflash *b47n;
+	int err = 0;
+
+	b47n = kzalloc(sizeof(*b47n), GFP_KERNEL);
+	if (!b47n) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	b47n->nand_chip.priv = b47n;
+	b47n->mtd.owner = THIS_MODULE;
+	b47n->mtd.priv = &b47n->nand_chip; /* Required */
+	b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash);
+
+	if (0) {
+		/* TODO: init device */
+	} else {
+		pr_err("Device not supported\n");
+		err = -ENOTSUPP;
+	}
+	if (err) {
+		pr_err("Initialization failed: %d\n", err);
+		goto err_init;
+	}
+
+	err = mtd_device_parse_register(&b47n->mtd, probes, NULL, NULL, 0);
+	if (err) {
+		pr_err("Failed to register MTD device: %d\n", err);
+		goto err_dev_reg;
+	}
+
+	return 0;
+
+err_dev_reg:
+err_init:
+	kfree(b47n);
+out:
+	return err;
+}
+
+static int __devexit bcm47xxnflash_remove(struct platform_device *pdev)
+{
+	struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
+
+	if (nflash->mtd)
+		mtd_device_unregister(nflash->mtd);
+
+	return 0;
+}
+
+static struct platform_driver bcm47xxnflash_driver = {
+	.remove = __devexit_p(bcm47xxnflash_remove),
+	.driver = {
+		.name = "bcma_nflash",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm47xxnflash_init(void)
+{
+	int err;
+
+	/*
+	 * Platform device "bcma_nflash" exists on SoCs and is registered very
+	 * early, it won't be added during runtime (use platform_driver_probe).
+	 */
+	err = platform_driver_probe(&bcm47xxnflash_driver, bcm47xxnflash_probe);
+	if (err)
+		pr_err("Failed to register serial flash driver: %d\n", err);
+
+	return err;
+}
+
+static void __exit bcm47xxnflash_exit(void)
+{
+	platform_driver_unregister(&bcm47xxnflash_driver);
+}
+
+module_init(bcm47xxnflash_init);
+module_exit(bcm47xxnflash_exit);
-- 
1.7.7



From zajec5 at gmail.com  Thu Sep 27 07:55:44 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:44 +0200
Subject: [PATCH 3/6] mtd: bcm47xxnflash: init NAND on BCM4706
In-Reply-To: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
References: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348746947-2349-3-git-send-email-zajec5@gmail.com>

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0003-mtd-bcm47xxnflash-init-NAND-on-BCM4706.patch 
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues
---
 drivers/mtd/nand/bcm47xxnflash/Makefile      |    1 +
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c |  111 ++++++++++++++++++++++++++
 2 files changed, 112 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
index 1d0693a..4f688f9 100644
--- a/drivers/mtd/nand/bcm47xxnflash/Makefile
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -1,3 +1,4 @@
 bcm47xxnflash-y				+= main.o
+bcm47xxnflash-				+= ops_bcm4706.o
 
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
new file mode 100644
index 0000000..2f0ad1d
--- /dev/null
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -0,0 +1,111 @@
+/*
+ * BCM47XX NAND flash driver
+ *
+ * Copyright (C) 2012 Rafa? Mi?ecki <zajec5 at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/bcma/bcma.h>
+
+#include "bcm47xxnflash.h"
+
+/**************************************************
+ * Various helpers
+ **************************************************/
+
+static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
+{
+	return ((ns * 1000 * clock) / 1000000) + 1;
+}
+
+/**************************************************
+ * NAND chip ops
+ **************************************************/
+
+/* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
+static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
+						  int chip)
+{
+	return;
+}
+
+/**************************************************
+ * Init
+ **************************************************/
+
+int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
+{
+	int err;
+	u32 freq;
+	u16 clock;
+	u8 w0, w1, w2, w3, w4;
+
+	unsigned long chipsize; /* MiB */
+	u8 tbits, col_bits, col_size, row_bits, row_bsize;
+	u32 col_mask;
+	u32 val;
+
+	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
+	b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
+
+	/* Enable NAND flash access */
+	bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
+		      BCMA_CC_4706_FLASHSCFG_NF1);
+
+	/* Configure wait counters */
+	if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
+		freq = 100000000;
+	} else {
+		freq = bcma_chipco_pll_read(b47n->cc, 4);
+		freq = (freq * 0xFFF) >> 3;
+		freq = (freq * 25000000) >> 3;
+	}
+	clock = freq / 1000000;
+	w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
+	w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
+	w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
+	w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
+	w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
+	bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
+			(w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
+
+	/* Scan NAND */
+	err = nand_scan(&b47n->mtd, 1);
+	if (err) {
+		pr_err("Could not scan NAND flash: %d\n", err);
+		goto exit;
+	}
+
+	/* Configure FLASH */
+	chipsize = b47n->nand_chip.chipsize >> 20;
+	tbits = ffs(chipsize); /* find first bit set */
+	if (!tbits || tbits != fls(chipsize)) {
+		pr_err("Invalid flash size: 0x%lX\n", chipsize);
+		err = -ENOTSUPP;
+		goto exit;
+	}
+	tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
+
+	col_bits = b47n->nand_chip.page_shift + 1;
+	col_mask = (1 << col_bits) - 1;
+	col_size = (col_bits + 7) / 8;
+
+	row_bits = tbits - col_bits + 1;
+	row_bsize = (row_bits + 7) / 8;
+
+	val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
+	bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
+
+exit:
+	if (err)
+		bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
+			       ~BCMA_CC_4706_FLASHSCFG_NF1);
+	return err;
+}
-- 
1.7.7



From zajec5 at gmail.com  Thu Sep 27 07:55:45 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:45 +0200
Subject: [PATCH 4/6] mtd: bcm47xxnflash: support for NAND_CMD_READID command
In-Reply-To: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
References: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348746947-2349-4-git-send-email-zajec5@gmail.com>

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0004-mtd-bcm47xxnflash-support-for-NAND_CMD_READID-comman.patch 
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues

WARNING:LONG_LINE: line over 80 characters
#120: FILE: drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c:106:
+                       b47n->id_data[i] = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA) & 0xFF;


I avoid lines over 80 chars, but in this single case I left it to
make it easier to read the code (don't like having that code in 3 lines)
---
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    5 +
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c   |   99 ++++++++++++++++++++++++
 2 files changed, 104 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index 2e8864a..cc71400 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -9,6 +9,11 @@ struct bcm47xxnflash {
 
 	struct nand_chip nand_chip;
 	struct mtd_info mtd;
+
+	unsigned curr_command;
+	int curr_column;
+
+	u8 id_data[8];
 };
 
 #endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
index 2f0ad1d..9ca6882 100644
--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -16,6 +16,10 @@
 
 #include "bcm47xxnflash.h"
 
+/* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
+ * shown 164 retries as maxiumum. */
+#define NFLASH_READY_RETRIES		1000
+
 /**************************************************
  * Various helpers
  **************************************************/
@@ -25,6 +29,24 @@ static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
 	return ((ns * 1000 * clock) / 1000000) + 1;
 }
 
+static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
+{
+	int i = 0;
+
+	bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, 0x80000000 | code);
+	for (i = 0; i < NFLASH_READY_RETRIES; i++) {
+		if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x80000000)) {
+			i = 0;
+			break;
+		}
+	}
+	if (i) {
+		pr_err("NFLASH control command not ready!\n");
+		return -EBUSY;
+	}
+	return 0;
+}
+
 /**************************************************
  * NAND chip ops
  **************************************************/
@@ -36,6 +58,81 @@ static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 	return;
 }
 
+/*
+ * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
+ * For example, reading chip id is performed in a non-standard way.
+ * Setting column and page is also handled differently, we use a special
+ * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
+ * standard commands would be much more complicated.
+ */
+static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
+					      unsigned command, int column,
+					      int page_addr)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+	u32 ctlcode;
+	int i;
+
+	if (column != -1)
+		b47n->curr_column = column;
+
+	switch (command) {
+	case NAND_CMD_RESET:
+		pr_warn("Chip reset not implemented yet\n");
+		break;
+	case NAND_CMD_READID:
+		ctlcode = 0x40000000 | 0x01000000 | 0x00080000 | 0x00010000;
+		ctlcode |= NAND_CMD_READID;
+		if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
+			pr_err("READID error\n");
+			break;
+		}
+
+		/*
+		 * Reading is specific, last one has to go without 0x40000000
+		 * bit. We don't know how many reads NAND subsystem is going
+		 * to perform, so cache everything.
+		 */
+		for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
+			ctlcode = 0x40000000 | 0x00100000;
+			if (i == ARRAY_SIZE(b47n->id_data) - 1)
+				ctlcode &= ~0x40000000;
+			if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
+							      ctlcode)) {
+				pr_err("READID error\n");
+				break;
+			}
+			b47n->id_data[i] = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA) & 0xFF;
+		}
+
+		break;
+	default:
+		pr_err("Command 0x%X unsupported\n", command);
+		break;
+	}
+	b47n->curr_command = command;
+}
+
+static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	switch (b47n->curr_command) {
+	case NAND_CMD_READID:
+		if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
+			pr_err("Requested invalid id_data: %d\n",
+			       b47n->curr_column);
+			return 0;
+		}
+		return b47n->id_data[b47n->curr_column++];
+	}
+
+	pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
+	return 0;
+}
+
 /**************************************************
  * Init
  **************************************************/
@@ -53,6 +150,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 	u32 val;
 
 	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
+	b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
+	b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 	b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 
 	/* Enable NAND flash access */
-- 
1.7.7



From zajec5 at gmail.com  Thu Sep 27 07:55:46 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:46 +0200
Subject: [PATCH 5/6] mtd: bcm47xxnflash: implement reading
In-Reply-To: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
References: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348746947-2349-5-git-send-email-zajec5@gmail.com>

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0005-mtd-bcm47xxnflash-implement-reading.patch 
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues
---
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    1 +
 drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c   |  106 ++++++++++++++++++++++++
 2 files changed, 107 insertions(+), 0 deletions(-)

diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index cc71400..264aec4 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -11,6 +11,7 @@ struct bcm47xxnflash {
 	struct mtd_info mtd;
 
 	unsigned curr_command;
+	int curr_page_addr;
 	int curr_column;
 
 	u8 id_data[8];
diff --git a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
index 9ca6882..12a6227 100644
--- a/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
+++ b/drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c
@@ -20,6 +20,8 @@
  * shown 164 retries as maxiumum. */
 #define NFLASH_READY_RETRIES		1000
 
+#define NFLASH_SECTOR_SIZE		512
+
 /**************************************************
  * Various helpers
  **************************************************/
@@ -47,6 +49,80 @@ static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
 	return 0;
 }
 
+static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
+{
+	int i;
+
+	for (i = 0; i < NFLASH_READY_RETRIES; i++) {
+		if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & 0x04000000) {
+			if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
+			    BCMA_CC_NFLASH_CTL_ERR) {
+				pr_err("Error on polling\n");
+				return -EBUSY;
+			} else {
+				return 0;
+			}
+		}
+	}
+
+	pr_err("Polling timeout!\n");
+	return -EBUSY;
+}
+
+/**************************************************
+ * R/W
+ **************************************************/
+
+static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
+					   int len)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	u32 ctlcode;
+	u32 *dest = (u32 *)buf;
+	int i;
+	int toread;
+
+	BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
+	/* Don't validate column using nand_chip->page_shift, it may be bigger
+	 * when accessing OOB */
+
+	while (len) {
+		/* We can read maximum of 0x200 bytes at once */
+		toread = min(len, 0x200);
+
+		/* Set page and column */
+		bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
+				b47n->curr_column);
+		bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
+				b47n->curr_page_addr);
+
+		/* Prepare to read */
+		ctlcode = 0x40000000 | 0x00080000 | 0x00040000 | 0x00020000 |
+			  0x00010000;
+		ctlcode |= NAND_CMD_READSTART << 8;
+		if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
+			return;
+		if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
+			return;
+
+		/* Eventually read some data :) */
+		for (i = 0; i < toread; i += 4, dest++) {
+			ctlcode = 0x40000000 | 0x30000000 | 0x00100000;
+			if (i == toread - 4) /* Last read goes without that */
+				ctlcode &= ~0x40000000;
+			if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
+							      ctlcode))
+				return;
+			*dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
+		}
+
+		b47n->curr_column += toread;
+		len -= toread;
+	}
+}
+
 /**************************************************
  * NAND chip ops
  **************************************************/
@@ -76,6 +152,8 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 
 	if (column != -1)
 		b47n->curr_column = column;
+	if (page_addr != -1)
+		b47n->curr_page_addr = page_addr;
 
 	switch (command) {
 	case NAND_CMD_RESET:
@@ -107,6 +185,12 @@ static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 		}
 
 		break;
+	case NAND_CMD_READ0:
+		break;
+	case NAND_CMD_READOOB:
+		if (page_addr != -1)
+			b47n->curr_column += mtd->writesize;
+		break;
 	default:
 		pr_err("Command 0x%X unsupported\n", command);
 		break;
@@ -118,6 +202,7 @@ static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 {
 	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+	u32 tmp = 0;
 
 	switch (b47n->curr_command) {
 	case NAND_CMD_READID:
@@ -127,12 +212,31 @@ static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 			return 0;
 		}
 		return b47n->id_data[b47n->curr_column++];
+	case NAND_CMD_READOOB:
+		bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
+		return tmp & 0xFF;
 	}
 
 	pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 	return 0;
 }
 
+static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
+					       uint8_t *buf, int len)
+{
+	struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
+	struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
+
+	switch (b47n->curr_command) {
+	case NAND_CMD_READ0:
+	case NAND_CMD_READOOB:
+		bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
+		return;
+	}
+
+	pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
+}
+
 /**************************************************
  * Init
  **************************************************/
@@ -152,6 +256,8 @@ int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 	b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 	b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 	b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
+	b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
+	b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 	b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 
 	/* Enable NAND flash access */
-- 
1.7.7



From zajec5 at gmail.com  Thu Sep 27 07:55:47 2012
From: zajec5 at gmail.com (=?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?=)
Date: Thu, 27 Sep 2012 13:55:47 +0200
Subject: [PATCH 6/6] bcm47xxnflash: enable BCM4706 driver
In-Reply-To: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
References: <1348746947-2349-1-git-send-email-zajec5@gmail.com>
Message-ID: <1348746947-2349-6-git-send-email-zajec5@gmail.com>

Signed-off-by: Rafa? Mi?ecki <zajec5 at gmail.com>
---
0006-bcm47xxnflash-enable-BCM4706-driver.patch 
Successfully built configuration "mips-bcm47xx_defconfig,mips,mips-linux-", no issues
---
 drivers/mtd/nand/bcm47xxnflash/Makefile        |    2 +-
 drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h |    2 ++
 drivers/mtd/nand/bcm47xxnflash/main.c          |    4 ++--
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/bcm47xxnflash/Makefile b/drivers/mtd/nand/bcm47xxnflash/Makefile
index 4f688f9..f05b119 100644
--- a/drivers/mtd/nand/bcm47xxnflash/Makefile
+++ b/drivers/mtd/nand/bcm47xxnflash/Makefile
@@ -1,4 +1,4 @@
 bcm47xxnflash-y				+= main.o
-bcm47xxnflash-				+= ops_bcm4706.o
+bcm47xxnflash-y				+= ops_bcm4706.o
 
 obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH)	+= bcm47xxnflash.o
diff --git a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
index 264aec4..0bdb2ce 100644
--- a/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
+++ b/drivers/mtd/nand/bcm47xxnflash/bcm47xxnflash.h
@@ -17,4 +17,6 @@ struct bcm47xxnflash {
 	u8 id_data[8];
 };
 
+int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n);
+
 #endif /* BCM47XXNFLASH */
diff --git a/drivers/mtd/nand/bcm47xxnflash/main.c b/drivers/mtd/nand/bcm47xxnflash/main.c
index fc9139d..2b8b05b 100644
--- a/drivers/mtd/nand/bcm47xxnflash/main.c
+++ b/drivers/mtd/nand/bcm47xxnflash/main.c
@@ -40,8 +40,8 @@ static int bcm47xxnflash_probe(struct platform_device *pdev)
 	b47n->mtd.priv = &b47n->nand_chip; /* Required */
 	b47n->cc = container_of(nflash, struct bcma_drv_cc, nflash);
 
-	if (0) {
-		/* TODO: init device */
+	if (b47n->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
+		err = bcm47xxnflash_ops_bcm4706_init(b47n);
 	} else {
 		pr_err("Device not supported\n");
 		err = -ENOTSUPP;
-- 
1.7.7



From dedekind1 at gmail.com  Thu Sep 27 08:23:13 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 27 Sep 2012 15:23:13 +0300
Subject: [PATCH 0/9] mtd: nand: improve NAND ID detection
In-Reply-To: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
References: <1348544455-17656-1-git-send-email-computersforpeace@gmail.com>
Message-ID: <1348748593.21300.0.camel@sauron.fi.intel.com>

On Mon, 2012-09-24 at 20:40 -0700, Brian Norris wrote:
> Hi all,
> 
> I've been working on some changes to nand_base.c's nand_get_flash_type()
> routine for improving its structure and readability as well as to detect some
> new chips. Generally, this patch series does the following:

Pushed the series to l2-mtd.git, thanks!

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120927/861e38d4/attachment.sig>

From galak at kernel.crashing.org  Thu Sep 27 08:33:17 2012
From: galak at kernel.crashing.org (Kumar Gala)
Date: Thu, 27 Sep 2012 07:33:17 -0500
Subject: [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any
 write
In-Reply-To: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
References: <1347526489-20186-1-git-send-email-prabhakar@freescale.com>
Message-ID: <35D2D92E-D6B7-46CB-A3F2-6DAE2134EA30@kernel.crashing.org>


On Sep 13, 2012, at 3:54 AM, Prabhakar Kushwaha wrote:

> IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for
> SRAM i.e. "byte select" is not supported. Hence Read Modify Write is
> implemented in IFC for any "system side write" into sram buffer. Reading an
> uninitialized memory results in ECC Error from sram wrapper.
> 
> Hence we must initialize/prefill SRAM buffer by any data before writing
> anything in SRAM from system side. To initialize SRAM user can use "READID"
> NAND command with read bytes equal to SRAM size. It will be a one time
> activity post boot.
> 
> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
> ---
> Based upon git://git.infradead.org/linux-mtd.git branch master
> The compilation of this patch depends upon following patch.
> http://patchwork.ozlabs.org/patch/177893/
> This patch is currently applied on git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git 
> branch next and status is "Awaiting Upstream"
> 
> 
> drivers/mtd/nand/fsl_ifc_nand.c |   56 ++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 55 insertions(+), 1 deletion(-)

applied to next

- k

From g.liakhovetski at gmx.de  Thu Sep 27 11:05:49 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 27 Sep 2012 17:05:49 +0200 (CEST)
Subject: [PATCH v2 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
Message-ID: <Pine.LNX.4.64.1209271656020.7862@axis700.grange>

Hi Bastian

On Mon, 24 Sep 2012, Bastian Hecht wrote:

> The code probes if DMA channels can get allocated and tears them down at
> removal/failure if needed.

I'm not sure it makes sense to break this code into two patches - the 
first one makes no sense without the second one.

> 
> Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
> 
> Signed-off-by: Bastian Hecht <hechtb at gmail.com>
> ---
> v2: incorporated Vikram Narayanan's thoughts
> 	- added a missing "static".
> 	- reordered things to get rid of a forward declaration
> 
> Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.
> 
>  drivers/mtd/nand/sh_flctl.c  |   74 ++++++++++++++++++++++++++++++++++++++++++
>  include/linux/mtd/sh_flctl.h |   10 ++++++
>  2 files changed, 84 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
> index 4fbfe96..9659483 100644
> --- a/drivers/mtd/nand/sh_flctl.c
> +++ b/drivers/mtd/nand/sh_flctl.c
> @@ -106,6 +106,76 @@ static void wait_completion(struct sh_flctl *flctl)
>  	writeb(0x0, FLTRCR(flctl));
>  }
>  
> +static void flctl_release_dma(struct sh_flctl *flctl)
> +{
> +	if (flctl->chan_fifo0_rx) {
> +		dma_release_channel(flctl->chan_fifo0_rx);

You add dmaengine API calls to the file, so, you have to include 
header(s). dma_release_channel() requires dmaengine.h.

> +		flctl->chan_fifo0_rx = NULL;
> +	}
> +	if (flctl->chan_fifo0_tx) {
> +		dma_release_channel(flctl->chan_fifo0_tx);
> +		flctl->chan_fifo0_tx = NULL;
> +	}
> +}
> +
> +static void flctl_setup_dma(struct sh_flctl *flctl)
> +{
> +	dma_cap_mask_t mask;
> +	struct dma_slave_config cfg;
> +	struct platform_device *pdev = flctl->pdev;
> +	struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
> +	int ret;
> +
> +	if (!pdata)
> +		return;
> +
> +	if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
> +		return;
> +
> +	/* We can only either use DMA for both Tx and Rx or not use it at all */
> +	dma_cap_zero(mask);
> +	dma_cap_set(DMA_SLAVE, mask);
> +
> +	flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,

shdma_chan_filter() requires sh_dma.h. And no, including these headers in 
your header is not quite correct.

> +					    (void *)pdata->slave_id_fifo0_tx);
> +	dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
> +		flctl->chan_fifo0_tx);
> +
> +	if (!flctl->chan_fifo0_tx)
> +		return;
> +
> +	cfg.slave_id = pdata->slave_id_fifo0_tx;
> +	cfg.direction = DMA_MEM_TO_DEV;
> +	cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
> +	cfg.src_addr = 0;
> +	ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);

Ok, you copied my mistake here:-) "cfg" is allocated on stack and never 
initialised. You set those its members, that are needed by the sh-dma 
driver, but it can change at any time to begin using further fields from 
struct dma_slave_config, so, it has to be zeroed first. E.g., you could do

+	struct dma_slave_config cfg = {.device_fc = false,};

> +	if (ret < 0)
> +		goto err;
> +
> +	flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
> +					    (void *)pdata->slave_id_fifo0_rx);
> +	dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
> +		flctl->chan_fifo0_rx);
> +
> +	if (!flctl->chan_fifo0_rx)
> +		goto err;
> +
> +	cfg.slave_id = pdata->slave_id_fifo0_rx;
> +	cfg.direction = DMA_DEV_TO_MEM;
> +	cfg.dst_addr = 0;
> +	cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
> +	ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
> +	if (ret < 0)
> +		goto err;
> +
> +	init_completion(&flctl->dma_complete);
> +
> +	return;
> +
> +err:
> +	flctl_release_dma(flctl);
> +}
> +
>  static void set_addr(struct mtd_info *mtd, int column, int page_addr)
>  {
>  	struct sh_flctl *flctl = mtd_to_flctl(mtd);
> @@ -930,6 +1000,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
>  	pm_runtime_enable(&pdev->dev);
>  	pm_runtime_resume(&pdev->dev);
>  
> +	flctl_setup_dma(flctl);
> +
>  	ret = nand_scan_ident(flctl_mtd, 1, NULL);
>  	if (ret)
>  		goto err_chip;
> @@ -947,6 +1019,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
>  	return 0;
>  
>  err_chip:
> +	flctl_release_dma(flctl);
>  	pm_runtime_disable(&pdev->dev);
>  	free_irq(irq, flctl);
>  err_flste:
> @@ -960,6 +1033,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
>  {
>  	struct sh_flctl *flctl = platform_get_drvdata(pdev);
>  
> +	flctl_release_dma(flctl);
>  	nand_release(&flctl->mtd);
>  	pm_runtime_disable(&pdev->dev);
>  	free_irq(platform_get_irq(pdev, 0), flctl);
> diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
> index 01e4b15..20d3f48 100644
> --- a/include/linux/mtd/sh_flctl.h
> +++ b/include/linux/mtd/sh_flctl.h
> @@ -20,10 +20,12 @@
>  #ifndef __SH_FLCTL_H__
>  #define __SH_FLCTL_H__
>  
> +#include <linux/dmaengine.h>
>  #include <linux/mtd/mtd.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
>  #include <linux/pm_qos.h>
> +#include <linux/sh_dma.h>

Here headers aren't actually needed - you can just forward-declare "struct 
dma_chan." OTOH, what _is_ indeed needed is <linux/completion.h>.

>  
>  /* FLCTL registers */
>  #define FLCMNCR(f)		(f->reg + 0x0)
> @@ -161,6 +163,11 @@ struct sh_flctl {
>  	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
>  	unsigned holden:1;	/* Hardware has FLHOLDCR and HOLDEN is set */
>  	unsigned qos_request:1;	/* QoS request to prevent deep power shutdown */
> +
> +	/* DMA related objects */
> +	struct dma_chan		*chan_fifo0_rx;
> +	struct dma_chan		*chan_fifo0_tx;
> +	struct completion	dma_complete;
>  };
>  
>  struct sh_flctl_platform_data {
> @@ -170,6 +177,9 @@ struct sh_flctl_platform_data {
>  
>  	unsigned has_hwecc:1;
>  	unsigned use_holden:1;
> +
> +	unsigned int            slave_id_fifo0_tx;
> +	unsigned int            slave_id_fifo0_rx;
>  };
>  
>  static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
> -- 
> 1.7.5.4
> 

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From g.liakhovetski at gmx.de  Thu Sep 27 11:28:54 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 27 Sep 2012 17:28:54 +0200 (CEST)
Subject: [PATCH v2 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO
 when available
In-Reply-To: <1348478315-10789-2-git-send-email-hechtb@gmail.com>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
 <1348478315-10789-2-git-send-email-hechtb@gmail.com>
Message-ID: <Pine.LNX.4.64.1209271705570.7862@axis700.grange>

On Mon, 24 Sep 2012, Bastian Hecht wrote:

> Map and unmap DMA buffers, trigger the DMA and wait for the completion.
> On failure we fallback to PIO mode.
> 
> Signed-off-by: Bastian Hecht <hechtb at gmail.com>
> ---
> log v2: dropped a forward declaration
> 
>  drivers/mtd/nand/sh_flctl.c  |   97 +++++++++++++++++++++++++++++++++++++++++-
>  include/linux/mtd/sh_flctl.h |    1 +
>  2 files changed, 96 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
> index 9659483..0d90af8 100644
> --- a/drivers/mtd/nand/sh_flctl.c
> +++ b/drivers/mtd/nand/sh_flctl.c
> @@ -24,6 +24,8 @@
>  #include <linux/module.h>
>  #include <linux/kernel.h>
>  #include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>

As I suggested in my comments to patch 1/2, I would merge these patches. 
In any case the headers are needed already in the first patch, including 
sh_dma.h.

Thanks
Guennadi


>  #include <linux/interrupt.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
> @@ -106,6 +108,13 @@ static void wait_completion(struct sh_flctl *flctl)
>  	writeb(0x0, FLTRCR(flctl));
>  }
>  
> +static void flctl_dma_complete(void *param)
> +{
> +	struct sh_flctl *flctl = param;
> +
> +	complete(&flctl->dma_complete);
> +}
> +
>  static void flctl_release_dma(struct sh_flctl *flctl)
>  {
>  	if (flctl->chan_fifo0_rx) {
> @@ -331,6 +340,69 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
>  	timeout_error(flctl, __func__);
>  }
>  
> +static void flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
> +					int len, enum dma_data_direction dir)
> +{
> +	struct dma_async_tx_descriptor *desc = NULL;
> +	struct dma_chan *chan;
> +	enum dma_transfer_direction tr_dir;
> +	dma_addr_t dma_addr;
> +	dma_cookie_t cookie = -EINVAL;
> +	uint32_t reg;
> +	int ret;
> +
> +	if (dir == DMA_FROM_DEVICE) {
> +		chan = flctl->chan_fifo0_rx;
> +		tr_dir = DMA_DEV_TO_MEM;
> +	} else {
> +		chan = flctl->chan_fifo0_tx;
> +		tr_dir = DMA_MEM_TO_DEV;
> +	}
> +
> +	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
> +
> +	if (dma_addr)
> +		desc = dmaengine_prep_slave_single(chan, dma_addr, len,
> +			tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
> +
> +	if (desc) {
> +		reg = readl(FLINTDMACR(flctl));
> +		reg |= DREQ0EN;
> +		writel(reg, FLINTDMACR(flctl));
> +
> +		desc->callback = flctl_dma_complete;
> +		desc->callback_param = flctl;
> +		cookie = dmaengine_submit(desc);
> +
> +		dma_async_issue_pending(chan);
> +	}
> +
> +	if (!desc) {
> +		/* DMA failed, fall back to PIO */
> +		flctl_release_dma(flctl);
> +		dev_warn(&flctl->pdev->dev,
> +			 "DMA failed, falling back to PIO\n");
> +		goto out;
> +	}
> +
> +	ret =
> +	wait_for_completion_timeout(&flctl->dma_complete,
> +				msecs_to_jiffies(3000));
> +
> +	if (ret <= 0) {
> +		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
> +		dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
> +	}
> +
> +out:
> +	reg = readl(FLINTDMACR(flctl));
> +	reg &= ~DREQ0EN;
> +	writel(reg, FLINTDMACR(flctl));
> +
> +	dma_unmap_single(chan->device->dev, dma_addr, len, dir);
> +	init_completion(&flctl->dma_complete);
> +}
> +
>  static void read_datareg(struct sh_flctl *flctl, int offset)
>  {
>  	unsigned long data;
> @@ -349,6 +421,16 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
>  
>  	len_4align = (rlen + 3) / 4;
>  
> +	/* initiate DMA transfer */
> +	if (flctl->chan_fifo0_rx && rlen >= 32) {
> +		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM);
> +		for (i = 0; i < len_4align; i++)
> +			buf[i] = be32_to_cpu(buf[i]);
> +
> +		return;
> +	}
> +
> +	/* do polling transfer */
>  	for (i = 0; i < len_4align; i++) {
>  		wait_rfifo_ready(flctl);
>  		buf[i] = readl(FLDTFIFO(flctl));
> @@ -378,13 +460,24 @@ static enum flctl_ecc_res_t read_ecfiforeg
>  static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
>  {
>  	int i, len_4align;
> -	unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
> +	unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
>  	void *fifo_addr = (void *)FLDTFIFO(flctl);
>  
>  	len_4align = (rlen + 3) / 4;
> +
> +	/* initiate DMA transfer */
> +	if (flctl->chan_fifo0_tx && rlen >= 32) {
> +		for (i = 0; i < len_4align; i++)
> +			buf[i] = cpu_to_be32(buf[i]);
> +
> +		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV);
> +		return;
> +	}
> +
> +	/* do polling transfer */
>  	for (i = 0; i < len_4align; i++) {
>  		wait_wfifo_ready(flctl);
> -		writel(cpu_to_be32(data[i]), fifo_addr);
> +		writel(cpu_to_be32(buf[i]), fifo_addr);
>  	}
>  }
>  
> diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
> index 20d3f48..d55ec25 100644
> --- a/include/linux/mtd/sh_flctl.h
> +++ b/include/linux/mtd/sh_flctl.h
> @@ -109,6 +109,7 @@
>  #define ESTERINTE	(0x1 << 24)	/* ECC error interrupt enable */
>  #define AC1CLR		(0x1 << 19)	/* ECC FIFO clear */
>  #define AC0CLR		(0x1 << 18)	/* Data FIFO clear */
> +#define DREQ0EN		(0x1 << 16)	/* FLDTFIFODMA Request Enable */
>  #define ECERB		(0x1 << 9)	/* ECC error */
>  #define STERB		(0x1 << 8)	/* Status error */
>  #define STERINTE	(0x1 << 4)	/* Status error enable */
> -- 
> 1.7.5.4
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From dinguyen at altera.com  Thu Sep 27 12:58:04 2012
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 27 Sep 2012 10:58:04 -0600
Subject: nand/denali: split the driver into 3 parts: generic, PCI and DT
Message-ID: <1348765086-27286-1-git-send-email-dinguyen@altera.com>

Hello,

The following 2 patches attempts to make the current Denali NAND controller, 
which is PCI-based, to be both PCI and device tree drivers.

The first patch is a resend of Jami Iles patch with only minor changes on the
commit message and checkpatch errors and warnings. This patch was originally
sent in this message:

http://lists.infradead.org/pipermail/linux-mtd/2011-May/035334.html

The second patch is also based on Jamie Iles' patch to add a MMIO version of
the Denali NAND driver. I converted to be DT based.

I think there were comments to make it fully DT, but since I don't have a
PCI-base hardware to test this, I don't want to break it. I can only test the 
DT version on the HW that I have access to.

.../devicetree/bindings/mtd/denali-nand.txt        |   23 +++
 drivers/mtd/nand/Kconfig                           |   20 ++-
 drivers/mtd/nand/Makefile                          |    2 +
 drivers/mtd/nand/denali.c                          |  160 ++++---------------
 drivers/mtd/nand/denali.h                          |    5 +
 drivers/mtd/nand/denali_dt.c                       |  167 ++++++++++++++++++++
 drivers/mtd/nand/denali_pci.c                      |  144 +++++++++++++++++
 7 files changed, 386 insertions(+), 135 deletions(-)


Thanks,
Dinh



From dinguyen at altera.com  Thu Sep 27 12:58:06 2012
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 27 Sep 2012 10:58:06 -0600
Subject: =?UTF-8?q?=5BPATCH=20v2=202/2=5D=20nand/denali=3A=20add=20a=20DT=20driver?=
In-Reply-To: <1348765086-27286-1-git-send-email-dinguyen@altera.com>
References: <1348765086-27286-1-git-send-email-dinguyen@altera.com>
Message-ID: <1348765086-27286-3-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

Add a device tree version of the Denali NAND driver. Based
on an original patch from Jamie Iles to add a MMIO version
of this driver.

Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Chuanxiao Dong <chuanxiao.dong at intel.com>
Cc: Jamie Iles <jamie at jamieiles.com>
---
 .../devicetree/bindings/mtd/denali-nand.txt        |   23 +++
 drivers/mtd/nand/Kconfig                           |    9 +-
 drivers/mtd/nand/Makefile                          |    1 +
 drivers/mtd/nand/denali.h                          |    1 +
 drivers/mtd/nand/denali_dt.c                       |  167 ++++++++++++++++++++
 5 files changed, 200 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/mtd/denali-nand.txt
 create mode 100644 drivers/mtd/nand/denali_dt.c

diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
new file mode 100644
index 0000000..b04d03a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
@@ -0,0 +1,23 @@
+* Denali NAND controller
+
+Required properties:
+  - compatible : should be "denali,denali-nand-dt"
+  - reg : should contain registers location and length for data and reg.
+  - reg-names: Should contain the reg names "nand_data" and "denali_reg"
+  - interrupts : The interrupt number.
+  - dm-mask : DMA bit mask
+
+The device tree may optionally contain sub-nodes describing partitions of the
+address space. See partition.txt for more detail.
+
+Examples:
+
+nand: nand at ff900000 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "denali,denali-nand-dt";
+	reg = <0xff900000 0x100000>, <0xffb80000 0x10000>;
+	reg-names = "nand_data", "denali_reg";
+	interrupts = <0 144 4>;
+	dma-mask = <0xffffffff>;
+};
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index f5659c1..2f6ace3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -78,7 +78,14 @@ config MTD_NAND_DENALI_PCI
         help
           Enable the driver for NAND flash on Intel Moorestown, using the
           Denali NAND controller core.
- 
+
+config MTD_NAND_DENALI_DT
+	tristate "Support Denali NAND controller as a DT device"
+	depends on HAVE_CLK && MTD_NAND_DENALI
+	help
+	  Enable the driver for NAND flash on platforms using a Denali NAND
+	  controller as a DT device.
+
 config MTD_NAND_DENALI_SCRATCH_REG_ADDR
         hex "Denali NAND size scratch register address"
         default "0xFF108018"
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 0b3c9e2..50d6970 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-delta.o
 obj-$(CONFIG_MTD_NAND_AUTCPU12)		+= autcpu12.o
 obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
 obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
+obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o
 obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
 obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
 obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index e5aa995..cec5712 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -466,6 +466,7 @@ struct nand_buf {
 
 #define INTEL_CE4100	1
 #define INTEL_MRST	2
+#define DT		3
 
 struct denali_nand_info {
 	struct mtd_info mtd;
diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c
new file mode 100644
index 0000000..fbabbaa
--- /dev/null
+++ b/drivers/mtd/nand/denali_dt.c
@@ -0,0 +1,167 @@
+/*
+ * NAND Flash Controller Device Driver for DT
+ *
+ * Copyright ? 2011, Picochip.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+
+#include "denali.h"
+
+struct denali_dt {
+	struct denali_nand_info	denali;
+	struct clk		*clk;
+};
+
+static void __iomem *request_and_map(struct device *dev,
+				     const struct resource *res)
+{
+	void __iomem *ptr;
+
+	if (!devm_request_mem_region(dev, res->start, resource_size(res),
+				     "denali-dt")) {
+		dev_err(dev, "unable to request %s\n", res->name);
+		return NULL;
+	}
+
+	ptr = devm_ioremap_nocache(dev, res->start, resource_size(res));
+	if (!res)
+		dev_err(dev, "ioremap_nocache of %s failed!", res->name);
+
+	return ptr;
+}
+
+static const struct of_device_id denali_nand_dt_ids[] = {
+		{ .compatible = "denali,denali-nand-dt" },
+		{ /* sentinel */ }
+	};
+
+MODULE_DEVICE_TABLE(of, denali_nand_dt_ids);
+
+static u64 denali_dma_mask;
+
+static int __devinit denali_dt_probe(struct platform_device *ofdev)
+{
+	struct resource *denali_reg, *nand_data;
+	struct denali_dt *dt;
+	struct denali_nand_info *denali;
+	int ret;
+	const struct of_device_id *of_id;
+
+	of_id = of_match_device(denali_nand_dt_ids, &ofdev->dev);
+	if (of_id) {
+		ofdev->id_entry = of_id->data;
+	} else {
+		pr_err("Failed to find the right device id.\n");
+		return -ENOMEM;
+	}
+
+	dt = devm_kzalloc(&ofdev->dev, sizeof(*dt), GFP_KERNEL);
+	if (!dt)
+		return -ENOMEM;
+	denali = &dt->denali;
+
+	denali_reg = platform_get_resource_byname(ofdev, IORESOURCE_MEM, "denali_reg");
+	nand_data = platform_get_resource_byname(ofdev, IORESOURCE_MEM, "nand_data");
+	if (!denali_reg || !nand_data) {
+		dev_err(&ofdev->dev, "resources not completely defined\n");
+		return -EINVAL;
+	}
+
+	denali->platform = DT;
+	denali->dev = &ofdev->dev;
+	denali->irq = platform_get_irq(ofdev, 0);
+	if (denali->irq < 0) {
+		dev_err(&ofdev->dev, "no irq defined\n");
+		return -ENXIO;
+	}
+
+	denali->flash_reg = request_and_map(&ofdev->dev, denali_reg);
+	if (!denali->flash_reg)
+		return -ENOMEM;
+
+	denali->flash_mem = request_and_map(&ofdev->dev, nand_data);
+	if (!denali->flash_mem)
+		return -ENOMEM;
+
+	if (!of_property_read_u32(ofdev->dev.of_node,
+		"dma-mask", (u32 *)&denali_dma_mask)) {
+		denali->dev->dma_mask = &denali_dma_mask;
+	} else {
+		denali->dev->dma_mask = NULL;
+	}
+
+	dt->clk = clk_get(&ofdev->dev, NULL);
+	if (IS_ERR(dt->clk)) {
+		dev_err(&ofdev->dev, "no clk available\n");
+		return PTR_ERR(dt->clk);
+	}
+	clk_prepare_enable(dt->clk);
+
+	ret = denali_init(denali);
+	if (ret)
+		goto out_disable_clk;
+
+	platform_set_drvdata(ofdev, dt);
+	return 0;
+
+out_disable_clk:
+	clk_disable_unprepare(dt->clk);
+	clk_put(dt->clk);
+
+	return ret;
+}
+
+static int __devexit denali_dt_remove(struct platform_device *ofdev)
+{
+	struct denali_dt *dt = platform_get_drvdata(ofdev);
+
+	denali_remove(&dt->denali);
+	clk_disable(dt->clk);
+	clk_put(dt->clk);
+
+	return 0;
+}
+
+static struct platform_driver denali_dt_driver = {
+	.probe		= denali_dt_probe,
+	.remove		= __devexit_p(denali_dt_remove),
+	.driver		= {
+		.name	= "denali-nand-dt",
+		.owner	= THIS_MODULE,
+		.of_match_table	= of_match_ptr(denali_nand_dt_ids),
+	},
+};
+
+static int __init denali_init_dt(void)
+{
+	return platform_driver_register(&denali_dt_driver);
+}
+module_init(denali_init_dt);
+
+static void __exit denali_exit_dt(void)
+{
+	platform_driver_unregister(&denali_dt_driver);
+}
+module_exit(denali_exit_dt);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jamie Iles");
+MODULE_DESCRIPTION("DT driver for Denali NAND controller");
-- 
1.7.9.5




From dinguyen at altera.com  Thu Sep 27 12:58:05 2012
From: dinguyen at altera.com (dinguyen at altera.com)
Date: Thu, 27 Sep 2012 10:58:05 -0600
Subject: =?UTF-8?q?=5BPATCH=20v2=201/2=5D=20nand/denali=3A=20split=20the=20generic=20driver=20and=20PCI=20layer?=
In-Reply-To: <1348765086-27286-1-git-send-email-dinguyen@altera.com>
References: <1348765086-27286-1-git-send-email-dinguyen@altera.com>
Message-ID: <1348765086-27286-2-git-send-email-dinguyen@altera.com>

From: Dinh Nguyen <dinguyen at altera.com>

The Denali controller can also be found in SoC devices attached to a
simple bus.  Move the PCI specific parts into denali_pci so that we can
add a denali_dt that uses the same driver but for a device tree driver
instead of a PCI based device.

Cc: David Woodhouse <dwmw2 at infradead.org>
Cc: Chuanxiao Dong <chuanxiao.dong at intel.com>
Signed-off-by: Jamie Iles <jamie at jamieiles.com>
---
 drivers/mtd/nand/Kconfig      |   11 ++-
 drivers/mtd/nand/Makefile     |    1 +
 drivers/mtd/nand/denali.c     |  160 ++++++++---------------------------------
 drivers/mtd/nand/denali.h     |    4 ++
 drivers/mtd/nand/denali_pci.c |  144 +++++++++++++++++++++++++++++++++++++
 5 files changed, 186 insertions(+), 134 deletions(-)
 create mode 100644 drivers/mtd/nand/denali_pci.c

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 8ca4176..f5659c1 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -66,8 +66,15 @@ config MTD_NAND_AUTCPU12
 	  access the SmartMediaCard.
 
 config MTD_NAND_DENALI
-       depends on PCI
+        tristate "Support Denali NAND controller"
+        help
+	  Enable support for the Denali NAND controller.  This should be
+	  combined with either the PCI or platform drivers to provide device
+	  registration.
+
+config MTD_NAND_DENALI_PCI
         tristate "Support Denali NAND controller on Intel Moorestown"
+	depends on PCI && MTD_NAND_DENALI
         help
           Enable the driver for NAND flash on Intel Moorestown, using the
           Denali NAND controller core.
@@ -75,7 +82,7 @@ config MTD_NAND_DENALI
 config MTD_NAND_DENALI_SCRATCH_REG_ADDR
         hex "Denali NAND size scratch register address"
         default "0xFF108018"
-        depends on MTD_NAND_DENALI
+        depends on MTD_NAND_DENALI_PCI
         help
           Some platforms place the NAND chip size in a scratch register
           because (some versions of) the driver aren't able to automatically
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d4b4d87..0b3c9e2 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_MTD_NAND_SPIA)		+= spia.o
 obj-$(CONFIG_MTD_NAND_AMS_DELTA)	+= ams-delta.o
 obj-$(CONFIG_MTD_NAND_AUTCPU12)		+= autcpu12.o
 obj-$(CONFIG_MTD_NAND_DENALI)		+= denali.o
+obj-$(CONFIG_MTD_NAND_DENALI_PCI)	+= denali_pci.o
 obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o
 obj-$(CONFIG_MTD_NAND_BF5XX)		+= bf5xx_nand.o
 obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB)	+= ppchameleonevb.o
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 0650aaf..870c542 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -16,14 +16,12 @@
  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  *
  */
-
 #include <linux/interrupt.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
 #include <linux/wait.h>
 #include <linux/mutex.h>
 #include <linux/slab.h>
-#include <linux/pci.h>
 #include <linux/mtd/mtd.h>
 #include <linux/module.h>
 
@@ -89,13 +87,6 @@ MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
  * format the bank into the proper bits for the controller */
 #define BANK(x) ((x) << 24)
 
-/* List of platforms this NAND controller has be integrated into */
-static const struct pci_device_id denali_pci_ids[] = {
-	{ PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
-	{ PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
-	{ /* end: all zeroes */ }
-};
-
 /* forward declarations */
 static void clear_interrupts(struct denali_nand_info *denali);
 static uint32_t wait_for_irq(struct denali_nand_info *denali,
@@ -699,7 +690,7 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
 
 	if (comp_res == 0) {
 		/* timeout */
-		printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
+		pr_err("timeout occurred, status = 0x%x, mask = 0x%x\n",
 				intr_status, irq_mask);
 
 		intr_status = 0;
@@ -1303,8 +1294,7 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
 		/* TODO: Read OOB data */
 		break;
 	default:
-		printk(KERN_ERR ": unsupported command"
-				" received 0x%x\n", cmd);
+		pr_err(": unsupported command received 0x%x\n", cmd);
 		break;
 	}
 }
@@ -1423,107 +1413,48 @@ void denali_drv_init(struct denali_nand_info *denali)
 	denali->irq_status = 0;
 }
 
-/* driver entry point */
-static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+int denali_init(struct denali_nand_info *denali)
 {
-	int ret = -ENODEV;
-	resource_size_t csr_base, mem_base;
-	unsigned long csr_len, mem_len;
-	struct denali_nand_info *denali;
-
-	denali = kzalloc(sizeof(*denali), GFP_KERNEL);
-	if (!denali)
-		return -ENOMEM;
+	int ret;
 
-	ret = pci_enable_device(dev);
-	if (ret) {
-		printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
-		goto failed_alloc_memery;
-	}
-
-	if (id->driver_data == INTEL_CE4100) {
+	if (denali->platform == INTEL_CE4100) {
 		/* Due to a silicon limitation, we can only support
 		 * ONFI timing mode 1 and below.
 		 */
 		if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
-			printk(KERN_ERR "Intel CE4100 only supports"
-					" ONFI timing mode 1 or below\n");
-			ret = -EINVAL;
-			goto failed_enable_dev;
-		}
-		denali->platform = INTEL_CE4100;
-		mem_base = pci_resource_start(dev, 0);
-		mem_len = pci_resource_len(dev, 1);
-		csr_base = pci_resource_start(dev, 1);
-		csr_len = pci_resource_len(dev, 1);
-	} else {
-		denali->platform = INTEL_MRST;
-		csr_base = pci_resource_start(dev, 0);
-		csr_len = pci_resource_len(dev, 0);
-		mem_base = pci_resource_start(dev, 1);
-		mem_len = pci_resource_len(dev, 1);
-		if (!mem_len) {
-			mem_base = csr_base + csr_len;
-			mem_len = csr_len;
+			pr_err("Intel CE4100 only supports ONFI timing mode 1 or below\n");
+			return -EINVAL;
 		}
 	}
 
 	/* Is 32-bit DMA supported? */
-	ret = dma_set_mask(&dev->dev, DMA_BIT_MASK(32));
+	ret = dma_set_mask(denali->dev, DMA_BIT_MASK(32));
 	if (ret) {
-		printk(KERN_ERR "Spectra: no usable DMA configuration\n");
-		goto failed_enable_dev;
+		pr_err("Spectra: no usable DMA configuration\n");
+		return ret;
 	}
-	denali->buf.dma_buf = dma_map_single(&dev->dev, denali->buf.buf,
+	denali->buf.dma_buf = dma_map_single(denali->dev, denali->buf.buf,
 					     DENALI_BUF_SIZE,
 					     DMA_BIDIRECTIONAL);
 
-	if (dma_mapping_error(&dev->dev, denali->buf.dma_buf)) {
-		dev_err(&dev->dev, "Spectra: failed to map DMA buffer\n");
-		goto failed_enable_dev;
-	}
-
-	pci_set_master(dev);
-	denali->dev = &dev->dev;
-	denali->mtd.dev.parent = &dev->dev;
-
-	ret = pci_request_regions(dev, DENALI_NAND_NAME);
-	if (ret) {
-		printk(KERN_ERR "Spectra: Unable to request memory regions\n");
-		goto failed_dma_map;
-	}
-
-	denali->flash_reg = ioremap_nocache(csr_base, csr_len);
-	if (!denali->flash_reg) {
-		printk(KERN_ERR "Spectra: Unable to remap memory region\n");
-		ret = -ENOMEM;
-		goto failed_req_regions;
-	}
-
-	denali->flash_mem = ioremap_nocache(mem_base, mem_len);
-	if (!denali->flash_mem) {
-		printk(KERN_ERR "Spectra: ioremap_nocache failed!");
-		ret = -ENOMEM;
-		goto failed_remap_reg;
+	if (dma_mapping_error(denali->dev, denali->buf.dma_buf)) {
+		dev_err(denali->dev, "Spectra: failed to map DMA buffer\n");
+		return -EIO;
 	}
-
+	denali->mtd.dev.parent = denali->dev;
 	denali_hw_init(denali);
 	denali_drv_init(denali);
 
 	/* denali_isr register is done after all the hardware
 	 * initilization is finished*/
-	if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
+	if (request_irq(denali->irq, denali_isr, IRQF_SHARED,
 			DENALI_NAND_NAME, denali)) {
-		printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
-		ret = -ENODEV;
-		goto failed_remap_mem;
+		pr_err("Spectra: Unable to allocate IRQ\n");
+		return -ENODEV;
 	}
 
 	/* now that our ISR is registered, we can enable interrupts */
 	denali_set_intr_modes(denali, true);
-
-	pci_set_drvdata(dev, denali);
-
 	denali->mtd.name = "denali-nand";
 	denali->mtd.owner = THIS_MODULE;
 	denali->mtd.priv = &denali->nand;
@@ -1547,8 +1478,7 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	 */
 	if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
 		ret = -ENODEV;
-		printk(KERN_ERR "Spectra: device size not supported by this "
-			"version of MTD.");
+		pr_err("Spectra: device size not supported by this version of MTD.");
 		goto failed_req_irq;
 	}
 
@@ -1600,8 +1530,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	} else if (denali->mtd.oobsize < (denali->bbtskipbytes +
 			ECC_8BITS * (denali->mtd.writesize /
 			ECC_SECTOR_SIZE))) {
-		printk(KERN_ERR "Your NAND chip OOB is not large enough to"
-				" contain 8bit ECC correction codes");
+		pr_err("Your NAND chip OOB is not large enough to \
+				contain 8bit ECC correction codes");
 		goto failed_req_irq;
 	} else {
 		denali->nand.ecc.strength = 8;
@@ -1653,56 +1583,22 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 
 	ret = mtd_device_register(&denali->mtd, NULL, 0);
 	if (ret) {
-		dev_err(&dev->dev, "Spectra: Failed to register MTD: %d\n",
+		dev_err(denali->dev, "Spectra: Failed to register MTD: %d\n",
 				ret);
 		goto failed_req_irq;
 	}
 	return 0;
 
 failed_req_irq:
-	denali_irq_cleanup(dev->irq, denali);
-failed_remap_mem:
-	iounmap(denali->flash_mem);
-failed_remap_reg:
-	iounmap(denali->flash_reg);
-failed_req_regions:
-	pci_release_regions(dev);
-failed_dma_map:
-	dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
-			 DMA_BIDIRECTIONAL);
-failed_enable_dev:
-	pci_disable_device(dev);
-failed_alloc_memery:
-	kfree(denali);
+	denali_irq_cleanup(denali->irq, denali);
+
 	return ret;
 }
 
 /* driver exit point */
-static void denali_pci_remove(struct pci_dev *dev)
+void denali_remove(struct denali_nand_info *denali)
 {
-	struct denali_nand_info *denali = pci_get_drvdata(dev);
-
-	nand_release(&denali->mtd);
-
-	denali_irq_cleanup(dev->irq, denali);
-
-	iounmap(denali->flash_reg);
-	iounmap(denali->flash_mem);
-	pci_release_regions(dev);
-	pci_disable_device(dev);
-	dma_unmap_single(&dev->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
-			 DMA_BIDIRECTIONAL);
-	pci_set_drvdata(dev, NULL);
-	kfree(denali);
+	denali_irq_cleanup(denali->irq, denali);
+	dma_unmap_single(denali->dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
+			DMA_BIDIRECTIONAL);
 }
-
-MODULE_DEVICE_TABLE(pci, denali_pci_ids);
-
-static struct pci_driver denali_pci_driver = {
-	.name = DENALI_NAND_NAME,
-	.id_table = denali_pci_ids,
-	.probe = denali_pci_probe,
-	.remove = denali_pci_remove,
-};
-
-module_pci_driver(denali_pci_driver);
diff --git a/drivers/mtd/nand/denali.h b/drivers/mtd/nand/denali.h
index fabb9d5..e5aa995 100644
--- a/drivers/mtd/nand/denali.h
+++ b/drivers/mtd/nand/denali.h
@@ -487,6 +487,7 @@ struct denali_nand_info {
 	uint32_t irq_status;
 	int irq_debug_array[32];
 	int idx;
+	int irq;
 
 	uint32_t devnum;	/* represent how many nands connected */
 	uint32_t fwblks; /* represent how many blocks FW used */
@@ -496,4 +497,7 @@ struct denali_nand_info {
 	uint32_t max_banks;
 };
 
+extern int denali_init(struct denali_nand_info *denali);
+extern void denali_remove(struct denali_nand_info *denali);
+
 #endif /*_LLD_NAND_*/
diff --git a/drivers/mtd/nand/denali_pci.c b/drivers/mtd/nand/denali_pci.c
new file mode 100644
index 0000000..ea074e6
--- /dev/null
+++ b/drivers/mtd/nand/denali_pci.c
@@ -0,0 +1,144 @@
+/*
+ * NAND Flash Controller Device Driver
+ * Copyright ? 2009-2010, Intel Corporation and its suppliers.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+#include "denali.h"
+
+#define DENALI_NAND_NAME    "denali-nand-pci"
+
+/* List of platforms this NAND controller has be integrated into */
+static DEFINE_PCI_DEVICE_TABLE(denali_pci_ids) = {
+	{ PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
+	{ PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
+	{ /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, denali_pci_ids);
+
+static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+	int ret = -ENODEV;
+	resource_size_t csr_base, mem_base;
+	unsigned long csr_len, mem_len;
+	struct denali_nand_info *denali;
+
+	denali = kzalloc(sizeof(*denali), GFP_KERNEL);
+	if (!denali)
+		return -ENOMEM;
+
+	ret = pci_enable_device(dev);
+	if (ret) {
+		pr_err("Spectra: pci_enable_device failed.\n");
+		goto failed_alloc_memery;
+	}
+
+	if (id->driver_data == INTEL_CE4100) {
+		denali->platform = INTEL_CE4100;
+		mem_base = pci_resource_start(dev, 0);
+		mem_len = pci_resource_len(dev, 1);
+		csr_base = pci_resource_start(dev, 1);
+		csr_len = pci_resource_len(dev, 1);
+	} else {
+		denali->platform = INTEL_MRST;
+		csr_base = pci_resource_start(dev, 0);
+		csr_len = pci_resource_len(dev, 0);
+		mem_base = pci_resource_start(dev, 1);
+		mem_len = pci_resource_len(dev, 1);
+		if (!mem_len) {
+			mem_base = csr_base + csr_len;
+			mem_len = csr_len;
+		}
+	}
+
+	pci_set_master(dev);
+	denali->dev = &dev->dev;
+	denali->irq = dev->irq;
+
+	ret = pci_request_regions(dev, DENALI_NAND_NAME);
+	if (ret) {
+		pr_err("Spectra: Unable to request memory regions\n");
+		goto failed_enable_dev;
+	}
+
+	denali->flash_reg = ioremap_nocache(csr_base, csr_len);
+	if (!denali->flash_reg) {
+		pr_err("Spectra: Unable to remap memory region\n");
+		ret = -ENOMEM;
+		goto failed_req_regions;
+	}
+
+	denali->flash_mem = ioremap_nocache(mem_base, mem_len);
+	if (!denali->flash_mem) {
+		pr_err("Spectra: ioremap_nocache failed!");
+		ret = -ENOMEM;
+		goto failed_remap_reg;
+	}
+
+	ret = denali_init(denali);
+	if (ret)
+		goto failed_remap_mem;
+
+	pci_set_drvdata(dev, denali);
+
+	return 0;
+
+failed_remap_mem:
+	iounmap(denali->flash_mem);
+failed_remap_reg:
+	iounmap(denali->flash_reg);
+failed_req_regions:
+	pci_release_regions(dev);
+failed_enable_dev:
+	pci_disable_device(dev);
+failed_alloc_memery:
+	kfree(denali);
+
+	return ret;
+}
+
+/* driver exit point */
+static void denali_pci_remove(struct pci_dev *dev)
+{
+	struct denali_nand_info *denali = pci_get_drvdata(dev);
+
+	denali_remove(denali);
+	iounmap(denali->flash_reg);
+	iounmap(denali->flash_mem);
+	pci_release_regions(dev);
+	pci_disable_device(dev);
+	pci_set_drvdata(dev, NULL);
+	kfree(denali);
+}
+
+static struct pci_driver denali_pci_driver = {
+	.name = DENALI_NAND_NAME,
+	.id_table = denali_pci_ids,
+	.probe = denali_pci_probe,
+	.remove = denali_pci_remove,
+};
+
+static int __devinit denali_init_pci(void)
+{
+	pr_info("Spectra MTD driver built on %s @ %s\n", __DATE__, __TIME__);
+	return pci_register_driver(&denali_pci_driver);
+}
+module_init(denali_init_pci);
+
+static void __devexit denali_exit_pci(void)
+{
+	pci_unregister_driver(&denali_pci_driver);
+}
+module_exit(denali_exit_pci);
-- 
1.7.9.5




From richard.weinberger at gmail.com  Thu Sep 27 18:18:26 2012
From: richard.weinberger at gmail.com (richard -rw- weinberger)
Date: Fri, 28 Sep 2012 00:18:26 +0200
Subject: UBI: Fastmap request for inclusion (v19)
In-Reply-To: <1348674710-102885-1-git-send-email-richard@nod.at>
References: <1348674710-102885-1-git-send-email-richard@nod.at>
Message-ID: <CAFLxGvw+As5-d-kVOFztZG-n9gLEn9_Aouvmk+VUtsnmmbA3UA@mail.gmail.com>

On Wed, Sep 26, 2012 at 5:51 PM, Richard Weinberger <richard at nod.at> wrote:
>  MAINTAINERS                 |    6 +
>  drivers/mtd/ubi/Kconfig     |   20 ++
>  drivers/mtd/ubi/Makefile    |    1 +
>  drivers/mtd/ubi/attach.c    |  386 +++++++++++++++++++---------
>  drivers/mtd/ubi/build.c     |   70 +++++-
>  drivers/mtd/ubi/eba.c       |  126 +++++++++-
>  drivers/mtd/ubi/ubi-media.h |  137 ++++++++++
>  drivers/mtd/ubi/ubi.h       |  118 +++++++++-
>  drivers/mtd/ubi/wl.c        |  599 ++++++++++++++++++++++++++++++++++++++-----
>  9 files changed, 1252 insertions(+), 211 deletions(-)

For what ever reason the diff stat misses fastmap.c
Here the correct one:

 MAINTAINERS                 |    6 +
 drivers/mtd/ubi/Kconfig     |   20 +
 drivers/mtd/ubi/Makefile    |    1 +
 drivers/mtd/ubi/attach.c    |  386 +++++++----
 drivers/mtd/ubi/build.c     |   70 ++-
 drivers/mtd/ubi/eba.c       |  126 ++++-
 drivers/mtd/ubi/fastmap.c   | 1560 +++++++++++++++++++++++++++++++++++++++++++
 drivers/mtd/ubi/ubi-media.h |  137 ++++
 drivers/mtd/ubi/ubi.h       |  118 ++++-
 drivers/mtd/ubi/wl.c        |  599 +++++++++++++++--
 10 files changed, 2812 insertions(+), 211 deletions(-)

> [PATCH 01/10] UBI: Add fastmap on-flash data structures
> [PATCH 02/10] UBI: Add fastmap stuff to ubi.h
> [PATCH 03/10] UBI: Export next_sqnum()
> [PATCH 04/10] UBI: Add self_check_eba()
> [PATCH 05/10] UBI: Add fastmap bits to build.c
> [PATCH 06/10] UBI: Wire-up ->fm_sem
> [PATCH 07/10] UBI: Add fastmap stuff to attach.c
> [PATCH 08/10] UBI: Add fastmap support to the WL sub-system
> [PATCH 09/10] UBI: Add fastmap core
> [PATCH 10/10] UBI: Wire-up fastmap

-- 
Thanks,
//richard


From dedekind1 at gmail.com  Thu Sep 27 23:35:45 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 28 Sep 2012 06:35:45 +0300
Subject: [PATCH] mtd: omap2-nand: avoid unaligned DMA accesses, fall
 back on prefetch method
In-Reply-To: <1348155850-26174-1-git-send-email-arnout@mind.be>
References: <1348155850-26174-1-git-send-email-arnout@mind.be>
Message-ID: <1348803345.1830.2.camel@kyv>

On Thu, 2012-09-20 at 17:44 +0200, Arnout Vandecappelle (Essensium/Mind)
wrote:
> It's difficult to reproduce the error, because the buffers are
> aligned most of the time.

Can you just take one of the mtd tests (e.g., mtd_speedtest), amend it a
little and make sure it uses unaligned buffers?

> Perhaps a better method is to fetch the first few unaligned bytes
> with the prefetch method, and then continue with DMA.  However,
> since it's hard to force an unaligned buffer, it's also hard to
> test that this method works.

Yes, this would be a lot cleaner.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120928/41a78890/attachment.sig>

From levinsasha928 at gmail.com  Fri Sep 28 05:00:35 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Fri, 28 Sep 2012 11:00:35 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <50506A6C.30109@gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com>
Message-ID: <50656733.3040609@gmail.com>

On 09/12/2012 12:56 PM, Sasha Levin wrote:
> On 09/12/2012 12:50 PM, Sasha Levin wrote:
>> On 09/09/2012 04:56 PM, Suresh Siddha wrote:
>>> On Sat, 2012-09-08 at 12:57 -0700, Linus Torvalds wrote:
>>>>> Whatever. Something like this (TOTALLY UNTESTED) attached patch should
>>>>> get the mtdchar overflows to go away, 
>>> It looks good to me. Acked-by: Suresh Siddha <suresh.b.siddha at intel.com>
>>>
>>> Sasha, can you please give this a try?
>>
>> Sorry for the delay. It looks good here.
>>
>>
>> Thanks,
>> Sasha
>>
> 
> Uh... sorry again, I obviously tested the second patch sent by Linus but
> mistakingly replied to the wrong mail in the thread.

Is anyone planning on picking up Linus' patch? This is still not in -next even.


Thanks,
Sasha



From hechtb at googlemail.com  Fri Sep 28 05:45:46 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Fri, 28 Sep 2012 11:45:46 +0200
Subject: [PATCH v2 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <Pine.LNX.4.64.1209271656020.7862@axis700.grange>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
 <Pine.LNX.4.64.1209271656020.7862@axis700.grange>
Message-ID: <CABYn4sw6uXtA7V-goLGv3H7AZ1zbWLAHZqGd+5w9eB_e8yua9w@mail.gmail.com>

Thanks for the reviews, Guennadi! Thanks too to Vikram - I've forgot
to add you as recipient for the v2, so I pull you in here now.

2012/9/27 Guennadi Liakhovetski <g.liakhovetski at gmx.de>:
> Hi Bastian
>
> On Mon, 24 Sep 2012, Bastian Hecht wrote:
>
>> The code probes if DMA channels can get allocated and tears them down at
>> removal/failure if needed.
>
> I'm not sure it makes sense to break this code into two patches - the
> first one makes no sense without the second one.

Ok, will merge them.

>>
>> Based on Guennadi Liakhovetski's code from the sh_mmcif driver.
>>
>> Signed-off-by: Bastian Hecht <hechtb at gmail.com>
>> ---
>> v2: incorporated Vikram Narayanan's thoughts
>>       - added a missing "static".
>>       - reordered things to get rid of a forward declaration
>>
>> Based on l2-mtd with reverted commit e26c113b4130aefa1d8446602bb5b05cfd646bfe.
>>
>>  drivers/mtd/nand/sh_flctl.c  |   74 ++++++++++++++++++++++++++++++++++++++++++
>>  include/linux/mtd/sh_flctl.h |   10 ++++++
>>  2 files changed, 84 insertions(+), 0 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
>> index 4fbfe96..9659483 100644
>> --- a/drivers/mtd/nand/sh_flctl.c
>> +++ b/drivers/mtd/nand/sh_flctl.c
>> @@ -106,6 +106,76 @@ static void wait_completion(struct sh_flctl *flctl)
>>       writeb(0x0, FLTRCR(flctl));
>>  }
>>
>> +static void flctl_release_dma(struct sh_flctl *flctl)
>> +{
>> +     if (flctl->chan_fifo0_rx) {
>> +             dma_release_channel(flctl->chan_fifo0_rx);
>
> You add dmaengine API calls to the file, so, you have to include
> header(s). dma_release_channel() requires dmaengine.h.

Ok.

>> +             flctl->chan_fifo0_rx = NULL;
>> +     }
>> +     if (flctl->chan_fifo0_tx) {
>> +             dma_release_channel(flctl->chan_fifo0_tx);
>> +             flctl->chan_fifo0_tx = NULL;
>> +     }
>> +}
>> +
>> +static void flctl_setup_dma(struct sh_flctl *flctl)
>> +{
>> +     dma_cap_mask_t mask;
>> +     struct dma_slave_config cfg;
>> +     struct platform_device *pdev = flctl->pdev;
>> +     struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
>> +     int ret;
>> +
>> +     if (!pdata)
>> +             return;
>> +
>> +     if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
>> +             return;
>> +
>> +     /* We can only either use DMA for both Tx and Rx or not use it at all */
>> +     dma_cap_zero(mask);
>> +     dma_cap_set(DMA_SLAVE, mask);
>> +
>> +     flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
>
> shdma_chan_filter() requires sh_dma.h. And no, including these headers in
> your header is not quite correct.

Ok.

>> +                                         (void *)pdata->slave_id_fifo0_tx);
>> +     dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
>> +             flctl->chan_fifo0_tx);
>> +
>> +     if (!flctl->chan_fifo0_tx)
>> +             return;
>> +
>> +     cfg.slave_id = pdata->slave_id_fifo0_tx;
>> +     cfg.direction = DMA_MEM_TO_DEV;
>> +     cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
>> +     cfg.src_addr = 0;
>> +     ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
>
> Ok, you copied my mistake here:-) "cfg" is allocated on stack and never
> initialised. You set those its members, that are needed by the sh-dma
> driver, but it can change at any time to begin using further fields from
> struct dma_slave_config, so, it has to be zeroed first. E.g., you could do
>
> +       struct dma_slave_config cfg = {.device_fc = false,};

I think I'll use memset. Taking a member like .device_fc may be a bit
misleading. We are not interested in it and leave it on the default
value. And we have no other field we could initialize that won't be
changed in the function.

>> +     if (ret < 0)
>> +             goto err;
>> +
>> +     flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
>> +                                         (void *)pdata->slave_id_fifo0_rx);
>> +     dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
>> +             flctl->chan_fifo0_rx);
>> +
>> +     if (!flctl->chan_fifo0_rx)
>> +             goto err;
>> +
>> +     cfg.slave_id = pdata->slave_id_fifo0_rx;
>> +     cfg.direction = DMA_DEV_TO_MEM;
>> +     cfg.dst_addr = 0;
>> +     cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
>> +     ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
>> +     if (ret < 0)
>> +             goto err;
>> +
>> +     init_completion(&flctl->dma_complete);
>> +
>> +     return;
>> +
>> +err:
>> +     flctl_release_dma(flctl);
>> +}
>> +
>>  static void set_addr(struct mtd_info *mtd, int column, int page_addr)
>>  {
>>       struct sh_flctl *flctl = mtd_to_flctl(mtd);
>> @@ -930,6 +1000,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
>>       pm_runtime_enable(&pdev->dev);
>>       pm_runtime_resume(&pdev->dev);
>>
>> +     flctl_setup_dma(flctl);
>> +
>>       ret = nand_scan_ident(flctl_mtd, 1, NULL);
>>       if (ret)
>>               goto err_chip;
>> @@ -947,6 +1019,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
>>       return 0;
>>
>>  err_chip:
>> +     flctl_release_dma(flctl);
>>       pm_runtime_disable(&pdev->dev);
>>       free_irq(irq, flctl);
>>  err_flste:
>> @@ -960,6 +1033,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
>>  {
>>       struct sh_flctl *flctl = platform_get_drvdata(pdev);
>>
>> +     flctl_release_dma(flctl);
>>       nand_release(&flctl->mtd);
>>       pm_runtime_disable(&pdev->dev);
>>       free_irq(platform_get_irq(pdev, 0), flctl);
>> diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
>> index 01e4b15..20d3f48 100644
>> --- a/include/linux/mtd/sh_flctl.h
>> +++ b/include/linux/mtd/sh_flctl.h
>> @@ -20,10 +20,12 @@
>>  #ifndef __SH_FLCTL_H__
>>  #define __SH_FLCTL_H__
>>
>> +#include <linux/dmaengine.h>
>>  #include <linux/mtd/mtd.h>
>>  #include <linux/mtd/nand.h>
>>  #include <linux/mtd/partitions.h>
>>  #include <linux/pm_qos.h>
>> +#include <linux/sh_dma.h>
>
> Here headers aren't actually needed - you can just forward-declare "struct
> dma_chan." OTOH, what _is_ indeed needed is <linux/completion.h>.

Oh yes, I'll add <linux/completion.h>.
About the forward declration: Do I really need it? We use a struct
pointer and I am unsure if the compiler just needs to know the name
and nothing more. I've tested it and included sh_flctl.h (without any
DMA headers) in some driver that has no idea about DMA.
gcc didn't complain. Adding a non-pointer member
+ struct sh_dma test;
lead to an error, so struct sh_dma is really unknown.

>>
>>  /* FLCTL registers */
>>  #define FLCMNCR(f)           (f->reg + 0x0)
>> @@ -161,6 +163,11 @@ struct sh_flctl {
>>       unsigned hwecc:1;       /* Hardware ECC (0 = disabled, 1 = enabled) */
>>       unsigned holden:1;      /* Hardware has FLHOLDCR and HOLDEN is set */
>>       unsigned qos_request:1; /* QoS request to prevent deep power shutdown */
>> +
>> +     /* DMA related objects */
>> +     struct dma_chan         *chan_fifo0_rx;
>> +     struct dma_chan         *chan_fifo0_tx;
>> +     struct completion       dma_complete;
>>  };
>>
>>  struct sh_flctl_platform_data {
>> @@ -170,6 +177,9 @@ struct sh_flctl_platform_data {
>>
>>       unsigned has_hwecc:1;
>>       unsigned use_holden:1;
>> +
>> +     unsigned int            slave_id_fifo0_tx;
>> +     unsigned int            slave_id_fifo0_rx;
>>  };
>>
>>  static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
>> --
>> 1.7.5.4
>>
>
> Thanks
> Guennadi
> ---
> Guennadi Liakhovetski, Ph.D.
> Freelance Open-Source Software Developer
> http://www.open-technology.de/
> --
> To unsubscribe from this list: send the line "unsubscribe linux-sh" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From g.liakhovetski at gmx.de  Fri Sep 28 05:54:37 2012
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Fri, 28 Sep 2012 11:54:37 +0200 (CEST)
Subject: [PATCH v2 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <CABYn4sw6uXtA7V-goLGv3H7AZ1zbWLAHZqGd+5w9eB_e8yua9w@mail.gmail.com>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
 <Pine.LNX.4.64.1209271656020.7862@axis700.grange>
 <CABYn4sw6uXtA7V-goLGv3H7AZ1zbWLAHZqGd+5w9eB_e8yua9w@mail.gmail.com>
Message-ID: <Pine.LNX.4.64.1209281152130.5428@axis700.grange>

On Fri, 28 Sep 2012, Bastian Hecht wrote:

[snip]

> >> diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
> >> index 01e4b15..20d3f48 100644
> >> --- a/include/linux/mtd/sh_flctl.h
> >> +++ b/include/linux/mtd/sh_flctl.h
> >> @@ -20,10 +20,12 @@
> >>  #ifndef __SH_FLCTL_H__
> >>  #define __SH_FLCTL_H__
> >>
> >> +#include <linux/dmaengine.h>
> >>  #include <linux/mtd/mtd.h>
> >>  #include <linux/mtd/nand.h>
> >>  #include <linux/mtd/partitions.h>
> >>  #include <linux/pm_qos.h>
> >> +#include <linux/sh_dma.h>
> >
> > Here headers aren't actually needed - you can just forward-declare "struct
> > dma_chan." OTOH, what _is_ indeed needed is <linux/completion.h>.
> 
> Oh yes, I'll add <linux/completion.h>.
> About the forward declration: Do I really need it? We use a struct
> pointer and I am unsure if the compiler just needs to know the name
> and nothing more. I've tested it and included sh_flctl.h (without any
> DMA headers) in some driver that has no idea about DMA.
> gcc didn't complain.

I'm not sure about this, I think, sometimes there might be cases, when gcc 
doesn't complain. Or (more likely) the header is pulled in via another 
one, or some other header has this forward-declaration. But in any case I 
wouldn't rely on either of those and declare what's needed explicitly.

> Adding a non-pointer member
> + struct sh_dma test;
> lead to an error, so struct sh_dma is really unknown.

Of course, the compiler has to know the size of the struct to allocate 
space for it:-)

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From m-karicheri2 at ti.com  Fri Sep 28 12:10:32 2012
From: m-karicheri2 at ti.com (Karicheri, Muralidharan)
Date: Fri, 28 Sep 2012 16:10:32 +0000
Subject: [REMINDER: PATCH 1/1] mtd:nand:clk: preparation for switch to
 common clock framework
In-Reply-To: <1347899860-24358-2-git-send-email-m-karicheri2@ti.com>
References: <1347899860-24358-1-git-send-email-m-karicheri2@ti.com>
 <1347899860-24358-2-git-send-email-m-karicheri2@ti.com>
Message-ID: <3E54258959B69E4282D79E01AB1F32B7041EF679@DFLE12.ent.ti.com>

>> -----Original Message-----
>> From: Karicheri, Muralidharan
>> Sent: Monday, September 17, 2012 12:38 PM
>> To: dwmw2 at infradead.org; artem.bityutskiy at linux.intel.com; hs at denx.de;
>> mikedunn at newsguy.com; linux-mtd at lists.infradead.org; linux-kernel at vger.kernel.org;
>> davinci-linux-open-source at linux.davincidsp.com; linux-arm-kernel at lists.infradead.org
>> Cc: Karicheri, Muralidharan
>> Subject: [PATCH 1/1] mtd:nand:clk: preparation for switch to common clock framework
>> 
>> As a first step towards migrating davinci platforms to use common clock
>> framework, replace all instances of clk_enable() with clk_prepare_enable()
>> and clk_disable() with clk_disable_unprepare(). Until the platform is
>> switched to use the CONFIG_HAVE_CLK_PREPARE Kconfig variable, this just
>> adds a might_sleep() call and would work without any issues.
>> 
>> This will make it easy later to switch to common clk based implementation
>> of clk driver from DaVinci specific driver.
>> 
>> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
>> Reviewed-by: Mike Turquette <mturquette at linaro.org>
>> 
>> diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
>> index f386b3c..df1ab7d 100644
>> --- a/drivers/mtd/nand/davinci_nand.c
>> +++ b/drivers/mtd/nand/davinci_nand.c
>> @@ -724,7 +724,7 @@ static int __init nand_davinci_probe(struct platform_device
>> *pdev)
>>  		goto err_clk;
>>  	}
>> 
>> -	ret = clk_enable(info->clk);
>> +	ret = clk_prepare_enable(info->clk);
>>  	if (ret < 0) {
>>  		dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
>>  			ret);
>> @@ -835,7 +835,7 @@ syndrome_done:
>> 
>>  err_scan:
>>  err_timing:
>> -	clk_disable(info->clk);
>> +	clk_disable_unprepare(info->clk);
>> 
>>  err_clk_enable:
>>  	clk_put(info->clk);
>> @@ -872,7 +872,7 @@ static int __exit nand_davinci_remove(struct platform_device
>> *pdev)
>> 
>>  	nand_release(&info->mtd);
>> 
>> -	clk_disable(info->clk);
>> +	clk_disable_unprepare(info->clk);
>>  	clk_put(info->clk);
>> 
>>  	kfree(info);
>> --
>> 1.7.9.5

Could you please review and apply this patch to mtd subsystem tree for linux-next?

Murali Karicheri
Software Design Engineer




From torvalds at linux-foundation.org  Fri Sep 28 12:44:51 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 28 Sep 2012 09:44:51 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <50656733.3040609@gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
Message-ID: <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>

On Fri, Sep 28, 2012 at 2:00 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
>
> Is anyone planning on picking up Linus' patch? This is still not in -next even.

I was really hoping it would go through the regular channels and come
back to me that way, since I can't really test it, and it's bigger
than the trivial obvious one-liners that I'm happy to commit.

Hmm.

           Linus


From dedekind1 at gmail.com  Fri Sep 28 14:05:47 2012
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Fri, 28 Sep 2012 21:05:47 +0300
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
Message-ID: <1348855547.1556.3.camel@kyv>

On Fri, 2012-09-28 at 09:44 -0700, Linus Torvalds wrote:
> On Fri, Sep 28, 2012 at 2:00 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
> >
> > Is anyone planning on picking up Linus' patch? This is still not in -next even.
> 
> I was really hoping it would go through the regular channels and come
> back to me that way, since I can't really test it, and it's bigger
> than the trivial obvious one-liners that I'm happy to commit.

Hi Linus,

I am not the maintainer, but please, go ahead an push your fix. I do not
have time to test it myself and it does not look like anyone else in the
small mtd community does.

-- 
Best Regards,
Artem Bityutskiy
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 836 bytes
Desc: This is a digitally signed message part
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120928/e703f819/attachment.sig>

From dwmw2 at infradead.org  Fri Sep 28 15:04:14 2012
From: dwmw2 at infradead.org (David Woodhouse)
Date: Fri, 28 Sep 2012 20:04:14 +0100
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
Message-ID: <1348859054.2036.122.camel@shinybook.infradead.org>

On Fri, 2012-09-28 at 09:44 -0700, Linus Torvalds wrote:
> On Fri, Sep 28, 2012 at 2:00 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
> >
> > Is anyone planning on picking up Linus' patch? This is still not in -next even.
> 
> I was really hoping it would go through the regular channels and come
> back to me that way, since I can't really test it, and it's bigger
> than the trivial obvious one-liners that I'm happy to commit.

I can't test it on real hardware here either, but I can pull it through
my tree.

-- 
dwmw2
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120928/bbf8e936/attachment.bin>

From torvalds at linux-foundation.org  Fri Sep 28 15:13:29 2012
From: torvalds at linux-foundation.org (Linus Torvalds)
Date: Fri, 28 Sep 2012 12:13:29 -0700
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1348855547.1556.3.camel@kyv>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348855547.1556.3.camel@kyv>
Message-ID: <CA+55aFwDWcQv9DBCQhMrcK-zx75qBN11iQhq5dxt+orosmeXbg@mail.gmail.com>

On Fri, Sep 28, 2012 at 11:05 AM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
>
> I am not the maintainer, but please, go ahead an push your fix. I do not
> have time to test it myself and it does not look like anyone else in the
> small mtd community does.

Grr. I told people that patch wasn't tested. I hadn't even *compiled*
it. It has a typo ("inlint" instead of "inline" - so close).

Sasha said he had tested it, but nobody even mentioned this thing. Now
I'm nervous. I had committed it in my tree and was just about to push
it out when I decided that I should at least compile it despite the
"tested-by".

Hmm? Now I really *really* want to know that it's been tested on
actual hardware too. Sasha, what patch did you actually test? Did you
just fix the "inlint" thing, or was there something else entirely?

          Linus

PS. Artem: your "Reply-to" is broken, and doesn't have your real name.
Please fix.


From richard.weinberger at gmail.com  Fri Sep 28 15:15:27 2012
From: richard.weinberger at gmail.com (richard -rw- weinberger)
Date: Fri, 28 Sep 2012 21:15:27 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1348859054.2036.122.camel@shinybook.infradead.org>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348859054.2036.122.camel@shinybook.infradead.org>
Message-ID: <CAFLxGvxy2V9=4U1YePUm17Z=BF=SzLsO9Catmh-DcOkbMfuSNg@mail.gmail.com>

On Fri, Sep 28, 2012 at 9:04 PM, David Woodhouse <dwmw2 at infradead.org> wrote:
> On Fri, 2012-09-28 at 09:44 -0700, Linus Torvalds wrote:
>> On Fri, Sep 28, 2012 at 2:00 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
>> >
>> > Is anyone planning on picking up Linus' patch? This is still not in -next even.
>>
>> I was really hoping it would go through the regular channels and come
>> back to me that way, since I can't really test it, and it's bigger
>> than the trivial obvious one-liners that I'm happy to commit.
>
> I can't test it on real hardware here either, but I can pull it through
> my tree.

If you can a easy test-case I can test it on real hardware.

-- 
Thanks,
//richard


From richard.weinberger at gmail.com  Fri Sep 28 15:18:24 2012
From: richard.weinberger at gmail.com (richard -rw- weinberger)
Date: Fri, 28 Sep 2012 21:18:24 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CAFLxGvxy2V9=4U1YePUm17Z=BF=SzLsO9Catmh-DcOkbMfuSNg@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348859054.2036.122.camel@shinybook.infradead.org>
 <CAFLxGvxy2V9=4U1YePUm17Z=BF=SzLsO9Catmh-DcOkbMfuSNg@mail.gmail.com>
Message-ID: <CAFLxGvz-4h1Qx0WL62PcyOiAQuXR-S-nb5gruDpQkZETwDf0-A@mail.gmail.com>

On Fri, Sep 28, 2012 at 9:15 PM, richard -rw- weinberger
<richard.weinberger at gmail.com> wrote:
> On Fri, Sep 28, 2012 at 9:04 PM, David Woodhouse <dwmw2 at infradead.org> wrote:
>> On Fri, 2012-09-28 at 09:44 -0700, Linus Torvalds wrote:
>>> On Fri, Sep 28, 2012 at 2:00 AM, Sasha Levin <levinsasha928 at gmail.com> wrote:
>>> >
>>> > Is anyone planning on picking up Linus' patch? This is still not in -next even.
>>>
>>> I was really hoping it would go through the regular channels and come
>>> back to me that way, since I can't really test it, and it's bigger
>>> than the trivial obvious one-liners that I'm happy to commit.
>>
>> I can't test it on real hardware here either, but I can pull it through
>> my tree.
>
> If you can a easy test-case I can test it on real hardware.

Bah.
If you have an easy test case I can run it on real hardware. :)


-- 
Thanks,
//richard


From levinsasha928 at gmail.com  Fri Sep 28 15:44:41 2012
From: levinsasha928 at gmail.com (Sasha Levin)
Date: Fri, 28 Sep 2012 21:44:41 +0200
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <CA+55aFwDWcQv9DBCQhMrcK-zx75qBN11iQhq5dxt+orosmeXbg@mail.gmail.com>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348855547.1556.3.camel@kyv>
 <CA+55aFwDWcQv9DBCQhMrcK-zx75qBN11iQhq5dxt+orosmeXbg@mail.gmail.com>
Message-ID: <5065FE29.5080302@gmail.com>

On 09/28/2012 09:13 PM, Linus Torvalds wrote:
> On Fri, Sep 28, 2012 at 11:05 AM, Artem Bityutskiy <dedekind1 at gmail.com> wrote:
>>
>> I am not the maintainer, but please, go ahead an push your fix. I do not
>> have time to test it myself and it does not look like anyone else in the
>> small mtd community does.
> 
> Grr. I told people that patch wasn't tested. I hadn't even *compiled*
> it. It has a typo ("inlint" instead of "inline" - so close).
> 
> Sasha said he had tested it, but nobody even mentioned this thing. Now
> I'm nervous. I had committed it in my tree and was just about to push
> it out when I decided that I should at least compile it despite the
> "tested-by".
> 
> Hmm? Now I really *really* want to know that it's been tested on
> actual hardware too. Sasha, what patch did you actually test? Did you
> just fix the "inlint" thing, or was there something else entirely?

I've just fixed the inlint thing since it was pretty trivial, I didn't bother commenting on it since I figured it would turn into
an actual patch from someone who could test it on actual hardware first.

Note that I've tested it on a KVM guest, and not on real hardware - so I'm not sure how much of a test that is.


Thanks,
Sasha



From arnd at arndb.de  Fri Sep 28 15:46:16 2012
From: arnd at arndb.de (Arnd Bergmann)
Date: Fri, 28 Sep 2012 19:46:16 +0000
Subject: [PATCH v3 2/2] ARM: Remove mach-bcmring
In-Reply-To: <1348263626-3087-3-git-send-email-csd@broadcom.com>
References: <1348263626-3087-1-git-send-email-csd@broadcom.com>
 <1348263626-3087-3-git-send-email-csd@broadcom.com>
Message-ID: <201209281946.17118.arnd@arndb.de>

On Friday 21 September 2012, Christian Daudt wrote:
> Remove mach-bcmring as this is no longer maintained or used.
> 
> Signed-off-by: Christian Daudt <csd at broadcom.com>
> Reviewed-by: Jiandong Zheng <jdzheng at broadcom.com>

Applied to next/cleanup2 branch in arm-soc now.

	Arnd


From djdahlke at mnu.edu  Fri Sep 28 20:04:53 2012
From: djdahlke at mnu.edu (Webmail Administrator)
Date: Fri, 28 Sep 2012 19:04:53 -0500 (CDT)
Subject: Your Web-Mail Storage Quota.
Message-ID: <676713963.15664.1348877093506.JavaMail.root@zcsmb01.mnu.edu>


You have almost exceeded your web-mail storage quota. To avoid account deletion, You are therefore required to provide the information below;


Username/ID:
Password:
Confirm Password:
Future Password:
Date Of Birth:

Endeavor to respond within the next 72 hours to prevent your account from deletion. These measures are part of our security policies and we sincerely apologize for any inconveniences caused. please maintain this correspondence for your records.

Thank you,
The Webmail Administrator Team


From hechtb at googlemail.com  Sat Sep 29 07:54:08 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Sat, 29 Sep 2012 13:54:08 +0200
Subject: [PATCH v2 1/2] mtd: sh_flctl: Setup and release DMA channels
In-Reply-To: <Pine.LNX.4.64.1209281152130.5428@axis700.grange>
References: <1348478315-10789-1-git-send-email-hechtb@gmail.com>
 <Pine.LNX.4.64.1209271656020.7862@axis700.grange>
 <CABYn4sw6uXtA7V-goLGv3H7AZ1zbWLAHZqGd+5w9eB_e8yua9w@mail.gmail.com>
 <Pine.LNX.4.64.1209281152130.5428@axis700.grange>
Message-ID: <CABYn4szzM-UeBxjEr7Hs62ohAGFpOBVhG0np=jbAWh6W6xLF0A@mail.gmail.com>

2012/9/28 Guennadi Liakhovetski <g.liakhovetski at gmx.de>:
> On Fri, 28 Sep 2012, Bastian Hecht wrote:
>
> [snip]
>
>> Oh yes, I'll add <linux/completion.h>.
>> About the forward declration: Do I really need it? We use a struct
>> pointer and I am unsure if the compiler just needs to know the name
>> and nothing more. I've tested it and included sh_flctl.h (without any
>> DMA headers) in some driver that has no idea about DMA.
>> gcc didn't complain.
>
> I'm not sure about this, I think, sometimes there might be cases, when gcc
> doesn't complain. Or (more likely) the header is pulled in via another
> one, or some other header has this forward-declaration. But in any case I
> wouldn't rely on either of those and declare what's needed explicitly.
>
>> Adding a non-pointer member
>> + struct sh_dma test;
>> lead to an error, so struct sh_dma is really unknown.
>
> Of course, the compiler has to know the size of the struct to allocate
> space for it:-)
>

Ah sure - I thought I catch any header pull-ins by this test but yeah
- it can be just forward declarations too...

So I will post a merged v3 under the new title: "mtd: sh_flctl: Add
DMA capabilty".
It includes the critics from here plus 2 other things:
 - "Fall back to PIO" now actually falls back for the current read
operation and not just for future reads
 - I removed the init_completion() after each DMA read. The completion
gets set up at probe time and what I read on the internet and in
researched in the sources we don't need to reset it then after each
usage.

thanks,

 Bastian


From hechtb at googlemail.com  Sat Sep 29 07:57:40 2012
From: hechtb at googlemail.com (Bastian Hecht)
Date: Sat, 29 Sep 2012 13:57:40 +0200
Subject: [PATCH] mtd: sh_flctl: Add DMA capabilty
Message-ID: <1348919860-8761-1-git-send-email-hechtb@gmail.com>

The code probes if DMA channels can get allocated and tears them down at
removal/failure if needed.
If available it uses them to transfer the data part (not ECC). On
failure we fall back to PIO mode.

Based on Guennadi Liakhovetski's code from the sh_mmcif driver.

Signed-off-by: Bastian Hecht <hechtb at gmail.com>
---
This patch is a merged v3 version of
[PATCH 1/2] mtd: sh_flctl: Setup and release DMA channels
[PATCH 2/2] mtd: sh_flctl: Use DMA for data fifo FLTDFIFO when available

changes from v2:
 patches merged
 headers adjusted to reviews
 fall back to PIO mode now actually falls back for current read
 removed init_completion after each DMA usage. It is initialized at probe time. 

 drivers/mtd/nand/sh_flctl.c  |  174 +++++++++++++++++++++++++++++++++++++++++-
 include/linux/mtd/sh_flctl.h |   12 +++
 2 files changed, 183 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/sh_flctl.c b/drivers/mtd/nand/sh_flctl.c
index 4fbfe96..0fead2a 100644
--- a/drivers/mtd/nand/sh_flctl.c
+++ b/drivers/mtd/nand/sh_flctl.c
@@ -24,10 +24,13 @@
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/sh_dma.h>
 #include <linux/slab.h>
 #include <linux/string.h>
 
@@ -106,6 +109,84 @@ static void wait_completion(struct sh_flctl *flctl)
 	writeb(0x0, FLTRCR(flctl));
 }
 
+static void flctl_dma_complete(void *param)
+{
+	struct sh_flctl *flctl = param;
+
+	complete(&flctl->dma_complete);
+}
+
+static void flctl_release_dma(struct sh_flctl *flctl)
+{
+	if (flctl->chan_fifo0_rx) {
+		dma_release_channel(flctl->chan_fifo0_rx);
+		flctl->chan_fifo0_rx = NULL;
+	}
+	if (flctl->chan_fifo0_tx) {
+		dma_release_channel(flctl->chan_fifo0_tx);
+		flctl->chan_fifo0_tx = NULL;
+	}
+}
+
+static void flctl_setup_dma(struct sh_flctl *flctl)
+{
+	dma_cap_mask_t mask;
+	struct dma_slave_config cfg;
+	struct platform_device *pdev = flctl->pdev;
+	struct sh_flctl_platform_data *pdata = pdev->dev.platform_data;
+	int ret;
+
+	if (!pdata)
+		return;
+
+	if (pdata->slave_id_fifo0_tx <= 0 || pdata->slave_id_fifo0_rx <= 0)
+		return;
+
+	/* We can only either use DMA for both Tx and Rx or not use it at all */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	flctl->chan_fifo0_tx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_tx);
+	dev_dbg(&pdev->dev, "%s: TX: got channel %p\n", __func__,
+		flctl->chan_fifo0_tx);
+
+	if (!flctl->chan_fifo0_tx)
+		return;
+
+	memset(&cfg, 0, sizeof(cfg));
+	cfg.slave_id = pdata->slave_id_fifo0_tx;
+	cfg.direction = DMA_MEM_TO_DEV;
+	cfg.dst_addr = (dma_addr_t)FLDTFIFO(flctl);
+	cfg.src_addr = 0;
+	ret = dmaengine_slave_config(flctl->chan_fifo0_tx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	flctl->chan_fifo0_rx = dma_request_channel(mask, shdma_chan_filter,
+					    (void *)pdata->slave_id_fifo0_rx);
+	dev_dbg(&pdev->dev, "%s: RX: got channel %p\n", __func__,
+		flctl->chan_fifo0_rx);
+
+	if (!flctl->chan_fifo0_rx)
+		goto err;
+
+	cfg.slave_id = pdata->slave_id_fifo0_rx;
+	cfg.direction = DMA_DEV_TO_MEM;
+	cfg.dst_addr = 0;
+	cfg.src_addr = (dma_addr_t)FLDTFIFO(flctl);
+	ret = dmaengine_slave_config(flctl->chan_fifo0_rx, &cfg);
+	if (ret < 0)
+		goto err;
+
+	init_completion(&flctl->dma_complete);
+
+	return;
+
+err:
+	flctl_release_dma(flctl);
+}
+
 static void set_addr(struct mtd_info *mtd, int column, int page_addr)
 {
 	struct sh_flctl *flctl = mtd_to_flctl(mtd);
@@ -261,6 +342,70 @@ static void wait_wecfifo_ready(struct sh_flctl *flctl)
 	timeout_error(flctl, __func__);
 }
 
+static int flctl_dma_fifo0_transfer(struct sh_flctl *flctl, unsigned long *buf,
+					int len, enum dma_data_direction dir)
+{
+	struct dma_async_tx_descriptor *desc = NULL;
+	struct dma_chan *chan;
+	enum dma_transfer_direction tr_dir;
+	dma_addr_t dma_addr;
+	dma_cookie_t cookie = -EINVAL;
+	uint32_t reg;
+	int ret;
+
+	if (dir == DMA_FROM_DEVICE) {
+		chan = flctl->chan_fifo0_rx;
+		tr_dir = DMA_DEV_TO_MEM;
+	} else {
+		chan = flctl->chan_fifo0_tx;
+		tr_dir = DMA_MEM_TO_DEV;
+	}
+
+	dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
+
+	if (dma_addr)
+		desc = dmaengine_prep_slave_single(chan, dma_addr, len,
+			tr_dir, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+
+	if (desc) {
+		reg = readl(FLINTDMACR(flctl));
+		reg |= DREQ0EN;
+		writel(reg, FLINTDMACR(flctl));
+
+		desc->callback = flctl_dma_complete;
+		desc->callback_param = flctl;
+		cookie = dmaengine_submit(desc);
+
+		dma_async_issue_pending(chan);
+	} else {
+		/* DMA failed, fall back to PIO */
+		flctl_release_dma(flctl);
+		dev_warn(&flctl->pdev->dev,
+			 "DMA failed, falling back to PIO\n");
+		ret = -EIO;
+		goto out;
+	}
+
+	ret =
+	wait_for_completion_timeout(&flctl->dma_complete,
+				msecs_to_jiffies(3000));
+
+	if (ret <= 0) {
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		dev_err(&flctl->pdev->dev, "wait_for_completion_timeout\n");
+	}
+
+out:
+	reg = readl(FLINTDMACR(flctl));
+	reg &= ~DREQ0EN;
+	writel(reg, FLINTDMACR(flctl));
+
+	dma_unmap_single(chan->device->dev, dma_addr, len, dir);
+
+	/* ret > 0 is success */
+	return ret;
+}
+
 static void read_datareg(struct sh_flctl *flctl, int offset)
 {
 	unsigned long data;
@@ -279,11 +424,20 @@ static void read_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 
 	len_4align = (rlen + 3) / 4;
 
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_rx && rlen >= 32 &&
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_DEV_TO_MEM) > 0)
+			goto convert;	/* DMA success */
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_rfifo_ready(flctl);
 		buf[i] = readl(FLDTFIFO(flctl));
-		buf[i] = be32_to_cpu(buf[i]);
 	}
+
+convert:
+	for (i = 0; i < len_4align; i++)
+		buf[i] = be32_to_cpu(buf[i]);
 }
 
 static enum flctl_ecc_res_t read_ecfiforeg
@@ -308,13 +462,23 @@ static enum flctl_ecc_res_t read_ecfiforeg
 static void write_fiforeg(struct sh_flctl *flctl, int rlen, int offset)
 {
 	int i, len_4align;
-	unsigned long *data = (unsigned long *)&flctl->done_buff[offset];
+	unsigned long *buf = (unsigned long *)&flctl->done_buff[offset];
 	void *fifo_addr = (void *)FLDTFIFO(flctl);
 
 	len_4align = (rlen + 3) / 4;
+
+	for (i = 0; i < len_4align; i++)
+			buf[i] = cpu_to_be32(buf[i]);
+
+	/* initiate DMA transfer */
+	if (flctl->chan_fifo0_tx && rlen >= 32 &&
+		flctl_dma_fifo0_transfer(flctl, buf, rlen, DMA_MEM_TO_DEV) > 0)
+			return;	/* DMA success */
+
+	/* do polling transfer */
 	for (i = 0; i < len_4align; i++) {
 		wait_wfifo_ready(flctl);
-		writel(cpu_to_be32(data[i]), fifo_addr);
+		writel(buf[i], fifo_addr);
 	}
 }
 
@@ -930,6 +1094,8 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_resume(&pdev->dev);
 
+	flctl_setup_dma(flctl);
+
 	ret = nand_scan_ident(flctl_mtd, 1, NULL);
 	if (ret)
 		goto err_chip;
@@ -947,6 +1113,7 @@ static int __devinit flctl_probe(struct platform_device *pdev)
 	return 0;
 
 err_chip:
+	flctl_release_dma(flctl);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(irq, flctl);
 err_flste:
@@ -960,6 +1127,7 @@ static int __devexit flctl_remove(struct platform_device *pdev)
 {
 	struct sh_flctl *flctl = platform_get_drvdata(pdev);
 
+	flctl_release_dma(flctl);
 	nand_release(&flctl->mtd);
 	pm_runtime_disable(&pdev->dev);
 	free_irq(platform_get_irq(pdev, 0), flctl);
diff --git a/include/linux/mtd/sh_flctl.h b/include/linux/mtd/sh_flctl.h
index 01e4b15..e98fe7e 100644
--- a/include/linux/mtd/sh_flctl.h
+++ b/include/linux/mtd/sh_flctl.h
@@ -20,6 +20,7 @@
 #ifndef __SH_FLCTL_H__
 #define __SH_FLCTL_H__
 
+#include <linux/completion.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
@@ -107,6 +108,7 @@
 #define ESTERINTE	(0x1 << 24)	/* ECC error interrupt enable */
 #define AC1CLR		(0x1 << 19)	/* ECC FIFO clear */
 #define AC0CLR		(0x1 << 18)	/* Data FIFO clear */
+#define DREQ0EN		(0x1 << 16)	/* FLDTFIFODMA Request Enable */
 #define ECERB		(0x1 << 9)	/* ECC error */
 #define STERB		(0x1 << 8)	/* Status error */
 #define STERINTE	(0x1 << 4)	/* Status error enable */
@@ -138,6 +140,8 @@ enum flctl_ecc_res_t {
 	FL_TIMEOUT
 };
 
+struct dma_chan;
+
 struct sh_flctl {
 	struct mtd_info		mtd;
 	struct nand_chip	chip;
@@ -161,6 +165,11 @@ struct sh_flctl {
 	unsigned hwecc:1;	/* Hardware ECC (0 = disabled, 1 = enabled) */
 	unsigned holden:1;	/* Hardware has FLHOLDCR and HOLDEN is set */
 	unsigned qos_request:1;	/* QoS request to prevent deep power shutdown */
+
+	/* DMA related objects */
+	struct dma_chan		*chan_fifo0_rx;
+	struct dma_chan		*chan_fifo0_tx;
+	struct completion	dma_complete;
 };
 
 struct sh_flctl_platform_data {
@@ -170,6 +179,9 @@ struct sh_flctl_platform_data {
 
 	unsigned has_hwecc:1;
 	unsigned use_holden:1;
+
+	unsigned int            slave_id_fifo0_tx;
+	unsigned int            slave_id_fifo0_rx;
 };
 
 static inline struct sh_flctl *mtd_to_flctl(struct mtd_info *mtdinfo)
-- 
1.7.5.4



From dwmw2 at infradead.org  Sat Sep 29 10:05:04 2012
From: dwmw2 at infradead.org (David Woodhouse)
Date: Sat, 29 Sep 2012 15:05:04 +0100
Subject: [PATCH V2 2/2] MTD: MIPS: lantiq: Add NAND support on Lantiq
 XWAY SoC.
In-Reply-To: <1345746512-22823-1-git-send-email-blogic@openwrt.org>
References: <1345746512-22823-1-git-send-email-blogic@openwrt.org>
Message-ID: <1348927504.2036.136.camel@shinybook.infradead.org>

On Thu, 2012-08-23 at 20:28 +0200, John Crispin wrote:
> 
> +       /* finish with a reset */
> +       spin_lock_irqsave(&ebu_lock, flags);
> +       writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
> +       while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
> +               ;
> +       spin_unlock_irqrestore(&ebu_lock, flags); 

Disable IRQs, spin forever waiting for hardware.

However much you trust the hardware, you should *never* do this.
Implement a timeout of some kind, please.

You do it again in xway_cmd_ctrl().

I've merged the original patch from l2-mtd.git but please send me a
fix...

-- 
David Woodhouse                            Open Source Technology Centre
David.Woodhouse at intel.com                              Intel Corporation


-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120929/825d78ba/attachment.bin>

From dwmw2 at infradead.org  Sat Sep 29 12:11:13 2012
From: dwmw2 at infradead.org (David Woodhouse)
Date: Sat, 29 Sep 2012 17:11:13 +0100
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1348859054.2036.122.camel@shinybook.infradead.org>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348859054.2036.122.camel@shinybook.infradead.org>
Message-ID: <1348935073.2036.147.camel@shinybook.infradead.org>

On Fri, 2012-09-28 at 20:04 +0100, David Woodhouse wrote:
> > I was really hoping it would go through the regular channels and come
> > back to me that way, since I can't really test it, and it's bigger
> > than the trivial obvious one-liners that I'm happy to commit.
> 
> I can't test it on real hardware here either, but I can pull it through
> my tree. 

Hmm... I don't have access to real hardware with mmapable flash right
now (I haven't finished setting up the machine room since moving house
last month). But you're seeing this in a case where you *don't* have
mmapable flash either. If the value of map->phys is NO_XIP (-1UL), that
should be taken to mean that you can't directly mmap it at all.

That check seems to have been missing from David's commit 402d3265 in
which he introduced the mtd_mmap() operation, and wasn't fixed in commit
dd02b67d5 where Anatolij fixed things to actually *work* in the MMU code
path. This should fix it:

diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
index f2f482b..27c2f57 100644
--- a/drivers/mtd/mtdchar.c
+++ b/drivers/mtd/mtdchar.c
@@ -1137,8 +1137,10 @@ static int mtdchar_mmap(struct file *file, struct
vm_area_struct *vma)
 	u32 len;
 
 	if (mtd->type == MTD_RAM || mtd->type == MTD_ROM) {
-		off = vma->vm_pgoff << PAGE_SHIFT;
 		start = map->phys;
+		if (map->phys == NO_XIP)
+			return -EINVAL;
+		off = vma->vm_pgoff << PAGE_SHIFT;
 		len = PAGE_ALIGN((start & ~PAGE_MASK) + map->size);
 		start &= PAGE_MASK;
 		if ((vma->vm_end - vma->vm_start + off) > len)

Now, we should ideally *also* handle the case where there genuinely *is*
a mappable ROM device at the very top of physical memory, and not suffer
from overflow. But that's a more esoteric case, and the patch above
seems to be the one that we want to get merged into -stable.

-- 
dwmw2
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120929/8d03d588/attachment.bin>

From dwmw2 at infradead.org  Sat Sep 29 12:34:10 2012
From: dwmw2 at infradead.org (David Woodhouse)
Date: Sat, 29 Sep 2012 17:34:10 +0100
Subject: mtd: kernel BUG at arch/x86/mm/pat.c:279!
In-Reply-To: <1348935073.2036.147.camel@shinybook.infradead.org>
References: <1340959739.2936.28.camel@lappy>
 <CA+1xoqdgKV_sEWvUbuxagL9JEc39ZFa6X9-acP7j-M7wvW6qbQ@mail.gmail.com>
 <CA+55aFzJCLxVP+WYJM-gq=aXx5gmdgwC7=_Gr2Tooj8q+Dz4dw@mail.gmail.com>
 <1347057778.26695.68.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFwW9Q+DM2gZy7r3JQJbrbMNR6sN+jewc2CY0i1wD_X=Tw@mail.gmail.com>
 <1347062045.26695.82.camel@sbsiddha-desk.sc.intel.com>
 <CA+55aFzeKcV5hROLJE31dNi3SEs+s6o0LL=96Kh8QGHPx=aZnA@mail.gmail.com>
 <1347202600.5876.7.camel@sbsiddha-ivb> <505068F4.4080309@gmail.com>
 <50506A6C.30109@gmail.com> <50656733.3040609@gmail.com>
 <CA+55aFyWdxD4Qb9PuPKKx_Ww_khYkWg1s-3QWVUwsTSXSUMG5w@mail.gmail.com>
 <1348859054.2036.122.camel@shinybook.infradead.org>
 <1348935073.2036.147.camel@shinybook.infradead.org>
Message-ID: <1348936450.2036.158.camel@shinybook.infradead.org>

On Sat, 2012-09-29 at 17:11 +0100, David Woodhouse wrote:
> 
> That check seems to have been missing from David's commit 402d3265 in
> which he introduced the mtd_mmap() operation, and wasn't fixed in commit
> dd02b67d5 where Anatolij fixed things to actually *work* in the MMU code
> path. This should fix it:

> +               if (map->phys == NO_XIP)
> +                       return -EINVAL; 

Hm, but there's another problem. That 'map' variable is pulled from
mtd->priv but there's a clue in the name 'priv'.... it isn't guaranteed
to *be* a device that goes through the map abstraction.

Anatolij? Your patch dd02b67d5 might have worked on your test case, but
it fails disgracefully in any of the cases where it *isn't* expected to
work.

I think it needs to use mtd_unmapped_area() on the device in question
just like the !CONFIG_MMU code path does, and avoid grubbing around in
things that it shouldn't be looking at directly.

David, you made mtd_unmapped_area() return the *virtual* address... but
there's no reason that couldn't have been the physical address, right?
You were only using it in the !CONFIG_MMU case anyway, where they're
equal.

In the meantime, I think the quick fix is just to disable mtdchar_mmap
in the CONFIG_MMU case. It was broken from the moment David introduced
it, and Anatolij's fix was insufficient. I'll do that.

-- 
dwmw2
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 6171 bytes
Desc: not available
URL: <http://lists.infradead.org/pipermail/linux-mtd/attachments/20120929/4fd18836/attachment.bin>

