GPMI-NAND: Wrong ECC size in driver

[Marek Vasut]

> On 01/04/2012 03:32 PM, Marek Vasut wrote:
> >> On 01/03/2012 11:58 PM, Huang Shijie wrote:
> >>> Hi Marek:
> >>>> Hi,
> >>>> 
> >>>> the gpmi-nand.c driver apparently has misconfigured ecc.size field:
> >>>> 
> >>>> drivers/mtd/nand/gpmi-nand/gpmi-nand.c:
> >>>> ---------->8 ----------
> >>>> 1493         chip->ecc.mode          = NAND_ECC_HW;
> >>>> 1494         chip->ecc.size          = 1;
> >>>> 1495         chip->ecc.layout        =&gpmi_hw_ecclayout;
> >>>> ---------- 8<  ----------
> >> 
> >> [snip]
> >> 
> >>> The gpmi driver does not support the subpage read/write.
> >>> I will be happy if the driver works only by setting the
> >>> NAND_NO_SUBPAGE_WRITE, without setting the ecc.size.
> >> 
> >> Can we just get rid of NAND_CHIPOPTIONS_MSK and trust that drivers won't
> >> set options that aren't appropriate?  Possibly replace it with
> >> documentation about which options are for chips, which are for drivers,
> >> and which (such as NAND_NO_SUBPAGE_WRITE) can be set by either.
> > 
> > Rather let's just adjust the mask?
> 
> The way the mask is used means that any given option can only be chip or
> driver, not both.  Though, I don't see anywhere this option is set by a
> chip -- maybe we can just renumber it to be in the controller half.

I suspect this was meant to allow controllers where one chip can do subpage-
write and the other can not.

> 
> I still don't see a whole lot of value in the mask, though -- seems to
> be just causing problems, especially given that bits set by the "wrong"
> component are silently discarded.

Yes. Patch is welcome to remove it and separate these two ;-)

M
> 
> -Scott